drivers/clocksource/timer-marco.c

   1 /*
   2  * System timer for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/cpu.h>
  14 #include <linux/bitops.h>
  15 #include <linux/irq.h>
  16 #include <linux/clk.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/sched_clock.h>
  22 #include <asm/mach/time.h>
  23
  24 #define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
  25 #define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
  26 #define SIRFSOC_TIMER_MATCH_0                           0x0018
  27 #define SIRFSOC_TIMER_MATCH_1                           0x001c
  28 #define SIRFSOC_TIMER_COUNTER_0                         0x0048
  29 #define SIRFSOC_TIMER_COUNTER_1                         0x004c
  30 #define SIRFSOC_TIMER_INTR_STATUS                       0x0060
  31 #define SIRFSOC_TIMER_WATCHDOG_EN                       0x0064
  32 #define SIRFSOC_TIMER_64COUNTER_CTRL                    0x0068
  33 #define SIRFSOC_TIMER_64COUNTER_LO                      0x006c
  34 #define SIRFSOC_TIMER_64COUNTER_HI                      0x0070
  35 #define SIRFSOC_TIMER_64COUNTER_LOAD_LO                 0x0074
  36 #define SIRFSOC_TIMER_64COUNTER_LOAD_HI                 0x0078
  37 #define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO             0x007c
  38 #define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI             0x0080
  39
  40 #define SIRFSOC_TIMER_REG_CNT 6
  41
  42 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  43         SIRFSOC_TIMER_WATCHDOG_EN,
  44         SIRFSOC_TIMER_32COUNTER_0_CTRL,
  45         SIRFSOC_TIMER_32COUNTER_1_CTRL,
  46         SIRFSOC_TIMER_64COUNTER_CTRL,
  47         SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
  48         SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
  49 };
  50
  51 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  52
  53 static void __iomem *sirfsoc_timer_base;
  54
  55 /* disable count and interrupt */
  56 static inline void sirfsoc_timer_count_disable(int idx)
  57 {
  58         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
  59                 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
  60 }
  61
  62 /* enable count and interrupt */
  63 static inline void sirfsoc_timer_count_enable(int idx)
  64 {
  65         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
  66                 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
  67 }
  68
  69 /* timer interrupt handler */
  70 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  71 {
  72         struct clock_event_device *ce = dev_id;
  73         int cpu = smp_processor_id();
  74
  75         /* clear timer interrupt */
  76         writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
  77
  78         if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
  79                 sirfsoc_timer_count_disable(cpu);
  80
  81         ce->event_handler(ce);
  82
  83         return IRQ_HANDLED;
  84 }
  85
  86 /* read 64-bit timer counter */
  87 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
  88 {
  89         u64 cycles;
  90
  91         writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
  92                         BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
  93
  94         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
  95         cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
  96
  97         return cycles;
  98 }
  99
 100 static int sirfsoc_timer_set_next_event(unsigned long delta,
 101         struct clock_event_device *ce)
 102 {
 103         int cpu = smp_processor_id();
 104
 105         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
 106                 4 * cpu);
 107         writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
 108                 4 * cpu);
 109
 110         /* enable the tick */
 111         sirfsoc_timer_count_enable(cpu);
 112
 113         return 0;
 114 }
 115
 116 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
 117         struct clock_event_device *ce)
 118 {
 119         switch (mode) {
 120         case CLOCK_EVT_MODE_ONESHOT:
 121                 /* enable in set_next_event */
 122                 break;
 123         default:
 124                 break;
 125         }
 126
 127         sirfsoc_timer_count_disable(smp_processor_id());
 128 }
 129
 130 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 131 {
 132         int i;
 133
 134         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 135                 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 136 }
 137
 138 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 139 {
 140         int i;
 141
 142         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 143                 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 144
 145         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
 146                 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
 147         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
 148                 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
 149
 150         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
 151                 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 152 }
 153
 154 static struct clock_event_device __percpu *sirfsoc_clockevent;
 155
 156 static struct clocksource sirfsoc_clocksource = {
 157         .name = "sirfsoc_clocksource",
 158         .rating = 200,
 159         .mask = CLOCKSOURCE_MASK(64),
 160         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 161         .read = sirfsoc_timer_read,
 162         .suspend = sirfsoc_clocksource_suspend,
 163         .resume = sirfsoc_clocksource_resume,
 164 };
 165
 166 static struct irqaction sirfsoc_timer_irq = {
 167         .name = "sirfsoc_timer0",
 168         .flags = IRQF_TIMER | IRQF_NOBALANCING,
 169         .handler = sirfsoc_timer_interrupt,
 170 };
 171
 172 static struct irqaction sirfsoc_timer1_irq = {
 173         .name = "sirfsoc_timer1",
 174         .flags = IRQF_TIMER | IRQF_NOBALANCING,
 175         .handler = sirfsoc_timer_interrupt,
 176 };
 177
 178 static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
 179 {
 180         int cpu = smp_processor_id();
 181         struct irqaction *action;
 182
 183         if (cpu == 0)
 184                 action = &sirfsoc_timer_irq;
 185         else
 186                 action = &sirfsoc_timer1_irq;
 187
 188         ce->irq = action->irq;
 189         ce->name = "local_timer";
 190         ce->features = CLOCK_EVT_FEAT_ONESHOT;
 191         ce->rating = 200;
 192         ce->set_mode = sirfsoc_timer_set_mode;
 193         ce->set_next_event = sirfsoc_timer_set_next_event;
 194         clockevents_calc_mult_shift(ce, CLOCK_TICK_RATE, 60);
 195         ce->max_delta_ns = clockevent_delta2ns(-2, ce);
 196         ce->min_delta_ns = clockevent_delta2ns(2, ce);
 197         ce->cpumask = cpumask_of(cpu);
 198
 199         action->dev_id = ce;
 200         BUG_ON(setup_irq(ce->irq, action));
 201         irq_set_affinity(action->irq, cpumask_of(cpu));
 202
 203         clockevents_register_device(ce);
 204         return 0;
 205 }
 206
 207 static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
 208 {
 209         int cpu = smp_processor_id();
 210
 211         sirfsoc_timer_count_disable(1);
 212
 213         if (cpu == 0)
 214                 remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
 215         else
 216                 remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
 217 }
 218
 219 static int sirfsoc_cpu_notify(struct notifier_block *self,
 220                               unsigned long action, void *hcpu)
 221 {
 222         /*
 223          * Grab cpu pointer in each case to avoid spurious
 224          * preemptible warnings
 225          */
 226         switch (action & ~CPU_TASKS_FROZEN) {
 227         case CPU_STARTING:
 228                 sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
 229                 break;
 230         case CPU_DYING:
 231                 sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
 232                 break;
 233         }
 234
 235         return NOTIFY_OK;
 236 }
 237
 238 static struct notifier_block sirfsoc_cpu_nb = {
 239         .notifier_call = sirfsoc_cpu_notify,
 240 };
 241
 242 static void __init sirfsoc_clockevent_init(void)
 243 {
 244         sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
 245         BUG_ON(!sirfsoc_clockevent);
 246
 247         BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
 248
 249         /* Immediately configure the timer on the boot CPU */
 250         sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
 251 }
 252
 253 /* initialize the kernel jiffy timer source */
 254 static void __init sirfsoc_marco_timer_init(void)
 255 {
 256         unsigned long rate;
 257         u32 timer_div;
 258         struct clk *clk;
 259
 260         /* timer's input clock is io clock */
 261         clk = clk_get_sys("io", NULL);
 262
 263         BUG_ON(IS_ERR(clk));
 264         rate = clk_get_rate(clk);
 265
 266         BUG_ON(rate < CLOCK_TICK_RATE);
 267         BUG_ON(rate % CLOCK_TICK_RATE);
 268
 269         /* Initialize the timer dividers */
 270         timer_div = rate / CLOCK_TICK_RATE - 1;
 271         writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 272         writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
 273         writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
 274
 275         /* Initialize timer counters to 0 */
 276         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
 277         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
 278         writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
 279                 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 280         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
 281         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
 282
 283         /* Clear all interrupts */
 284         writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
 285
 286         BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
 287
 288         sirfsoc_clockevent_init();
 289 }
 290
 291 static void __init sirfsoc_of_timer_init(struct device_node *np)
 292 {
 293         sirfsoc_timer_base = of_iomap(np, 0);
 294         if (!sirfsoc_timer_base)
 295                 panic("unable to map timer cpu registers\n");
 296
 297         sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 298         if (!sirfsoc_timer_irq.irq)
 299                 panic("No irq passed for timer0 via DT\n");
 300
 301         sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
 302         if (!sirfsoc_timer1_irq.irq)
 303                 panic("No irq passed for timer1 via DT\n");
 304
 305         sirfsoc_marco_timer_init();
 306 }
 307 CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );