2 * Copyright (C) ST-Ericsson SA 2011
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
13 * source on DB8500 and Timer 3 on DB5500.
15 #include <linux/clockchips.h>
16 #include <linux/clksrc-dbx500-prcmu.h>
18 #include <asm/sched_clock.h>
20 #define RATE_32K 32768
22 #define TIMER_MODE_CONTINOUS 0x1
23 #define TIMER_DOWNCOUNT_VAL 0xffffffff
25 #define PRCMU_TIMER_REF 0
26 #define PRCMU_TIMER_DOWNCOUNT 0x4
27 #define PRCMU_TIMER_MODE 0x8
29 #define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
31 static void __iomem
*clksrc_dbx500_timer_base
;
33 static cycle_t
clksrc_dbx500_prcmu_read(struct clocksource
*cs
)
38 count
= readl(clksrc_dbx500_timer_base
+
39 PRCMU_TIMER_DOWNCOUNT
);
40 count2
= readl(clksrc_dbx500_timer_base
+
41 PRCMU_TIMER_DOWNCOUNT
);
42 } while (count2
!= count
);
44 /* Negate because the timer is a decrementing counter */
48 static struct clocksource clocksource_dbx500_prcmu
= {
49 .name
= "dbx500-prcmu-timer",
51 .read
= clksrc_dbx500_prcmu_read
,
52 .mask
= CLOCKSOURCE_MASK(32),
53 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
56 #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
58 static u32 notrace
dbx500_prcmu_sched_clock_read(void)
60 if (unlikely(!clksrc_dbx500_timer_base
))
63 return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu
);
68 void __init
clksrc_dbx500_prcmu_init(void __iomem
*base
)
70 clksrc_dbx500_timer_base
= base
;
73 * The A9 sub system expects the timer to be configured as
74 * a continous looping timer.
75 * The PRCMU should configure it but if it for some reason
76 * don't we do it here.
78 if (readl(clksrc_dbx500_timer_base
+ PRCMU_TIMER_MODE
) !=
79 TIMER_MODE_CONTINOUS
) {
80 writel(TIMER_MODE_CONTINOUS
,
81 clksrc_dbx500_timer_base
+ PRCMU_TIMER_MODE
);
82 writel(TIMER_DOWNCOUNT_VAL
,
83 clksrc_dbx500_timer_base
+ PRCMU_TIMER_REF
);
85 #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
86 setup_sched_clock(dbx500_prcmu_sched_clock_read
,
89 clocksource_register_hz(&clocksource_dbx500_prcmu
, RATE_32K
);