2 * Freescale MXS SPI master driver
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
42 #include <linux/highmem.h>
43 #include <linux/clk.h>
44 #include <linux/err.h>
45 #include <linux/completion.h>
46 #include <linux/gpio.h>
47 #include <linux/regulator/consumer.h>
48 #include <linux/module.h>
49 #include <linux/pinctrl/consumer.h>
50 #include <linux/stmp_device.h>
51 #include <linux/spi/spi.h>
52 #include <linux/spi/mxs-spi.h>
54 #define DRIVER_NAME "mxs-spi"
56 /* Use 10S timeout for very long transfers, it should suffice. */
57 #define SSP_TIMEOUT 10000
59 #define SG_MAXLEN 0xff00
66 static int mxs_spi_setup_transfer(struct spi_device
*dev
,
67 struct spi_transfer
*t
)
69 struct mxs_spi
*spi
= spi_master_get_devdata(dev
->master
);
70 struct mxs_ssp
*ssp
= &spi
->ssp
;
71 uint8_t bits_per_word
;
74 bits_per_word
= dev
->bits_per_word
;
75 if (t
&& t
->bits_per_word
)
76 bits_per_word
= t
->bits_per_word
;
78 if (bits_per_word
!= 8) {
79 dev_err(&dev
->dev
, "%s, unsupported bits_per_word=%d\n",
80 __func__
, bits_per_word
);
84 hz
= dev
->max_speed_hz
;
86 hz
= min(hz
, t
->speed_hz
);
88 dev_err(&dev
->dev
, "Cannot continue with zero clock\n");
92 mxs_ssp_set_clk_rate(ssp
, hz
);
94 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI
) |
95 BF_SSP_CTRL1_WORD_LENGTH
96 (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS
) |
97 ((dev
->mode
& SPI_CPOL
) ? BM_SSP_CTRL1_POLARITY
: 0) |
98 ((dev
->mode
& SPI_CPHA
) ? BM_SSP_CTRL1_PHASE
: 0),
99 ssp
->base
+ HW_SSP_CTRL1(ssp
));
101 writel(0x0, ssp
->base
+ HW_SSP_CMD0
);
102 writel(0x0, ssp
->base
+ HW_SSP_CMD1
);
107 static int mxs_spi_setup(struct spi_device
*dev
)
111 if (!dev
->bits_per_word
)
112 dev
->bits_per_word
= 8;
114 if (dev
->mode
& ~(SPI_CPOL
| SPI_CPHA
))
117 err
= mxs_spi_setup_transfer(dev
, NULL
);
120 "Failed to setup transfer, error = %d\n", err
);
126 static uint32_t mxs_spi_cs_to_reg(unsigned cs
)
131 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
133 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
134 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
135 * the datasheet for further details. In SPI mode, they are used to
136 * toggle the chip-select lines (nCS pins).
139 select
|= BM_SSP_CTRL0_WAIT_FOR_CMD
;
141 select
|= BM_SSP_CTRL0_WAIT_FOR_IRQ
;
146 static void mxs_spi_set_cs(struct mxs_spi
*spi
, unsigned cs
)
148 const uint32_t mask
=
149 BM_SSP_CTRL0_WAIT_FOR_CMD
| BM_SSP_CTRL0_WAIT_FOR_IRQ
;
151 struct mxs_ssp
*ssp
= &spi
->ssp
;
153 writel(mask
, ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
154 select
= mxs_spi_cs_to_reg(cs
);
155 writel(select
, ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
158 static inline void mxs_spi_enable(struct mxs_spi
*spi
)
160 struct mxs_ssp
*ssp
= &spi
->ssp
;
162 writel(BM_SSP_CTRL0_LOCK_CS
,
163 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
164 writel(BM_SSP_CTRL0_IGNORE_CRC
,
165 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
168 static inline void mxs_spi_disable(struct mxs_spi
*spi
)
170 struct mxs_ssp
*ssp
= &spi
->ssp
;
172 writel(BM_SSP_CTRL0_LOCK_CS
,
173 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
174 writel(BM_SSP_CTRL0_IGNORE_CRC
,
175 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
178 static int mxs_ssp_wait(struct mxs_spi
*spi
, int offset
, int mask
, bool set
)
180 const unsigned long timeout
= jiffies
+ msecs_to_jiffies(SSP_TIMEOUT
);
181 struct mxs_ssp
*ssp
= &spi
->ssp
;
185 reg
= readl_relaxed(ssp
->base
+ offset
);
194 } while (time_before(jiffies
, timeout
));
199 static void mxs_ssp_dma_irq_callback(void *param
)
201 struct mxs_spi
*spi
= param
;
205 static irqreturn_t
mxs_ssp_irq_handler(int irq
, void *dev_id
)
207 struct mxs_ssp
*ssp
= dev_id
;
208 dev_err(ssp
->dev
, "%s[%i] CTRL1=%08x STATUS=%08x\n",
210 readl(ssp
->base
+ HW_SSP_CTRL1(ssp
)),
211 readl(ssp
->base
+ HW_SSP_STATUS(ssp
)));
215 static int mxs_spi_txrx_dma(struct mxs_spi
*spi
, int cs
,
216 unsigned char *buf
, int len
,
217 int *first
, int *last
, int write
)
219 struct mxs_ssp
*ssp
= &spi
->ssp
;
220 struct dma_async_tx_descriptor
*desc
= NULL
;
221 const bool vmalloced_buf
= is_vmalloc_addr(buf
);
222 const int desc_len
= vmalloced_buf
? PAGE_SIZE
: SG_MAXLEN
;
223 const int sgs
= DIV_ROUND_UP(len
, desc_len
);
227 struct page
*vm_page
;
231 struct scatterlist sg
;
237 dma_xfer
= kzalloc(sizeof(*dma_xfer
) * sgs
, GFP_KERNEL
);
241 INIT_COMPLETION(spi
->c
);
243 ctrl0
= readl(ssp
->base
+ HW_SSP_CTRL0
);
244 ctrl0
|= BM_SSP_CTRL0_DATA_XFER
| mxs_spi_cs_to_reg(cs
);
247 ctrl0
|= BM_SSP_CTRL0_LOCK_CS
;
249 ctrl0
|= BM_SSP_CTRL0_READ
;
251 /* Queue the DMA data transfer. */
252 for (sg_count
= 0; sg_count
< sgs
; sg_count
++) {
253 min
= min(len
, desc_len
);
255 /* Prepare the transfer descriptor. */
256 if ((sg_count
+ 1 == sgs
) && *last
)
257 ctrl0
|= BM_SSP_CTRL0_IGNORE_CRC
;
259 if (ssp
->devid
== IMX23_SSP
)
262 dma_xfer
[sg_count
].pio
[0] = ctrl0
;
263 dma_xfer
[sg_count
].pio
[3] = min
;
266 vm_page
= vmalloc_to_page(buf
);
271 sg_buf
= page_address(vm_page
) +
272 ((size_t)buf
& ~PAGE_MASK
);
277 sg_init_one(&dma_xfer
[sg_count
].sg
, sg_buf
, min
);
278 ret
= dma_map_sg(ssp
->dev
, &dma_xfer
[sg_count
].sg
, 1,
279 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
284 /* Queue the PIO register write transfer. */
285 desc
= dmaengine_prep_slave_sg(ssp
->dmach
,
286 (struct scatterlist
*)dma_xfer
[sg_count
].pio
,
287 (ssp
->devid
== IMX23_SSP
) ? 1 : 4,
289 sg_count
? DMA_PREP_INTERRUPT
: 0);
292 "Failed to get PIO reg. write descriptor.\n");
297 desc
= dmaengine_prep_slave_sg(ssp
->dmach
,
298 &dma_xfer
[sg_count
].sg
, 1,
299 write
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
300 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
304 "Failed to get DMA data write descriptor.\n");
311 * The last descriptor must have this callback,
312 * to finish the DMA transaction.
314 desc
->callback
= mxs_ssp_dma_irq_callback
;
315 desc
->callback_param
= spi
;
317 /* Start the transfer. */
318 dmaengine_submit(desc
);
319 dma_async_issue_pending(ssp
->dmach
);
321 ret
= wait_for_completion_timeout(&spi
->c
,
322 msecs_to_jiffies(SSP_TIMEOUT
));
324 dev_err(ssp
->dev
, "DMA transfer timeout\n");
332 while (--sg_count
>= 0) {
334 dma_unmap_sg(ssp
->dev
, &dma_xfer
[sg_count
].sg
, 1,
335 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
343 static int mxs_spi_txrx_pio(struct mxs_spi
*spi
, int cs
,
344 unsigned char *buf
, int len
,
345 int *first
, int *last
, int write
)
347 struct mxs_ssp
*ssp
= &spi
->ssp
;
352 mxs_spi_set_cs(spi
, cs
);
355 if (*last
&& len
== 0)
356 mxs_spi_disable(spi
);
358 if (ssp
->devid
== IMX23_SSP
) {
359 writel(BM_SSP_CTRL0_XFER_COUNT
,
360 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
362 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
364 writel(1, ssp
->base
+ HW_SSP_XFER_SIZE
);
368 writel(BM_SSP_CTRL0_READ
,
369 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
371 writel(BM_SSP_CTRL0_READ
,
372 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
374 writel(BM_SSP_CTRL0_RUN
,
375 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
377 if (mxs_ssp_wait(spi
, HW_SSP_CTRL0
, BM_SSP_CTRL0_RUN
, 1))
381 writel(*buf
, ssp
->base
+ HW_SSP_DATA(ssp
));
383 writel(BM_SSP_CTRL0_DATA_XFER
,
384 ssp
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
387 if (mxs_ssp_wait(spi
, HW_SSP_STATUS(ssp
),
388 BM_SSP_STATUS_FIFO_EMPTY
, 0))
391 *buf
= (readl(ssp
->base
+ HW_SSP_DATA(ssp
)) & 0xff);
394 if (mxs_ssp_wait(spi
, HW_SSP_CTRL0
, BM_SSP_CTRL0_RUN
, 0))
406 static int mxs_spi_transfer_one(struct spi_master
*master
,
407 struct spi_message
*m
)
409 struct mxs_spi
*spi
= spi_master_get_devdata(master
);
410 struct mxs_ssp
*ssp
= &spi
->ssp
;
412 struct spi_transfer
*t
, *tmp_t
;
418 cs
= m
->spi
->chip_select
;
420 list_for_each_entry_safe(t
, tmp_t
, &m
->transfers
, transfer_list
) {
422 status
= mxs_spi_setup_transfer(m
->spi
, t
);
426 if (&t
->transfer_list
== m
->transfers
.next
)
428 if (&t
->transfer_list
== m
->transfers
.prev
)
430 if ((t
->rx_buf
&& t
->tx_buf
) || (t
->rx_dma
&& t
->tx_dma
)) {
432 "Cannot send and receive simultaneously\n");
438 * Small blocks can be transfered via PIO.
439 * Measured by empiric means:
441 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
443 * DMA only: 2.164808 seconds, 473.0KB/s
444 * Combined: 1.676276 seconds, 610.9KB/s
447 writel(BM_SSP_CTRL1_DMA_ENABLE
,
448 ssp
->base
+ HW_SSP_CTRL1(ssp
) +
449 STMP_OFFSET_REG_CLR
);
452 status
= mxs_spi_txrx_pio(spi
, cs
,
454 t
->len
, &first
, &last
, 1);
456 status
= mxs_spi_txrx_pio(spi
, cs
,
460 writel(BM_SSP_CTRL1_DMA_ENABLE
,
461 ssp
->base
+ HW_SSP_CTRL1(ssp
) +
462 STMP_OFFSET_REG_SET
);
465 status
= mxs_spi_txrx_dma(spi
, cs
,
466 (void *)t
->tx_buf
, t
->len
,
469 status
= mxs_spi_txrx_dma(spi
, cs
,
475 stmp_reset_block(ssp
->base
);
479 m
->actual_length
+= t
->len
;
484 spi_finalize_current_message(master
);
489 static bool mxs_ssp_dma_filter(struct dma_chan
*chan
, void *param
)
491 struct mxs_ssp
*ssp
= param
;
493 if (!mxs_dma_is_apbh(chan
))
496 if (chan
->chan_id
!= ssp
->dma_channel
)
499 chan
->private = &ssp
->dma_data
;
504 static const struct of_device_id mxs_spi_dt_ids
[] = {
505 { .compatible
= "fsl,imx23-spi", .data
= (void *) IMX23_SSP
, },
506 { .compatible
= "fsl,imx28-spi", .data
= (void *) IMX28_SSP
, },
509 MODULE_DEVICE_TABLE(of
, mxs_spi_dt_ids
);
511 static int __devinit
mxs_spi_probe(struct platform_device
*pdev
)
513 const struct of_device_id
*of_id
=
514 of_match_device(mxs_spi_dt_ids
, &pdev
->dev
);
515 struct device_node
*np
= pdev
->dev
.of_node
;
516 struct spi_master
*master
;
519 struct resource
*iores
, *dmares
;
520 struct pinctrl
*pinctrl
;
523 int devid
, dma_channel
, clk_freq
;
524 int ret
= 0, irq_err
, irq_dma
;
528 * Default clock speed for the SPI core. 160MHz seems to
529 * work reasonably well with most SPI flashes, so use this
530 * as a default. Override with "clock-frequency" DT prop.
532 const int clk_freq_default
= 160000000;
534 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
535 irq_err
= platform_get_irq(pdev
, 0);
536 irq_dma
= platform_get_irq(pdev
, 1);
537 if (!iores
|| irq_err
< 0 || irq_dma
< 0)
540 base
= devm_request_and_ioremap(&pdev
->dev
, iores
);
542 return -EADDRNOTAVAIL
;
544 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
546 return PTR_ERR(pinctrl
);
548 clk
= devm_clk_get(&pdev
->dev
, NULL
);
553 devid
= (enum mxs_ssp_id
) of_id
->data
;
555 * TODO: This is a temporary solution and should be changed
556 * to use generic DMA binding later when the helpers get in.
558 ret
= of_property_read_u32(np
, "fsl,ssp-dma-channel",
562 "Failed to get DMA channel\n");
566 ret
= of_property_read_u32(np
, "clock-frequency",
569 clk_freq
= clk_freq_default
;
571 dmares
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
574 devid
= pdev
->id_entry
->driver_data
;
575 dma_channel
= dmares
->start
;
576 clk_freq
= clk_freq_default
;
579 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
583 master
->transfer_one_message
= mxs_spi_transfer_one
;
584 master
->setup
= mxs_spi_setup
;
585 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
;
586 master
->num_chipselect
= 3;
587 master
->dev
.of_node
= np
;
588 master
->flags
= SPI_MASTER_HALF_DUPLEX
;
590 spi
= spi_master_get_devdata(master
);
592 ssp
->dev
= &pdev
->dev
;
596 ssp
->dma_channel
= dma_channel
;
598 init_completion(&spi
->c
);
600 ret
= devm_request_irq(&pdev
->dev
, irq_err
, mxs_ssp_irq_handler
, 0,
603 goto out_master_free
;
606 dma_cap_set(DMA_SLAVE
, mask
);
607 ssp
->dma_data
.chan_irq
= irq_dma
;
608 ssp
->dmach
= dma_request_channel(mask
, mxs_ssp_dma_filter
, ssp
);
610 dev_err(ssp
->dev
, "Failed to request DMA\n");
611 goto out_master_free
;
614 clk_prepare_enable(ssp
->clk
);
615 clk_set_rate(ssp
->clk
, clk_freq
);
616 ssp
->clk_rate
= clk_get_rate(ssp
->clk
) / 1000;
618 stmp_reset_block(ssp
->base
);
620 platform_set_drvdata(pdev
, master
);
622 ret
= spi_register_master(master
);
624 dev_err(&pdev
->dev
, "Cannot register SPI master, %d\n", ret
);
631 dma_release_channel(ssp
->dmach
);
632 clk_disable_unprepare(ssp
->clk
);
634 spi_master_put(master
);
638 static int __devexit
mxs_spi_remove(struct platform_device
*pdev
)
640 struct spi_master
*master
;
644 master
= spi_master_get(platform_get_drvdata(pdev
));
645 spi
= spi_master_get_devdata(master
);
648 spi_unregister_master(master
);
650 dma_release_channel(ssp
->dmach
);
652 clk_disable_unprepare(ssp
->clk
);
654 spi_master_put(master
);
659 static struct platform_driver mxs_spi_driver
= {
660 .probe
= mxs_spi_probe
,
661 .remove
= __devexit_p(mxs_spi_remove
),
664 .owner
= THIS_MODULE
,
665 .of_match_table
= mxs_spi_dt_ids
,
669 module_platform_driver(mxs_spi_driver
);
671 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
672 MODULE_DESCRIPTION("MXS SPI master driver");
673 MODULE_LICENSE("GPL");
674 MODULE_ALIAS("platform:mxs-spi");