arch/sparc64/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/msi.h>
  18 #include <linux/irq.h>
  19 #include <linux/init.h>
  20
  21 #include <asm/uaccess.h>
  22 #include <asm/pbm.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/irq.h>
  25 #include <asm/ebus.h>
  26 #include <asm/isa.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31
  32 unsigned long pci_memspace_mask = 0xffffffffUL;
  33
  34 #ifndef CONFIG_PCI
  35 /* A "nop" PCI implementation. */
  36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  37                                   unsigned long off, unsigned long len,
  38                                   unsigned char *buf)
  39 {
  40         return 0;
  41 }
  42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  43                                    unsigned long off, unsigned long len,
  44                                    unsigned char *buf)
  45 {
  46         return 0;
  47 }
  48 #else
  49
  50 /* List of all PCI controllers found in the system. */
  51 struct pci_controller_info *pci_controller_root = NULL;
  52
  53 /* Each PCI controller found gets a unique index. */
  54 int pci_num_controllers = 0;
  55
  56 volatile int pci_poke_in_progress;
  57 volatile int pci_poke_cpu = -1;
  58 volatile int pci_poke_faulted;
  59
  60 static DEFINE_SPINLOCK(pci_poke_lock);
  61
  62 void pci_config_read8(u8 *addr, u8 *ret)
  63 {
  64         unsigned long flags;
  65         u8 byte;
  66
  67         spin_lock_irqsave(&pci_poke_lock, flags);
  68         pci_poke_cpu = smp_processor_id();
  69         pci_poke_in_progress = 1;
  70         pci_poke_faulted = 0;
  71         __asm__ __volatile__("membar #Sync\n\t"
  72                              "lduba [%1] %2, %0\n\t"
  73                              "membar #Sync"
  74                              : "=r" (byte)
  75                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  76                              : "memory");
  77         pci_poke_in_progress = 0;
  78         pci_poke_cpu = -1;
  79         if (!pci_poke_faulted)
  80                 *ret = byte;
  81         spin_unlock_irqrestore(&pci_poke_lock, flags);
  82 }
  83
  84 void pci_config_read16(u16 *addr, u16 *ret)
  85 {
  86         unsigned long flags;
  87         u16 word;
  88
  89         spin_lock_irqsave(&pci_poke_lock, flags);
  90         pci_poke_cpu = smp_processor_id();
  91         pci_poke_in_progress = 1;
  92         pci_poke_faulted = 0;
  93         __asm__ __volatile__("membar #Sync\n\t"
  94                              "lduha [%1] %2, %0\n\t"
  95                              "membar #Sync"
  96                              : "=r" (word)
  97                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  98                              : "memory");
  99         pci_poke_in_progress = 0;
 100         pci_poke_cpu = -1;
 101         if (!pci_poke_faulted)
 102                 *ret = word;
 103         spin_unlock_irqrestore(&pci_poke_lock, flags);
 104 }
 105
 106 void pci_config_read32(u32 *addr, u32 *ret)
 107 {
 108         unsigned long flags;
 109         u32 dword;
 110
 111         spin_lock_irqsave(&pci_poke_lock, flags);
 112         pci_poke_cpu = smp_processor_id();
 113         pci_poke_in_progress = 1;
 114         pci_poke_faulted = 0;
 115         __asm__ __volatile__("membar #Sync\n\t"
 116                              "lduwa [%1] %2, %0\n\t"
 117                              "membar #Sync"
 118                              : "=r" (dword)
 119                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 120                              : "memory");
 121         pci_poke_in_progress = 0;
 122         pci_poke_cpu = -1;
 123         if (!pci_poke_faulted)
 124                 *ret = dword;
 125         spin_unlock_irqrestore(&pci_poke_lock, flags);
 126 }
 127
 128 void pci_config_write8(u8 *addr, u8 val)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&pci_poke_lock, flags);
 133         pci_poke_cpu = smp_processor_id();
 134         pci_poke_in_progress = 1;
 135         pci_poke_faulted = 0;
 136         __asm__ __volatile__("membar #Sync\n\t"
 137                              "stba %0, [%1] %2\n\t"
 138                              "membar #Sync"
 139                              : /* no outputs */
 140                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 141                              : "memory");
 142         pci_poke_in_progress = 0;
 143         pci_poke_cpu = -1;
 144         spin_unlock_irqrestore(&pci_poke_lock, flags);
 145 }
 146
 147 void pci_config_write16(u16 *addr, u16 val)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&pci_poke_lock, flags);
 152         pci_poke_cpu = smp_processor_id();
 153         pci_poke_in_progress = 1;
 154         pci_poke_faulted = 0;
 155         __asm__ __volatile__("membar #Sync\n\t"
 156                              "stha %0, [%1] %2\n\t"
 157                              "membar #Sync"
 158                              : /* no outputs */
 159                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 160                              : "memory");
 161         pci_poke_in_progress = 0;
 162         pci_poke_cpu = -1;
 163         spin_unlock_irqrestore(&pci_poke_lock, flags);
 164 }
 165
 166 void pci_config_write32(u32 *addr, u32 val)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&pci_poke_lock, flags);
 171         pci_poke_cpu = smp_processor_id();
 172         pci_poke_in_progress = 1;
 173         pci_poke_faulted = 0;
 174         __asm__ __volatile__("membar #Sync\n\t"
 175                              "stwa %0, [%1] %2\n\t"
 176                              "membar #Sync"
 177                              : /* no outputs */
 178                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 179                              : "memory");
 180         pci_poke_in_progress = 0;
 181         pci_poke_cpu = -1;
 182         spin_unlock_irqrestore(&pci_poke_lock, flags);
 183 }
 184
 185 /* Probe for all PCI controllers in the system. */
 186 extern void sabre_init(struct device_node *, const char *);
 187 extern void psycho_init(struct device_node *, const char *);
 188 extern void schizo_init(struct device_node *, const char *);
 189 extern void schizo_plus_init(struct device_node *, const char *);
 190 extern void tomatillo_init(struct device_node *, const char *);
 191 extern void sun4v_pci_init(struct device_node *, const char *);
 192 extern void fire_pci_init(struct device_node *, const char *);
 193
 194 static struct {
 195         char *model_name;
 196         void (*init)(struct device_node *, const char *);
 197 } pci_controller_table[] __initdata = {
 198         { "SUNW,sabre", sabre_init },
 199         { "pci108e,a000", sabre_init },
 200         { "pci108e,a001", sabre_init },
 201         { "SUNW,psycho", psycho_init },
 202         { "pci108e,8000", psycho_init },
 203         { "SUNW,schizo", schizo_init },
 204         { "pci108e,8001", schizo_init },
 205         { "SUNW,schizo+", schizo_plus_init },
 206         { "pci108e,8002", schizo_plus_init },
 207         { "SUNW,tomatillo", tomatillo_init },
 208         { "pci108e,a801", tomatillo_init },
 209         { "SUNW,sun4v-pci", sun4v_pci_init },
 210         { "pciex108e,80f0", fire_pci_init },
 211 };
 212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 213                                   sizeof(pci_controller_table[0]))
 214
 215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
 216 {
 217         int i;
 218
 219         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 220                 if (!strncmp(model_name,
 221                              pci_controller_table[i].model_name,
 222                              namelen)) {
 223                         pci_controller_table[i].init(dp, model_name);
 224                         return 1;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
 232 {
 233         int i;
 234
 235         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 236                 if (!strncmp(model_name,
 237                              pci_controller_table[i].model_name,
 238                              namelen)) {
 239                         return 1;
 240                 }
 241         }
 242         return 0;
 243 }
 244
 245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
 246 {
 247         struct device_node *dp;
 248         int count = 0;
 249
 250         for_each_node_by_name(dp, "pci") {
 251                 struct property *prop;
 252                 int len;
 253
 254                 prop = of_find_property(dp, "model", &len);
 255                 if (!prop)
 256                         prop = of_find_property(dp, "compatible", &len);
 257
 258                 if (prop) {
 259                         const char *model = prop->value;
 260                         int item_len = 0;
 261
 262                         /* Our value may be a multi-valued string in the
 263                          * case of some compatible properties. For sanity,
 264                          * only try the first one.
 265                          */
 266                         while (model[item_len] && len) {
 267                                 len--;
 268                                 item_len++;
 269                         }
 270
 271                         if (handler(model, item_len, dp))
 272                                 count++;
 273                 }
 274         }
 275
 276         return count;
 277 }
 278
 279
 280 /* Is there some PCI controller in the system?  */
 281 int __init pcic_present(void)
 282 {
 283         return pci_controller_scan(pci_is_controller);
 284 }
 285
 286 const struct pci_iommu_ops *pci_iommu_ops;
 287 EXPORT_SYMBOL(pci_iommu_ops);
 288
 289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
 290         pci_sun4v_iommu_ops;
 291
 292 /* Find each controller in the system, attach and initialize
 293  * software state structure for each and link into the
 294  * pci_controller_root.  Setup the controller enough such
 295  * that bus scanning can be done.
 296  */
 297 static void __init pci_controller_probe(void)
 298 {
 299         if (tlb_type == hypervisor)
 300                 pci_iommu_ops = &pci_sun4v_iommu_ops;
 301         else
 302                 pci_iommu_ops = &pci_sun4u_iommu_ops;
 303
 304         printk("PCI: Probing for controllers.\n");
 305
 306         pci_controller_scan(pci_controller_init);
 307 }
 308
 309 static unsigned long pci_parse_of_flags(u32 addr0)
 310 {
 311         unsigned long flags = 0;
 312
 313         if (addr0 & 0x02000000) {
 314                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 315                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
 316                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 317                 if (addr0 & 0x40000000)
 318                         flags |= IORESOURCE_PREFETCH
 319                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 320         } else if (addr0 & 0x01000000)
 321                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 322         return flags;
 323 }
 324
 325 /* The of_device layer has translated all of the assigned-address properties
 326  * into physical address resources, we only have to figure out the register
 327  * mapping.
 328  */
 329 static void pci_parse_of_addrs(struct of_device *op,
 330                                struct device_node *node,
 331                                struct pci_dev *dev)
 332 {
 333         struct resource *op_res;
 334         const u32 *addrs;
 335         int proplen;
 336
 337         addrs = of_get_property(node, "assigned-addresses", &proplen);
 338         if (!addrs)
 339                 return;
 340         printk("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
 341         op_res = &op->resource[0];
 342         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 343                 struct resource *res;
 344                 unsigned long flags;
 345                 int i;
 346
 347                 flags = pci_parse_of_flags(addrs[0]);
 348                 if (!flags)
 349                         continue;
 350                 i = addrs[0] & 0xff;
 351                 printk("  start: %lx, end: %lx, i: %x\n",
 352                        op_res->start, op_res->end, i);
 353
 354                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 355                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 356                 } else if (i == dev->rom_base_reg) {
 357                         res = &dev->resource[PCI_ROM_RESOURCE];
 358                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 359                 } else {
 360                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 361                         continue;
 362                 }
 363                 res->start = op_res->start;
 364                 res->end = op_res->end;
 365                 res->flags = flags;
 366                 res->name = pci_name(dev);
 367         }
 368 }
 369
 370 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 371                                   struct device_node *node,
 372                                   struct pci_bus *bus, int devfn,
 373                                   int host_controller)
 374 {
 375         struct dev_archdata *sd;
 376         struct pci_dev *dev;
 377         const char *type;
 378         u32 class;
 379
 380         dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
 381         if (!dev)
 382                 return NULL;
 383
 384         sd = &dev->dev.archdata;
 385         sd->iommu = pbm->iommu;
 386         sd->stc = &pbm->stc;
 387         sd->host_controller = pbm;
 388         sd->prom_node = node;
 389         sd->op = of_find_device_by_node(node);
 390         sd->msi_num = 0xffffffff;
 391
 392         type = of_get_property(node, "device_type", NULL);
 393         if (type == NULL)
 394                 type = "";
 395
 396         printk("    create device, devfn: %x, type: %s hostcontroller(%d)\n",
 397                devfn, type, host_controller);
 398
 399         dev->bus = bus;
 400         dev->sysdata = node;
 401         dev->dev.parent = bus->bridge;
 402         dev->dev.bus = &pci_bus_type;
 403         dev->devfn = devfn;
 404         dev->multifunction = 0;         /* maybe a lie? */
 405
 406         if (host_controller) {
 407                 dev->vendor = 0x108e;
 408                 dev->device = 0x8000;
 409                 dev->subsystem_vendor = 0x0000;
 410                 dev->subsystem_device = 0x0000;
 411                 dev->cfg_size = 256;
 412                 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
 413                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 414                         0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
 415         } else {
 416                 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 417                 dev->device = of_getintprop_default(node, "device-id", 0xffff);
 418                 dev->subsystem_vendor =
 419                         of_getintprop_default(node, "subsystem-vendor-id", 0);
 420                 dev->subsystem_device =
 421                         of_getintprop_default(node, "subsystem-id", 0);
 422
 423                 dev->cfg_size = pci_cfg_space_size(dev);
 424
 425                 /* We can't actually use the firmware value, we have
 426                  * to read what is in the register right now.  One
 427                  * reason is that in the case of IDE interfaces the
 428                  * firmware can sample the value before the the IDE
 429                  * interface is programmed into native mode.
 430                  */
 431                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 432                 dev->class = class >> 8;
 433
 434                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 435                         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 436         }
 437         printk("    class: 0x%x device name: %s\n",
 438                dev->class, pci_name(dev));
 439
 440         /* I have seen IDE devices which will not respond to
 441          * the bmdma simplex check reads if bus mastering is
 442          * disabled.
 443          */
 444         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 445                 pci_set_master(dev);
 446
 447         dev->current_state = 4;         /* unknown power state */
 448         dev->error_state = pci_channel_io_normal;
 449
 450         if (host_controller) {
 451                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 452                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 453                 dev->irq = PCI_IRQ_NONE;
 454         } else {
 455                 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 456                         /* a PCI-PCI bridge */
 457                         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 458                         dev->rom_base_reg = PCI_ROM_ADDRESS1;
 459                 } else if (!strcmp(type, "cardbus")) {
 460                         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 461                 } else {
 462                         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 463                         dev->rom_base_reg = PCI_ROM_ADDRESS;
 464
 465                         dev->irq = sd->op->irqs[0];
 466                         if (dev->irq == 0xffffffff)
 467                                 dev->irq = PCI_IRQ_NONE;
 468                 }
 469         }
 470         pci_parse_of_addrs(sd->op, node, dev);
 471
 472         printk("    adding to system ...\n");
 473
 474         pci_device_add(dev, bus);
 475
 476         return dev;
 477 }
 478
 479 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 480 {
 481         u32 idx, first, last;
 482
 483         first = 8;
 484         last = 0;
 485         for (idx = 0; idx < 8; idx++) {
 486                 if ((map & (1 << idx)) != 0) {
 487                         if (first > idx)
 488                                 first = idx;
 489                         if (last < idx)
 490                                 last = idx;
 491                 }
 492         }
 493
 494         *first_p = first;
 495         *last_p = last;
 496 }
 497
 498 static void __init pci_resource_adjust(struct resource *res,
 499                                        struct resource *root)
 500 {
 501         res->start += root->start;
 502         res->end += root->start;
 503 }
 504
 505 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 506  * a proper 'ranges' property.
 507  */
 508 static void __devinit apb_fake_ranges(struct pci_dev *dev,
 509                                       struct pci_bus *bus,
 510                                       struct pci_pbm_info *pbm)
 511 {
 512         struct resource *res;
 513         u32 first, last;
 514         u8 map;
 515
 516         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 517         apb_calc_first_last(map, &first, &last);
 518         res = bus->resource[0];
 519         res->start = (first << 21);
 520         res->end = (last << 21) + ((1 << 21) - 1);
 521         res->flags = IORESOURCE_IO;
 522         pci_resource_adjust(res, &pbm->io_space);
 523
 524         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 525         apb_calc_first_last(map, &first, &last);
 526         res = bus->resource[1];
 527         res->start = (first << 21);
 528         res->end = (last << 21) + ((1 << 21) - 1);
 529         res->flags = IORESOURCE_MEM;
 530         pci_resource_adjust(res, &pbm->mem_space);
 531 }
 532
 533 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 534                                       struct device_node *node,
 535                                       struct pci_bus *bus);
 536
 537 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 538
 539 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
 540                                          struct device_node *node,
 541                                          struct pci_dev *dev)
 542 {
 543         struct pci_bus *bus;
 544         const u32 *busrange, *ranges;
 545         int len, i, simba;
 546         struct resource *res;
 547         unsigned int flags;
 548         u64 size;
 549
 550         printk("of_scan_pci_bridge(%s)\n", node->full_name);
 551
 552         /* parse bus-range property */
 553         busrange = of_get_property(node, "bus-range", &len);
 554         if (busrange == NULL || len != 8) {
 555                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 556                        node->full_name);
 557                 return;
 558         }
 559         ranges = of_get_property(node, "ranges", &len);
 560         simba = 0;
 561         if (ranges == NULL) {
 562                 const char *model = of_get_property(node, "model", NULL);
 563                 if (model && !strcmp(model, "SUNW,simba")) {
 564                         simba = 1;
 565                 } else {
 566                         printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
 567                                node->full_name);
 568                         return;
 569                 }
 570         }
 571
 572         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 573         if (!bus) {
 574                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 575                        node->full_name);
 576                 return;
 577         }
 578
 579         bus->primary = dev->bus->number;
 580         bus->subordinate = busrange[1];
 581         bus->bridge_ctl = 0;
 582
 583         /* parse ranges property, or cook one up by hand for Simba */
 584         /* PCI #address-cells == 3 and #size-cells == 2 always */
 585         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 586         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 587                 res->flags = 0;
 588                 bus->resource[i] = res;
 589                 ++res;
 590         }
 591         if (simba) {
 592                 apb_fake_ranges(dev, bus, pbm);
 593                 goto simba_cont;
 594         }
 595         i = 1;
 596         for (; len >= 32; len -= 32, ranges += 8) {
 597                 struct resource *root;
 598
 599                 flags = pci_parse_of_flags(ranges[0]);
 600                 size = GET_64BIT(ranges, 6);
 601                 if (flags == 0 || size == 0)
 602                         continue;
 603                 if (flags & IORESOURCE_IO) {
 604                         res = bus->resource[0];
 605                         if (res->flags) {
 606                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 607                                        " for bridge %s\n", node->full_name);
 608                                 continue;
 609                         }
 610                         root = &pbm->io_space;
 611                 } else {
 612                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 613                                 printk(KERN_ERR "PCI: too many memory ranges"
 614                                        " for bridge %s\n", node->full_name);
 615                                 continue;
 616                         }
 617                         res = bus->resource[i];
 618                         ++i;
 619                         root = &pbm->mem_space;
 620                 }
 621
 622                 res->start = GET_64BIT(ranges, 1);
 623                 res->end = res->start + size - 1;
 624                 res->flags = flags;
 625
 626                 /* Another way to implement this would be to add an of_device
 627                  * layer routine that can calculate a resource for a given
 628                  * range property value in a PCI device.
 629                  */
 630                 pci_resource_adjust(res, root);
 631         }
 632 simba_cont:
 633         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 634                 bus->number);
 635         printk("    bus name: %s\n", bus->name);
 636
 637         pci_of_scan_bus(pbm, node, bus);
 638 }
 639
 640 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 641                                       struct device_node *node,
 642                                       struct pci_bus *bus)
 643 {
 644         struct device_node *child;
 645         const u32 *reg;
 646         int reglen, devfn;
 647         struct pci_dev *dev;
 648
 649         printk("PCI: scan_bus[%s] bus no %d\n",
 650                node->full_name, bus->number);
 651
 652         child = NULL;
 653         while ((child = of_get_next_child(node, child)) != NULL) {
 654                 printk("  * %s\n", child->full_name);
 655                 reg = of_get_property(child, "reg", &reglen);
 656                 if (reg == NULL || reglen < 20)
 657                         continue;
 658                 devfn = (reg[0] >> 8) & 0xff;
 659
 660                 /* create a new pci_dev for this device */
 661                 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
 662                 if (!dev)
 663                         continue;
 664                 printk("PCI: dev header type: %x\n", dev->hdr_type);
 665
 666                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 667                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 668                         of_scan_pci_bridge(pbm, child, dev);
 669         }
 670 }
 671
 672 static ssize_t
 673 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 674 {
 675         struct pci_dev *pdev;
 676         struct device_node *dp;
 677
 678         pdev = to_pci_dev(dev);
 679         dp = pdev->dev.archdata.prom_node;
 680
 681         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 682 }
 683
 684 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 685
 686 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
 687 {
 688         struct pci_dev *dev;
 689         struct pci_bus *child_bus;
 690         int err;
 691
 692         list_for_each_entry(dev, &bus->devices, bus_list) {
 693                 /* we don't really care if we can create this file or
 694                  * not, but we need to assign the result of the call
 695                  * or the world will fall under alien invasion and
 696                  * everybody will be frozen on a spaceship ready to be
 697                  * eaten on alpha centauri by some green and jelly
 698                  * humanoid.
 699                  */
 700                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 701         }
 702         list_for_each_entry(child_bus, &bus->children, node)
 703                 pci_bus_register_of_sysfs(child_bus);
 704 }
 705
 706 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
 707                                  unsigned int devfn,
 708                                  int where, int size,
 709                                  u32 *value)
 710 {
 711         static u8 fake_pci_config[] = {
 712                 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
 713                 0x00, 0x80, /* Device: 0x8000 (PBM) */
 714                 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
 715                 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
 716                 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
 717                 0x00, /* Cacheline: 0x00 */
 718                 0x40, /* Latency: 0x40 */
 719                 0x00, /* Header-Type: 0x00 normal */
 720         };
 721
 722         *value = 0;
 723         if (where >= 0 && where < sizeof(fake_pci_config) &&
 724             (where + size) >= 0 &&
 725             (where + size) < sizeof(fake_pci_config) &&
 726             size <= sizeof(u32)) {
 727                 while (size--) {
 728                         *value <<= 8;
 729                         *value |= fake_pci_config[where + size];
 730                 }
 731         }
 732
 733         return PCIBIOS_SUCCESSFUL;
 734 }
 735
 736 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
 737                                   unsigned int devfn,
 738                                   int where, int size,
 739                                   u32 value)
 740 {
 741         return PCIBIOS_SUCCESSFUL;
 742 }
 743
 744 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
 745 {
 746         struct pci_controller_info *p = pbm->parent;
 747         struct device_node *node = pbm->prom_node;
 748         struct pci_dev *host_pdev;
 749         struct pci_bus *bus;
 750
 751         printk("PCI: Scanning PBM %s\n", node->full_name);
 752
 753         /* XXX parent device? XXX */
 754         bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
 755         if (!bus) {
 756                 printk(KERN_ERR "Failed to create bus for %s\n",
 757                        node->full_name);
 758                 return NULL;
 759         }
 760         bus->secondary = pbm->pci_first_busno;
 761         bus->subordinate = pbm->pci_last_busno;
 762
 763         bus->resource[0] = &pbm->io_space;
 764         bus->resource[1] = &pbm->mem_space;
 765
 766         /* Create the dummy host bridge and link it in.  */
 767         host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
 768         bus->self = host_pdev;
 769
 770         pci_of_scan_bus(pbm, node, bus);
 771         pci_bus_add_devices(bus);
 772         pci_bus_register_of_sysfs(bus);
 773
 774         return bus;
 775 }
 776
 777 static void __init pci_scan_each_controller_bus(void)
 778 {
 779         struct pci_controller_info *p;
 780
 781         for (p = pci_controller_root; p; p = p->next)
 782                 p->scan_bus(p);
 783 }
 784
 785 extern void power_init(void);
 786
 787 static int __init pcibios_init(void)
 788 {
 789         pci_controller_probe();
 790         if (pci_controller_root == NULL)
 791                 return 0;
 792
 793         pci_scan_each_controller_bus();
 794
 795         isa_init();
 796         ebus_init();
 797         power_init();
 798
 799         return 0;
 800 }
 801
 802 subsys_initcall(pcibios_init);
 803
 804 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 805 {
 806         struct pci_pbm_info *pbm = pbus->sysdata;
 807
 808         /* Generic PCI bus probing sets these to point at
 809          * &io{port,mem}_resouce which is wrong for us.
 810          */
 811         pbus->resource[0] = &pbm->io_space;
 812         pbus->resource[1] = &pbm->mem_space;
 813 }
 814
 815 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 816 {
 817         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 818         struct resource *root = NULL;
 819
 820         if (r->flags & IORESOURCE_IO)
 821                 root = &pbm->io_space;
 822         if (r->flags & IORESOURCE_MEM)
 823                 root = &pbm->mem_space;
 824
 825         return root;
 826 }
 827
 828 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 829 {
 830 }
 831
 832 void pcibios_align_resource(void *data, struct resource *res,
 833                             resource_size_t size, resource_size_t align)
 834 {
 835 }
 836
 837 int pcibios_enable_device(struct pci_dev *dev, int mask)
 838 {
 839         u16 cmd, oldcmd;
 840         int i;
 841
 842         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 843         oldcmd = cmd;
 844
 845         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 846                 struct resource *res = &dev->resource[i];
 847
 848                 /* Only set up the requested stuff */
 849                 if (!(mask & (1<<i)))
 850                         continue;
 851
 852                 if (res->flags & IORESOURCE_IO)
 853                         cmd |= PCI_COMMAND_IO;
 854                 if (res->flags & IORESOURCE_MEM)
 855                         cmd |= PCI_COMMAND_MEMORY;
 856         }
 857
 858         if (cmd != oldcmd) {
 859                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 860                        pci_name(dev), cmd);
 861                 /* Enable the appropriate bits in the PCI command register.  */
 862                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 863         }
 864         return 0;
 865 }
 866
 867 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 868                              struct resource *res)
 869 {
 870         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 871         struct resource zero_res, *root;
 872
 873         zero_res.start = 0;
 874         zero_res.end = 0;
 875         zero_res.flags = res->flags;
 876
 877         if (res->flags & IORESOURCE_IO)
 878                 root = &pbm->io_space;
 879         else
 880                 root = &pbm->mem_space;
 881
 882         pci_resource_adjust(&zero_res, root);
 883
 884         region->start = res->start - zero_res.start;
 885         region->end = res->end - zero_res.start;
 886 }
 887 EXPORT_SYMBOL(pcibios_resource_to_bus);
 888
 889 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
 890                              struct pci_bus_region *region)
 891 {
 892         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 893         struct resource *root;
 894
 895         res->start = region->start;
 896         res->end = region->end;
 897
 898         if (res->flags & IORESOURCE_IO)
 899                 root = &pbm->io_space;
 900         else
 901                 root = &pbm->mem_space;
 902
 903         pci_resource_adjust(res, root);
 904 }
 905 EXPORT_SYMBOL(pcibios_bus_to_resource);
 906
 907 char * __devinit pcibios_setup(char *str)
 908 {
 909         return str;
 910 }
 911
 912 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 913
 914 /* If the user uses a host-bridge as the PCI device, he may use
 915  * this to perform a raw mmap() of the I/O or MEM space behind
 916  * that controller.
 917  *
 918  * This can be useful for execution of x86 PCI bios initialization code
 919  * on a PCI card, like the xfree86 int10 stuff does.
 920  */
 921 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
 922                                       enum pci_mmap_state mmap_state)
 923 {
 924         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 925         struct pci_controller_info *p;
 926         unsigned long space_size, user_offset, user_size;
 927
 928         p = pbm->parent;
 929         if (mmap_state == pci_mmap_io) {
 930                 space_size = (pbm->io_space.end -
 931                               pbm->io_space.start) + 1;
 932         } else {
 933                 space_size = (pbm->mem_space.end -
 934                               pbm->mem_space.start) + 1;
 935         }
 936
 937         /* Make sure the request is in range. */
 938         user_offset = vma->vm_pgoff << PAGE_SHIFT;
 939         user_size = vma->vm_end - vma->vm_start;
 940
 941         if (user_offset >= space_size ||
 942             (user_offset + user_size) > space_size)
 943                 return -EINVAL;
 944
 945         if (mmap_state == pci_mmap_io) {
 946                 vma->vm_pgoff = (pbm->io_space.start +
 947                                  user_offset) >> PAGE_SHIFT;
 948         } else {
 949                 vma->vm_pgoff = (pbm->mem_space.start +
 950                                  user_offset) >> PAGE_SHIFT;
 951         }
 952
 953         return 0;
 954 }
 955
 956 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
 957  * to the 32-bit pci bus offset for DEV requested by the user.
 958  *
 959  * Basically, the user finds the base address for his device which he wishes
 960  * to mmap.  They read the 32-bit value from the config space base register,
 961  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 962  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 963  *
 964  * Returns negative error code on failure, zero on success.
 965  */
 966 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
 967                                   enum pci_mmap_state mmap_state)
 968 {
 969         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
 970         unsigned long user32 = user_offset & pci_memspace_mask;
 971         unsigned long largest_base, this_base, addr32;
 972         int i;
 973
 974         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 975                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
 976
 977         /* Figure out which base address this is for. */
 978         largest_base = 0UL;
 979         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 980                 struct resource *rp = &dev->resource[i];
 981
 982                 /* Active? */
 983                 if (!rp->flags)
 984                         continue;
 985
 986                 /* Same type? */
 987                 if (i == PCI_ROM_RESOURCE) {
 988                         if (mmap_state != pci_mmap_mem)
 989                                 continue;
 990                 } else {
 991                         if ((mmap_state == pci_mmap_io &&
 992                              (rp->flags & IORESOURCE_IO) == 0) ||
 993                             (mmap_state == pci_mmap_mem &&
 994                              (rp->flags & IORESOURCE_MEM) == 0))
 995                                 continue;
 996                 }
 997
 998                 this_base = rp->start;
 999
1000                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1001
1002                 if (mmap_state == pci_mmap_io)
1003                         addr32 &= 0xffffff;
1004
1005                 if (addr32 <= user32 && this_base > largest_base)
1006                         largest_base = this_base;
1007         }
1008
1009         if (largest_base == 0UL)
1010                 return -EINVAL;
1011
1012         /* Now construct the final physical address. */
1013         if (mmap_state == pci_mmap_io)
1014                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1015         else
1016                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1017
1018         return 0;
1019 }
1020
1021 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1022  * mapping.
1023  */
1024 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1025                                             enum pci_mmap_state mmap_state)
1026 {
1027         vma->vm_flags |= (VM_IO | VM_RESERVED);
1028 }
1029
1030 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1031  * device mapping.
1032  */
1033 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1034                                              enum pci_mmap_state mmap_state)
1035 {
1036         /* Our io_remap_pfn_range takes care of this, do nothing.  */
1037 }
1038
1039 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1040  * for this architecture.  The region in the process to map is described by vm_start
1041  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1042  * The pci device structure is provided so that architectures may make mapping
1043  * decisions on a per-device or per-bus basis.
1044  *
1045  * Returns a negative error code on failure, zero on success.
1046  */
1047 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1048                         enum pci_mmap_state mmap_state,
1049                         int write_combine)
1050 {
1051         int ret;
1052
1053         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1054         if (ret < 0)
1055                 return ret;
1056
1057         __pci_mmap_set_flags(dev, vma, mmap_state);
1058         __pci_mmap_set_pgprot(dev, vma, mmap_state);
1059
1060         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1061         ret = io_remap_pfn_range(vma, vma->vm_start,
1062                                  vma->vm_pgoff,
1063                                  vma->vm_end - vma->vm_start,
1064                                  vma->vm_page_prot);
1065         if (ret)
1066                 return ret;
1067
1068         return 0;
1069 }
1070
1071 /* Return the domain nuber for this pci bus */
1072
1073 int pci_domain_nr(struct pci_bus *pbus)
1074 {
1075         struct pci_pbm_info *pbm = pbus->sysdata;
1076         int ret;
1077
1078         if (pbm == NULL || pbm->parent == NULL) {
1079                 ret = -ENXIO;
1080         } else {
1081                 struct pci_controller_info *p = pbm->parent;
1082
1083                 ret = p->index;
1084                 ret = ((ret << 1) +
1085                        ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
1086         }
1087
1088         return ret;
1089 }
1090 EXPORT_SYMBOL(pci_domain_nr);
1091
1092 #ifdef CONFIG_PCI_MSI
1093 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1094 {
1095         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1096         struct pci_controller_info *p = pbm->parent;
1097         int virt_irq, err;
1098
1099         if (!pbm->msi_num || !p->setup_msi_irq)
1100                 return -EINVAL;
1101
1102         err = p->setup_msi_irq(&virt_irq, pdev, desc);
1103         if (err)
1104                 return err;
1105
1106         return 0;
1107 }
1108
1109 void arch_teardown_msi_irq(unsigned int virt_irq)
1110 {
1111         struct msi_desc *entry = get_irq_msi(virt_irq);
1112         struct pci_dev *pdev = entry->dev;
1113         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1114         struct pci_controller_info *p = pbm->parent;
1115
1116         if (!pbm->msi_num || !p->setup_msi_irq)
1117                 return;
1118
1119         return p->teardown_msi_irq(virt_irq, pdev);
1120 }
1121 #endif /* !(CONFIG_PCI_MSI) */
1122
1123 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1124 {
1125         return pdev->dev.archdata.prom_node;
1126 }
1127 EXPORT_SYMBOL(pci_device_to_OF_node);
1128
1129 #endif /* !(CONFIG_PCI) */