drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FIMC_CORE_H_
  10 #define FIMC_CORE_H_
  11
  12 /*#define DEBUG*/
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/sched.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/types.h>
  18 #include <linux/videodev2.h>
  19 #include <linux/io.h>
  20
  21 #include <media/media-entity.h>
  22 #include <media/videobuf2-core.h>
  23 #include <media/v4l2-device.h>
  24 #include <media/v4l2-mem2mem.h>
  25 #include <media/v4l2-mediabus.h>
  26 #include <media/s5p_fimc.h>
  27
  28 #include "regs-fimc.h"
  29
  30 #define err(fmt, args...) \
  31         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  32
  33 #define dbg(fmt, args...) \
  34         pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  35
  36 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
  37 #define FIMC_SHUTDOWN_TIMEOUT   ((100*HZ)/1000)
  38 #define MAX_FIMC_CLOCKS         2
  39 #define FIMC_MODULE_NAME        "s5p-fimc"
  40 #define FIMC_MAX_DEVS           4
  41 #define FIMC_MAX_OUT_BUFS       4
  42 #define SCALER_MAX_HRATIO       64
  43 #define SCALER_MAX_VRATIO       64
  44 #define DMA_MIN_SIZE            8
  45
  46 /* indices to the clocks array */
  47 enum {
  48         CLK_BUS,
  49         CLK_GATE,
  50 };
  51
  52 enum fimc_dev_flags {
  53         ST_LPM,
  54         /* m2m node */
  55         ST_M2M_RUN,
  56         ST_M2M_PEND,
  57         ST_M2M_SUSPENDING,
  58         ST_M2M_SUSPENDED,
  59         /* capture node */
  60         ST_CAPT_PEND,
  61         ST_CAPT_RUN,
  62         ST_CAPT_STREAM,
  63         ST_CAPT_SHUT,
  64         ST_CAPT_BUSY,
  65 };
  66
  67 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
  68 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  69
  70 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
  71 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
  72 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
  73
  74 enum fimc_datapath {
  75         FIMC_CAMERA,
  76         FIMC_DMA,
  77         FIMC_LCDFIFO,
  78         FIMC_WRITEBACK
  79 };
  80
  81 enum fimc_color_fmt {
  82         S5P_FIMC_RGB565 = 0x10,
  83         S5P_FIMC_RGB666,
  84         S5P_FIMC_RGB888,
  85         S5P_FIMC_RGB30_LOCAL,
  86         S5P_FIMC_YCBCR420 = 0x20,
  87         S5P_FIMC_YCBYCR422,
  88         S5P_FIMC_YCRYCB422,
  89         S5P_FIMC_CBYCRY422,
  90         S5P_FIMC_CRYCBY422,
  91         S5P_FIMC_YCBCR444_LOCAL,
  92 };
  93
  94 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
  95
  96 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
  97 #define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
  98
  99 /* The embedded image effect selection */
 100 #define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
 101 #define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
 102 #define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
 103 #define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
 104 #define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
 105 #define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
 106
 107 /* The hardware context state. */
 108 #define FIMC_PARAMS             (1 << 0)
 109 #define FIMC_SRC_ADDR           (1 << 1)
 110 #define FIMC_DST_ADDR           (1 << 2)
 111 #define FIMC_SRC_FMT            (1 << 3)
 112 #define FIMC_DST_FMT            (1 << 4)
 113 #define FIMC_CTX_M2M            (1 << 5)
 114 #define FIMC_CTX_CAP            (1 << 6)
 115 #define FIMC_CTX_SHUT           (1 << 7)
 116
 117 /* Image conversion flags */
 118 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 119 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 120 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 121 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 122 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 123 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 124 /*
 125  * YCbCr data dynamic range for RGB-YUV color conversion.
 126  * Y/Cb/Cr: (0 ~ 255) */
 127 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 128 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 129 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 130
 131 #define FLIP_NONE                       0
 132 #define FLIP_X_AXIS                     1
 133 #define FLIP_Y_AXIS                     2
 134 #define FLIP_XY_AXIS                    (FLIP_X_AXIS | FLIP_Y_AXIS)
 135
 136 /**
 137  * struct fimc_fmt - the driver's internal color format data
 138  * @mbus_code: Media Bus pixel code, -1 if not applicable
 139  * @name: format description
 140  * @fourcc: the fourcc code for this format, 0 if not applicable
 141  * @color: the corresponding fimc_color_fmt
 142  * @memplanes: number of physically non-contiguous data planes
 143  * @colplanes: number of physically contiguous data planes
 144  * @depth: per plane driver's private 'number of bits per pixel'
 145  * @flags: flags indicating which operation mode format applies to
 146  */
 147 struct fimc_fmt {
 148         enum v4l2_mbus_pixelcode mbus_code;
 149         char    *name;
 150         u32     fourcc;
 151         u32     color;
 152         u16     memplanes;
 153         u16     colplanes;
 154         u8      depth[VIDEO_MAX_PLANES];
 155         u16     flags;
 156 #define FMT_FLAGS_CAM   (1 << 0)
 157 #define FMT_FLAGS_M2M   (1 << 1)
 158 };
 159
 160 /**
 161  * struct fimc_dma_offset - pixel offset information for DMA
 162  * @y_h:        y value horizontal offset
 163  * @y_v:        y value vertical offset
 164  * @cb_h:       cb value horizontal offset
 165  * @cb_v:       cb value vertical offset
 166  * @cr_h:       cr value horizontal offset
 167  * @cr_v:       cr value vertical offset
 168  */
 169 struct fimc_dma_offset {
 170         int     y_h;
 171         int     y_v;
 172         int     cb_h;
 173         int     cb_v;
 174         int     cr_h;
 175         int     cr_v;
 176 };
 177
 178 /**
 179  * struct fimc_effect - color effect information
 180  * @type:       effect type
 181  * @pat_cb:     cr value when type is "arbitrary"
 182  * @pat_cr:     cr value when type is "arbitrary"
 183  */
 184 struct fimc_effect {
 185         u32     type;
 186         u8      pat_cb;
 187         u8      pat_cr;
 188 };
 189
 190 /**
 191  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 192  * @scaleup_h:          flag indicating scaling up horizontally
 193  * @scaleup_v:          flag indicating scaling up vertically
 194  * @copy_mode:          flag indicating transparent DMA transfer (no scaling
 195  *                      and color format conversion)
 196  * @enabled:            flag indicating if the scaler is used
 197  * @hfactor:            horizontal shift factor
 198  * @vfactor:            vertical shift factor
 199  * @pre_hratio:         horizontal ratio of the prescaler
 200  * @pre_vratio:         vertical ratio of the prescaler
 201  * @pre_dst_width:      the prescaler's destination width
 202  * @pre_dst_height:     the prescaler's destination height
 203  * @main_hratio:        the main scaler's horizontal ratio
 204  * @main_vratio:        the main scaler's vertical ratio
 205  * @real_width:         source pixel (width - offset)
 206  * @real_height:        source pixel (height - offset)
 207  */
 208 struct fimc_scaler {
 209         unsigned int scaleup_h:1;
 210         unsigned int scaleup_v:1;
 211         unsigned int copy_mode:1;
 212         unsigned int enabled:1;
 213         u32     hfactor;
 214         u32     vfactor;
 215         u32     pre_hratio;
 216         u32     pre_vratio;
 217         u32     pre_dst_width;
 218         u32     pre_dst_height;
 219         u32     main_hratio;
 220         u32     main_vratio;
 221         u32     real_width;
 222         u32     real_height;
 223 };
 224
 225 /**
 226  * struct fimc_addr - the FIMC physical address set for DMA
 227  * @y:   luminance plane physical address
 228  * @cb:  Cb plane physical address
 229  * @cr:  Cr plane physical address
 230  */
 231 struct fimc_addr {
 232         u32     y;
 233         u32     cb;
 234         u32     cr;
 235 };
 236
 237 /**
 238  * struct fimc_vid_buffer - the driver's video buffer
 239  * @vb:    v4l videobuf buffer
 240  * @list:  linked list structure for buffer queue
 241  * @paddr: precalculated physical address set
 242  * @index: buffer index for the output DMA engine
 243  */
 244 struct fimc_vid_buffer {
 245         struct vb2_buffer       vb;
 246         struct list_head        list;
 247         struct fimc_addr        paddr;
 248         int                     index;
 249 };
 250
 251 /**
 252  * struct fimc_frame - source/target frame properties
 253  * @f_width:    image full width (virtual screen size)
 254  * @f_height:   image full height (virtual screen size)
 255  * @o_width:    original image width as set by S_FMT
 256  * @o_height:   original image height as set by S_FMT
 257  * @offs_h:     image horizontal pixel offset
 258  * @offs_v:     image vertical pixel offset
 259  * @width:      image pixel width
 260  * @height:     image pixel weight
 261  * @payload:    image size in bytes (w x h x bpp)
 262  * @paddr:      image frame buffer physical addresses
 263  * @dma_offset: DMA offset in bytes
 264  * @fmt:        fimc color format pointer
 265  */
 266 struct fimc_frame {
 267         u32     f_width;
 268         u32     f_height;
 269         u32     o_width;
 270         u32     o_height;
 271         u32     offs_h;
 272         u32     offs_v;
 273         u32     width;
 274         u32     height;
 275         unsigned long           payload[VIDEO_MAX_PLANES];
 276         struct fimc_addr        paddr;
 277         struct fimc_dma_offset  dma_offset;
 278         struct fimc_fmt         *fmt;
 279 };
 280
 281 /**
 282  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 283  * @vfd: the video device node for v4l2 m2m mode
 284  * @m2m_dev: v4l2 memory-to-memory device data
 285  * @ctx: hardware context data
 286  * @refcnt: the reference counter
 287  */
 288 struct fimc_m2m_device {
 289         struct video_device     *vfd;
 290         struct v4l2_m2m_dev     *m2m_dev;
 291         struct fimc_ctx         *ctx;
 292         int                     refcnt;
 293 };
 294
 295 /**
 296  * struct fimc_vid_cap - camera capture device information
 297  * @ctx: hardware context data
 298  * @vfd: video device node for camera capture mode
 299  * @sd: pointer to camera sensor subdevice currently in use
 300  * @vd_pad: fimc video capture node pad
 301  * @fmt: Media Bus format configured at selected image sensor
 302  * @pending_buf_q: the pending buffer queue head
 303  * @active_buf_q: the queue head of buffers scheduled in hardware
 304  * @vbq: the capture am video buffer queue
 305  * @active_buf_cnt: number of video buffers scheduled in hardware
 306  * @buf_index: index for managing the output DMA buffers
 307  * @frame_count: the frame counter for statistics
 308  * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
 309  * @input_index: input (camera sensor) index
 310  * @refcnt: driver's private reference counter
 311  * @user_subdev_api: true if subdevs are not configured by the host driver
 312  */
 313 struct fimc_vid_cap {
 314         struct fimc_ctx                 *ctx;
 315         struct vb2_alloc_ctx            *alloc_ctx;
 316         struct video_device             *vfd;
 317         struct v4l2_subdev              *sd;;
 318         struct media_pad                vd_pad;
 319         struct v4l2_mbus_framefmt       fmt;
 320         struct list_head                pending_buf_q;
 321         struct list_head                active_buf_q;
 322         struct vb2_queue                vbq;
 323         int                             active_buf_cnt;
 324         int                             buf_index;
 325         unsigned int                    frame_count;
 326         unsigned int                    reqbufs_count;
 327         int                             input_index;
 328         int                             refcnt;
 329         bool                            user_subdev_api;
 330 };
 331
 332 /**
 333  *  struct fimc_pix_limit - image pixel size limits in various IP configurations
 334  *
 335  *  @scaler_en_w: max input pixel width when the scaler is enabled
 336  *  @scaler_dis_w: max input pixel width when the scaler is disabled
 337  *  @in_rot_en_h: max input width with the input rotator is on
 338  *  @in_rot_dis_w: max input width with the input rotator is off
 339  *  @out_rot_en_w: max output width with the output rotator on
 340  *  @out_rot_dis_w: max output width with the output rotator off
 341  */
 342 struct fimc_pix_limit {
 343         u16 scaler_en_w;
 344         u16 scaler_dis_w;
 345         u16 in_rot_en_h;
 346         u16 in_rot_dis_w;
 347         u16 out_rot_en_w;
 348         u16 out_rot_dis_w;
 349 };
 350
 351 /**
 352  * struct samsung_fimc_variant - camera interface variant information
 353  *
 354  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 355  * @has_inp_rot: set if has input rotator
 356  * @has_out_rot: set if has output rotator
 357  * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
 358  * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
 359  *                       are present in this IP revision
 360  * @has_cam_if: set if this instance has a camera input interface
 361  * @pix_limit: pixel size constraints for the scaler
 362  * @min_inp_pixsize: minimum input pixel size
 363  * @min_out_pixsize: minimum output pixel size
 364  * @hor_offs_align: horizontal pixel offset aligment
 365  * @out_buf_count: the number of buffers in output DMA sequence
 366  */
 367 struct samsung_fimc_variant {
 368         unsigned int    pix_hoff:1;
 369         unsigned int    has_inp_rot:1;
 370         unsigned int    has_out_rot:1;
 371         unsigned int    has_cistatus2:1;
 372         unsigned int    has_mainscaler_ext:1;
 373         unsigned int    has_cam_if:1;
 374         struct fimc_pix_limit *pix_limit;
 375         u16             min_inp_pixsize;
 376         u16             min_out_pixsize;
 377         u16             hor_offs_align;
 378         u16             out_buf_count;
 379 };
 380
 381 /**
 382  * struct samsung_fimc_driverdata - per device type driver data for init time.
 383  *
 384  * @variant: the variant information for this driver.
 385  * @dev_cnt: number of fimc sub-devices available in SoC
 386  * @lclk_frequency: fimc bus clock frequency
 387  */
 388 struct samsung_fimc_driverdata {
 389         struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
 390         unsigned long   lclk_frequency;
 391         int             num_entities;
 392 };
 393
 394 struct fimc_pipeline {
 395         struct media_pipeline *pipe;
 396         struct v4l2_subdev *sensor;
 397         struct v4l2_subdev *csis;
 398 };
 399
 400 struct fimc_ctx;
 401
 402 /**
 403  * struct fimc_dev - abstraction for FIMC entity
 404  * @slock:      the spinlock protecting this data structure
 405  * @lock:       the mutex protecting this data structure
 406  * @pdev:       pointer to the FIMC platform device
 407  * @pdata:      pointer to the device platform data
 408  * @variant:    the IP variant information
 409  * @id:         FIMC device index (0..FIMC_MAX_DEVS)
 410  * @num_clocks: the number of clocks managed by this device instance
 411  * @clock:      clocks required for FIMC operation
 412  * @regs:       the mapped hardware registers
 413  * @regs_res:   the resource claimed for IO registers
 414  * @irq:        FIMC interrupt number
 415  * @irq_queue:  interrupt handler waitqueue
 416  * @v4l2_dev:   root v4l2_device
 417  * @m2m:        memory-to-memory V4L2 device information
 418  * @vid_cap:    camera capture device information
 419  * @state:      flags used to synchronize m2m and capture mode operation
 420  * @alloc_ctx:  videobuf2 memory allocator context
 421  * @pipeline:   fimc video capture pipeline data structure
 422  */
 423 struct fimc_dev {
 424         spinlock_t                      slock;
 425         struct mutex                    lock;
 426         struct platform_device          *pdev;
 427         struct s5p_platform_fimc        *pdata;
 428         struct samsung_fimc_variant     *variant;
 429         u16                             id;
 430         u16                             num_clocks;
 431         struct clk                      *clock[MAX_FIMC_CLOCKS];
 432         void __iomem                    *regs;
 433         struct resource                 *regs_res;
 434         int                             irq;
 435         wait_queue_head_t               irq_queue;
 436         struct v4l2_device              *v4l2_dev;
 437         struct fimc_m2m_device          m2m;
 438         struct fimc_vid_cap             vid_cap;
 439         unsigned long                   state;
 440         struct vb2_alloc_ctx            *alloc_ctx;
 441         struct fimc_pipeline            pipeline;
 442 };
 443
 444 /**
 445  * fimc_ctx - the device context data
 446  * @slock:              spinlock protecting this data structure
 447  * @s_frame:            source frame properties
 448  * @d_frame:            destination frame properties
 449  * @out_order_1p:       output 1-plane YCBCR order
 450  * @out_order_2p:       output 2-plane YCBCR order
 451  * @in_order_1p         input 1-plane YCBCR order
 452  * @in_order_2p:        input 2-plane YCBCR order
 453  * @in_path:            input mode (DMA or camera)
 454  * @out_path:           output mode (DMA or FIFO)
 455  * @scaler:             image scaler properties
 456  * @effect:             image effect
 457  * @rotation:           image clockwise rotation in degrees
 458  * @flip:               image flip mode
 459  * @flags:              additional flags for image conversion
 460  * @state:              flags to keep track of user configuration
 461  * @fimc_dev:           the FIMC device this context applies to
 462  * @m2m_ctx:            memory-to-memory device context
 463  * @fh:                 v4l2 file handle
 464  */
 465 struct fimc_ctx {
 466         spinlock_t              slock;
 467         struct fimc_frame       s_frame;
 468         struct fimc_frame       d_frame;
 469         u32                     out_order_1p;
 470         u32                     out_order_2p;
 471         u32                     in_order_1p;
 472         u32                     in_order_2p;
 473         enum fimc_datapath      in_path;
 474         enum fimc_datapath      out_path;
 475         struct fimc_scaler      scaler;
 476         struct fimc_effect      effect;
 477         int                     rotation;
 478         u32                     flip;
 479         u32                     flags;
 480         u32                     state;
 481         struct fimc_dev         *fimc_dev;
 482         struct v4l2_m2m_ctx     *m2m_ctx;
 483         struct v4l2_fh          fh;
 484 };
 485
 486 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
 487
 488 static inline bool fimc_capture_active(struct fimc_dev *fimc)
 489 {
 490         unsigned long flags;
 491         bool ret;
 492
 493         spin_lock_irqsave(&fimc->slock, flags);
 494         ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
 495                  fimc->state & (1 << ST_CAPT_PEND));
 496         spin_unlock_irqrestore(&fimc->slock, flags);
 497         return ret;
 498 }
 499
 500 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
 501 {
 502         unsigned long flags;
 503
 504         spin_lock_irqsave(&ctx->slock, flags);
 505         ctx->state |= state;
 506         spin_unlock_irqrestore(&ctx->slock, flags);
 507 }
 508
 509 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
 510 {
 511         unsigned long flags;
 512         bool ret;
 513
 514         spin_lock_irqsave(&ctx->slock, flags);
 515         ret = (ctx->state & mask) == mask;
 516         spin_unlock_irqrestore(&ctx->slock, flags);
 517         return ret;
 518 }
 519
 520 static inline int tiled_fmt(struct fimc_fmt *fmt)
 521 {
 522         return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
 523 }
 524
 525 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
 526 {
 527         u32 cfg = readl(dev->regs + S5P_CIGCTRL);
 528         cfg |= S5P_CIGCTRL_IRQ_CLR;
 529         writel(cfg, dev->regs + S5P_CIGCTRL);
 530 }
 531
 532 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
 533 {
 534         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 535         if (on)
 536                 cfg |= S5P_CISCCTRL_SCALERSTART;
 537         else
 538                 cfg &= ~S5P_CISCCTRL_SCALERSTART;
 539         writel(cfg, dev->regs + S5P_CISCCTRL);
 540 }
 541
 542 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
 543 {
 544         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 545         if (on)
 546                 cfg |= S5P_MSCTRL_ENVID;
 547         else
 548                 cfg &= ~S5P_MSCTRL_ENVID;
 549         writel(cfg, dev->regs + S5P_MSCTRL);
 550 }
 551
 552 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 553 {
 554         u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
 555         cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
 556         writel(cfg, dev->regs + S5P_CIIMGCPT);
 557 }
 558
 559 /**
 560  * fimc_hw_set_dma_seq - configure output DMA buffer sequence
 561  * @mask: each bit corresponds to one of 32 output buffer registers set
 562  *        1 to include buffer in the sequence, 0 to disable
 563  *
 564  * This function mask output DMA ring buffers, i.e. it allows to configure
 565  * which of the output buffer address registers will be used by the DMA
 566  * engine.
 567  */
 568 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
 569 {
 570         writel(mask, dev->regs + S5P_CIFCNTSEQ);
 571 }
 572
 573 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
 574                                                enum v4l2_buf_type type)
 575 {
 576         struct fimc_frame *frame;
 577
 578         if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
 579                 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
 580                         frame = &ctx->s_frame;
 581                 else
 582                         return ERR_PTR(-EINVAL);
 583         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
 584                 frame = &ctx->d_frame;
 585         } else {
 586                 v4l2_err(ctx->fimc_dev->v4l2_dev,
 587                         "Wrong buffer/video queue type (%d)\n", type);
 588                 return ERR_PTR(-EINVAL);
 589         }
 590
 591         return frame;
 592 }
 593
 594 /* Return an index to the buffer actually being written. */
 595 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
 596 {
 597         u32 reg;
 598
 599         if (dev->variant->has_cistatus2) {
 600                 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
 601                 return reg > 0 ? --reg : reg;
 602         } else {
 603                 reg = readl(dev->regs + S5P_CISTATUS);
 604                 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
 605                         S5P_CISTATUS_FRAMECNT_SHIFT;
 606         }
 607 }
 608
 609 /* -----------------------------------------------------*/
 610 /* fimc-reg.c                                           */
 611 void fimc_hw_reset(struct fimc_dev *fimc);
 612 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 613 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 614 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
 615 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
 616 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
 617 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
 618 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
 619 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 620 void fimc_hw_set_effect(struct fimc_ctx *ctx);
 621 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 622 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 623 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 624 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
 625 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
 626                              int index);
 627 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 628                               struct s5p_fimc_isp_info *cam);
 629 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
 630 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 631                                 struct s5p_fimc_isp_info *cam);
 632 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 633                             struct s5p_fimc_isp_info *cam);
 634
 635 /* -----------------------------------------------------*/
 636 /* fimc-core.c */
 637 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
 638                                 struct v4l2_fmtdesc *f);
 639 int fimc_vidioc_queryctrl(struct file *file, void *priv,
 640                           struct v4l2_queryctrl *qc);
 641 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
 642                        struct v4l2_control *ctrl);
 643
 644 int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f);
 645 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
 646 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl);
 647 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
 648 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
 649
 650 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
 651 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 652                                   unsigned int mask);
 653
 654 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
 655 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 656 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 657 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 658                       struct fimc_frame *frame, struct fimc_addr *paddr);
 659 int fimc_register_m2m_device(struct fimc_dev *fimc,
 660                              struct v4l2_device *v4l2_dev);
 661 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
 662 int fimc_register_driver(void);
 663 void fimc_unregister_driver(void);
 664
 665 /* -----------------------------------------------------*/
 666 /* fimc-capture.c                                       */
 667 int fimc_register_capture_device(struct fimc_dev *fimc,
 668                                  struct v4l2_device *v4l2_dev);
 669 void fimc_unregister_capture_device(struct fimc_dev *fimc);
 670 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
 671                              struct fimc_vid_buffer *fimc_vb);
 672 int fimc_capture_suspend(struct fimc_dev *fimc);
 673 int fimc_capture_resume(struct fimc_dev *fimc);
 674
 675 /* Locking: the caller holds fimc->slock */
 676 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
 677 {
 678         fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
 679         fimc_hw_en_capture(ctx);
 680 }
 681
 682 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
 683 {
 684         fimc_hw_en_lastirq(fimc, true);
 685         fimc_hw_dis_capture(fimc);
 686         fimc_hw_enable_scaler(fimc, false);
 687         fimc_hw_en_lastirq(fimc, false);
 688 }
 689
 690 /*
 691  * Add buf to the capture active buffers queue.
 692  * Locking: Need to be called with fimc_dev::slock held.
 693  */
 694 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
 695                                     struct fimc_vid_buffer *buf)
 696 {
 697         list_add_tail(&buf->list, &vid_cap->active_buf_q);
 698         vid_cap->active_buf_cnt++;
 699 }
 700
 701 /*
 702  * Pop a video buffer from the capture active buffers queue
 703  * Locking: Need to be called with fimc_dev::slock held.
 704  */
 705 static inline struct fimc_vid_buffer *
 706 active_queue_pop(struct fimc_vid_cap *vid_cap)
 707 {
 708         struct fimc_vid_buffer *buf;
 709         buf = list_entry(vid_cap->active_buf_q.next,
 710                          struct fimc_vid_buffer, list);
 711         list_del(&buf->list);
 712         vid_cap->active_buf_cnt--;
 713         return buf;
 714 }
 715
 716 /* Add video buffer to the capture pending buffers queue */
 717 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
 718                                           struct fimc_vid_buffer *buf)
 719 {
 720         list_add_tail(&buf->list, &vid_cap->pending_buf_q);
 721 }
 722
 723 /* Add video buffer to the capture pending buffers queue */
 724 static inline struct fimc_vid_buffer *
 725 pending_queue_pop(struct fimc_vid_cap *vid_cap)
 726 {
 727         struct fimc_vid_buffer *buf;
 728         buf = list_entry(vid_cap->pending_buf_q.next,
 729                         struct fimc_vid_buffer, list);
 730         list_del(&buf->list);
 731         return buf;
 732 }
 733
 734 #endif /* FIMC_CORE_H_ */