2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug
= -1;
75 static DEFINE_SPINLOCK(ioapic_lock
);
76 static DEFINE_SPINLOCK(vector_lock
);
79 * # of IRQ routing registers
81 int nr_ioapic_registers
[MAX_IO_APICS
];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
97 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
99 int skip_ioapic_setup
;
101 void arch_disable_smp_support(void)
105 noioapicreroute
= -1;
107 skip_ioapic_setup
= 1;
110 static int __init
parse_noapic(char *str
)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic
);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list
{
129 struct irq_pin_list
*next
;
132 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
134 struct irq_pin_list
*pin
;
136 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
142 struct irq_pin_list
*irq_2_pin
;
143 cpumask_var_t domain
;
144 cpumask_var_t old_domain
;
145 unsigned move_cleanup_count
;
147 u8 move_in_progress
: 1;
150 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
151 #ifdef CONFIG_SPARSE_IRQ
152 static struct irq_cfg irq_cfgx
[] = {
154 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
156 [0] = { .vector
= IRQ0_VECTOR
, },
157 [1] = { .vector
= IRQ1_VECTOR
, },
158 [2] = { .vector
= IRQ2_VECTOR
, },
159 [3] = { .vector
= IRQ3_VECTOR
, },
160 [4] = { .vector
= IRQ4_VECTOR
, },
161 [5] = { .vector
= IRQ5_VECTOR
, },
162 [6] = { .vector
= IRQ6_VECTOR
, },
163 [7] = { .vector
= IRQ7_VECTOR
, },
164 [8] = { .vector
= IRQ8_VECTOR
, },
165 [9] = { .vector
= IRQ9_VECTOR
, },
166 [10] = { .vector
= IRQ10_VECTOR
, },
167 [11] = { .vector
= IRQ11_VECTOR
, },
168 [12] = { .vector
= IRQ12_VECTOR
, },
169 [13] = { .vector
= IRQ13_VECTOR
, },
170 [14] = { .vector
= IRQ14_VECTOR
, },
171 [15] = { .vector
= IRQ15_VECTOR
, },
174 int __init
arch_early_irq_init(void)
177 struct irq_desc
*desc
;
182 count
= ARRAY_SIZE(irq_cfgx
);
184 for (i
= 0; i
< count
; i
++) {
185 desc
= irq_to_desc(i
);
186 desc
->chip_data
= &cfg
[i
];
187 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
188 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
189 if (i
< NR_IRQS_LEGACY
)
190 cpumask_setall(cfg
[i
].domain
);
196 #ifdef CONFIG_SPARSE_IRQ
197 static struct irq_cfg
*irq_cfg(unsigned int irq
)
199 struct irq_cfg
*cfg
= NULL
;
200 struct irq_desc
*desc
;
202 desc
= irq_to_desc(irq
);
204 cfg
= desc
->chip_data
;
209 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
213 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
215 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
218 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
220 free_cpumask_var(cfg
->domain
);
224 cpumask_clear(cfg
->domain
);
225 cpumask_clear(cfg
->old_domain
);
232 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
236 cfg
= desc
->chip_data
;
238 desc
->chip_data
= get_one_free_irq_cfg(node
);
239 if (!desc
->chip_data
) {
240 printk(KERN_ERR
"can not alloc irq_cfg\n");
248 /* for move_irq_desc */
250 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
252 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
254 cfg
->irq_2_pin
= NULL
;
255 old_entry
= old_cfg
->irq_2_pin
;
259 entry
= get_one_free_irq_2_pin(node
);
263 entry
->apic
= old_entry
->apic
;
264 entry
->pin
= old_entry
->pin
;
267 old_entry
= old_entry
->next
;
269 entry
= get_one_free_irq_2_pin(node
);
277 /* still use the old one */
280 entry
->apic
= old_entry
->apic
;
281 entry
->pin
= old_entry
->pin
;
284 old_entry
= old_entry
->next
;
288 cfg
->irq_2_pin
= head
;
291 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
293 struct irq_pin_list
*entry
, *next
;
295 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
298 entry
= old_cfg
->irq_2_pin
;
305 old_cfg
->irq_2_pin
= NULL
;
308 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
309 struct irq_desc
*desc
, int node
)
312 struct irq_cfg
*old_cfg
;
314 cfg
= get_one_free_irq_cfg(node
);
319 desc
->chip_data
= cfg
;
321 old_cfg
= old_desc
->chip_data
;
323 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
325 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
328 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
333 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
335 struct irq_cfg
*old_cfg
, *cfg
;
337 old_cfg
= old_desc
->chip_data
;
338 cfg
= desc
->chip_data
;
344 free_irq_2_pin(old_cfg
, cfg
);
345 free_irq_cfg(old_cfg
);
346 old_desc
->chip_data
= NULL
;
349 /* end for move_irq_desc */
352 static struct irq_cfg
*irq_cfg(unsigned int irq
)
354 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
361 unsigned int unused
[3];
363 unsigned int unused2
[11];
367 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
369 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
370 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
373 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
375 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
376 writel(vector
, &io_apic
->eoi
);
379 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
381 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
382 writel(reg
, &io_apic
->index
);
383 return readl(&io_apic
->data
);
386 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
388 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
389 writel(reg
, &io_apic
->index
);
390 writel(value
, &io_apic
->data
);
394 * Re-write a value: to be used for read-modify-write
395 * cycles where the read already set up the index register.
397 * Older SiS APIC requires we rewrite the index register
399 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
401 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
404 writel(reg
, &io_apic
->index
);
405 writel(value
, &io_apic
->data
);
408 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
410 struct irq_pin_list
*entry
;
413 spin_lock_irqsave(&ioapic_lock
, flags
);
414 entry
= cfg
->irq_2_pin
;
422 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
423 /* Is the remote IRR bit set? */
424 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
425 spin_unlock_irqrestore(&ioapic_lock
, flags
);
432 spin_unlock_irqrestore(&ioapic_lock
, flags
);
438 struct { u32 w1
, w2
; };
439 struct IO_APIC_route_entry entry
;
442 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
444 union entry_union eu
;
446 spin_lock_irqsave(&ioapic_lock
, flags
);
447 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
448 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
449 spin_unlock_irqrestore(&ioapic_lock
, flags
);
454 * When we write a new IO APIC routing entry, we need to write the high
455 * word first! If the mask bit in the low word is clear, we will enable
456 * the interrupt, and we need to make sure the entry is fully populated
457 * before that happens.
460 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
462 union entry_union eu
;
464 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
465 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
468 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
471 spin_lock_irqsave(&ioapic_lock
, flags
);
472 __ioapic_write_entry(apic
, pin
, e
);
473 spin_unlock_irqrestore(&ioapic_lock
, flags
);
477 * When we mask an IO APIC routing entry, we need to write the low
478 * word first, in order to set the mask bit before we change the
481 static void ioapic_mask_entry(int apic
, int pin
)
484 union entry_union eu
= { .entry
.mask
= 1 };
486 spin_lock_irqsave(&ioapic_lock
, flags
);
487 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
488 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
489 spin_unlock_irqrestore(&ioapic_lock
, flags
);
493 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
494 * shared ISA-space IRQs, so we have to support them. We are super
495 * fast in the common case, and fast for shared ISA-space IRQs.
497 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
499 struct irq_pin_list
*entry
;
501 entry
= cfg
->irq_2_pin
;
503 entry
= get_one_free_irq_2_pin(node
);
505 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
509 cfg
->irq_2_pin
= entry
;
515 while (entry
->next
) {
516 /* not again, please */
517 if (entry
->apic
== apic
&& entry
->pin
== pin
)
523 entry
->next
= get_one_free_irq_2_pin(node
);
530 * Reroute an IRQ to a different pin.
532 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
533 int oldapic
, int oldpin
,
534 int newapic
, int newpin
)
536 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
540 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
541 entry
->apic
= newapic
;
544 /* every one is different, right? */
550 /* why? call replace before add? */
552 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
555 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
556 int mask_and
, int mask_or
,
557 void (*final
)(struct irq_pin_list
*entry
))
560 struct irq_pin_list
*entry
;
562 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
565 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
568 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
574 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
576 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
580 static void io_apic_sync(struct irq_pin_list
*entry
)
583 * Synchronize the IO-APIC and the CPU by doing
584 * a dummy read from the IO-APIC
586 struct io_apic __iomem
*io_apic
;
587 io_apic
= io_apic_base(entry
->apic
);
588 readl(&io_apic
->data
);
591 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
593 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
595 #else /* CONFIG_X86_32 */
596 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
598 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
601 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
603 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
604 IO_APIC_REDIR_MASKED
, NULL
);
607 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
609 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
610 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
612 #endif /* CONFIG_X86_32 */
614 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
616 struct irq_cfg
*cfg
= desc
->chip_data
;
621 spin_lock_irqsave(&ioapic_lock
, flags
);
622 __mask_IO_APIC_irq(cfg
);
623 spin_unlock_irqrestore(&ioapic_lock
, flags
);
626 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
628 struct irq_cfg
*cfg
= desc
->chip_data
;
631 spin_lock_irqsave(&ioapic_lock
, flags
);
632 __unmask_IO_APIC_irq(cfg
);
633 spin_unlock_irqrestore(&ioapic_lock
, flags
);
636 static void mask_IO_APIC_irq(unsigned int irq
)
638 struct irq_desc
*desc
= irq_to_desc(irq
);
640 mask_IO_APIC_irq_desc(desc
);
642 static void unmask_IO_APIC_irq(unsigned int irq
)
644 struct irq_desc
*desc
= irq_to_desc(irq
);
646 unmask_IO_APIC_irq_desc(desc
);
649 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
651 struct IO_APIC_route_entry entry
;
653 /* Check delivery_mode to be sure we're not clearing an SMI pin */
654 entry
= ioapic_read_entry(apic
, pin
);
655 if (entry
.delivery_mode
== dest_SMI
)
658 * Disable it in the IO-APIC irq-routing table:
660 ioapic_mask_entry(apic
, pin
);
663 static void clear_IO_APIC (void)
667 for (apic
= 0; apic
< nr_ioapics
; apic
++)
668 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
669 clear_IO_APIC_pin(apic
, pin
);
674 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
675 * specific CPU-side IRQs.
679 static int pirq_entries
[MAX_PIRQS
] = {
680 [0 ... MAX_PIRQS
- 1] = -1
683 static int __init
ioapic_pirq_setup(char *str
)
686 int ints
[MAX_PIRQS
+1];
688 get_options(str
, ARRAY_SIZE(ints
), ints
);
690 apic_printk(APIC_VERBOSE
, KERN_INFO
691 "PIRQ redirection, working around broken MP-BIOS.\n");
693 if (ints
[0] < MAX_PIRQS
)
696 for (i
= 0; i
< max
; i
++) {
697 apic_printk(APIC_VERBOSE
, KERN_DEBUG
698 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
700 * PIRQs are mapped upside down, usually.
702 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
707 __setup("pirq=", ioapic_pirq_setup
);
708 #endif /* CONFIG_X86_32 */
710 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
713 struct IO_APIC_route_entry
**ioapic_entries
;
715 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
720 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
721 ioapic_entries
[apic
] =
722 kzalloc(sizeof(struct IO_APIC_route_entry
) *
723 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
724 if (!ioapic_entries
[apic
])
728 return ioapic_entries
;
732 kfree(ioapic_entries
[apic
]);
733 kfree(ioapic_entries
);
739 * Saves all the IO-APIC RTE's
741 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
748 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
749 if (!ioapic_entries
[apic
])
752 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
753 ioapic_entries
[apic
][pin
] =
754 ioapic_read_entry(apic
, pin
);
761 * Mask all IO APIC entries.
763 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
770 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
771 if (!ioapic_entries
[apic
])
774 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
775 struct IO_APIC_route_entry entry
;
777 entry
= ioapic_entries
[apic
][pin
];
780 ioapic_write_entry(apic
, pin
, entry
);
787 * Restore IO APIC entries which was saved in ioapic_entries.
789 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
796 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
797 if (!ioapic_entries
[apic
])
800 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
801 ioapic_write_entry(apic
, pin
,
802 ioapic_entries
[apic
][pin
]);
807 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
811 for (apic
= 0; apic
< nr_ioapics
; apic
++)
812 kfree(ioapic_entries
[apic
]);
814 kfree(ioapic_entries
);
818 * Find the IRQ entry number of a certain pin.
820 static int find_irq_entry(int apic
, int pin
, int type
)
824 for (i
= 0; i
< mp_irq_entries
; i
++)
825 if (mp_irqs
[i
].irqtype
== type
&&
826 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
827 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
828 mp_irqs
[i
].dstirq
== pin
)
835 * Find the pin to which IRQ[irq] (ISA) is connected
837 static int __init
find_isa_irq_pin(int irq
, int type
)
841 for (i
= 0; i
< mp_irq_entries
; i
++) {
842 int lbus
= mp_irqs
[i
].srcbus
;
844 if (test_bit(lbus
, mp_bus_not_pci
) &&
845 (mp_irqs
[i
].irqtype
== type
) &&
846 (mp_irqs
[i
].srcbusirq
== irq
))
848 return mp_irqs
[i
].dstirq
;
853 static int __init
find_isa_irq_apic(int irq
, int type
)
857 for (i
= 0; i
< mp_irq_entries
; i
++) {
858 int lbus
= mp_irqs
[i
].srcbus
;
860 if (test_bit(lbus
, mp_bus_not_pci
) &&
861 (mp_irqs
[i
].irqtype
== type
) &&
862 (mp_irqs
[i
].srcbusirq
== irq
))
865 if (i
< mp_irq_entries
) {
867 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
868 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
876 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
878 * EISA Edge/Level control register, ELCR
880 static int EISA_ELCR(unsigned int irq
)
882 if (irq
< NR_IRQS_LEGACY
) {
883 unsigned int port
= 0x4d0 + (irq
>> 3);
884 return (inb(port
) >> (irq
& 7)) & 1;
886 apic_printk(APIC_VERBOSE
, KERN_INFO
887 "Broken MPtable reports ISA irq %d\n", irq
);
893 /* ISA interrupts are always polarity zero edge triggered,
894 * when listed as conforming in the MP table. */
896 #define default_ISA_trigger(idx) (0)
897 #define default_ISA_polarity(idx) (0)
899 /* EISA interrupts are always polarity zero and can be edge or level
900 * trigger depending on the ELCR value. If an interrupt is listed as
901 * EISA conforming in the MP table, that means its trigger type must
902 * be read in from the ELCR */
904 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
905 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
907 /* PCI interrupts are always polarity one level triggered,
908 * when listed as conforming in the MP table. */
910 #define default_PCI_trigger(idx) (1)
911 #define default_PCI_polarity(idx) (1)
913 /* MCA interrupts are always polarity zero level triggered,
914 * when listed as conforming in the MP table. */
916 #define default_MCA_trigger(idx) (1)
917 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
919 static int MPBIOS_polarity(int idx
)
921 int bus
= mp_irqs
[idx
].srcbus
;
925 * Determine IRQ line polarity (high active or low active):
927 switch (mp_irqs
[idx
].irqflag
& 3)
929 case 0: /* conforms, ie. bus-type dependent polarity */
930 if (test_bit(bus
, mp_bus_not_pci
))
931 polarity
= default_ISA_polarity(idx
);
933 polarity
= default_PCI_polarity(idx
);
935 case 1: /* high active */
940 case 2: /* reserved */
942 printk(KERN_WARNING
"broken BIOS!!\n");
946 case 3: /* low active */
951 default: /* invalid */
953 printk(KERN_WARNING
"broken BIOS!!\n");
961 static int MPBIOS_trigger(int idx
)
963 int bus
= mp_irqs
[idx
].srcbus
;
967 * Determine IRQ trigger mode (edge or level sensitive):
969 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
971 case 0: /* conforms, ie. bus-type dependent */
972 if (test_bit(bus
, mp_bus_not_pci
))
973 trigger
= default_ISA_trigger(idx
);
975 trigger
= default_PCI_trigger(idx
);
976 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
977 switch (mp_bus_id_to_type
[bus
]) {
978 case MP_BUS_ISA
: /* ISA pin */
980 /* set before the switch */
983 case MP_BUS_EISA
: /* EISA pin */
985 trigger
= default_EISA_trigger(idx
);
988 case MP_BUS_PCI
: /* PCI pin */
990 /* set before the switch */
993 case MP_BUS_MCA
: /* MCA pin */
995 trigger
= default_MCA_trigger(idx
);
1000 printk(KERN_WARNING
"broken BIOS!!\n");
1012 case 2: /* reserved */
1014 printk(KERN_WARNING
"broken BIOS!!\n");
1023 default: /* invalid */
1025 printk(KERN_WARNING
"broken BIOS!!\n");
1033 static inline int irq_polarity(int idx
)
1035 return MPBIOS_polarity(idx
);
1038 static inline int irq_trigger(int idx
)
1040 return MPBIOS_trigger(idx
);
1043 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1044 static int pin_2_irq(int idx
, int apic
, int pin
)
1047 int bus
= mp_irqs
[idx
].srcbus
;
1050 * Debugging check, we are in big trouble if this message pops up!
1052 if (mp_irqs
[idx
].dstirq
!= pin
)
1053 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1055 if (test_bit(bus
, mp_bus_not_pci
)) {
1056 irq
= mp_irqs
[idx
].srcbusirq
;
1059 * PCI IRQs are mapped in order
1063 irq
+= nr_ioapic_registers
[i
++];
1066 * For MPS mode, so far only needed by ES7000 platform
1068 if (ioapic_renumber_irq
)
1069 irq
= ioapic_renumber_irq(apic
, irq
);
1072 #ifdef CONFIG_X86_32
1074 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1076 if ((pin
>= 16) && (pin
<= 23)) {
1077 if (pirq_entries
[pin
-16] != -1) {
1078 if (!pirq_entries
[pin
-16]) {
1079 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1080 "disabling PIRQ%d\n", pin
-16);
1082 irq
= pirq_entries
[pin
-16];
1083 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1084 "using PIRQ%d -> IRQ %d\n",
1095 * Find a specific PCI IRQ entry.
1096 * Not an __init, possibly needed by modules
1098 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1099 struct io_apic_irq_attr
*irq_attr
)
1101 int apic
, i
, best_guess
= -1;
1103 apic_printk(APIC_DEBUG
,
1104 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1106 if (test_bit(bus
, mp_bus_not_pci
)) {
1107 apic_printk(APIC_VERBOSE
,
1108 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1111 for (i
= 0; i
< mp_irq_entries
; i
++) {
1112 int lbus
= mp_irqs
[i
].srcbus
;
1114 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1115 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1116 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1119 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1120 !mp_irqs
[i
].irqtype
&&
1122 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1123 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1125 if (!(apic
|| IO_APIC_IRQ(irq
)))
1128 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1129 set_io_apic_irq_attr(irq_attr
, apic
,
1136 * Use the first all-but-pin matching entry as a
1137 * best-guess fuzzy result for broken mptables.
1139 if (best_guess
< 0) {
1140 set_io_apic_irq_attr(irq_attr
, apic
,
1150 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1152 void lock_vector_lock(void)
1154 /* Used to the online set of cpus does not change
1155 * during assign_irq_vector.
1157 spin_lock(&vector_lock
);
1160 void unlock_vector_lock(void)
1162 spin_unlock(&vector_lock
);
1166 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1169 * NOTE! The local APIC isn't very good at handling
1170 * multiple interrupts at the same interrupt level.
1171 * As the interrupt level is determined by taking the
1172 * vector number and shifting that right by 4, we
1173 * want to spread these out a bit so that they don't
1174 * all fall in the same interrupt level.
1176 * Also, we've got to be careful not to trash gate
1177 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1179 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1180 unsigned int old_vector
;
1182 cpumask_var_t tmp_mask
;
1184 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1187 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1190 old_vector
= cfg
->vector
;
1192 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1193 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1194 if (!cpumask_empty(tmp_mask
)) {
1195 free_cpumask_var(tmp_mask
);
1200 /* Only try and allocate irqs on cpus that are present */
1202 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1206 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1208 vector
= current_vector
;
1209 offset
= current_offset
;
1212 if (vector
>= first_system_vector
) {
1213 /* If out of vectors on large boxen, must share them. */
1214 offset
= (offset
+ 1) % 8;
1215 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1217 if (unlikely(current_vector
== vector
))
1220 if (test_bit(vector
, used_vectors
))
1223 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1224 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1227 current_vector
= vector
;
1228 current_offset
= offset
;
1230 cfg
->move_in_progress
= 1;
1231 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1233 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1234 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1235 cfg
->vector
= vector
;
1236 cpumask_copy(cfg
->domain
, tmp_mask
);
1240 free_cpumask_var(tmp_mask
);
1245 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1248 unsigned long flags
;
1250 spin_lock_irqsave(&vector_lock
, flags
);
1251 err
= __assign_irq_vector(irq
, cfg
, mask
);
1252 spin_unlock_irqrestore(&vector_lock
, flags
);
1256 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1260 BUG_ON(!cfg
->vector
);
1262 vector
= cfg
->vector
;
1263 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1264 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1267 cpumask_clear(cfg
->domain
);
1269 if (likely(!cfg
->move_in_progress
))
1271 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1272 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1274 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1276 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1280 cfg
->move_in_progress
= 0;
1283 void __setup_vector_irq(int cpu
)
1285 /* Initialize vector_irq on a new cpu */
1286 /* This function must be called with vector_lock held */
1288 struct irq_cfg
*cfg
;
1289 struct irq_desc
*desc
;
1291 /* Mark the inuse vectors */
1292 for_each_irq_desc(irq
, desc
) {
1293 cfg
= desc
->chip_data
;
1294 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1296 vector
= cfg
->vector
;
1297 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1299 /* Mark the free vectors */
1300 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1301 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1306 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1307 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1311 static struct irq_chip ioapic_chip
;
1312 static struct irq_chip ir_ioapic_chip
;
1314 #define IOAPIC_AUTO -1
1315 #define IOAPIC_EDGE 0
1316 #define IOAPIC_LEVEL 1
1318 #ifdef CONFIG_X86_32
1319 static inline int IO_APIC_irq_trigger(int irq
)
1323 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1324 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1325 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1326 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1327 return irq_trigger(idx
);
1331 * nonexistent IRQs are edge default
1336 static inline int IO_APIC_irq_trigger(int irq
)
1342 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1345 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1346 trigger
== IOAPIC_LEVEL
)
1347 desc
->status
|= IRQ_LEVEL
;
1349 desc
->status
&= ~IRQ_LEVEL
;
1351 if (irq_remapped(irq
)) {
1352 desc
->status
|= IRQ_MOVE_PCNTXT
;
1354 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1358 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1359 handle_edge_irq
, "edge");
1363 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1364 trigger
== IOAPIC_LEVEL
)
1365 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1369 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1370 handle_edge_irq
, "edge");
1373 int setup_ioapic_entry(int apic_id
, int irq
,
1374 struct IO_APIC_route_entry
*entry
,
1375 unsigned int destination
, int trigger
,
1376 int polarity
, int vector
, int pin
)
1379 * add it to the IO-APIC irq-routing table:
1381 memset(entry
,0,sizeof(*entry
));
1383 if (intr_remapping_enabled
) {
1384 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1386 struct IR_IO_APIC_route_entry
*ir_entry
=
1387 (struct IR_IO_APIC_route_entry
*) entry
;
1391 panic("No mapping iommu for ioapic %d\n", apic_id
);
1393 index
= alloc_irte(iommu
, irq
, 1);
1395 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1397 memset(&irte
, 0, sizeof(irte
));
1400 irte
.dst_mode
= apic
->irq_dest_mode
;
1402 * Trigger mode in the IRTE will always be edge, and the
1403 * actual level or edge trigger will be setup in the IO-APIC
1404 * RTE. This will help simplify level triggered irq migration.
1405 * For more details, see the comments above explainig IO-APIC
1406 * irq migration in the presence of interrupt-remapping.
1408 irte
.trigger_mode
= 0;
1409 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1410 irte
.vector
= vector
;
1411 irte
.dest_id
= IRTE_DEST(destination
);
1413 modify_irte(irq
, &irte
);
1415 ir_entry
->index2
= (index
>> 15) & 0x1;
1417 ir_entry
->format
= 1;
1418 ir_entry
->index
= (index
& 0x7fff);
1420 * IO-APIC RTE will be configured with virtual vector.
1421 * irq handler will do the explicit EOI to the io-apic.
1423 ir_entry
->vector
= pin
;
1425 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1426 entry
->dest_mode
= apic
->irq_dest_mode
;
1427 entry
->dest
= destination
;
1428 entry
->vector
= vector
;
1431 entry
->mask
= 0; /* enable IRQ */
1432 entry
->trigger
= trigger
;
1433 entry
->polarity
= polarity
;
1435 /* Mask level triggered irqs.
1436 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1443 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1444 int trigger
, int polarity
)
1446 struct irq_cfg
*cfg
;
1447 struct IO_APIC_route_entry entry
;
1450 if (!IO_APIC_IRQ(irq
))
1453 cfg
= desc
->chip_data
;
1455 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1458 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1460 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1461 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1462 "IRQ %d Mode:%i Active:%i)\n",
1463 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1464 irq
, trigger
, polarity
);
1467 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1468 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1469 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1470 mp_ioapics
[apic_id
].apicid
, pin
);
1471 __clear_irq_vector(irq
, cfg
);
1475 ioapic_register_intr(irq
, desc
, trigger
);
1476 if (irq
< NR_IRQS_LEGACY
)
1477 disable_8259A_irq(irq
);
1479 ioapic_write_entry(apic_id
, pin
, entry
);
1483 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1484 } mp_ioapic_routing
[MAX_IO_APICS
];
1486 static void __init
setup_IO_APIC_irqs(void)
1488 int apic_id
= 0, pin
, idx
, irq
;
1490 struct irq_desc
*desc
;
1491 struct irq_cfg
*cfg
;
1492 int node
= cpu_to_node(boot_cpu_id
);
1494 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1497 if (!acpi_disabled
&& acpi_ioapic
) {
1498 apic_id
= mp_find_ioapic(0);
1504 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1505 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1509 apic_printk(APIC_VERBOSE
,
1510 KERN_DEBUG
" %d-%d",
1511 mp_ioapics
[apic_id
].apicid
, pin
);
1513 apic_printk(APIC_VERBOSE
, " %d-%d",
1514 mp_ioapics
[apic_id
].apicid
, pin
);
1518 apic_printk(APIC_VERBOSE
,
1519 " (apicid-pin) not connected\n");
1523 irq
= pin_2_irq(idx
, apic_id
, pin
);
1526 * Skip the timer IRQ if there's a quirk handler
1527 * installed and if it returns 1:
1529 if (apic
->multi_timer_check
&&
1530 apic
->multi_timer_check(apic_id
, irq
))
1533 desc
= irq_to_desc_alloc_node(irq
, node
);
1535 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1538 cfg
= desc
->chip_data
;
1539 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1540 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1541 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1542 irq_trigger(idx
), irq_polarity(idx
));
1546 apic_printk(APIC_VERBOSE
,
1547 " (apicid-pin) not connected\n");
1551 * Set up the timer pin, possibly with the 8259A-master behind.
1553 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1556 struct IO_APIC_route_entry entry
;
1558 if (intr_remapping_enabled
)
1561 memset(&entry
, 0, sizeof(entry
));
1564 * We use logical delivery to get the timer IRQ
1567 entry
.dest_mode
= apic
->irq_dest_mode
;
1568 entry
.mask
= 0; /* don't mask IRQ for edge */
1569 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1570 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1573 entry
.vector
= vector
;
1576 * The timer IRQ doesn't have to know that behind the
1577 * scene we may have a 8259A-master in AEOI mode ...
1579 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1582 * Add it to the IO-APIC irq-routing table:
1584 ioapic_write_entry(apic_id
, pin
, entry
);
1588 __apicdebuginit(void) print_IO_APIC(void)
1591 union IO_APIC_reg_00 reg_00
;
1592 union IO_APIC_reg_01 reg_01
;
1593 union IO_APIC_reg_02 reg_02
;
1594 union IO_APIC_reg_03 reg_03
;
1595 unsigned long flags
;
1596 struct irq_cfg
*cfg
;
1597 struct irq_desc
*desc
;
1600 if (apic_verbosity
== APIC_QUIET
)
1603 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1604 for (i
= 0; i
< nr_ioapics
; i
++)
1605 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1606 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1609 * We are a bit conservative about what we expect. We have to
1610 * know about every hardware change ASAP.
1612 printk(KERN_INFO
"testing the IO APIC.......................\n");
1614 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1616 spin_lock_irqsave(&ioapic_lock
, flags
);
1617 reg_00
.raw
= io_apic_read(apic
, 0);
1618 reg_01
.raw
= io_apic_read(apic
, 1);
1619 if (reg_01
.bits
.version
>= 0x10)
1620 reg_02
.raw
= io_apic_read(apic
, 2);
1621 if (reg_01
.bits
.version
>= 0x20)
1622 reg_03
.raw
= io_apic_read(apic
, 3);
1623 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1626 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1627 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1628 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1629 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1630 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1632 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1633 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1635 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1636 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1639 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1640 * but the value of reg_02 is read as the previous read register
1641 * value, so ignore it if reg_02 == reg_01.
1643 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1644 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1645 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1649 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1650 * or reg_03, but the value of reg_0[23] is read as the previous read
1651 * register value, so ignore it if reg_03 == reg_0[12].
1653 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1654 reg_03
.raw
!= reg_01
.raw
) {
1655 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1656 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1659 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1661 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1662 " Stat Dmod Deli Vect: \n");
1664 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1665 struct IO_APIC_route_entry entry
;
1667 entry
= ioapic_read_entry(apic
, i
);
1669 printk(KERN_DEBUG
" %02x %03X ",
1674 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1679 entry
.delivery_status
,
1681 entry
.delivery_mode
,
1686 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1687 for_each_irq_desc(irq
, desc
) {
1688 struct irq_pin_list
*entry
;
1690 cfg
= desc
->chip_data
;
1691 entry
= cfg
->irq_2_pin
;
1694 printk(KERN_DEBUG
"IRQ%d ", irq
);
1696 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1699 entry
= entry
->next
;
1704 printk(KERN_INFO
".................................... done.\n");
1709 __apicdebuginit(void) print_APIC_bitfield(int base
)
1714 if (apic_verbosity
== APIC_QUIET
)
1717 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1718 for (i
= 0; i
< 8; i
++) {
1719 v
= apic_read(base
+ i
*0x10);
1720 for (j
= 0; j
< 32; j
++) {
1730 __apicdebuginit(void) print_local_APIC(void *dummy
)
1732 unsigned int i
, v
, ver
, maxlvt
;
1735 if (apic_verbosity
== APIC_QUIET
)
1738 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1739 smp_processor_id(), hard_smp_processor_id());
1740 v
= apic_read(APIC_ID
);
1741 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1742 v
= apic_read(APIC_LVR
);
1743 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1744 ver
= GET_APIC_VERSION(v
);
1745 maxlvt
= lapic_get_maxlvt();
1747 v
= apic_read(APIC_TASKPRI
);
1748 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1750 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1751 if (!APIC_XAPIC(ver
)) {
1752 v
= apic_read(APIC_ARBPRI
);
1753 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1754 v
& APIC_ARBPRI_MASK
);
1756 v
= apic_read(APIC_PROCPRI
);
1757 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1761 * Remote read supported only in the 82489DX and local APIC for
1762 * Pentium processors.
1764 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1765 v
= apic_read(APIC_RRR
);
1766 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1769 v
= apic_read(APIC_LDR
);
1770 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1771 if (!x2apic_enabled()) {
1772 v
= apic_read(APIC_DFR
);
1773 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1775 v
= apic_read(APIC_SPIV
);
1776 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1778 printk(KERN_DEBUG
"... APIC ISR field:\n");
1779 print_APIC_bitfield(APIC_ISR
);
1780 printk(KERN_DEBUG
"... APIC TMR field:\n");
1781 print_APIC_bitfield(APIC_TMR
);
1782 printk(KERN_DEBUG
"... APIC IRR field:\n");
1783 print_APIC_bitfield(APIC_IRR
);
1785 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1786 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1787 apic_write(APIC_ESR
, 0);
1789 v
= apic_read(APIC_ESR
);
1790 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1793 icr
= apic_icr_read();
1794 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1795 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1797 v
= apic_read(APIC_LVTT
);
1798 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1800 if (maxlvt
> 3) { /* PC is LVT#4. */
1801 v
= apic_read(APIC_LVTPC
);
1802 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1804 v
= apic_read(APIC_LVT0
);
1805 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1806 v
= apic_read(APIC_LVT1
);
1807 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1809 if (maxlvt
> 2) { /* ERR is LVT#3. */
1810 v
= apic_read(APIC_LVTERR
);
1811 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1814 v
= apic_read(APIC_TMICT
);
1815 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1816 v
= apic_read(APIC_TMCCT
);
1817 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1818 v
= apic_read(APIC_TDCR
);
1819 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1821 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1822 v
= apic_read(APIC_EFEAT
);
1823 maxlvt
= (v
>> 16) & 0xff;
1824 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1825 v
= apic_read(APIC_ECTRL
);
1826 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1827 for (i
= 0; i
< maxlvt
; i
++) {
1828 v
= apic_read(APIC_EILVTn(i
));
1829 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1835 __apicdebuginit(void) print_all_local_APICs(void)
1840 for_each_online_cpu(cpu
)
1841 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1845 __apicdebuginit(void) print_PIC(void)
1848 unsigned long flags
;
1850 if (apic_verbosity
== APIC_QUIET
)
1853 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1855 spin_lock_irqsave(&i8259A_lock
, flags
);
1857 v
= inb(0xa1) << 8 | inb(0x21);
1858 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1860 v
= inb(0xa0) << 8 | inb(0x20);
1861 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1865 v
= inb(0xa0) << 8 | inb(0x20);
1869 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1871 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1873 v
= inb(0x4d1) << 8 | inb(0x4d0);
1874 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1877 __apicdebuginit(int) print_all_ICs(void)
1881 /* don't print out if apic is not there */
1882 if (!cpu_has_apic
|| disable_apic
)
1885 print_all_local_APICs();
1891 fs_initcall(print_all_ICs
);
1894 /* Where if anywhere is the i8259 connect in external int mode */
1895 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1897 void __init
enable_IO_APIC(void)
1899 union IO_APIC_reg_01 reg_01
;
1900 int i8259_apic
, i8259_pin
;
1902 unsigned long flags
;
1905 * The number of IO-APIC IRQ registers (== #pins):
1907 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1908 spin_lock_irqsave(&ioapic_lock
, flags
);
1909 reg_01
.raw
= io_apic_read(apic
, 1);
1910 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1911 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1913 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1915 /* See if any of the pins is in ExtINT mode */
1916 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1917 struct IO_APIC_route_entry entry
;
1918 entry
= ioapic_read_entry(apic
, pin
);
1920 /* If the interrupt line is enabled and in ExtInt mode
1921 * I have found the pin where the i8259 is connected.
1923 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1924 ioapic_i8259
.apic
= apic
;
1925 ioapic_i8259
.pin
= pin
;
1931 /* Look to see what if the MP table has reported the ExtINT */
1932 /* If we could not find the appropriate pin by looking at the ioapic
1933 * the i8259 probably is not connected the ioapic but give the
1934 * mptable a chance anyway.
1936 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1937 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1938 /* Trust the MP table if nothing is setup in the hardware */
1939 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1940 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1941 ioapic_i8259
.pin
= i8259_pin
;
1942 ioapic_i8259
.apic
= i8259_apic
;
1944 /* Complain if the MP table and the hardware disagree */
1945 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1946 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1948 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1952 * Do not trust the IO-APIC being empty at bootup
1958 * Not an __init, needed by the reboot code
1960 void disable_IO_APIC(void)
1963 * Clear the IO-APIC before rebooting:
1968 * If the i8259 is routed through an IOAPIC
1969 * Put that IOAPIC in virtual wire mode
1970 * so legacy interrupts can be delivered.
1972 * With interrupt-remapping, for now we will use virtual wire A mode,
1973 * as virtual wire B is little complex (need to configure both
1974 * IOAPIC RTE aswell as interrupt-remapping table entry).
1975 * As this gets called during crash dump, keep this simple for now.
1977 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1978 struct IO_APIC_route_entry entry
;
1980 memset(&entry
, 0, sizeof(entry
));
1981 entry
.mask
= 0; /* Enabled */
1982 entry
.trigger
= 0; /* Edge */
1984 entry
.polarity
= 0; /* High */
1985 entry
.delivery_status
= 0;
1986 entry
.dest_mode
= 0; /* Physical */
1987 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1989 entry
.dest
= read_apic_id();
1992 * Add it to the IO-APIC irq-routing table:
1994 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1998 * Use virtual wire A mode when interrupt remapping is enabled.
2000 disconnect_bsp_APIC(!intr_remapping_enabled
&& ioapic_i8259
.pin
!= -1);
2003 #ifdef CONFIG_X86_32
2005 * function to set the IO-APIC physical IDs based on the
2006 * values stored in the MPC table.
2008 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2011 static void __init
setup_ioapic_ids_from_mpc(void)
2013 union IO_APIC_reg_00 reg_00
;
2014 physid_mask_t phys_id_present_map
;
2017 unsigned char old_id
;
2018 unsigned long flags
;
2020 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2024 * Don't check I/O APIC IDs for xAPIC systems. They have
2025 * no meaning without the serial APIC bus.
2027 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2028 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2031 * This is broken; anything with a real cpu count has to
2032 * circumvent this idiocy regardless.
2034 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2037 * Set the IOAPIC ID to the value stored in the MPC table.
2039 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2041 /* Read the register 0 value */
2042 spin_lock_irqsave(&ioapic_lock
, flags
);
2043 reg_00
.raw
= io_apic_read(apic_id
, 0);
2044 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2046 old_id
= mp_ioapics
[apic_id
].apicid
;
2048 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2049 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2050 apic_id
, mp_ioapics
[apic_id
].apicid
);
2051 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2053 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2057 * Sanity check, is the ID really free? Every APIC in a
2058 * system must have a unique ID or we get lots of nice
2059 * 'stuck on smp_invalidate_needed IPI wait' messages.
2061 if (apic
->check_apicid_used(phys_id_present_map
,
2062 mp_ioapics
[apic_id
].apicid
)) {
2063 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2064 apic_id
, mp_ioapics
[apic_id
].apicid
);
2065 for (i
= 0; i
< get_physical_broadcast(); i
++)
2066 if (!physid_isset(i
, phys_id_present_map
))
2068 if (i
>= get_physical_broadcast())
2069 panic("Max APIC ID exceeded!\n");
2070 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2072 physid_set(i
, phys_id_present_map
);
2073 mp_ioapics
[apic_id
].apicid
= i
;
2076 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2077 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2078 "phys_id_present_map\n",
2079 mp_ioapics
[apic_id
].apicid
);
2080 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2085 * We need to adjust the IRQ routing table
2086 * if the ID changed.
2088 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2089 for (i
= 0; i
< mp_irq_entries
; i
++)
2090 if (mp_irqs
[i
].dstapic
== old_id
)
2092 = mp_ioapics
[apic_id
].apicid
;
2095 * Read the right value from the MPC table and
2096 * write it into the ID register.
2098 apic_printk(APIC_VERBOSE
, KERN_INFO
2099 "...changing IO-APIC physical APIC ID to %d ...",
2100 mp_ioapics
[apic_id
].apicid
);
2102 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2103 spin_lock_irqsave(&ioapic_lock
, flags
);
2104 io_apic_write(apic_id
, 0, reg_00
.raw
);
2105 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2110 spin_lock_irqsave(&ioapic_lock
, flags
);
2111 reg_00
.raw
= io_apic_read(apic_id
, 0);
2112 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2113 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2114 printk("could not set ID!\n");
2116 apic_printk(APIC_VERBOSE
, " ok.\n");
2121 int no_timer_check __initdata
;
2123 static int __init
notimercheck(char *s
)
2128 __setup("no_timer_check", notimercheck
);
2131 * There is a nasty bug in some older SMP boards, their mptable lies
2132 * about the timer IRQ. We do the following to work around the situation:
2134 * - timer IRQ defaults to IO-APIC IRQ
2135 * - if this function detects that timer IRQs are defunct, then we fall
2136 * back to ISA timer IRQs
2138 static int __init
timer_irq_works(void)
2140 unsigned long t1
= jiffies
;
2141 unsigned long flags
;
2146 local_save_flags(flags
);
2148 /* Let ten ticks pass... */
2149 mdelay((10 * 1000) / HZ
);
2150 local_irq_restore(flags
);
2153 * Expect a few ticks at least, to be sure some possible
2154 * glue logic does not lock up after one or two first
2155 * ticks in a non-ExtINT mode. Also the local APIC
2156 * might have cached one ExtINT interrupt. Finally, at
2157 * least one tick may be lost due to delays.
2161 if (time_after(jiffies
, t1
+ 4))
2167 * In the SMP+IOAPIC case it might happen that there are an unspecified
2168 * number of pending IRQ events unhandled. These cases are very rare,
2169 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2170 * better to do it this way as thus we do not have to be aware of
2171 * 'pending' interrupts in the IRQ path, except at this point.
2174 * Edge triggered needs to resend any interrupt
2175 * that was delayed but this is now handled in the device
2180 * Starting up a edge-triggered IO-APIC interrupt is
2181 * nasty - we need to make sure that we get the edge.
2182 * If it is already asserted for some reason, we need
2183 * return 1 to indicate that is was pending.
2185 * This is not complete - we should be able to fake
2186 * an edge even if it isn't on the 8259A...
2189 static unsigned int startup_ioapic_irq(unsigned int irq
)
2191 int was_pending
= 0;
2192 unsigned long flags
;
2193 struct irq_cfg
*cfg
;
2195 spin_lock_irqsave(&ioapic_lock
, flags
);
2196 if (irq
< NR_IRQS_LEGACY
) {
2197 disable_8259A_irq(irq
);
2198 if (i8259A_irq_pending(irq
))
2202 __unmask_IO_APIC_irq(cfg
);
2203 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2208 #ifdef CONFIG_X86_64
2209 static int ioapic_retrigger_irq(unsigned int irq
)
2212 struct irq_cfg
*cfg
= irq_cfg(irq
);
2213 unsigned long flags
;
2215 spin_lock_irqsave(&vector_lock
, flags
);
2216 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2217 spin_unlock_irqrestore(&vector_lock
, flags
);
2222 static int ioapic_retrigger_irq(unsigned int irq
)
2224 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2231 * Level and edge triggered IO-APIC interrupts need different handling,
2232 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2233 * handled with the level-triggered descriptor, but that one has slightly
2234 * more overhead. Level-triggered interrupts cannot be handled with the
2235 * edge-triggered handler, without risking IRQ storms and other ugly
2240 static void send_cleanup_vector(struct irq_cfg
*cfg
)
2242 cpumask_var_t cleanup_mask
;
2244 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2246 cfg
->move_cleanup_count
= 0;
2247 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2248 cfg
->move_cleanup_count
++;
2249 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2250 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2252 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2253 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
2254 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2255 free_cpumask_var(cleanup_mask
);
2257 cfg
->move_in_progress
= 0;
2260 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2263 struct irq_pin_list
*entry
;
2264 u8 vector
= cfg
->vector
;
2266 entry
= cfg
->irq_2_pin
;
2276 * With interrupt-remapping, destination information comes
2277 * from interrupt-remapping table entry.
2279 if (!irq_remapped(irq
))
2280 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2281 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2282 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2284 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2287 entry
= entry
->next
;
2292 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
2295 * Either sets desc->affinity to a valid value, and returns
2296 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2297 * leaves desc->affinity untouched.
2300 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
2302 struct irq_cfg
*cfg
;
2305 if (!cpumask_intersects(mask
, cpu_online_mask
))
2309 cfg
= desc
->chip_data
;
2310 if (assign_irq_vector(irq
, cfg
, mask
))
2313 cpumask_copy(desc
->affinity
, mask
);
2315 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2319 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2321 struct irq_cfg
*cfg
;
2322 unsigned long flags
;
2328 cfg
= desc
->chip_data
;
2330 spin_lock_irqsave(&ioapic_lock
, flags
);
2331 dest
= set_desc_affinity(desc
, mask
);
2332 if (dest
!= BAD_APICID
) {
2333 /* Only the high 8 bits are valid. */
2334 dest
= SET_APIC_LOGICAL_ID(dest
);
2335 __target_IO_APIC_irq(irq
, dest
, cfg
);
2338 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2344 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2346 struct irq_desc
*desc
;
2348 desc
= irq_to_desc(irq
);
2350 return set_ioapic_affinity_irq_desc(desc
, mask
);
2353 #ifdef CONFIG_INTR_REMAP
2356 * Migrate the IO-APIC irq in the presence of intr-remapping.
2358 * For both level and edge triggered, irq migration is a simple atomic
2359 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2361 * For level triggered, we eliminate the io-apic RTE modification (with the
2362 * updated vector information), by using a virtual vector (io-apic pin number).
2363 * Real vector that is used for interrupting cpu will be coming from
2364 * the interrupt-remapping table entry.
2367 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2369 struct irq_cfg
*cfg
;
2375 if (!cpumask_intersects(mask
, cpu_online_mask
))
2379 if (get_irte(irq
, &irte
))
2382 cfg
= desc
->chip_data
;
2383 if (assign_irq_vector(irq
, cfg
, mask
))
2386 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2388 irte
.vector
= cfg
->vector
;
2389 irte
.dest_id
= IRTE_DEST(dest
);
2392 * Modified the IRTE and flushes the Interrupt entry cache.
2394 modify_irte(irq
, &irte
);
2396 if (cfg
->move_in_progress
)
2397 send_cleanup_vector(cfg
);
2399 cpumask_copy(desc
->affinity
, mask
);
2405 * Migrates the IRQ destination in the process context.
2407 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2408 const struct cpumask
*mask
)
2410 return migrate_ioapic_irq_desc(desc
, mask
);
2412 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2413 const struct cpumask
*mask
)
2415 struct irq_desc
*desc
= irq_to_desc(irq
);
2417 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2420 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2421 const struct cpumask
*mask
)
2427 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2429 unsigned vector
, me
;
2435 me
= smp_processor_id();
2436 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2439 struct irq_desc
*desc
;
2440 struct irq_cfg
*cfg
;
2441 irq
= __get_cpu_var(vector_irq
)[vector
];
2446 desc
= irq_to_desc(irq
);
2451 spin_lock(&desc
->lock
);
2452 if (!cfg
->move_cleanup_count
)
2455 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2458 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2460 * Check if the vector that needs to be cleanedup is
2461 * registered at the cpu's IRR. If so, then this is not
2462 * the best time to clean it up. Lets clean it up in the
2463 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2466 if (irr
& (1 << (vector
% 32))) {
2467 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2470 __get_cpu_var(vector_irq
)[vector
] = -1;
2471 cfg
->move_cleanup_count
--;
2473 spin_unlock(&desc
->lock
);
2479 static void irq_complete_move(struct irq_desc
**descp
)
2481 struct irq_desc
*desc
= *descp
;
2482 struct irq_cfg
*cfg
= desc
->chip_data
;
2483 unsigned vector
, me
;
2485 if (likely(!cfg
->move_in_progress
))
2488 vector
= ~get_irq_regs()->orig_ax
;
2489 me
= smp_processor_id();
2491 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2492 send_cleanup_vector(cfg
);
2495 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2498 static void ack_apic_edge(unsigned int irq
)
2500 struct irq_desc
*desc
= irq_to_desc(irq
);
2502 irq_complete_move(&desc
);
2503 move_native_irq(irq
);
2507 atomic_t irq_mis_count
;
2509 static void ack_apic_level(unsigned int irq
)
2511 struct irq_desc
*desc
= irq_to_desc(irq
);
2513 #ifdef CONFIG_X86_32
2517 struct irq_cfg
*cfg
;
2518 int do_unmask_irq
= 0;
2520 irq_complete_move(&desc
);
2521 #ifdef CONFIG_GENERIC_PENDING_IRQ
2522 /* If we are moving the irq we need to mask it */
2523 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2525 mask_IO_APIC_irq_desc(desc
);
2529 #ifdef CONFIG_X86_32
2531 * It appears there is an erratum which affects at least version 0x11
2532 * of I/O APIC (that's the 82093AA and cores integrated into various
2533 * chipsets). Under certain conditions a level-triggered interrupt is
2534 * erroneously delivered as edge-triggered one but the respective IRR
2535 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2536 * message but it will never arrive and further interrupts are blocked
2537 * from the source. The exact reason is so far unknown, but the
2538 * phenomenon was observed when two consecutive interrupt requests
2539 * from a given source get delivered to the same CPU and the source is
2540 * temporarily disabled in between.
2542 * A workaround is to simulate an EOI message manually. We achieve it
2543 * by setting the trigger mode to edge and then to level when the edge
2544 * trigger mode gets detected in the TMR of a local APIC for a
2545 * level-triggered interrupt. We mask the source for the time of the
2546 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2547 * The idea is from Manfred Spraul. --macro
2549 cfg
= desc
->chip_data
;
2552 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2556 * We must acknowledge the irq before we move it or the acknowledge will
2557 * not propagate properly.
2561 /* Now we can move and renable the irq */
2562 if (unlikely(do_unmask_irq
)) {
2563 /* Only migrate the irq if the ack has been received.
2565 * On rare occasions the broadcast level triggered ack gets
2566 * delayed going to ioapics, and if we reprogram the
2567 * vector while Remote IRR is still set the irq will never
2570 * To prevent this scenario we read the Remote IRR bit
2571 * of the ioapic. This has two effects.
2572 * - On any sane system the read of the ioapic will
2573 * flush writes (and acks) going to the ioapic from
2575 * - We get to see if the ACK has actually been delivered.
2577 * Based on failed experiments of reprogramming the
2578 * ioapic entry from outside of irq context starting
2579 * with masking the ioapic entry and then polling until
2580 * Remote IRR was clear before reprogramming the
2581 * ioapic I don't trust the Remote IRR bit to be
2582 * completey accurate.
2584 * However there appears to be no other way to plug
2585 * this race, so if the Remote IRR bit is not
2586 * accurate and is causing problems then it is a hardware bug
2587 * and you can go talk to the chipset vendor about it.
2589 cfg
= desc
->chip_data
;
2590 if (!io_apic_level_ack_pending(cfg
))
2591 move_masked_irq(irq
);
2592 unmask_IO_APIC_irq_desc(desc
);
2595 #ifdef CONFIG_X86_32
2596 if (!(v
& (1 << (i
& 0x1f)))) {
2597 atomic_inc(&irq_mis_count
);
2598 spin_lock(&ioapic_lock
);
2599 __mask_and_edge_IO_APIC_irq(cfg
);
2600 __unmask_and_level_IO_APIC_irq(cfg
);
2601 spin_unlock(&ioapic_lock
);
2606 #ifdef CONFIG_INTR_REMAP
2607 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2610 struct irq_pin_list
*entry
;
2612 entry
= cfg
->irq_2_pin
;
2620 io_apic_eoi(apic
, pin
);
2621 entry
= entry
->next
;
2626 eoi_ioapic_irq(struct irq_desc
*desc
)
2628 struct irq_cfg
*cfg
;
2629 unsigned long flags
;
2633 cfg
= desc
->chip_data
;
2635 spin_lock_irqsave(&ioapic_lock
, flags
);
2636 __eoi_ioapic_irq(irq
, cfg
);
2637 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2640 static void ir_ack_apic_edge(unsigned int irq
)
2645 static void ir_ack_apic_level(unsigned int irq
)
2647 struct irq_desc
*desc
= irq_to_desc(irq
);
2650 eoi_ioapic_irq(desc
);
2652 #endif /* CONFIG_INTR_REMAP */
2654 static struct irq_chip ioapic_chip __read_mostly
= {
2656 .startup
= startup_ioapic_irq
,
2657 .mask
= mask_IO_APIC_irq
,
2658 .unmask
= unmask_IO_APIC_irq
,
2659 .ack
= ack_apic_edge
,
2660 .eoi
= ack_apic_level
,
2662 .set_affinity
= set_ioapic_affinity_irq
,
2664 .retrigger
= ioapic_retrigger_irq
,
2667 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2668 .name
= "IR-IO-APIC",
2669 .startup
= startup_ioapic_irq
,
2670 .mask
= mask_IO_APIC_irq
,
2671 .unmask
= unmask_IO_APIC_irq
,
2672 #ifdef CONFIG_INTR_REMAP
2673 .ack
= ir_ack_apic_edge
,
2674 .eoi
= ir_ack_apic_level
,
2676 .set_affinity
= set_ir_ioapic_affinity_irq
,
2679 .retrigger
= ioapic_retrigger_irq
,
2682 static inline void init_IO_APIC_traps(void)
2685 struct irq_desc
*desc
;
2686 struct irq_cfg
*cfg
;
2689 * NOTE! The local APIC isn't very good at handling
2690 * multiple interrupts at the same interrupt level.
2691 * As the interrupt level is determined by taking the
2692 * vector number and shifting that right by 4, we
2693 * want to spread these out a bit so that they don't
2694 * all fall in the same interrupt level.
2696 * Also, we've got to be careful not to trash gate
2697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2699 for_each_irq_desc(irq
, desc
) {
2700 cfg
= desc
->chip_data
;
2701 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2703 * Hmm.. We don't have an entry for this,
2704 * so default to an old-fashioned 8259
2705 * interrupt if we can..
2707 if (irq
< NR_IRQS_LEGACY
)
2708 make_8259A_irq(irq
);
2710 /* Strange. Oh, well.. */
2711 desc
->chip
= &no_irq_chip
;
2717 * The local APIC irq-chip implementation:
2720 static void mask_lapic_irq(unsigned int irq
)
2724 v
= apic_read(APIC_LVT0
);
2725 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2728 static void unmask_lapic_irq(unsigned int irq
)
2732 v
= apic_read(APIC_LVT0
);
2733 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2736 static void ack_lapic_irq(unsigned int irq
)
2741 static struct irq_chip lapic_chip __read_mostly
= {
2742 .name
= "local-APIC",
2743 .mask
= mask_lapic_irq
,
2744 .unmask
= unmask_lapic_irq
,
2745 .ack
= ack_lapic_irq
,
2748 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2750 desc
->status
&= ~IRQ_LEVEL
;
2751 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2755 static void __init
setup_nmi(void)
2758 * Dirty trick to enable the NMI watchdog ...
2759 * We put the 8259A master into AEOI mode and
2760 * unmask on all local APICs LVT0 as NMI.
2762 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2763 * is from Maciej W. Rozycki - so we do not have to EOI from
2764 * the NMI handler or the timer interrupt.
2766 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2768 enable_NMI_through_LVT0();
2770 apic_printk(APIC_VERBOSE
, " done.\n");
2774 * This looks a bit hackish but it's about the only one way of sending
2775 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2776 * not support the ExtINT mode, unfortunately. We need to send these
2777 * cycles as some i82489DX-based boards have glue logic that keeps the
2778 * 8259A interrupt line asserted until INTA. --macro
2780 static inline void __init
unlock_ExtINT_logic(void)
2783 struct IO_APIC_route_entry entry0
, entry1
;
2784 unsigned char save_control
, save_freq_select
;
2786 pin
= find_isa_irq_pin(8, mp_INT
);
2791 apic
= find_isa_irq_apic(8, mp_INT
);
2797 entry0
= ioapic_read_entry(apic
, pin
);
2798 clear_IO_APIC_pin(apic
, pin
);
2800 memset(&entry1
, 0, sizeof(entry1
));
2802 entry1
.dest_mode
= 0; /* physical delivery */
2803 entry1
.mask
= 0; /* unmask IRQ now */
2804 entry1
.dest
= hard_smp_processor_id();
2805 entry1
.delivery_mode
= dest_ExtINT
;
2806 entry1
.polarity
= entry0
.polarity
;
2810 ioapic_write_entry(apic
, pin
, entry1
);
2812 save_control
= CMOS_READ(RTC_CONTROL
);
2813 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2814 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2816 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2821 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2825 CMOS_WRITE(save_control
, RTC_CONTROL
);
2826 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2827 clear_IO_APIC_pin(apic
, pin
);
2829 ioapic_write_entry(apic
, pin
, entry0
);
2832 static int disable_timer_pin_1 __initdata
;
2833 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2834 static int __init
disable_timer_pin_setup(char *arg
)
2836 disable_timer_pin_1
= 1;
2839 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2841 int timer_through_8259 __initdata
;
2844 * This code may look a bit paranoid, but it's supposed to cooperate with
2845 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2846 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2847 * fanatically on his truly buggy board.
2849 * FIXME: really need to revamp this for all platforms.
2851 static inline void __init
check_timer(void)
2853 struct irq_desc
*desc
= irq_to_desc(0);
2854 struct irq_cfg
*cfg
= desc
->chip_data
;
2855 int node
= cpu_to_node(boot_cpu_id
);
2856 int apic1
, pin1
, apic2
, pin2
;
2857 unsigned long flags
;
2860 local_irq_save(flags
);
2863 * get/set the timer IRQ vector:
2865 disable_8259A_irq(0);
2866 assign_irq_vector(0, cfg
, apic
->target_cpus());
2869 * As IRQ0 is to be enabled in the 8259A, the virtual
2870 * wire has to be disabled in the local APIC. Also
2871 * timer interrupts need to be acknowledged manually in
2872 * the 8259A for the i82489DX when using the NMI
2873 * watchdog as that APIC treats NMIs as level-triggered.
2874 * The AEOI mode will finish them in the 8259A
2877 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2879 #ifdef CONFIG_X86_32
2883 ver
= apic_read(APIC_LVR
);
2884 ver
= GET_APIC_VERSION(ver
);
2885 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2889 pin1
= find_isa_irq_pin(0, mp_INT
);
2890 apic1
= find_isa_irq_apic(0, mp_INT
);
2891 pin2
= ioapic_i8259
.pin
;
2892 apic2
= ioapic_i8259
.apic
;
2894 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2895 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2896 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2899 * Some BIOS writers are clueless and report the ExtINTA
2900 * I/O APIC input from the cascaded 8259A as the timer
2901 * interrupt input. So just in case, if only one pin
2902 * was found above, try it both directly and through the
2906 if (intr_remapping_enabled
)
2907 panic("BIOS bug: timer not connected to IO-APIC");
2911 } else if (pin2
== -1) {
2918 * Ok, does IRQ0 through the IOAPIC work?
2921 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2922 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2924 /* for edge trigger, setup_IO_APIC_irq already
2925 * leave it unmasked.
2926 * so only need to unmask if it is level-trigger
2927 * do we really have level trigger timer?
2930 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2931 if (idx
!= -1 && irq_trigger(idx
))
2932 unmask_IO_APIC_irq_desc(desc
);
2934 if (timer_irq_works()) {
2935 if (nmi_watchdog
== NMI_IO_APIC
) {
2937 enable_8259A_irq(0);
2939 if (disable_timer_pin_1
> 0)
2940 clear_IO_APIC_pin(0, pin1
);
2943 if (intr_remapping_enabled
)
2944 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2945 local_irq_disable();
2946 clear_IO_APIC_pin(apic1
, pin1
);
2948 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2949 "8254 timer not connected to IO-APIC\n");
2951 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2952 "(IRQ0) through the 8259A ...\n");
2953 apic_printk(APIC_QUIET
, KERN_INFO
2954 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2956 * legacy devices should be connected to IO APIC #0
2958 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2959 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2960 enable_8259A_irq(0);
2961 if (timer_irq_works()) {
2962 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2963 timer_through_8259
= 1;
2964 if (nmi_watchdog
== NMI_IO_APIC
) {
2965 disable_8259A_irq(0);
2967 enable_8259A_irq(0);
2972 * Cleanup, just in case ...
2974 local_irq_disable();
2975 disable_8259A_irq(0);
2976 clear_IO_APIC_pin(apic2
, pin2
);
2977 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2980 if (nmi_watchdog
== NMI_IO_APIC
) {
2981 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2982 "through the IO-APIC - disabling NMI Watchdog!\n");
2983 nmi_watchdog
= NMI_NONE
;
2985 #ifdef CONFIG_X86_32
2989 apic_printk(APIC_QUIET
, KERN_INFO
2990 "...trying to set up timer as Virtual Wire IRQ...\n");
2992 lapic_register_intr(0, desc
);
2993 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2994 enable_8259A_irq(0);
2996 if (timer_irq_works()) {
2997 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3000 local_irq_disable();
3001 disable_8259A_irq(0);
3002 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3003 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3005 apic_printk(APIC_QUIET
, KERN_INFO
3006 "...trying to set up timer as ExtINT IRQ...\n");
3010 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3012 unlock_ExtINT_logic();
3014 if (timer_irq_works()) {
3015 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3018 local_irq_disable();
3019 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3020 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3021 "report. Then try booting with the 'noapic' option.\n");
3023 local_irq_restore(flags
);
3027 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3028 * to devices. However there may be an I/O APIC pin available for
3029 * this interrupt regardless. The pin may be left unconnected, but
3030 * typically it will be reused as an ExtINT cascade interrupt for
3031 * the master 8259A. In the MPS case such a pin will normally be
3032 * reported as an ExtINT interrupt in the MP table. With ACPI
3033 * there is no provision for ExtINT interrupts, and in the absence
3034 * of an override it would be treated as an ordinary ISA I/O APIC
3035 * interrupt, that is edge-triggered and unmasked by default. We
3036 * used to do this, but it caused problems on some systems because
3037 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3038 * the same ExtINT cascade interrupt to drive the local APIC of the
3039 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3040 * the I/O APIC in all cases now. No actual device should request
3041 * it anyway. --macro
3043 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3045 void __init
setup_IO_APIC(void)
3049 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3052 io_apic_irqs
= ~PIC_IRQS
;
3054 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3056 * Set up IO-APIC IRQ routing.
3058 #ifdef CONFIG_X86_32
3060 setup_ioapic_ids_from_mpc();
3063 setup_IO_APIC_irqs();
3064 init_IO_APIC_traps();
3069 * Called after all the initialization is done. If we didnt find any
3070 * APIC bugs then we can allow the modify fast path
3073 static int __init
io_apic_bug_finalize(void)
3075 if (sis_apic_bug
== -1)
3080 late_initcall(io_apic_bug_finalize
);
3082 struct sysfs_ioapic_data
{
3083 struct sys_device dev
;
3084 struct IO_APIC_route_entry entry
[0];
3086 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3088 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3090 struct IO_APIC_route_entry
*entry
;
3091 struct sysfs_ioapic_data
*data
;
3094 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3095 entry
= data
->entry
;
3096 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3097 *entry
= ioapic_read_entry(dev
->id
, i
);
3102 static int ioapic_resume(struct sys_device
*dev
)
3104 struct IO_APIC_route_entry
*entry
;
3105 struct sysfs_ioapic_data
*data
;
3106 unsigned long flags
;
3107 union IO_APIC_reg_00 reg_00
;
3110 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3111 entry
= data
->entry
;
3113 spin_lock_irqsave(&ioapic_lock
, flags
);
3114 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3115 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3116 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3117 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3119 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3120 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3121 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3126 static struct sysdev_class ioapic_sysdev_class
= {
3128 .suspend
= ioapic_suspend
,
3129 .resume
= ioapic_resume
,
3132 static int __init
ioapic_init_sysfs(void)
3134 struct sys_device
* dev
;
3137 error
= sysdev_class_register(&ioapic_sysdev_class
);
3141 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3142 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3143 * sizeof(struct IO_APIC_route_entry
);
3144 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3145 if (!mp_ioapic_data
[i
]) {
3146 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3149 dev
= &mp_ioapic_data
[i
]->dev
;
3151 dev
->cls
= &ioapic_sysdev_class
;
3152 error
= sysdev_register(dev
);
3154 kfree(mp_ioapic_data
[i
]);
3155 mp_ioapic_data
[i
] = NULL
;
3156 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3164 device_initcall(ioapic_init_sysfs
);
3166 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3168 * Dynamic irq allocate and deallocation
3170 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3172 /* Allocate an unused irq */
3175 unsigned long flags
;
3176 struct irq_cfg
*cfg_new
= NULL
;
3177 struct irq_desc
*desc_new
= NULL
;
3180 if (irq_want
< nr_irqs_gsi
)
3181 irq_want
= nr_irqs_gsi
;
3183 spin_lock_irqsave(&vector_lock
, flags
);
3184 for (new = irq_want
; new < nr_irqs
; new++) {
3185 desc_new
= irq_to_desc_alloc_node(new, node
);
3187 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3190 cfg_new
= desc_new
->chip_data
;
3192 if (cfg_new
->vector
!= 0)
3195 desc_new
= move_irq_desc(desc_new
, node
);
3197 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3201 spin_unlock_irqrestore(&vector_lock
, flags
);
3204 dynamic_irq_init(irq
);
3205 /* restore it, in case dynamic_irq_init clear it */
3207 desc_new
->chip_data
= cfg_new
;
3212 int create_irq(void)
3214 int node
= cpu_to_node(boot_cpu_id
);
3215 unsigned int irq_want
;
3218 irq_want
= nr_irqs_gsi
;
3219 irq
= create_irq_nr(irq_want
, node
);
3227 void destroy_irq(unsigned int irq
)
3229 unsigned long flags
;
3230 struct irq_cfg
*cfg
;
3231 struct irq_desc
*desc
;
3233 /* store it, in case dynamic_irq_cleanup clear it */
3234 desc
= irq_to_desc(irq
);
3235 cfg
= desc
->chip_data
;
3236 dynamic_irq_cleanup(irq
);
3237 /* connect back irq_cfg */
3239 desc
->chip_data
= cfg
;
3242 spin_lock_irqsave(&vector_lock
, flags
);
3243 __clear_irq_vector(irq
, cfg
);
3244 spin_unlock_irqrestore(&vector_lock
, flags
);
3248 * MSI message composition
3250 #ifdef CONFIG_PCI_MSI
3251 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3253 struct irq_cfg
*cfg
;
3261 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3265 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3267 if (irq_remapped(irq
)) {
3272 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3273 BUG_ON(ir_index
== -1);
3275 memset (&irte
, 0, sizeof(irte
));
3278 irte
.dst_mode
= apic
->irq_dest_mode
;
3279 irte
.trigger_mode
= 0; /* edge */
3280 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3281 irte
.vector
= cfg
->vector
;
3282 irte
.dest_id
= IRTE_DEST(dest
);
3284 modify_irte(irq
, &irte
);
3286 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3287 msg
->data
= sub_handle
;
3288 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3290 MSI_ADDR_IR_INDEX1(ir_index
) |
3291 MSI_ADDR_IR_INDEX2(ir_index
);
3293 if (x2apic_enabled())
3294 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3295 MSI_ADDR_EXT_DEST_ID(dest
);
3297 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3301 ((apic
->irq_dest_mode
== 0) ?
3302 MSI_ADDR_DEST_MODE_PHYSICAL
:
3303 MSI_ADDR_DEST_MODE_LOGICAL
) |
3304 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3305 MSI_ADDR_REDIRECTION_CPU
:
3306 MSI_ADDR_REDIRECTION_LOWPRI
) |
3307 MSI_ADDR_DEST_ID(dest
);
3310 MSI_DATA_TRIGGER_EDGE
|
3311 MSI_DATA_LEVEL_ASSERT
|
3312 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3313 MSI_DATA_DELIVERY_FIXED
:
3314 MSI_DATA_DELIVERY_LOWPRI
) |
3315 MSI_DATA_VECTOR(cfg
->vector
);
3321 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3323 struct irq_desc
*desc
= irq_to_desc(irq
);
3324 struct irq_cfg
*cfg
;
3328 dest
= set_desc_affinity(desc
, mask
);
3329 if (dest
== BAD_APICID
)
3332 cfg
= desc
->chip_data
;
3334 read_msi_msg_desc(desc
, &msg
);
3336 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3337 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3338 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3339 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3341 write_msi_msg_desc(desc
, &msg
);
3345 #ifdef CONFIG_INTR_REMAP
3347 * Migrate the MSI irq to another cpumask. This migration is
3348 * done in the process context using interrupt-remapping hardware.
3351 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3353 struct irq_desc
*desc
= irq_to_desc(irq
);
3354 struct irq_cfg
*cfg
= desc
->chip_data
;
3358 if (get_irte(irq
, &irte
))
3361 dest
= set_desc_affinity(desc
, mask
);
3362 if (dest
== BAD_APICID
)
3365 irte
.vector
= cfg
->vector
;
3366 irte
.dest_id
= IRTE_DEST(dest
);
3369 * atomically update the IRTE with the new destination and vector.
3371 modify_irte(irq
, &irte
);
3374 * After this point, all the interrupts will start arriving
3375 * at the new destination. So, time to cleanup the previous
3376 * vector allocation.
3378 if (cfg
->move_in_progress
)
3379 send_cleanup_vector(cfg
);
3385 #endif /* CONFIG_SMP */
3388 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3389 * which implement the MSI or MSI-X Capability Structure.
3391 static struct irq_chip msi_chip
= {
3393 .unmask
= unmask_msi_irq
,
3394 .mask
= mask_msi_irq
,
3395 .ack
= ack_apic_edge
,
3397 .set_affinity
= set_msi_irq_affinity
,
3399 .retrigger
= ioapic_retrigger_irq
,
3402 static struct irq_chip msi_ir_chip
= {
3403 .name
= "IR-PCI-MSI",
3404 .unmask
= unmask_msi_irq
,
3405 .mask
= mask_msi_irq
,
3406 #ifdef CONFIG_INTR_REMAP
3407 .ack
= ir_ack_apic_edge
,
3409 .set_affinity
= ir_set_msi_irq_affinity
,
3412 .retrigger
= ioapic_retrigger_irq
,
3416 * Map the PCI dev to the corresponding remapping hardware unit
3417 * and allocate 'nvec' consecutive interrupt-remapping table entries
3420 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3422 struct intel_iommu
*iommu
;
3425 iommu
= map_dev_to_ir(dev
);
3428 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3432 index
= alloc_irte(iommu
, irq
, nvec
);
3435 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3442 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3447 ret
= msi_compose_msg(dev
, irq
, &msg
);
3451 set_irq_msi(irq
, msidesc
);
3452 write_msi_msg(irq
, &msg
);
3454 if (irq_remapped(irq
)) {
3455 struct irq_desc
*desc
= irq_to_desc(irq
);
3457 * irq migration in process context
3459 desc
->status
|= IRQ_MOVE_PCNTXT
;
3460 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3462 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3464 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3469 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3472 int ret
, sub_handle
;
3473 struct msi_desc
*msidesc
;
3474 unsigned int irq_want
;
3475 struct intel_iommu
*iommu
= NULL
;
3479 /* x86 doesn't support multiple MSI yet */
3480 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3483 node
= dev_to_node(&dev
->dev
);
3484 irq_want
= nr_irqs_gsi
;
3486 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3487 irq
= create_irq_nr(irq_want
, node
);
3491 if (!intr_remapping_enabled
)
3496 * allocate the consecutive block of IRTE's
3499 index
= msi_alloc_irte(dev
, irq
, nvec
);
3505 iommu
= map_dev_to_ir(dev
);
3511 * setup the mapping between the irq and the IRTE
3512 * base index, the sub_handle pointing to the
3513 * appropriate interrupt remap table entry.
3515 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3518 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3530 void arch_teardown_msi_irq(unsigned int irq
)
3535 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3537 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3539 struct irq_desc
*desc
= irq_to_desc(irq
);
3540 struct irq_cfg
*cfg
;
3544 dest
= set_desc_affinity(desc
, mask
);
3545 if (dest
== BAD_APICID
)
3548 cfg
= desc
->chip_data
;
3550 dmar_msi_read(irq
, &msg
);
3552 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3553 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3554 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3555 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3557 dmar_msi_write(irq
, &msg
);
3562 #endif /* CONFIG_SMP */
3564 struct irq_chip dmar_msi_type
= {
3566 .unmask
= dmar_msi_unmask
,
3567 .mask
= dmar_msi_mask
,
3568 .ack
= ack_apic_edge
,
3570 .set_affinity
= dmar_msi_set_affinity
,
3572 .retrigger
= ioapic_retrigger_irq
,
3575 int arch_setup_dmar_msi(unsigned int irq
)
3580 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3583 dmar_msi_write(irq
, &msg
);
3584 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3590 #ifdef CONFIG_HPET_TIMER
3593 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3595 struct irq_desc
*desc
= irq_to_desc(irq
);
3596 struct irq_cfg
*cfg
;
3600 dest
= set_desc_affinity(desc
, mask
);
3601 if (dest
== BAD_APICID
)
3604 cfg
= desc
->chip_data
;
3606 hpet_msi_read(irq
, &msg
);
3608 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3609 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3610 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3611 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3613 hpet_msi_write(irq
, &msg
);
3618 #endif /* CONFIG_SMP */
3620 static struct irq_chip hpet_msi_type
= {
3622 .unmask
= hpet_msi_unmask
,
3623 .mask
= hpet_msi_mask
,
3624 .ack
= ack_apic_edge
,
3626 .set_affinity
= hpet_msi_set_affinity
,
3628 .retrigger
= ioapic_retrigger_irq
,
3631 int arch_setup_hpet_msi(unsigned int irq
)
3635 struct irq_desc
*desc
= irq_to_desc(irq
);
3637 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3641 hpet_msi_write(irq
, &msg
);
3642 desc
->status
|= IRQ_MOVE_PCNTXT
;
3643 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3650 #endif /* CONFIG_PCI_MSI */
3652 * Hypertransport interrupt support
3654 #ifdef CONFIG_HT_IRQ
3658 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3660 struct ht_irq_msg msg
;
3661 fetch_ht_irq_msg(irq
, &msg
);
3663 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3664 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3666 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3667 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3669 write_ht_irq_msg(irq
, &msg
);
3672 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3674 struct irq_desc
*desc
= irq_to_desc(irq
);
3675 struct irq_cfg
*cfg
;
3678 dest
= set_desc_affinity(desc
, mask
);
3679 if (dest
== BAD_APICID
)
3682 cfg
= desc
->chip_data
;
3684 target_ht_irq(irq
, dest
, cfg
->vector
);
3691 static struct irq_chip ht_irq_chip
= {
3693 .mask
= mask_ht_irq
,
3694 .unmask
= unmask_ht_irq
,
3695 .ack
= ack_apic_edge
,
3697 .set_affinity
= set_ht_irq_affinity
,
3699 .retrigger
= ioapic_retrigger_irq
,
3702 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3704 struct irq_cfg
*cfg
;
3711 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3713 struct ht_irq_msg msg
;
3716 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3717 apic
->target_cpus());
3719 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3723 HT_IRQ_LOW_DEST_ID(dest
) |
3724 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3725 ((apic
->irq_dest_mode
== 0) ?
3726 HT_IRQ_LOW_DM_PHYSICAL
:
3727 HT_IRQ_LOW_DM_LOGICAL
) |
3728 HT_IRQ_LOW_RQEOI_EDGE
|
3729 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3730 HT_IRQ_LOW_MT_FIXED
:
3731 HT_IRQ_LOW_MT_ARBITRATED
) |
3732 HT_IRQ_LOW_IRQ_MASKED
;
3734 write_ht_irq_msg(irq
, &msg
);
3736 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3737 handle_edge_irq
, "edge");
3739 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3743 #endif /* CONFIG_HT_IRQ */
3745 #ifdef CONFIG_X86_UV
3747 * Re-target the irq to the specified CPU and enable the specified MMR located
3748 * on the specified blade to allow the sending of MSIs to the specified CPU.
3750 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3751 unsigned long mmr_offset
)
3753 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3754 struct irq_cfg
*cfg
;
3756 unsigned long mmr_value
;
3757 struct uv_IO_APIC_route_entry
*entry
;
3758 unsigned long flags
;
3761 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3765 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3769 spin_lock_irqsave(&vector_lock
, flags
);
3770 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3772 spin_unlock_irqrestore(&vector_lock
, flags
);
3775 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3776 entry
->vector
= cfg
->vector
;
3777 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3778 entry
->dest_mode
= apic
->irq_dest_mode
;
3779 entry
->polarity
= 0;
3782 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3784 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3785 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3791 * Disable the specified MMR located on the specified blade so that MSIs are
3792 * longer allowed to be sent.
3794 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3796 unsigned long mmr_value
;
3797 struct uv_IO_APIC_route_entry
*entry
;
3800 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3803 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3806 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3807 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3809 #endif /* CONFIG_X86_64 */
3811 int __init
io_apic_get_redir_entries (int ioapic
)
3813 union IO_APIC_reg_01 reg_01
;
3814 unsigned long flags
;
3816 spin_lock_irqsave(&ioapic_lock
, flags
);
3817 reg_01
.raw
= io_apic_read(ioapic
, 1);
3818 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3820 return reg_01
.bits
.entries
;
3823 void __init
probe_nr_irqs_gsi(void)
3827 nr
= acpi_probe_gsi();
3828 if (nr
> nr_irqs_gsi
) {
3831 /* for acpi=off or acpi is not compiled in */
3835 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3836 nr
+= io_apic_get_redir_entries(idx
) + 1;
3838 if (nr
> nr_irqs_gsi
)
3842 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3845 #ifdef CONFIG_SPARSE_IRQ
3846 int __init
arch_probe_nr_irqs(void)
3850 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3851 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3853 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3854 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3856 * for MSI and HT dyn irq
3858 nr
+= nr_irqs_gsi
* 16;
3867 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3868 struct io_apic_irq_attr
*irq_attr
)
3870 struct irq_desc
*desc
;
3871 struct irq_cfg
*cfg
;
3874 int trigger
, polarity
;
3876 ioapic
= irq_attr
->ioapic
;
3877 if (!IO_APIC_IRQ(irq
)) {
3878 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3884 node
= dev_to_node(dev
);
3886 node
= cpu_to_node(boot_cpu_id
);
3888 desc
= irq_to_desc_alloc_node(irq
, node
);
3890 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3894 pin
= irq_attr
->ioapic_pin
;
3895 trigger
= irq_attr
->trigger
;
3896 polarity
= irq_attr
->polarity
;
3899 * IRQs < 16 are already in the irq_2_pin[] map
3901 if (irq
>= NR_IRQS_LEGACY
) {
3902 cfg
= desc
->chip_data
;
3903 add_pin_to_irq_node(cfg
, node
, ioapic
, pin
);
3906 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3911 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3912 struct io_apic_irq_attr
*irq_attr
)
3916 * Avoid pin reprogramming. PRTs typically include entries
3917 * with redundant pin->gsi mappings (but unique PCI devices);
3918 * we only program the IOAPIC on the first.
3920 ioapic
= irq_attr
->ioapic
;
3921 pin
= irq_attr
->ioapic_pin
;
3922 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3923 pr_debug("Pin %d-%d already programmed\n",
3924 mp_ioapics
[ioapic
].apicid
, pin
);
3927 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3929 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3932 /* --------------------------------------------------------------------------
3933 ACPI-based IOAPIC Configuration
3934 -------------------------------------------------------------------------- */
3938 #ifdef CONFIG_X86_32
3939 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3941 union IO_APIC_reg_00 reg_00
;
3942 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3944 unsigned long flags
;
3948 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3949 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3950 * supports up to 16 on one shared APIC bus.
3952 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3953 * advantage of new APIC bus architecture.
3956 if (physids_empty(apic_id_map
))
3957 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3959 spin_lock_irqsave(&ioapic_lock
, flags
);
3960 reg_00
.raw
= io_apic_read(ioapic
, 0);
3961 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3963 if (apic_id
>= get_physical_broadcast()) {
3964 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3965 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3966 apic_id
= reg_00
.bits
.ID
;
3970 * Every APIC in a system must have a unique ID or we get lots of nice
3971 * 'stuck on smp_invalidate_needed IPI wait' messages.
3973 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3975 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3976 if (!apic
->check_apicid_used(apic_id_map
, i
))
3980 if (i
== get_physical_broadcast())
3981 panic("Max apic_id exceeded!\n");
3983 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3984 "trying %d\n", ioapic
, apic_id
, i
);
3989 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3990 physids_or(apic_id_map
, apic_id_map
, tmp
);
3992 if (reg_00
.bits
.ID
!= apic_id
) {
3993 reg_00
.bits
.ID
= apic_id
;
3995 spin_lock_irqsave(&ioapic_lock
, flags
);
3996 io_apic_write(ioapic
, 0, reg_00
.raw
);
3997 reg_00
.raw
= io_apic_read(ioapic
, 0);
3998 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4001 if (reg_00
.bits
.ID
!= apic_id
) {
4002 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4007 apic_printk(APIC_VERBOSE
, KERN_INFO
4008 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4013 int __init
io_apic_get_version(int ioapic
)
4015 union IO_APIC_reg_01 reg_01
;
4016 unsigned long flags
;
4018 spin_lock_irqsave(&ioapic_lock
, flags
);
4019 reg_01
.raw
= io_apic_read(ioapic
, 1);
4020 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4022 return reg_01
.bits
.version
;
4026 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4030 if (skip_ioapic_setup
)
4033 for (i
= 0; i
< mp_irq_entries
; i
++)
4034 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4035 mp_irqs
[i
].srcbusirq
== bus_irq
)
4037 if (i
>= mp_irq_entries
)
4040 *trigger
= irq_trigger(i
);
4041 *polarity
= irq_polarity(i
);
4045 #endif /* CONFIG_ACPI */
4048 * This function currently is only a helper for the i386 smp boot process where
4049 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4050 * so mask in all cases should simply be apic->target_cpus()
4053 void __init
setup_ioapic_dest(void)
4055 int pin
, ioapic
= 0, irq
, irq_entry
;
4056 struct irq_desc
*desc
;
4057 const struct cpumask
*mask
;
4059 if (skip_ioapic_setup
== 1)
4063 if (!acpi_disabled
&& acpi_ioapic
) {
4064 ioapic
= mp_find_ioapic(0);
4070 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4071 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4072 if (irq_entry
== -1)
4074 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4076 desc
= irq_to_desc(irq
);
4079 * Honour affinities which have been set in early boot
4082 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4083 mask
= desc
->affinity
;
4085 mask
= apic
->target_cpus();
4087 if (intr_remapping_enabled
)
4088 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4090 set_ioapic_affinity_irq_desc(desc
, mask
);
4096 #define IOAPIC_RESOURCE_NAME_SIZE 11
4098 static struct resource
*ioapic_resources
;
4100 static struct resource
* __init
ioapic_setup_resources(void)
4103 struct resource
*res
;
4107 if (nr_ioapics
<= 0)
4110 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4113 mem
= alloc_bootmem(n
);
4117 mem
+= sizeof(struct resource
) * nr_ioapics
;
4119 for (i
= 0; i
< nr_ioapics
; i
++) {
4121 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4122 sprintf(mem
, "IOAPIC %u", i
);
4123 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4127 ioapic_resources
= res
;
4132 void __init
ioapic_init_mappings(void)
4134 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4135 struct resource
*ioapic_res
;
4138 ioapic_res
= ioapic_setup_resources();
4139 for (i
= 0; i
< nr_ioapics
; i
++) {
4140 if (smp_found_config
) {
4141 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4142 #ifdef CONFIG_X86_32
4145 "WARNING: bogus zero IO-APIC "
4146 "address found in MPTABLE, "
4147 "disabling IO/APIC support!\n");
4148 smp_found_config
= 0;
4149 skip_ioapic_setup
= 1;
4150 goto fake_ioapic_page
;
4154 #ifdef CONFIG_X86_32
4157 ioapic_phys
= (unsigned long)
4158 alloc_bootmem_pages(PAGE_SIZE
);
4159 ioapic_phys
= __pa(ioapic_phys
);
4161 set_fixmap_nocache(idx
, ioapic_phys
);
4162 apic_printk(APIC_VERBOSE
,
4163 "mapped IOAPIC to %08lx (%08lx)\n",
4164 __fix_to_virt(idx
), ioapic_phys
);
4167 if (ioapic_res
!= NULL
) {
4168 ioapic_res
->start
= ioapic_phys
;
4169 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4175 static int __init
ioapic_insert_resources(void)
4178 struct resource
*r
= ioapic_resources
;
4181 if (nr_ioapics
> 0) {
4183 "IO APIC resources couldn't be allocated.\n");
4189 for (i
= 0; i
< nr_ioapics
; i
++) {
4190 insert_resource(&iomem_resource
, r
);
4197 /* Insert the IO APIC resources after PCI initialization has occured to handle
4198 * IO APICS that are mapped in on a BAR in PCI space. */
4199 late_initcall(ioapic_insert_resources
);