2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
40 #define SH_ETH_DEF_MSG_ENABLE \
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device
*ndev
)
51 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
53 if (mdp
->duplex
) /* Full */
54 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
56 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
59 static void sh_eth_set_rate(struct net_device
*ndev
)
61 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
65 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
67 case 100:/* 100BASE */
68 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
77 .set_duplex
= sh_eth_set_duplex
,
78 .set_rate
= sh_eth_set_rate
,
80 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
81 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
82 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
84 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
85 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
86 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
87 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
94 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_RESET_DEFAULT 1
98 static void sh_eth_set_duplex(struct net_device
*ndev
)
100 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
102 if (mdp
->duplex
) /* Full */
103 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
105 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
108 static void sh_eth_set_rate(struct net_device
*ndev
)
110 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
112 switch (mdp
->speed
) {
113 case 10: /* 10BASE */
114 sh_eth_write(ndev
, 0, RTRATE
);
116 case 100:/* 100BASE */
117 sh_eth_write(ndev
, 1, RTRATE
);
125 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
126 .set_duplex
= sh_eth_set_duplex
,
127 .set_rate
= sh_eth_set_rate
,
129 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
130 .rmcr_value
= 0x00000001,
132 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
133 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
134 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
135 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
144 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
145 #define SH_ETH_HAS_TSU 1
146 static void sh_eth_chip_reset(struct net_device
*ndev
)
148 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
151 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
155 static void sh_eth_reset(struct net_device
*ndev
)
159 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
160 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
162 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
168 printk(KERN_ERR
"Device reset fail\n");
171 sh_eth_write(ndev
, 0x0, TDLAR
);
172 sh_eth_write(ndev
, 0x0, TDFAR
);
173 sh_eth_write(ndev
, 0x0, TDFXR
);
174 sh_eth_write(ndev
, 0x0, TDFFR
);
175 sh_eth_write(ndev
, 0x0, RDLAR
);
176 sh_eth_write(ndev
, 0x0, RDFAR
);
177 sh_eth_write(ndev
, 0x0, RDFXR
);
178 sh_eth_write(ndev
, 0x0, RDFFR
);
181 static void sh_eth_set_duplex(struct net_device
*ndev
)
183 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
185 if (mdp
->duplex
) /* Full */
186 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
188 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
191 static void sh_eth_set_rate(struct net_device
*ndev
)
193 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
195 switch (mdp
->speed
) {
196 case 10: /* 10BASE */
197 sh_eth_write(ndev
, GECMR_10
, GECMR
);
199 case 100:/* 100BASE */
200 sh_eth_write(ndev
, GECMR_100
, GECMR
);
202 case 1000: /* 1000BASE */
203 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
211 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
212 .chip_reset
= sh_eth_chip_reset
,
213 .set_duplex
= sh_eth_set_duplex
,
214 .set_rate
= sh_eth_set_rate
,
216 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
217 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
218 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
220 .tx_check
= EESR_TC1
| EESR_FTC
,
221 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
222 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
224 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
237 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
238 #define SH_ETH_RESET_DEFAULT 1
239 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
240 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
247 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
248 #define SH_ETH_RESET_DEFAULT 1
249 #define SH_ETH_HAS_TSU 1
250 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
251 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
256 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
259 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
261 if (!cd
->ecsipr_value
)
262 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
264 if (!cd
->fcftr_value
)
265 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
266 DEFAULT_FIFO_F_D_RFD
;
269 cd
->fdr_value
= DEFAULT_FDR_INIT
;
272 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
275 cd
->tx_check
= DEFAULT_TX_CHECK
;
277 if (!cd
->eesr_err_check
)
278 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
280 if (!cd
->tx_error_check
)
281 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
284 #if defined(SH_ETH_RESET_DEFAULT)
286 static void sh_eth_reset(struct net_device
*ndev
)
288 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
290 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
294 #if defined(CONFIG_CPU_SH4)
295 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
299 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
301 skb_reserve(skb
, reserve
);
304 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
306 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
311 /* CPU <-> EDMAC endian convert */
312 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
314 switch (mdp
->edmac_endian
) {
315 case EDMAC_LITTLE_ENDIAN
:
316 return cpu_to_le32(x
);
317 case EDMAC_BIG_ENDIAN
:
318 return cpu_to_be32(x
);
323 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
325 switch (mdp
->edmac_endian
) {
326 case EDMAC_LITTLE_ENDIAN
:
327 return le32_to_cpu(x
);
328 case EDMAC_BIG_ENDIAN
:
329 return be32_to_cpu(x
);
335 * Program the hardware MAC address from dev->dev_addr.
337 static void update_mac_address(struct net_device
*ndev
)
340 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
341 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
343 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
347 * Get MAC address from SuperH MAC address register
349 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
350 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
351 * When you want use this device, you must set MAC address in bootloader.
354 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
356 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
357 memcpy(ndev
->dev_addr
, mac
, 6);
359 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
360 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
361 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
362 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
363 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
364 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
368 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
370 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
376 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
378 if (sh_eth_is_gether(mdp
))
379 return EDTRR_TRNS_GETHER
;
381 return EDTRR_TRNS_ETHER
;
385 struct mdiobb_ctrl ctrl
;
387 u32 mmd_msk
;/* MMD */
394 static void bb_set(u32 addr
, u32 msk
)
396 writel(readl(addr
) | msk
, addr
);
400 static void bb_clr(u32 addr
, u32 msk
)
402 writel((readl(addr
) & ~msk
), addr
);
406 static int bb_read(u32 addr
, u32 msk
)
408 return (readl(addr
) & msk
) != 0;
411 /* Data I/O pin control */
412 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
414 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
416 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
418 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
422 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
424 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
427 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
429 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
433 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
435 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
436 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
439 /* MDC pin control */
440 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
442 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
445 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
447 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
450 /* mdio bus control struct */
451 static struct mdiobb_ops bb_ops
= {
452 .owner
= THIS_MODULE
,
453 .set_mdc
= sh_mdc_ctrl
,
454 .set_mdio_dir
= sh_mmd_ctrl
,
455 .set_mdio_data
= sh_set_mdio
,
456 .get_mdio_data
= sh_get_mdio
,
459 /* free skb and descriptor buffer */
460 static void sh_eth_ring_free(struct net_device
*ndev
)
462 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
465 /* Free Rx skb ringbuffer */
466 if (mdp
->rx_skbuff
) {
467 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
468 if (mdp
->rx_skbuff
[i
])
469 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
472 kfree(mdp
->rx_skbuff
);
474 /* Free Tx skb ringbuffer */
475 if (mdp
->tx_skbuff
) {
476 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
477 if (mdp
->tx_skbuff
[i
])
478 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
481 kfree(mdp
->tx_skbuff
);
484 /* format skb and descriptor buffer */
485 static void sh_eth_ring_format(struct net_device
*ndev
)
487 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
490 struct sh_eth_rxdesc
*rxdesc
= NULL
;
491 struct sh_eth_txdesc
*txdesc
= NULL
;
492 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
493 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
495 mdp
->cur_rx
= mdp
->cur_tx
= 0;
496 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
498 memset(mdp
->rx_ring
, 0, rx_ringsize
);
500 /* build Rx ring buffer */
501 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
503 mdp
->rx_skbuff
[i
] = NULL
;
504 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
505 mdp
->rx_skbuff
[i
] = skb
;
508 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
510 skb
->dev
= ndev
; /* Mark as being used by this device. */
511 sh_eth_set_receive_align(skb
);
514 rxdesc
= &mdp
->rx_ring
[i
];
515 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
516 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
518 /* The size of the buffer is 16 byte boundary. */
519 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
520 /* Rx descriptor address set */
522 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
523 if (sh_eth_is_gether(mdp
))
524 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
528 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
530 /* Mark the last entry as wrapping the ring. */
531 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
533 memset(mdp
->tx_ring
, 0, tx_ringsize
);
535 /* build Tx ring buffer */
536 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
537 mdp
->tx_skbuff
[i
] = NULL
;
538 txdesc
= &mdp
->tx_ring
[i
];
539 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
540 txdesc
->buffer_length
= 0;
542 /* Tx descriptor address set */
543 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
544 if (sh_eth_is_gether(mdp
))
545 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
549 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
552 /* Get skb and descriptor buffer */
553 static int sh_eth_ring_init(struct net_device
*ndev
)
555 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
556 int rx_ringsize
, tx_ringsize
, ret
= 0;
559 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
560 * card needs room to do 8 byte alignment, +2 so we can reserve
561 * the first 2 bytes, and +16 gets room for the status word from the
564 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
565 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
567 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
569 /* Allocate RX and TX skb rings */
570 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
572 if (!mdp
->rx_skbuff
) {
573 dev_err(&ndev
->dev
, "Cannot allocate Rx skb\n");
578 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
580 if (!mdp
->tx_skbuff
) {
581 dev_err(&ndev
->dev
, "Cannot allocate Tx skb\n");
586 /* Allocate all Rx descriptors. */
587 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
588 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
592 dev_err(&ndev
->dev
, "Cannot allocate Rx Ring (size %d bytes)\n",
600 /* Allocate all Tx descriptors. */
601 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
602 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
605 dev_err(&ndev
->dev
, "Cannot allocate Tx Ring (size %d bytes)\n",
613 /* free DMA buffer */
614 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
617 /* Free Rx and Tx skb ring buffer */
618 sh_eth_ring_free(ndev
);
623 static int sh_eth_dev_init(struct net_device
*ndev
)
626 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
627 u_int32_t rx_int_var
, tx_int_var
;
633 /* Descriptor format */
634 sh_eth_ring_format(ndev
);
636 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
638 /* all sh_eth int mask */
639 sh_eth_write(ndev
, 0, EESIPR
);
641 #if defined(__LITTLE_ENDIAN__)
642 if (mdp
->cd
->hw_swap
)
643 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
646 sh_eth_write(ndev
, 0, EDMR
);
649 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
650 sh_eth_write(ndev
, 0, TFTR
);
652 /* Frame recv control */
653 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
655 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
656 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
657 sh_eth_write(ndev
, rx_int_var
| tx_int_var
, TRSCER
);
660 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
662 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
664 if (!mdp
->cd
->no_trimd
)
665 sh_eth_write(ndev
, 0, TRIMD
);
667 /* Recv frame limit set register */
668 sh_eth_write(ndev
, RFLR_VALUE
, RFLR
);
670 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
671 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
673 /* PAUSE Prohibition */
674 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
675 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
677 sh_eth_write(ndev
, val
, ECMR
);
679 if (mdp
->cd
->set_rate
)
680 mdp
->cd
->set_rate(ndev
);
682 /* E-MAC Status Register clear */
683 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
685 /* E-MAC Interrupt Enable register */
686 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
688 /* Set MAC address */
689 update_mac_address(ndev
);
693 sh_eth_write(ndev
, APR_AP
, APR
);
695 sh_eth_write(ndev
, MPR_MP
, MPR
);
696 if (mdp
->cd
->tpauser
)
697 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
699 /* Setting the Rx mode will start the Rx process. */
700 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
702 netif_start_queue(ndev
);
707 /* free Tx skb function */
708 static int sh_eth_txfree(struct net_device
*ndev
)
710 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
711 struct sh_eth_txdesc
*txdesc
;
715 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
716 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
717 txdesc
= &mdp
->tx_ring
[entry
];
718 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
720 /* Free the original skb. */
721 if (mdp
->tx_skbuff
[entry
]) {
722 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
723 mdp
->tx_skbuff
[entry
] = NULL
;
726 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
727 if (entry
>= TX_RING_SIZE
- 1)
728 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
730 mdp
->stats
.tx_packets
++;
731 mdp
->stats
.tx_bytes
+= txdesc
->buffer_length
;
736 /* Packet receive function */
737 static int sh_eth_rx(struct net_device
*ndev
)
739 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
740 struct sh_eth_rxdesc
*rxdesc
;
742 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
743 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
748 rxdesc
= &mdp
->rx_ring
[entry
];
749 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
750 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
751 pkt_len
= rxdesc
->frame_length
;
756 if (!(desc_status
& RDFEND
))
757 mdp
->stats
.rx_length_errors
++;
759 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
760 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
761 mdp
->stats
.rx_errors
++;
762 if (desc_status
& RD_RFS1
)
763 mdp
->stats
.rx_crc_errors
++;
764 if (desc_status
& RD_RFS2
)
765 mdp
->stats
.rx_frame_errors
++;
766 if (desc_status
& RD_RFS3
)
767 mdp
->stats
.rx_length_errors
++;
768 if (desc_status
& RD_RFS4
)
769 mdp
->stats
.rx_length_errors
++;
770 if (desc_status
& RD_RFS6
)
771 mdp
->stats
.rx_missed_errors
++;
772 if (desc_status
& RD_RFS10
)
773 mdp
->stats
.rx_over_errors
++;
775 if (!mdp
->cd
->hw_swap
)
777 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
779 skb
= mdp
->rx_skbuff
[entry
];
780 mdp
->rx_skbuff
[entry
] = NULL
;
782 skb_reserve(skb
, NET_IP_ALIGN
);
783 skb_put(skb
, pkt_len
);
784 skb
->protocol
= eth_type_trans(skb
, ndev
);
786 mdp
->stats
.rx_packets
++;
787 mdp
->stats
.rx_bytes
+= pkt_len
;
789 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
790 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
791 rxdesc
= &mdp
->rx_ring
[entry
];
794 /* Refill the Rx ring buffers. */
795 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
796 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
797 rxdesc
= &mdp
->rx_ring
[entry
];
798 /* The size of the buffer is 16 byte boundary. */
799 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
801 if (mdp
->rx_skbuff
[entry
] == NULL
) {
802 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
803 mdp
->rx_skbuff
[entry
] = skb
;
805 break; /* Better luck next round. */
806 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
809 sh_eth_set_receive_align(skb
);
811 skb_checksum_none_assert(skb
);
812 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
814 if (entry
>= RX_RING_SIZE
- 1)
816 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
819 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
822 /* Restart Rx engine if stopped. */
823 /* If we don't need to check status, don't. -KDU */
824 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
))
825 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
830 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
832 /* disable tx and rx */
833 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
834 ~(ECMR_RE
| ECMR_TE
), ECMR
);
837 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
839 /* enable tx and rx */
840 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
841 (ECMR_RE
| ECMR_TE
), ECMR
);
844 /* error control function */
845 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
847 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
852 if (intr_status
& EESR_ECI
) {
853 felic_stat
= sh_eth_read(ndev
, ECSR
);
854 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
855 if (felic_stat
& ECSR_ICD
)
856 mdp
->stats
.tx_carrier_errors
++;
857 if (felic_stat
& ECSR_LCHNG
) {
859 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
860 if (mdp
->link
== PHY_DOWN
)
863 link_stat
= PHY_ST_LINK
;
865 link_stat
= (sh_eth_read(ndev
, PSR
));
866 if (mdp
->ether_link_active_low
)
867 link_stat
= ~link_stat
;
869 if (!(link_stat
& PHY_ST_LINK
))
870 sh_eth_rcv_snd_disable(ndev
);
873 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
874 ~DMAC_M_ECI
, EESIPR
);
876 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
878 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
880 /* enable tx and rx */
881 sh_eth_rcv_snd_enable(ndev
);
886 if (intr_status
& EESR_TWB
) {
887 /* Write buck end. unused write back interrupt */
888 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
889 mdp
->stats
.tx_aborted_errors
++;
890 if (netif_msg_tx_err(mdp
))
891 dev_err(&ndev
->dev
, "Transmit Abort\n");
894 if (intr_status
& EESR_RABT
) {
895 /* Receive Abort int */
896 if (intr_status
& EESR_RFRMER
) {
897 /* Receive Frame Overflow int */
898 mdp
->stats
.rx_frame_errors
++;
899 if (netif_msg_rx_err(mdp
))
900 dev_err(&ndev
->dev
, "Receive Abort\n");
904 if (intr_status
& EESR_TDE
) {
905 /* Transmit Descriptor Empty int */
906 mdp
->stats
.tx_fifo_errors
++;
907 if (netif_msg_tx_err(mdp
))
908 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
911 if (intr_status
& EESR_TFE
) {
912 /* FIFO under flow */
913 mdp
->stats
.tx_fifo_errors
++;
914 if (netif_msg_tx_err(mdp
))
915 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
918 if (intr_status
& EESR_RDE
) {
919 /* Receive Descriptor Empty int */
920 mdp
->stats
.rx_over_errors
++;
922 if (sh_eth_read(ndev
, EDRRR
) ^ EDRRR_R
)
923 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
924 if (netif_msg_rx_err(mdp
))
925 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
928 if (intr_status
& EESR_RFE
) {
929 /* Receive FIFO Overflow int */
930 mdp
->stats
.rx_fifo_errors
++;
931 if (netif_msg_rx_err(mdp
))
932 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
935 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
937 mdp
->stats
.tx_fifo_errors
++;
938 if (netif_msg_tx_err(mdp
))
939 dev_err(&ndev
->dev
, "Address Error\n");
942 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
945 if (intr_status
& mask
) {
947 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
949 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
950 intr_status
, mdp
->cur_tx
);
951 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
952 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
953 /* dirty buffer free */
957 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
959 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
962 netif_wake_queue(ndev
);
966 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
968 struct net_device
*ndev
= netdev
;
969 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
970 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
971 irqreturn_t ret
= IRQ_NONE
;
974 spin_lock(&mdp
->lock
);
976 /* Get interrpt stat */
977 intr_status
= sh_eth_read(ndev
, EESR
);
978 /* Clear interrupt */
979 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
980 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
981 cd
->tx_check
| cd
->eesr_err_check
)) {
982 sh_eth_write(ndev
, intr_status
, EESR
);
987 if (intr_status
& (EESR_FRC
| /* Frame recv*/
988 EESR_RMAF
| /* Multi cast address recv*/
989 EESR_RRF
| /* Bit frame recv */
990 EESR_RTLF
| /* Long frame recv*/
991 EESR_RTSF
| /* short frame recv */
992 EESR_PRE
| /* PHY-LSI recv error */
993 EESR_CERF
)){ /* recv frame CRC error */
998 if (intr_status
& cd
->tx_check
) {
1000 netif_wake_queue(ndev
);
1003 if (intr_status
& cd
->eesr_err_check
)
1004 sh_eth_error(ndev
, intr_status
);
1007 spin_unlock(&mdp
->lock
);
1012 static void sh_eth_timer(unsigned long data
)
1014 struct net_device
*ndev
= (struct net_device
*)data
;
1015 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1017 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
1020 /* PHY state control function */
1021 static void sh_eth_adjust_link(struct net_device
*ndev
)
1023 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1024 struct phy_device
*phydev
= mdp
->phydev
;
1027 if (phydev
->link
!= PHY_DOWN
) {
1028 if (phydev
->duplex
!= mdp
->duplex
) {
1030 mdp
->duplex
= phydev
->duplex
;
1031 if (mdp
->cd
->set_duplex
)
1032 mdp
->cd
->set_duplex(ndev
);
1035 if (phydev
->speed
!= mdp
->speed
) {
1037 mdp
->speed
= phydev
->speed
;
1038 if (mdp
->cd
->set_rate
)
1039 mdp
->cd
->set_rate(ndev
);
1041 if (mdp
->link
== PHY_DOWN
) {
1042 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
)
1045 mdp
->link
= phydev
->link
;
1047 } else if (mdp
->link
) {
1049 mdp
->link
= PHY_DOWN
;
1054 if (new_state
&& netif_msg_link(mdp
))
1055 phy_print_status(phydev
);
1058 /* PHY init function */
1059 static int sh_eth_phy_init(struct net_device
*ndev
)
1061 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1062 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1063 struct phy_device
*phydev
= NULL
;
1065 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1066 mdp
->mii_bus
->id
, mdp
->phy_id
);
1068 mdp
->link
= PHY_DOWN
;
1072 /* Try connect to PHY */
1073 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1074 0, mdp
->phy_interface
);
1075 if (IS_ERR(phydev
)) {
1076 dev_err(&ndev
->dev
, "phy_connect failed\n");
1077 return PTR_ERR(phydev
);
1080 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1081 phydev
->addr
, phydev
->drv
->name
);
1083 mdp
->phydev
= phydev
;
1088 /* PHY control start function */
1089 static int sh_eth_phy_start(struct net_device
*ndev
)
1091 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1094 ret
= sh_eth_phy_init(ndev
);
1098 /* reset phy - this also wakes it from PDOWN */
1099 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1100 phy_start(mdp
->phydev
);
1105 static int sh_eth_get_settings(struct net_device
*ndev
,
1106 struct ethtool_cmd
*ecmd
)
1108 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1109 unsigned long flags
;
1112 spin_lock_irqsave(&mdp
->lock
, flags
);
1113 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1114 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1119 static int sh_eth_set_settings(struct net_device
*ndev
,
1120 struct ethtool_cmd
*ecmd
)
1122 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1123 unsigned long flags
;
1126 spin_lock_irqsave(&mdp
->lock
, flags
);
1128 /* disable tx and rx */
1129 sh_eth_rcv_snd_disable(ndev
);
1131 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1135 if (ecmd
->duplex
== DUPLEX_FULL
)
1140 if (mdp
->cd
->set_duplex
)
1141 mdp
->cd
->set_duplex(ndev
);
1146 /* enable tx and rx */
1147 sh_eth_rcv_snd_enable(ndev
);
1149 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1154 static int sh_eth_nway_reset(struct net_device
*ndev
)
1156 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1157 unsigned long flags
;
1160 spin_lock_irqsave(&mdp
->lock
, flags
);
1161 ret
= phy_start_aneg(mdp
->phydev
);
1162 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1167 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1169 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1170 return mdp
->msg_enable
;
1173 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1175 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1176 mdp
->msg_enable
= value
;
1179 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1180 "rx_current", "tx_current",
1181 "rx_dirty", "tx_dirty",
1183 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1185 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1189 return SH_ETH_STATS_LEN
;
1195 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1196 struct ethtool_stats
*stats
, u64
*data
)
1198 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1201 /* device-specific stats */
1202 data
[i
++] = mdp
->cur_rx
;
1203 data
[i
++] = mdp
->cur_tx
;
1204 data
[i
++] = mdp
->dirty_rx
;
1205 data
[i
++] = mdp
->dirty_tx
;
1208 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1210 switch (stringset
) {
1212 memcpy(data
, *sh_eth_gstrings_stats
,
1213 sizeof(sh_eth_gstrings_stats
));
1218 static struct ethtool_ops sh_eth_ethtool_ops
= {
1219 .get_settings
= sh_eth_get_settings
,
1220 .set_settings
= sh_eth_set_settings
,
1221 .nway_reset
= sh_eth_nway_reset
,
1222 .get_msglevel
= sh_eth_get_msglevel
,
1223 .set_msglevel
= sh_eth_set_msglevel
,
1224 .get_link
= ethtool_op_get_link
,
1225 .get_strings
= sh_eth_get_strings
,
1226 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1227 .get_sset_count
= sh_eth_get_sset_count
,
1230 /* network device open function */
1231 static int sh_eth_open(struct net_device
*ndev
)
1234 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1236 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1238 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1239 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1240 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1241 defined(CONFIG_CPU_SUBTYPE_SH7757)
1248 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1252 /* Descriptor set */
1253 ret
= sh_eth_ring_init(ndev
);
1258 ret
= sh_eth_dev_init(ndev
);
1262 /* PHY control start*/
1263 ret
= sh_eth_phy_start(ndev
);
1267 /* Set the timer to check for link beat. */
1268 init_timer(&mdp
->timer
);
1269 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1270 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
1275 free_irq(ndev
->irq
, ndev
);
1276 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1280 /* Timeout function */
1281 static void sh_eth_tx_timeout(struct net_device
*ndev
)
1283 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1284 struct sh_eth_rxdesc
*rxdesc
;
1287 netif_stop_queue(ndev
);
1289 if (netif_msg_timer(mdp
))
1290 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
1291 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
1293 /* tx_errors count up */
1294 mdp
->stats
.tx_errors
++;
1297 del_timer_sync(&mdp
->timer
);
1299 /* Free all the skbuffs in the Rx queue. */
1300 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1301 rxdesc
= &mdp
->rx_ring
[i
];
1303 rxdesc
->addr
= 0xBADF00D0;
1304 if (mdp
->rx_skbuff
[i
])
1305 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1306 mdp
->rx_skbuff
[i
] = NULL
;
1308 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1309 if (mdp
->tx_skbuff
[i
])
1310 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1311 mdp
->tx_skbuff
[i
] = NULL
;
1315 sh_eth_dev_init(ndev
);
1318 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1319 add_timer(&mdp
->timer
);
1322 /* Packet transmit function */
1323 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1325 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1326 struct sh_eth_txdesc
*txdesc
;
1328 unsigned long flags
;
1330 spin_lock_irqsave(&mdp
->lock
, flags
);
1331 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
1332 if (!sh_eth_txfree(ndev
)) {
1333 if (netif_msg_tx_queued(mdp
))
1334 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
1335 netif_stop_queue(ndev
);
1336 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1337 return NETDEV_TX_BUSY
;
1340 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1342 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
1343 mdp
->tx_skbuff
[entry
] = skb
;
1344 txdesc
= &mdp
->tx_ring
[entry
];
1345 txdesc
->addr
= virt_to_phys(skb
->data
);
1347 if (!mdp
->cd
->hw_swap
)
1348 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
1351 __flush_purge_region(skb
->data
, skb
->len
);
1352 if (skb
->len
< ETHERSMALL
)
1353 txdesc
->buffer_length
= ETHERSMALL
;
1355 txdesc
->buffer_length
= skb
->len
;
1357 if (entry
>= TX_RING_SIZE
- 1)
1358 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
1360 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
1364 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
1365 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1367 return NETDEV_TX_OK
;
1370 /* device close function */
1371 static int sh_eth_close(struct net_device
*ndev
)
1373 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1376 netif_stop_queue(ndev
);
1378 /* Disable interrupts by clearing the interrupt mask. */
1379 sh_eth_write(ndev
, 0x0000, EESIPR
);
1381 /* Stop the chip's Tx and Rx processes. */
1382 sh_eth_write(ndev
, 0, EDTRR
);
1383 sh_eth_write(ndev
, 0, EDRRR
);
1385 /* PHY Disconnect */
1387 phy_stop(mdp
->phydev
);
1388 phy_disconnect(mdp
->phydev
);
1391 free_irq(ndev
->irq
, ndev
);
1393 del_timer_sync(&mdp
->timer
);
1395 /* Free all the skbuffs in the Rx queue. */
1396 sh_eth_ring_free(ndev
);
1398 /* free DMA buffer */
1399 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1400 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1402 /* free DMA buffer */
1403 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1404 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1406 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1411 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1413 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1415 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1417 mdp
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
1418 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
1419 mdp
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
1420 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
1421 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
1422 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
1423 if (sh_eth_is_gether(mdp
)) {
1424 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
1425 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
1426 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
1427 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
1429 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
1430 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
1432 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1437 /* ioctl to device funciotn*/
1438 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1441 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1442 struct phy_device
*phydev
= mdp
->phydev
;
1444 if (!netif_running(ndev
))
1450 return phy_mii_ioctl(phydev
, rq
, cmd
);
1453 #if defined(SH_ETH_HAS_TSU)
1454 /* Multicast reception directions set */
1455 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1457 if (ndev
->flags
& IFF_PROMISC
) {
1458 /* Set promiscuous. */
1459 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_MCT
) |
1462 /* Normal, unicast/broadcast-only mode. */
1463 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) |
1467 #endif /* SH_ETH_HAS_TSU */
1469 /* SuperH's TSU register init function */
1470 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
1472 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
1473 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
1474 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
1475 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
1476 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
1477 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
1478 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
1479 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
1480 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
1481 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
1482 if (sh_eth_is_gether(mdp
)) {
1483 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
1484 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
1486 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
1487 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
1489 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
1490 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
1491 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
1492 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1493 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
1494 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
1495 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
1498 /* MDIO bus release function */
1499 static int sh_mdio_release(struct net_device
*ndev
)
1501 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1503 /* unregister mdio bus */
1504 mdiobus_unregister(bus
);
1506 /* remove mdio bus info from net_device */
1507 dev_set_drvdata(&ndev
->dev
, NULL
);
1509 /* free interrupts memory */
1512 /* free bitbang info */
1513 free_mdio_bitbang(bus
);
1518 /* MDIO bus init function */
1519 static int sh_mdio_init(struct net_device
*ndev
, int id
)
1522 struct bb_info
*bitbang
;
1523 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1525 /* create bit control struct for PHY */
1526 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1533 bitbang
->addr
= ndev
->base_addr
+ mdp
->reg_offset
[PIR
];
1534 bitbang
->mdi_msk
= 0x08;
1535 bitbang
->mdo_msk
= 0x04;
1536 bitbang
->mmd_msk
= 0x02;/* MMD */
1537 bitbang
->mdc_msk
= 0x01;
1538 bitbang
->ctrl
.ops
= &bb_ops
;
1540 /* MII controller setting */
1541 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1542 if (!mdp
->mii_bus
) {
1544 goto out_free_bitbang
;
1547 /* Hook up MII support for ethtool */
1548 mdp
->mii_bus
->name
= "sh_mii";
1549 mdp
->mii_bus
->parent
= &ndev
->dev
;
1550 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", id
);
1553 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1554 if (!mdp
->mii_bus
->irq
) {
1559 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1560 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1562 /* regist mdio bus */
1563 ret
= mdiobus_register(mdp
->mii_bus
);
1567 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1572 kfree(mdp
->mii_bus
->irq
);
1575 free_mdio_bitbang(mdp
->mii_bus
);
1584 static const u16
*sh_eth_get_register_offset(int register_type
)
1586 const u16
*reg_offset
= NULL
;
1588 switch (register_type
) {
1589 case SH_ETH_REG_GIGABIT
:
1590 reg_offset
= sh_eth_offset_gigabit
;
1592 case SH_ETH_REG_FAST_SH4
:
1593 reg_offset
= sh_eth_offset_fast_sh4
;
1595 case SH_ETH_REG_FAST_SH3_SH2
:
1596 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
1599 printk(KERN_ERR
"Unknown register type (%d)\n", register_type
);
1606 static const struct net_device_ops sh_eth_netdev_ops
= {
1607 .ndo_open
= sh_eth_open
,
1608 .ndo_stop
= sh_eth_close
,
1609 .ndo_start_xmit
= sh_eth_start_xmit
,
1610 .ndo_get_stats
= sh_eth_get_stats
,
1611 #if defined(SH_ETH_HAS_TSU)
1612 .ndo_set_multicast_list
= sh_eth_set_multicast_list
,
1614 .ndo_tx_timeout
= sh_eth_tx_timeout
,
1615 .ndo_do_ioctl
= sh_eth_do_ioctl
,
1616 .ndo_validate_addr
= eth_validate_addr
,
1617 .ndo_set_mac_address
= eth_mac_addr
,
1618 .ndo_change_mtu
= eth_change_mtu
,
1621 static int sh_eth_drv_probe(struct platform_device
*pdev
)
1624 struct resource
*res
;
1625 struct net_device
*ndev
= NULL
;
1626 struct sh_eth_private
*mdp
;
1627 struct sh_eth_plat_data
*pd
;
1630 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1631 if (unlikely(res
== NULL
)) {
1632 dev_err(&pdev
->dev
, "invalid resource\n");
1637 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
1639 dev_err(&pdev
->dev
, "Could not allocate device.\n");
1644 /* The sh Ether-specific entries in the device structure. */
1645 ndev
->base_addr
= res
->start
;
1651 ret
= platform_get_irq(pdev
, 0);
1658 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1660 /* Fill in the fields of the device structure with ethernet values. */
1663 mdp
= netdev_priv(ndev
);
1664 spin_lock_init(&mdp
->lock
);
1666 pm_runtime_enable(&pdev
->dev
);
1667 pm_runtime_resume(&pdev
->dev
);
1669 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
1671 mdp
->phy_id
= pd
->phy
;
1672 mdp
->phy_interface
= pd
->phy_interface
;
1674 mdp
->edmac_endian
= pd
->edmac_endian
;
1675 mdp
->no_ether_link
= pd
->no_ether_link
;
1676 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
1677 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
1680 mdp
->cd
= &sh_eth_my_cpu_data
;
1681 sh_eth_set_default_cpu_data(mdp
->cd
);
1684 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
1685 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
1686 ndev
->watchdog_timeo
= TX_TIMEOUT
;
1688 /* debug message level */
1689 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
1690 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
1691 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
1693 /* read and set MAC address */
1694 read_mac_address(ndev
, pd
->mac_addr
);
1696 /* First device only init */
1699 struct resource
*rtsu
;
1700 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1702 dev_err(&pdev
->dev
, "Not found TSU resource\n");
1705 mdp
->tsu_addr
= ioremap(rtsu
->start
,
1706 resource_size(rtsu
));
1708 if (mdp
->cd
->chip_reset
)
1709 mdp
->cd
->chip_reset(ndev
);
1712 /* TSU init (Init only)*/
1713 sh_eth_tsu_init(mdp
);
1717 /* network device register */
1718 ret
= register_netdev(ndev
);
1723 ret
= sh_mdio_init(ndev
, pdev
->id
);
1725 goto out_unregister
;
1727 /* print device infomation */
1728 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1729 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
1731 platform_set_drvdata(pdev
, ndev
);
1736 unregister_netdev(ndev
);
1741 iounmap(mdp
->tsu_addr
);
1749 static int sh_eth_drv_remove(struct platform_device
*pdev
)
1751 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1752 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1754 iounmap(mdp
->tsu_addr
);
1755 sh_mdio_release(ndev
);
1756 unregister_netdev(ndev
);
1757 pm_runtime_disable(&pdev
->dev
);
1759 platform_set_drvdata(pdev
, NULL
);
1764 static int sh_eth_runtime_nop(struct device
*dev
)
1767 * Runtime PM callback shared between ->runtime_suspend()
1768 * and ->runtime_resume(). Simply returns success.
1770 * This driver re-initializes all registers after
1771 * pm_runtime_get_sync() anyway so there is no need
1772 * to save and restore registers here.
1777 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
1778 .runtime_suspend
= sh_eth_runtime_nop
,
1779 .runtime_resume
= sh_eth_runtime_nop
,
1782 static struct platform_driver sh_eth_driver
= {
1783 .probe
= sh_eth_drv_probe
,
1784 .remove
= sh_eth_drv_remove
,
1787 .pm
= &sh_eth_dev_pm_ops
,
1791 static int __init
sh_eth_init(void)
1793 return platform_driver_register(&sh_eth_driver
);
1796 static void __exit
sh_eth_cleanup(void)
1798 platform_driver_unregister(&sh_eth_driver
);
1801 module_init(sh_eth_init
);
1802 module_exit(sh_eth_cleanup
);
1804 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1805 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1806 MODULE_LICENSE("GPL v2");