drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/kfifo.h>
  19
  20 #include "tilcdc_drv.h"
  21 #include "tilcdc_regs.h"
  22
  23 struct tilcdc_crtc {
  24         struct drm_crtc base;
  25
  26         const struct tilcdc_panel_info *info;
  27         uint32_t dirty;
  28         dma_addr_t start, end;
  29         struct drm_pending_vblank_event *event;
  30         int dpms;
  31         wait_queue_head_t frame_done_wq;
  32         bool frame_done;
  33
  34         /* fb currently set to scanout 0/1: */
  35         struct drm_framebuffer *scanout[2];
  36
  37         /* for deferred fb unref's: */
  38         DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *);
  39         struct work_struct work;
  40 };
  41 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  42
  43 static void unref_worker(struct work_struct *work)
  44 {
  45         struct tilcdc_crtc *tilcdc_crtc = container_of(work, struct tilcdc_crtc, work);
  46         struct drm_device *dev = tilcdc_crtc->base.dev;
  47         struct drm_framebuffer *fb;
  48
  49         mutex_lock(&dev->mode_config.mutex);
  50         while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb))
  51                 drm_framebuffer_unreference(fb);
  52         mutex_unlock(&dev->mode_config.mutex);
  53 }
  54
  55 static void set_scanout(struct drm_crtc *crtc, int n)
  56 {
  57         static const uint32_t base_reg[] = {
  58                         LCDC_DMA_FB_BASE_ADDR_0_REG, LCDC_DMA_FB_BASE_ADDR_1_REG,
  59         };
  60         static const uint32_t ceil_reg[] = {
  61                         LCDC_DMA_FB_CEILING_ADDR_0_REG, LCDC_DMA_FB_CEILING_ADDR_1_REG,
  62         };
  63         static const uint32_t stat[] = {
  64                         LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
  65         };
  66         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  67         struct drm_device *dev = crtc->dev;
  68
  69         pm_runtime_get_sync(dev->dev);
  70         tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
  71         tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
  72         if (tilcdc_crtc->scanout[n]) {
  73                 if (kfifo_put(&tilcdc_crtc->unref_fifo,
  74                                 (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) {
  75                         struct tilcdc_drm_private *priv = dev->dev_private;
  76                         queue_work(priv->wq, &tilcdc_crtc->work);
  77                 } else {
  78                         dev_err(dev->dev, "unref fifo full!\n");
  79                         drm_framebuffer_unreference(tilcdc_crtc->scanout[n]);
  80                 }
  81         }
  82         tilcdc_crtc->scanout[n] = crtc->fb;
  83         drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
  84         tilcdc_crtc->dirty &= ~stat[n];
  85         pm_runtime_put_sync(dev->dev);
  86 }
  87
  88 static void update_scanout(struct drm_crtc *crtc)
  89 {
  90         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  91         struct drm_device *dev = crtc->dev;
  92         struct drm_framebuffer *fb = crtc->fb;
  93         struct drm_gem_cma_object *gem;
  94         unsigned int depth, bpp;
  95
  96         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  97         gem = drm_fb_cma_get_gem_obj(fb, 0);
  98
  99         tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
 100                         (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
 101
 102         tilcdc_crtc->end = tilcdc_crtc->start +
 103                         (crtc->mode.vdisplay * fb->pitches[0]);
 104
 105         if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
 106                 /* already enabled, so just mark the frames that need
 107                  * updating and they will be updated on vblank:
 108                  */
 109                 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
 110                 drm_vblank_get(dev, 0);
 111         } else {
 112                 /* not enabled yet, so update registers immediately: */
 113                 set_scanout(crtc, 0);
 114                 set_scanout(crtc, 1);
 115         }
 116 }
 117
 118 static void start(struct drm_crtc *crtc)
 119 {
 120         struct drm_device *dev = crtc->dev;
 121         struct tilcdc_drm_private *priv = dev->dev_private;
 122
 123         if (priv->rev == 2) {
 124                 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 125                 msleep(1);
 126                 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 127                 msleep(1);
 128         }
 129
 130         tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 131         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 132         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 133 }
 134
 135 static void stop(struct drm_crtc *crtc)
 136 {
 137         struct drm_device *dev = crtc->dev;
 138
 139         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 140 }
 141
 142 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 143 {
 144         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 145
 146         WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
 147
 148         drm_crtc_cleanup(crtc);
 149         WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo));
 150         kfifo_free(&tilcdc_crtc->unref_fifo);
 151         kfree(tilcdc_crtc);
 152 }
 153
 154 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 155                 struct drm_framebuffer *fb,
 156                 struct drm_pending_vblank_event *event)
 157 {
 158         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 159         struct drm_device *dev = crtc->dev;
 160
 161         if (tilcdc_crtc->event) {
 162                 dev_err(dev->dev, "already pending page flip!\n");
 163                 return -EBUSY;
 164         }
 165
 166         crtc->fb = fb;
 167         tilcdc_crtc->event = event;
 168         update_scanout(crtc);
 169
 170         return 0;
 171 }
 172
 173 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 174 {
 175         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 176         struct drm_device *dev = crtc->dev;
 177         struct tilcdc_drm_private *priv = dev->dev_private;
 178
 179         /* we really only care about on or off: */
 180         if (mode != DRM_MODE_DPMS_ON)
 181                 mode = DRM_MODE_DPMS_OFF;
 182
 183         if (tilcdc_crtc->dpms == mode)
 184                 return;
 185
 186         tilcdc_crtc->dpms = mode;
 187
 188         pm_runtime_get_sync(dev->dev);
 189
 190         if (mode == DRM_MODE_DPMS_ON) {
 191                 pm_runtime_forbid(dev->dev);
 192                 start(crtc);
 193         } else {
 194                 tilcdc_crtc->frame_done = false;
 195                 stop(crtc);
 196
 197                 /* if necessary wait for framedone irq which will still come
 198                  * before putting things to sleep..
 199                  */
 200                 if (priv->rev == 2) {
 201                         int ret = wait_event_timeout(
 202                                         tilcdc_crtc->frame_done_wq,
 203                                         tilcdc_crtc->frame_done,
 204                                         msecs_to_jiffies(50));
 205                         if (ret == 0)
 206                                 dev_err(dev->dev, "timeout waiting for framedone\n");
 207                 }
 208                 pm_runtime_allow(dev->dev);
 209         }
 210
 211         pm_runtime_put_sync(dev->dev);
 212 }
 213
 214 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 215                 const struct drm_display_mode *mode,
 216                 struct drm_display_mode *adjusted_mode)
 217 {
 218         return true;
 219 }
 220
 221 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
 222 {
 223         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 224 }
 225
 226 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
 227 {
 228         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 229 }
 230
 231 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 232                 struct drm_display_mode *mode,
 233                 struct drm_display_mode *adjusted_mode,
 234                 int x, int y,
 235                 struct drm_framebuffer *old_fb)
 236 {
 237         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 238         struct drm_device *dev = crtc->dev;
 239         struct tilcdc_drm_private *priv = dev->dev_private;
 240         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 241         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 242         int ret;
 243
 244         ret = tilcdc_crtc_mode_valid(crtc, mode);
 245         if (WARN_ON(ret))
 246                 return ret;
 247
 248         if (WARN_ON(!info))
 249                 return -EINVAL;
 250
 251         pm_runtime_get_sync(dev->dev);
 252
 253         /* Configure the Burst Size and fifo threshold of DMA: */
 254         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 255         switch (info->dma_burst_sz) {
 256         case 1:
 257                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 258                 break;
 259         case 2:
 260                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 261                 break;
 262         case 4:
 263                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 264                 break;
 265         case 8:
 266                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 267                 break;
 268         case 16:
 269                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 270                 break;
 271         default:
 272                 return -EINVAL;
 273         }
 274         reg |= (info->fifo_th << 8);
 275         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 276
 277         /* Configure timings: */
 278         hbp = mode->htotal - mode->hsync_end;
 279         hfp = mode->hsync_start - mode->hdisplay;
 280         hsw = mode->hsync_end - mode->hsync_start;
 281         vbp = mode->vtotal - mode->vsync_end;
 282         vfp = mode->vsync_start - mode->vdisplay;
 283         vsw = mode->vsync_end - mode->vsync_start;
 284
 285         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 286                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 287
 288         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 289         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 290         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 291                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 292
 293         /*
 294          * subtract one from hfp, hbp, hsw because the hardware uses
 295          * a value of 0 as 1
 296          */
 297         if (priv->rev == 2) {
 298                 reg |= ((hfp-1) & 0x300) >> 8;
 299                 reg |= ((hbp-1) & 0x300) >> 4;
 300                 reg |= ((hsw-1) & 0x3c0) << 21;
 301         }
 302         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 303
 304         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 305                 (((hbp-1) & 0xff) << 24) |
 306                 (((hfp-1) & 0xff) << 16) |
 307                 (((hsw-1) & 0x3f) << 10);
 308         if (priv->rev == 2)
 309                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 310         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 311
 312         reg = ((mode->vdisplay - 1) & 0x3ff) |
 313                 ((vbp & 0xff) << 24) |
 314                 ((vfp & 0xff) << 16) |
 315                 (((vsw-1) & 0x3f) << 10);
 316         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 317
 318         /*
 319          * be sure to set Bit 10 for the V2 LCDC controller,
 320          * otherwise limited to 1024 pixels width, stopping
 321          * 1920x1080 being suppoted.
 322          */
 323         if (priv->rev == 2) {
 324                 if ((mode->vdisplay - 1) & 0x400) {
 325                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 326                                 LCDC_LPP_B10);
 327                 } else {
 328                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 329                                 LCDC_LPP_B10);
 330                 }
 331         }
 332
 333         /* Configure display type: */
 334         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 335                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 336                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 337         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 338         if (info->tft_alt_mode)
 339                 reg |= LCDC_TFT_ALT_ENABLE;
 340         if (priv->rev == 2) {
 341                 unsigned int depth, bpp;
 342
 343                 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp);
 344                 switch (bpp) {
 345                 case 16:
 346                         break;
 347                 case 32:
 348                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 349                         /* fallthrough */
 350                 case 24:
 351                         reg |= LCDC_V2_TFT_24BPP_MODE;
 352                         break;
 353                 default:
 354                         dev_err(dev->dev, "invalid pixel format\n");
 355                         return -EINVAL;
 356                 }
 357         }
 358         reg |= info->fdd < 12;
 359         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 360
 361         if (info->invert_pxl_clk)
 362                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 363         else
 364                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 365
 366         if (info->sync_ctrl)
 367                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 368         else
 369                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 370
 371         if (info->sync_edge)
 372                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 373         else
 374                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 375
 376         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 377                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 378         else
 379                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 380
 381         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 382                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 383         else
 384                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 385
 386         if (info->raster_order)
 387                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 388         else
 389                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 390
 391
 392         update_scanout(crtc);
 393         tilcdc_crtc_update_clk(crtc);
 394
 395         pm_runtime_put_sync(dev->dev);
 396
 397         return 0;
 398 }
 399
 400 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 401                 struct drm_framebuffer *old_fb)
 402 {
 403         update_scanout(crtc);
 404         return 0;
 405 }
 406
 407 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 408                 .destroy        = tilcdc_crtc_destroy,
 409                 .set_config     = drm_crtc_helper_set_config,
 410                 .page_flip      = tilcdc_crtc_page_flip,
 411 };
 412
 413 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 414                 .dpms           = tilcdc_crtc_dpms,
 415                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 416                 .prepare        = tilcdc_crtc_prepare,
 417                 .commit         = tilcdc_crtc_commit,
 418                 .mode_set       = tilcdc_crtc_mode_set,
 419                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 420 };
 421
 422 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         struct tilcdc_drm_private *priv = dev->dev_private;
 426         int max_width = 0;
 427
 428         if (priv->rev == 1)
 429                 max_width = 1024;
 430         else if (priv->rev == 2)
 431                 max_width = 2048;
 432
 433         return max_width;
 434 }
 435
 436 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 437 {
 438         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 439         unsigned int bandwidth;
 440         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 441
 442         /*
 443          * check to see if the width is within the range that
 444          * the LCD Controller physically supports
 445          */
 446         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 447                 return MODE_VIRTUAL_X;
 448
 449         /* width must be multiple of 16 */
 450         if (mode->hdisplay & 0xf)
 451                 return MODE_VIRTUAL_X;
 452
 453         if (mode->vdisplay > 2048)
 454                 return MODE_VIRTUAL_Y;
 455
 456         DBG("Processing mode %dx%d@%d with pixel clock %d",
 457                 mode->hdisplay, mode->vdisplay,
 458                 drm_mode_vrefresh(mode), mode->clock);
 459
 460         hbp = mode->htotal - mode->hsync_end;
 461         hfp = mode->hsync_start - mode->hdisplay;
 462         hsw = mode->hsync_end - mode->hsync_start;
 463         vbp = mode->vtotal - mode->vsync_end;
 464         vfp = mode->vsync_start - mode->vdisplay;
 465         vsw = mode->vsync_end - mode->vsync_start;
 466
 467         if ((hbp-1) & ~0x3ff) {
 468                 DBG("Pruning mode: Horizontal Back Porch out of range");
 469                 return MODE_HBLANK_WIDE;
 470         }
 471
 472         if ((hfp-1) & ~0x3ff) {
 473                 DBG("Pruning mode: Horizontal Front Porch out of range");
 474                 return MODE_HBLANK_WIDE;
 475         }
 476
 477         if ((hsw-1) & ~0x3ff) {
 478                 DBG("Pruning mode: Horizontal Sync Width out of range");
 479                 return MODE_HSYNC_WIDE;
 480         }
 481
 482         if (vbp & ~0xff) {
 483                 DBG("Pruning mode: Vertical Back Porch out of range");
 484                 return MODE_VBLANK_WIDE;
 485         }
 486
 487         if (vfp & ~0xff) {
 488                 DBG("Pruning mode: Vertical Front Porch out of range");
 489                 return MODE_VBLANK_WIDE;
 490         }
 491
 492         if ((vsw-1) & ~0x3f) {
 493                 DBG("Pruning mode: Vertical Sync Width out of range");
 494                 return MODE_VSYNC_WIDE;
 495         }
 496
 497         /*
 498          * some devices have a maximum allowed pixel clock
 499          * configured from the DT
 500          */
 501         if (mode->clock > priv->max_pixelclock) {
 502                 DBG("Pruning mode, pixel clock too high");
 503                 return MODE_CLOCK_HIGH;
 504         }
 505
 506         /*
 507          * some devices further limit the max horizontal resolution
 508          * configured from the DT
 509          */
 510         if (mode->hdisplay > priv->max_width)
 511                 return MODE_BAD_WIDTH;
 512
 513         /* filter out modes that would require too much memory bandwidth: */
 514         bandwidth = mode->hdisplay * mode->vdisplay *
 515                 drm_mode_vrefresh(mode);
 516         if (bandwidth > priv->max_bandwidth) {
 517                 DBG("Pruning mode, exceeds defined bandwidth limit");
 518                 return MODE_BAD;
 519         }
 520
 521         return MODE_OK;
 522 }
 523
 524 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 525                 const struct tilcdc_panel_info *info)
 526 {
 527         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 528         tilcdc_crtc->info = info;
 529 }
 530
 531 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 532 {
 533         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 534         struct drm_device *dev = crtc->dev;
 535         struct tilcdc_drm_private *priv = dev->dev_private;
 536         int dpms = tilcdc_crtc->dpms;
 537         unsigned int lcd_clk, div;
 538         int ret;
 539
 540         pm_runtime_get_sync(dev->dev);
 541
 542         if (dpms == DRM_MODE_DPMS_ON)
 543                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 544
 545         /* in raster mode, minimum divisor is 2: */
 546         ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
 547         if (ret) {
 548                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 549                                 crtc->mode.clock);
 550                 goto out;
 551         }
 552
 553         lcd_clk = clk_get_rate(priv->clk);
 554         div = lcd_clk / (crtc->mode.clock * 1000);
 555
 556         DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
 557         DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
 558
 559         /* Configure the LCD clock divisor. */
 560         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
 561                         LCDC_RASTER_MODE);
 562
 563         if (priv->rev == 2)
 564                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 565                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 566                                 LCDC_V2_CORE_CLK_EN);
 567
 568         if (dpms == DRM_MODE_DPMS_ON)
 569                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 570
 571 out:
 572         pm_runtime_put_sync(dev->dev);
 573 }
 574
 575 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 576 {
 577         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 578         struct drm_device *dev = crtc->dev;
 579         struct tilcdc_drm_private *priv = dev->dev_private;
 580         uint32_t stat = tilcdc_read_irqstatus(dev);
 581
 582         if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
 583                 stop(crtc);
 584                 dev_err(dev->dev, "error: %08x\n", stat);
 585                 tilcdc_clear_irqstatus(dev, stat);
 586                 start(crtc);
 587         } else if (stat & LCDC_PL_LOAD_DONE) {
 588                 tilcdc_clear_irqstatus(dev, stat);
 589         } else {
 590                 struct drm_pending_vblank_event *event;
 591                 unsigned long flags;
 592                 uint32_t dirty = tilcdc_crtc->dirty & stat;
 593
 594                 tilcdc_clear_irqstatus(dev, stat);
 595
 596                 if (dirty & LCDC_END_OF_FRAME0)
 597                         set_scanout(crtc, 0);
 598
 599                 if (dirty & LCDC_END_OF_FRAME1)
 600                         set_scanout(crtc, 1);
 601
 602                 drm_handle_vblank(dev, 0);
 603
 604                 spin_lock_irqsave(&dev->event_lock, flags);
 605                 event = tilcdc_crtc->event;
 606                 tilcdc_crtc->event = NULL;
 607                 if (event)
 608                         drm_send_vblank_event(dev, 0, event);
 609                 spin_unlock_irqrestore(&dev->event_lock, flags);
 610
 611                 if (dirty && !tilcdc_crtc->dirty)
 612                         drm_vblank_put(dev, 0);
 613         }
 614
 615         if (priv->rev == 2) {
 616                 if (stat & LCDC_FRAME_DONE) {
 617                         tilcdc_crtc->frame_done = true;
 618                         wake_up(&tilcdc_crtc->frame_done_wq);
 619                 }
 620                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 621         }
 622
 623         return IRQ_HANDLED;
 624 }
 625
 626 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 627 {
 628         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 629         struct drm_pending_vblank_event *event;
 630         struct drm_device *dev = crtc->dev;
 631         unsigned long flags;
 632
 633         /* Destroy the pending vertical blanking event associated with the
 634          * pending page flip, if any, and disable vertical blanking interrupts.
 635          */
 636         spin_lock_irqsave(&dev->event_lock, flags);
 637         event = tilcdc_crtc->event;
 638         if (event && event->base.file_priv == file) {
 639                 tilcdc_crtc->event = NULL;
 640                 event->base.destroy(&event->base);
 641                 drm_vblank_put(dev, 0);
 642         }
 643         spin_unlock_irqrestore(&dev->event_lock, flags);
 644 }
 645
 646 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 647 {
 648         struct tilcdc_crtc *tilcdc_crtc;
 649         struct drm_crtc *crtc;
 650         int ret;
 651
 652         tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
 653         if (!tilcdc_crtc) {
 654                 dev_err(dev->dev, "allocation failed\n");
 655                 return NULL;
 656         }
 657
 658         crtc = &tilcdc_crtc->base;
 659
 660         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 661         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 662
 663         ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL);
 664         if (ret) {
 665                 dev_err(dev->dev, "could not allocate unref FIFO\n");
 666                 goto fail;
 667         }
 668
 669         INIT_WORK(&tilcdc_crtc->work, unref_worker);
 670
 671         ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
 672         if (ret < 0)
 673                 goto fail;
 674
 675         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 676
 677         return crtc;
 678
 679 fail:
 680         tilcdc_crtc_destroy(crtc);
 681         return NULL;
 682 }