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ARM: 6621/1: bitops: remove condition code clobber for CLZ
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_phy.c
blob8f7123e8fc0a8b1ae06ce8c54374ee8f6fd78889
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
34
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49
50 /**
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
57 {
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63 hw->phy.mdio.prtad = phy_addr;
64 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
65 ixgbe_get_phy_id(hw);
66 hw->phy.type =
67 ixgbe_get_phy_type_from_id(hw->phy.id);
68 status = 0;
69 break;
70 }
71 }
72 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0;
74 } else {
75 status = 0;
76 }
77
78 return status;
79 }
80
81 /**
82 * ixgbe_get_phy_id - Get the phy type
83 * @hw: pointer to hardware structure
84 *
85 **/
86 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
87 {
88 u32 status;
89 u16 phy_id_high = 0;
90 u16 phy_id_low = 0;
91
92 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
93 &phy_id_high);
94
95 if (status == 0) {
96 hw->phy.id = (u32)(phy_id_high << 16);
97 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
98 &phy_id_low);
99 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
100 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
101 }
102 return status;
103 }
104
105 /**
106 * ixgbe_get_phy_type_from_id - Get the phy type
107 * @hw: pointer to hardware structure
108 *
109 **/
110 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
111 {
112 enum ixgbe_phy_type phy_type;
113
114 switch (phy_id) {
115 case TN1010_PHY_ID:
116 phy_type = ixgbe_phy_tn;
117 break;
118 case X540_PHY_ID:
119 phy_type = ixgbe_phy_aq;
120 break;
121 case QT2022_PHY_ID:
122 phy_type = ixgbe_phy_qt;
123 break;
124 case ATH_PHY_ID:
125 phy_type = ixgbe_phy_nl;
126 break;
127 default:
128 phy_type = ixgbe_phy_unknown;
129 break;
130 }
131
132 return phy_type;
133 }
134
135 /**
136 * ixgbe_reset_phy_generic - Performs a PHY reset
137 * @hw: pointer to hardware structure
138 **/
139 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
140 {
141 /* Don't reset PHY if it's shut down due to overtemp. */
142 if (!hw->phy.reset_if_overtemp &&
143 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
144 return 0;
145
146 /*
147 * Perform soft PHY reset to the PHY_XS.
148 * This will cause a soft reset to the PHY
149 */
150 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
151 MDIO_CTRL1_RESET);
152 }
153
154 /**
155 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
156 * @hw: pointer to hardware structure
157 * @reg_addr: 32 bit address of PHY register to read
158 * @phy_data: Pointer to read data from PHY register
159 **/
160 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
161 u32 device_type, u16 *phy_data)
162 {
163 u32 command;
164 u32 i;
165 u32 data;
166 s32 status = 0;
167 u16 gssr;
168
169 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
170 gssr = IXGBE_GSSR_PHY1_SM;
171 else
172 gssr = IXGBE_GSSR_PHY0_SM;
173
174 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
175 status = IXGBE_ERR_SWFW_SYNC;
176
177 if (status == 0) {
178 /* Setup and write the address cycle command */
179 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
180 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
181 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
182 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
183
184 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
185
186 /*
187 * Check every 10 usec to see if the address cycle completed.
188 * The MDI Command bit will clear when the operation is
189 * complete
190 */
191 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
192 udelay(10);
193
194 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
195
196 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
197 break;
198 }
199
200 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
201 hw_dbg(hw, "PHY address command did not complete.\n");
202 status = IXGBE_ERR_PHY;
203 }
204
205 if (status == 0) {
206 /*
207 * Address cycle complete, setup and write the read
208 * command
209 */
210 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
211 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
212 (hw->phy.mdio.prtad <<
213 IXGBE_MSCA_PHY_ADDR_SHIFT) |
214 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
215
216 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
217
218 /*
219 * Check every 10 usec to see if the address cycle
220 * completed. The MDI Command bit will clear when the
221 * operation is complete
222 */
223 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
224 udelay(10);
225
226 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
227
228 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
229 break;
230 }
231
232 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
233 hw_dbg(hw, "PHY read command didn't complete\n");
234 status = IXGBE_ERR_PHY;
235 } else {
236 /*
237 * Read operation is complete. Get the data
238 * from MSRWD
239 */
240 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
241 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
242 *phy_data = (u16)(data);
243 }
244 }
245
246 ixgbe_release_swfw_sync(hw, gssr);
247 }
248
249 return status;
250 }
251
252 /**
253 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
254 * @hw: pointer to hardware structure
255 * @reg_addr: 32 bit PHY register to write
256 * @device_type: 5 bit device type
257 * @phy_data: Data to write to the PHY register
258 **/
259 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
260 u32 device_type, u16 phy_data)
261 {
262 u32 command;
263 u32 i;
264 s32 status = 0;
265 u16 gssr;
266
267 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
268 gssr = IXGBE_GSSR_PHY1_SM;
269 else
270 gssr = IXGBE_GSSR_PHY0_SM;
271
272 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
273 status = IXGBE_ERR_SWFW_SYNC;
274
275 if (status == 0) {
276 /* Put the data in the MDI single read and write data register*/
277 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
278
279 /* Setup and write the address cycle command */
280 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
281 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
282 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
283 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
284
285 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
286
287 /*
288 * Check every 10 usec to see if the address cycle completed.
289 * The MDI Command bit will clear when the operation is
290 * complete
291 */
292 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
293 udelay(10);
294
295 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
296
297 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
298 break;
299 }
300
301 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
302 hw_dbg(hw, "PHY address cmd didn't complete\n");
303 status = IXGBE_ERR_PHY;
304 }
305
306 if (status == 0) {
307 /*
308 * Address cycle complete, setup and write the write
309 * command
310 */
311 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
312 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
313 (hw->phy.mdio.prtad <<
314 IXGBE_MSCA_PHY_ADDR_SHIFT) |
315 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
316
317 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
318
319 /*
320 * Check every 10 usec to see if the address cycle
321 * completed. The MDI Command bit will clear when the
322 * operation is complete
323 */
324 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
325 udelay(10);
326
327 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
328
329 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
330 break;
331 }
332
333 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
334 hw_dbg(hw, "PHY address cmd didn't complete\n");
335 status = IXGBE_ERR_PHY;
336 }
337 }
338
339 ixgbe_release_swfw_sync(hw, gssr);
340 }
341
342 return status;
343 }
344
345 /**
346 * ixgbe_setup_phy_link_generic - Set and restart autoneg
347 * @hw: pointer to hardware structure
348 *
349 * Restart autonegotiation and PHY and waits for completion.
350 **/
351 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
352 {
353 s32 status = IXGBE_NOT_IMPLEMENTED;
354 u32 time_out;
355 u32 max_time_out = 10;
356 u16 autoneg_reg;
357
358 /*
359 * Set advertisement settings in PHY based on autoneg_advertised
360 * settings. If autoneg_advertised = 0, then advertise default values
361 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
362 * for a 1G.
363 */
364 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
365
366 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
367 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
368 else
369 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
370
371 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
372
373 /* Restart PHY autonegotiation and wait for completion */
374 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
375
376 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
377
378 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
379
380 /* Wait for autonegotiation to finish */
381 for (time_out = 0; time_out < max_time_out; time_out++) {
382 udelay(10);
383 /* Restart PHY autonegotiation and wait for completion */
384 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
385 &autoneg_reg);
386
387 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
388 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
389 status = 0;
390 break;
391 }
392 }
393
394 if (time_out == max_time_out)
395 status = IXGBE_ERR_LINK_SETUP;
396
397 return status;
398 }
399
400 /**
401 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
402 * @hw: pointer to hardware structure
403 * @speed: new link speed
404 * @autoneg: true if autonegotiation enabled
405 **/
406 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
407 ixgbe_link_speed speed,
408 bool autoneg,
409 bool autoneg_wait_to_complete)
410 {
411
412 /*
413 * Clear autoneg_advertised and set new values based on input link
414 * speed.
415 */
416 hw->phy.autoneg_advertised = 0;
417
418 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
419 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
420
421 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
422 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
423
424 /* Setup link based on the new speed settings */
425 hw->phy.ops.setup_link(hw);
426
427 return 0;
428 }
429
430 /**
431 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
432 * @hw: pointer to hardware structure
433 * @speed: pointer to link speed
434 * @autoneg: boolean auto-negotiation value
435 *
436 * Determines the link capabilities by reading the AUTOC register.
437 */
438 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
439 ixgbe_link_speed *speed,
440 bool *autoneg)
441 {
442 s32 status = IXGBE_ERR_LINK_SETUP;
443 u16 speed_ability;
444
445 *speed = 0;
446 *autoneg = true;
447
448 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
449 &speed_ability);
450
451 if (status == 0) {
452 if (speed_ability & MDIO_SPEED_10G)
453 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
454 if (speed_ability & MDIO_PMA_SPEED_1000)
455 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
456 if (speed_ability & MDIO_PMA_SPEED_100)
457 *speed |= IXGBE_LINK_SPEED_100_FULL;
458 }
459
460 return status;
461 }
462
463 /**
464 * ixgbe_reset_phy_nl - Performs a PHY reset
465 * @hw: pointer to hardware structure
466 **/
467 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
468 {
469 u16 phy_offset, control, eword, edata, block_crc;
470 bool end_data = false;
471 u16 list_offset, data_offset;
472 u16 phy_data = 0;
473 s32 ret_val = 0;
474 u32 i;
475
476 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
477
478 /* reset the PHY and poll for completion */
479 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
480 (phy_data | MDIO_CTRL1_RESET));
481
482 for (i = 0; i < 100; i++) {
483 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
484 &phy_data);
485 if ((phy_data & MDIO_CTRL1_RESET) == 0)
486 break;
487 msleep(10);
488 }
489
490 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
491 hw_dbg(hw, "PHY reset did not complete.\n");
492 ret_val = IXGBE_ERR_PHY;
493 goto out;
494 }
495
496 /* Get init offsets */
497 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
498 &data_offset);
499 if (ret_val != 0)
500 goto out;
501
502 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
503 data_offset++;
504 while (!end_data) {
505 /*
506 * Read control word from PHY init contents offset
507 */
508 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
509 control = (eword & IXGBE_CONTROL_MASK_NL) >>
510 IXGBE_CONTROL_SHIFT_NL;
511 edata = eword & IXGBE_DATA_MASK_NL;
512 switch (control) {
513 case IXGBE_DELAY_NL:
514 data_offset++;
515 hw_dbg(hw, "DELAY: %d MS\n", edata);
516 msleep(edata);
517 break;
518 case IXGBE_DATA_NL:
519 hw_dbg(hw, "DATA:\n");
520 data_offset++;
521 hw->eeprom.ops.read(hw, data_offset++,
522 &phy_offset);
523 for (i = 0; i < edata; i++) {
524 hw->eeprom.ops.read(hw, data_offset, &eword);
525 hw->phy.ops.write_reg(hw, phy_offset,
526 MDIO_MMD_PMAPMD, eword);
527 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
528 phy_offset);
529 data_offset++;
530 phy_offset++;
531 }
532 break;
533 case IXGBE_CONTROL_NL:
534 data_offset++;
535 hw_dbg(hw, "CONTROL:\n");
536 if (edata == IXGBE_CONTROL_EOL_NL) {
537 hw_dbg(hw, "EOL\n");
538 end_data = true;
539 } else if (edata == IXGBE_CONTROL_SOL_NL) {
540 hw_dbg(hw, "SOL\n");
541 } else {
542 hw_dbg(hw, "Bad control value\n");
543 ret_val = IXGBE_ERR_PHY;
544 goto out;
545 }
546 break;
547 default:
548 hw_dbg(hw, "Bad control type\n");
549 ret_val = IXGBE_ERR_PHY;
550 goto out;
551 }
552 }
553
554 out:
555 return ret_val;
556 }
557
558 /**
559 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
560 * the PHY type.
561 * @hw: pointer to hardware structure
562 *
563 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
564 **/
565 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
566 {
567 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
568 u32 vendor_oui = 0;
569 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
570 u8 identifier = 0;
571 u8 comp_codes_1g = 0;
572 u8 comp_codes_10g = 0;
573 u8 oui_bytes[3] = {0, 0, 0};
574 u8 cable_tech = 0;
575 u8 cable_spec = 0;
576 u16 enforce_sfp = 0;
577
578 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
579 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
580 status = IXGBE_ERR_SFP_NOT_PRESENT;
581 goto out;
582 }
583
584 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
585 &identifier);
586
587 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
588 status = IXGBE_ERR_SFP_NOT_PRESENT;
589 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
590 if (hw->phy.type != ixgbe_phy_nl) {
591 hw->phy.id = 0;
592 hw->phy.type = ixgbe_phy_unknown;
593 }
594 goto out;
595 }
596
597 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
598 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
599 &comp_codes_1g);
600 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
601 &comp_codes_10g);
602 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
603 &cable_tech);
604
605 /* ID Module
606 * =========
607 * 0 SFP_DA_CU
608 * 1 SFP_SR
609 * 2 SFP_LR
610 * 3 SFP_DA_CORE0 - 82599-specific
611 * 4 SFP_DA_CORE1 - 82599-specific
612 * 5 SFP_SR/LR_CORE0 - 82599-specific
613 * 6 SFP_SR/LR_CORE1 - 82599-specific
614 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
615 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
616 * 9 SFP_1g_cu_CORE0 - 82599-specific
617 * 10 SFP_1g_cu_CORE1 - 82599-specific
618 */
619 if (hw->mac.type == ixgbe_mac_82598EB) {
620 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
621 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
622 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
623 hw->phy.sfp_type = ixgbe_sfp_type_sr;
624 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
625 hw->phy.sfp_type = ixgbe_sfp_type_lr;
626 else
627 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
628 } else if (hw->mac.type == ixgbe_mac_82599EB) {
629 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
630 if (hw->bus.lan_id == 0)
631 hw->phy.sfp_type =
632 ixgbe_sfp_type_da_cu_core0;
633 else
634 hw->phy.sfp_type =
635 ixgbe_sfp_type_da_cu_core1;
636 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
637 hw->phy.ops.read_i2c_eeprom(
638 hw, IXGBE_SFF_CABLE_SPEC_COMP,
639 &cable_spec);
640 if (cable_spec &
641 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
642 if (hw->bus.lan_id == 0)
643 hw->phy.sfp_type =
644 ixgbe_sfp_type_da_act_lmt_core0;
645 else
646 hw->phy.sfp_type =
647 ixgbe_sfp_type_da_act_lmt_core1;
648 } else {
649 hw->phy.sfp_type =
650 ixgbe_sfp_type_unknown;
651 }
652 } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
653 if (hw->bus.lan_id == 0)
654 hw->phy.sfp_type =
655 ixgbe_sfp_type_srlr_core0;
656 else
657 hw->phy.sfp_type =
658 ixgbe_sfp_type_srlr_core1;
659 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
660 if (hw->bus.lan_id == 0)
661 hw->phy.sfp_type =
662 ixgbe_sfp_type_srlr_core0;
663 else
664 hw->phy.sfp_type =
665 ixgbe_sfp_type_srlr_core1;
666 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
667 if (hw->bus.lan_id == 0)
668 hw->phy.sfp_type =
669 ixgbe_sfp_type_1g_cu_core0;
670 else
671 hw->phy.sfp_type =
672 ixgbe_sfp_type_1g_cu_core1;
673 else
674 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
675 }
676
677 if (hw->phy.sfp_type != stored_sfp_type)
678 hw->phy.sfp_setup_needed = true;
679
680 /* Determine if the SFP+ PHY is dual speed or not. */
681 hw->phy.multispeed_fiber = false;
682 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
683 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
684 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
685 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
686 hw->phy.multispeed_fiber = true;
687
688 /* Determine PHY vendor */
689 if (hw->phy.type != ixgbe_phy_nl) {
690 hw->phy.id = identifier;
691 hw->phy.ops.read_i2c_eeprom(hw,
692 IXGBE_SFF_VENDOR_OUI_BYTE0,
693 &oui_bytes[0]);
694 hw->phy.ops.read_i2c_eeprom(hw,
695 IXGBE_SFF_VENDOR_OUI_BYTE1,
696 &oui_bytes[1]);
697 hw->phy.ops.read_i2c_eeprom(hw,
698 IXGBE_SFF_VENDOR_OUI_BYTE2,
699 &oui_bytes[2]);
700
701 vendor_oui =
702 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
703 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
704 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
705
706 switch (vendor_oui) {
707 case IXGBE_SFF_VENDOR_OUI_TYCO:
708 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
709 hw->phy.type =
710 ixgbe_phy_sfp_passive_tyco;
711 break;
712 case IXGBE_SFF_VENDOR_OUI_FTL:
713 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
714 hw->phy.type = ixgbe_phy_sfp_ftl_active;
715 else
716 hw->phy.type = ixgbe_phy_sfp_ftl;
717 break;
718 case IXGBE_SFF_VENDOR_OUI_AVAGO:
719 hw->phy.type = ixgbe_phy_sfp_avago;
720 break;
721 case IXGBE_SFF_VENDOR_OUI_INTEL:
722 hw->phy.type = ixgbe_phy_sfp_intel;
723 break;
724 default:
725 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
726 hw->phy.type =
727 ixgbe_phy_sfp_passive_unknown;
728 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
729 hw->phy.type =
730 ixgbe_phy_sfp_active_unknown;
731 else
732 hw->phy.type = ixgbe_phy_sfp_unknown;
733 break;
734 }
735 }
736
737 /* All passive DA cables are supported */
738 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
739 IXGBE_SFF_DA_ACTIVE_CABLE)) {
740 status = 0;
741 goto out;
742 }
743
744 /* Verify supported 1G SFP modules */
745 if (comp_codes_10g == 0 &&
746 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
747 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
748 hw->phy.type = ixgbe_phy_sfp_unsupported;
749 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
750 goto out;
751 }
752
753 /* Anything else 82598-based is supported */
754 if (hw->mac.type == ixgbe_mac_82598EB) {
755 status = 0;
756 goto out;
757 }
758
759 /* This is guaranteed to be 82599, no need to check for NULL */
760 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
761 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
762 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
763 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
764 /* Make sure we're a supported PHY type */
765 if (hw->phy.type == ixgbe_phy_sfp_intel) {
766 status = 0;
767 } else {
768 hw_dbg(hw, "SFP+ module not supported\n");
769 hw->phy.type = ixgbe_phy_sfp_unsupported;
770 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
771 }
772 } else {
773 status = 0;
774 }
775 }
776
777 out:
778 return status;
779 }
780
781 /**
782 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
783 * if it supports a given SFP+ module type, if so it returns the offsets to the
784 * phy init sequence block.
785 * @hw: pointer to hardware structure
786 * @list_offset: offset to the SFP ID list
787 * @data_offset: offset to the SFP data block
788 **/
789 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
790 u16 *list_offset,
791 u16 *data_offset)
792 {
793 u16 sfp_id;
794 u16 sfp_type = hw->phy.sfp_type;
795
796 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
797 return IXGBE_ERR_SFP_NOT_SUPPORTED;
798
799 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
800 return IXGBE_ERR_SFP_NOT_PRESENT;
801
802 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
803 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
804 return IXGBE_ERR_SFP_NOT_SUPPORTED;
805
806 /*
807 * Limiting active cables and 1G Phys must be initialized as
808 * SR modules
809 */
810 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
811 sfp_type == ixgbe_sfp_type_1g_cu_core0)
812 sfp_type = ixgbe_sfp_type_srlr_core0;
813 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
814 sfp_type == ixgbe_sfp_type_1g_cu_core1)
815 sfp_type = ixgbe_sfp_type_srlr_core1;
816
817 /* Read offset to PHY init contents */
818 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
819
820 if ((!*list_offset) || (*list_offset == 0xFFFF))
821 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
822
823 /* Shift offset to first ID word */
824 (*list_offset)++;
825
826 /*
827 * Find the matching SFP ID in the EEPROM
828 * and program the init sequence
829 */
830 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
831
832 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
833 if (sfp_id == sfp_type) {
834 (*list_offset)++;
835 hw->eeprom.ops.read(hw, *list_offset, data_offset);
836 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
837 hw_dbg(hw, "SFP+ module not supported\n");
838 return IXGBE_ERR_SFP_NOT_SUPPORTED;
839 } else {
840 break;
841 }
842 } else {
843 (*list_offset) += 2;
844 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
845 return IXGBE_ERR_PHY;
846 }
847 }
848
849 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
850 hw_dbg(hw, "No matching SFP+ module found\n");
851 return IXGBE_ERR_SFP_NOT_SUPPORTED;
852 }
853
854 return 0;
855 }
856
857 /**
858 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
859 * @hw: pointer to hardware structure
860 * @byte_offset: EEPROM byte offset to read
861 * @eeprom_data: value read
862 *
863 * Performs byte read operation to SFP module's EEPROM over I2C interface.
864 **/
865 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
866 u8 *eeprom_data)
867 {
868 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
869 IXGBE_I2C_EEPROM_DEV_ADDR,
870 eeprom_data);
871 }
872
873 /**
874 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
875 * @hw: pointer to hardware structure
876 * @byte_offset: EEPROM byte offset to write
877 * @eeprom_data: value to write
878 *
879 * Performs byte write operation to SFP module's EEPROM over I2C interface.
880 **/
881 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
882 u8 eeprom_data)
883 {
884 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
885 IXGBE_I2C_EEPROM_DEV_ADDR,
886 eeprom_data);
887 }
888
889 /**
890 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
891 * @hw: pointer to hardware structure
892 * @byte_offset: byte offset to read
893 * @data: value read
894 *
895 * Performs byte read operation to SFP module's EEPROM over I2C interface at
896 * a specified deivce address.
897 **/
898 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
899 u8 dev_addr, u8 *data)
900 {
901 s32 status = 0;
902 u32 max_retry = 1;
903 u32 retry = 0;
904 bool nack = 1;
905
906 do {
907 ixgbe_i2c_start(hw);
908
909 /* Device Address and write indication */
910 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
911 if (status != 0)
912 goto fail;
913
914 status = ixgbe_get_i2c_ack(hw);
915 if (status != 0)
916 goto fail;
917
918 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
919 if (status != 0)
920 goto fail;
921
922 status = ixgbe_get_i2c_ack(hw);
923 if (status != 0)
924 goto fail;
925
926 ixgbe_i2c_start(hw);
927
928 /* Device Address and read indication */
929 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
930 if (status != 0)
931 goto fail;
932
933 status = ixgbe_get_i2c_ack(hw);
934 if (status != 0)
935 goto fail;
936
937 status = ixgbe_clock_in_i2c_byte(hw, data);
938 if (status != 0)
939 goto fail;
940
941 status = ixgbe_clock_out_i2c_bit(hw, nack);
942 if (status != 0)
943 goto fail;
944
945 ixgbe_i2c_stop(hw);
946 break;
947
948 fail:
949 ixgbe_i2c_bus_clear(hw);
950 retry++;
951 if (retry < max_retry)
952 hw_dbg(hw, "I2C byte read error - Retrying.\n");
953 else
954 hw_dbg(hw, "I2C byte read error.\n");
955
956 } while (retry < max_retry);
957
958 return status;
959 }
960
961 /**
962 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
963 * @hw: pointer to hardware structure
964 * @byte_offset: byte offset to write
965 * @data: value to write
966 *
967 * Performs byte write operation to SFP module's EEPROM over I2C interface at
968 * a specified device address.
969 **/
970 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
971 u8 dev_addr, u8 data)
972 {
973 s32 status = 0;
974 u32 max_retry = 1;
975 u32 retry = 0;
976
977 do {
978 ixgbe_i2c_start(hw);
979
980 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
981 if (status != 0)
982 goto fail;
983
984 status = ixgbe_get_i2c_ack(hw);
985 if (status != 0)
986 goto fail;
987
988 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
989 if (status != 0)
990 goto fail;
991
992 status = ixgbe_get_i2c_ack(hw);
993 if (status != 0)
994 goto fail;
995
996 status = ixgbe_clock_out_i2c_byte(hw, data);
997 if (status != 0)
998 goto fail;
999
1000 status = ixgbe_get_i2c_ack(hw);
1001 if (status != 0)
1002 goto fail;
1003
1004 ixgbe_i2c_stop(hw);
1005 break;
1006
1007 fail:
1008 ixgbe_i2c_bus_clear(hw);
1009 retry++;
1010 if (retry < max_retry)
1011 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1012 else
1013 hw_dbg(hw, "I2C byte write error.\n");
1014 } while (retry < max_retry);
1015
1016 return status;
1017 }
1018
1019 /**
1020 * ixgbe_i2c_start - Sets I2C start condition
1021 * @hw: pointer to hardware structure
1022 *
1023 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1024 **/
1025 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1026 {
1027 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1028
1029 /* Start condition must begin with data and clock high */
1030 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1031 ixgbe_raise_i2c_clk(hw, &i2cctl);
1032
1033 /* Setup time for start condition (4.7us) */
1034 udelay(IXGBE_I2C_T_SU_STA);
1035
1036 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1037
1038 /* Hold time for start condition (4us) */
1039 udelay(IXGBE_I2C_T_HD_STA);
1040
1041 ixgbe_lower_i2c_clk(hw, &i2cctl);
1042
1043 /* Minimum low period of clock is 4.7 us */
1044 udelay(IXGBE_I2C_T_LOW);
1045
1046 }
1047
1048 /**
1049 * ixgbe_i2c_stop - Sets I2C stop condition
1050 * @hw: pointer to hardware structure
1051 *
1052 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1053 **/
1054 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1055 {
1056 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1057
1058 /* Stop condition must begin with data low and clock high */
1059 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1060 ixgbe_raise_i2c_clk(hw, &i2cctl);
1061
1062 /* Setup time for stop condition (4us) */
1063 udelay(IXGBE_I2C_T_SU_STO);
1064
1065 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1066
1067 /* bus free time between stop and start (4.7us)*/
1068 udelay(IXGBE_I2C_T_BUF);
1069 }
1070
1071 /**
1072 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1073 * @hw: pointer to hardware structure
1074 * @data: data byte to clock in
1075 *
1076 * Clocks in one byte data via I2C data/clock
1077 **/
1078 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1079 {
1080 s32 status = 0;
1081 s32 i;
1082 bool bit = 0;
1083
1084 for (i = 7; i >= 0; i--) {
1085 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1086 *data |= bit << i;
1087
1088 if (status != 0)
1089 break;
1090 }
1091
1092 return status;
1093 }
1094
1095 /**
1096 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1097 * @hw: pointer to hardware structure
1098 * @data: data byte clocked out
1099 *
1100 * Clocks out one byte data via I2C data/clock
1101 **/
1102 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1103 {
1104 s32 status = 0;
1105 s32 i;
1106 u32 i2cctl;
1107 bool bit = 0;
1108
1109 for (i = 7; i >= 0; i--) {
1110 bit = (data >> i) & 0x1;
1111 status = ixgbe_clock_out_i2c_bit(hw, bit);
1112
1113 if (status != 0)
1114 break;
1115 }
1116
1117 /* Release SDA line (set high) */
1118 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1119 i2cctl |= IXGBE_I2C_DATA_OUT;
1120 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1121
1122 return status;
1123 }
1124
1125 /**
1126 * ixgbe_get_i2c_ack - Polls for I2C ACK
1127 * @hw: pointer to hardware structure
1128 *
1129 * Clocks in/out one bit via I2C data/clock
1130 **/
1131 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1132 {
1133 s32 status;
1134 u32 i = 0;
1135 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1136 u32 timeout = 10;
1137 bool ack = 1;
1138
1139 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1140
1141 if (status != 0)
1142 goto out;
1143
1144 /* Minimum high period of clock is 4us */
1145 udelay(IXGBE_I2C_T_HIGH);
1146
1147 /* Poll for ACK. Note that ACK in I2C spec is
1148 * transition from 1 to 0 */
1149 for (i = 0; i < timeout; i++) {
1150 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1151 ack = ixgbe_get_i2c_data(&i2cctl);
1152
1153 udelay(1);
1154 if (ack == 0)
1155 break;
1156 }
1157
1158 if (ack == 1) {
1159 hw_dbg(hw, "I2C ack was not received.\n");
1160 status = IXGBE_ERR_I2C;
1161 }
1162
1163 ixgbe_lower_i2c_clk(hw, &i2cctl);
1164
1165 /* Minimum low period of clock is 4.7 us */
1166 udelay(IXGBE_I2C_T_LOW);
1167
1168 out:
1169 return status;
1170 }
1171
1172 /**
1173 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1174 * @hw: pointer to hardware structure
1175 * @data: read data value
1176 *
1177 * Clocks in one bit via I2C data/clock
1178 **/
1179 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1180 {
1181 s32 status;
1182 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1183
1184 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1185
1186 /* Minimum high period of clock is 4us */
1187 udelay(IXGBE_I2C_T_HIGH);
1188
1189 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1190 *data = ixgbe_get_i2c_data(&i2cctl);
1191
1192 ixgbe_lower_i2c_clk(hw, &i2cctl);
1193
1194 /* Minimum low period of clock is 4.7 us */
1195 udelay(IXGBE_I2C_T_LOW);
1196
1197 return status;
1198 }
1199
1200 /**
1201 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1202 * @hw: pointer to hardware structure
1203 * @data: data value to write
1204 *
1205 * Clocks out one bit via I2C data/clock
1206 **/
1207 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1208 {
1209 s32 status;
1210 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1211
1212 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1213 if (status == 0) {
1214 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1215
1216 /* Minimum high period of clock is 4us */
1217 udelay(IXGBE_I2C_T_HIGH);
1218
1219 ixgbe_lower_i2c_clk(hw, &i2cctl);
1220
1221 /* Minimum low period of clock is 4.7 us.
1222 * This also takes care of the data hold time.
1223 */
1224 udelay(IXGBE_I2C_T_LOW);
1225 } else {
1226 status = IXGBE_ERR_I2C;
1227 hw_dbg(hw, "I2C data was not set to %X\n", data);
1228 }
1229
1230 return status;
1231 }
1232 /**
1233 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1234 * @hw: pointer to hardware structure
1235 * @i2cctl: Current value of I2CCTL register
1236 *
1237 * Raises the I2C clock line '0'->'1'
1238 **/
1239 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1240 {
1241 s32 status = 0;
1242
1243 *i2cctl |= IXGBE_I2C_CLK_OUT;
1244
1245 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1246
1247 /* SCL rise time (1000ns) */
1248 udelay(IXGBE_I2C_T_RISE);
1249
1250 return status;
1251 }
1252
1253 /**
1254 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1255 * @hw: pointer to hardware structure
1256 * @i2cctl: Current value of I2CCTL register
1257 *
1258 * Lowers the I2C clock line '1'->'0'
1259 **/
1260 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1261 {
1262
1263 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1264
1265 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1266
1267 /* SCL fall time (300ns) */
1268 udelay(IXGBE_I2C_T_FALL);
1269 }
1270
1271 /**
1272 * ixgbe_set_i2c_data - Sets the I2C data bit
1273 * @hw: pointer to hardware structure
1274 * @i2cctl: Current value of I2CCTL register
1275 * @data: I2C data value (0 or 1) to set
1276 *
1277 * Sets the I2C data bit
1278 **/
1279 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1280 {
1281 s32 status = 0;
1282
1283 if (data)
1284 *i2cctl |= IXGBE_I2C_DATA_OUT;
1285 else
1286 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1287
1288 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1289
1290 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1291 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1292
1293 /* Verify data was set correctly */
1294 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1295 if (data != ixgbe_get_i2c_data(i2cctl)) {
1296 status = IXGBE_ERR_I2C;
1297 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1298 }
1299
1300 return status;
1301 }
1302
1303 /**
1304 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1305 * @hw: pointer to hardware structure
1306 * @i2cctl: Current value of I2CCTL register
1307 *
1308 * Returns the I2C data bit value
1309 **/
1310 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1311 {
1312 bool data;
1313
1314 if (*i2cctl & IXGBE_I2C_DATA_IN)
1315 data = 1;
1316 else
1317 data = 0;
1318
1319 return data;
1320 }
1321
1322 /**
1323 * ixgbe_i2c_bus_clear - Clears the I2C bus
1324 * @hw: pointer to hardware structure
1325 *
1326 * Clears the I2C bus by sending nine clock pulses.
1327 * Used when data line is stuck low.
1328 **/
1329 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1330 {
1331 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1332 u32 i;
1333
1334 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1335
1336 for (i = 0; i < 9; i++) {
1337 ixgbe_raise_i2c_clk(hw, &i2cctl);
1338
1339 /* Min high period of clock is 4us */
1340 udelay(IXGBE_I2C_T_HIGH);
1341
1342 ixgbe_lower_i2c_clk(hw, &i2cctl);
1343
1344 /* Min low period of clock is 4.7us*/
1345 udelay(IXGBE_I2C_T_LOW);
1346 }
1347
1348 /* Put the i2c bus back to default state */
1349 ixgbe_i2c_stop(hw);
1350 }
1351
1352 /**
1353 * ixgbe_check_phy_link_tnx - Determine link and speed status
1354 * @hw: pointer to hardware structure
1355 *
1356 * Reads the VS1 register to determine if link is up and the current speed for
1357 * the PHY.
1358 **/
1359 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1360 bool *link_up)
1361 {
1362 s32 status = 0;
1363 u32 time_out;
1364 u32 max_time_out = 10;
1365 u16 phy_link = 0;
1366 u16 phy_speed = 0;
1367 u16 phy_data = 0;
1368
1369 /* Initialize speed and link to default case */
1370 *link_up = false;
1371 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1372
1373 /*
1374 * Check current speed and link status of the PHY register.
1375 * This is a vendor specific register and may have to
1376 * be changed for other copper PHYs.
1377 */
1378 for (time_out = 0; time_out < max_time_out; time_out++) {
1379 udelay(10);
1380 status = hw->phy.ops.read_reg(hw,
1381 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1382 MDIO_MMD_VEND1,
1383 &phy_data);
1384 phy_link = phy_data &
1385 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1386 phy_speed = phy_data &
1387 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1388 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1389 *link_up = true;
1390 if (phy_speed ==
1391 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1392 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1393 break;
1394 }
1395 }
1396
1397 return status;
1398 }
1399
1400 /**
1401 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1402 * @hw: pointer to hardware structure
1403 * @firmware_version: pointer to the PHY Firmware Version
1404 **/
1405 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1406 u16 *firmware_version)
1407 {
1408 s32 status = 0;
1409
1410 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1411 firmware_version);
1412
1413 return status;
1414 }
1415
1416 /**
1417 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1418 * @hw: pointer to hardware structure
1419 * @firmware_version: pointer to the PHY Firmware Version
1420 **/
1421 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1422 u16 *firmware_version)
1423 {
1424 s32 status = 0;
1425
1426 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
1427 firmware_version);
1428
1429 return status;
1430 }
1431
1432 /**
1433 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1434 * @hw: pointer to hardware structure
1435 *
1436 * Checks if the LASI temp alarm status was triggered due to overtemp
1437 **/
1438 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1439 {
1440 s32 status = 0;
1441 u16 phy_data = 0;
1442
1443 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1444 goto out;
1445
1446 /* Check that the LASI temp alarm status was triggered */
1447 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1448 MDIO_MMD_PMAPMD, &phy_data);
1449
1450 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1451 goto out;
1452
1453 status = IXGBE_ERR_OVERTEMP;
1454 out:
1455 return status;
1456 }
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