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ARM: 6621/1: bitops: remove condition code clobber for CLZ
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
blob38ab4f3f8197c42a09d38efc6fbdddf4bdd7b359
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "3.0.12-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 [board_X540] = &ixgbe_X540_info,
63 };
64
65 /* ixgbe_pci_tbl - PCI Device ID Table
66 *
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
113 board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
115 board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
117 board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
119 board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
121 board_X540 },
122
123 /* required last entry */
124 {0, }
125 };
126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
127
128 #ifdef CONFIG_IXGBE_DCA
129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
130 void *p);
131 static struct notifier_block dca_notifier = {
132 .notifier_call = ixgbe_notify_dca,
133 .next = NULL,
134 .priority = 0
135 };
136 #endif
137
138 #ifdef CONFIG_PCI_IOV
139 static unsigned int max_vfs;
140 module_param(max_vfs, uint, 0);
141 MODULE_PARM_DESC(max_vfs,
142 "Maximum number of virtual functions to allocate per physical function");
143 #endif /* CONFIG_PCI_IOV */
144
145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_VERSION);
149
150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
151
152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
153 {
154 struct ixgbe_hw *hw = &adapter->hw;
155 u32 gcr;
156 u32 gpie;
157 u32 vmdctl;
158
159 #ifdef CONFIG_PCI_IOV
160 /* disable iov and allow time for transactions to clear */
161 pci_disable_sriov(adapter->pdev);
162 #endif
163
164 /* turn off device IOV mode */
165 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
166 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
168 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
169 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
171
172 /* set default pool back to 0 */
173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
174 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
176
177 /* take a breather then clean up driver data */
178 msleep(100);
179
180 kfree(adapter->vfinfo);
181 adapter->vfinfo = NULL;
182
183 adapter->num_vfs = 0;
184 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
185 }
186
187 struct ixgbe_reg_info {
188 u32 ofs;
189 char *name;
190 };
191
192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
193
194 /* General Registers */
195 {IXGBE_CTRL, "CTRL"},
196 {IXGBE_STATUS, "STATUS"},
197 {IXGBE_CTRL_EXT, "CTRL_EXT"},
198
199 /* Interrupt Registers */
200 {IXGBE_EICR, "EICR"},
201
202 /* RX Registers */
203 {IXGBE_SRRCTL(0), "SRRCTL"},
204 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
205 {IXGBE_RDLEN(0), "RDLEN"},
206 {IXGBE_RDH(0), "RDH"},
207 {IXGBE_RDT(0), "RDT"},
208 {IXGBE_RXDCTL(0), "RXDCTL"},
209 {IXGBE_RDBAL(0), "RDBAL"},
210 {IXGBE_RDBAH(0), "RDBAH"},
211
212 /* TX Registers */
213 {IXGBE_TDBAL(0), "TDBAL"},
214 {IXGBE_TDBAH(0), "TDBAH"},
215 {IXGBE_TDLEN(0), "TDLEN"},
216 {IXGBE_TDH(0), "TDH"},
217 {IXGBE_TDT(0), "TDT"},
218 {IXGBE_TXDCTL(0), "TXDCTL"},
219
220 /* List Terminator */
221 {}
222 };
223
224
225 /*
226 * ixgbe_regdump - register printout routine
227 */
228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
229 {
230 int i = 0, j = 0;
231 char rname[16];
232 u32 regs[64];
233
234 switch (reginfo->ofs) {
235 case IXGBE_SRRCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
238 break;
239 case IXGBE_DCA_RXCTRL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
242 break;
243 case IXGBE_RDLEN(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
246 break;
247 case IXGBE_RDH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
250 break;
251 case IXGBE_RDT(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
254 break;
255 case IXGBE_RXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
258 break;
259 case IXGBE_RDBAL(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
262 break;
263 case IXGBE_RDBAH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
266 break;
267 case IXGBE_TDBAL(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
270 break;
271 case IXGBE_TDBAH(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
274 break;
275 case IXGBE_TDLEN(0):
276 for (i = 0; i < 64; i++)
277 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
278 break;
279 case IXGBE_TDH(0):
280 for (i = 0; i < 64; i++)
281 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
282 break;
283 case IXGBE_TDT(0):
284 for (i = 0; i < 64; i++)
285 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
286 break;
287 case IXGBE_TXDCTL(0):
288 for (i = 0; i < 64; i++)
289 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
290 break;
291 default:
292 pr_info("%-15s %08x\n", reginfo->name,
293 IXGBE_READ_REG(hw, reginfo->ofs));
294 return;
295 }
296
297 for (i = 0; i < 8; i++) {
298 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
299 pr_err("%-15s", rname);
300 for (j = 0; j < 8; j++)
301 pr_cont(" %08x", regs[i*8+j]);
302 pr_cont("\n");
303 }
304
305 }
306
307 /*
308 * ixgbe_dump - Print registers, tx-rings and rx-rings
309 */
310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
311 {
312 struct net_device *netdev = adapter->netdev;
313 struct ixgbe_hw *hw = &adapter->hw;
314 struct ixgbe_reg_info *reginfo;
315 int n = 0;
316 struct ixgbe_ring *tx_ring;
317 struct ixgbe_tx_buffer *tx_buffer_info;
318 union ixgbe_adv_tx_desc *tx_desc;
319 struct my_u0 { u64 a; u64 b; } *u0;
320 struct ixgbe_ring *rx_ring;
321 union ixgbe_adv_rx_desc *rx_desc;
322 struct ixgbe_rx_buffer *rx_buffer_info;
323 u32 staterr;
324 int i = 0;
325
326 if (!netif_msg_hw(adapter))
327 return;
328
329 /* Print netdevice Info */
330 if (netdev) {
331 dev_info(&adapter->pdev->dev, "Net device Info\n");
332 pr_info("Device Name state "
333 "trans_start last_rx\n");
334 pr_info("%-15s %016lX %016lX %016lX\n",
335 netdev->name,
336 netdev->state,
337 netdev->trans_start,
338 netdev->last_rx);
339 }
340
341 /* Print Registers */
342 dev_info(&adapter->pdev->dev, "Register Dump\n");
343 pr_info(" Register Name Value\n");
344 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
345 reginfo->name; reginfo++) {
346 ixgbe_regdump(hw, reginfo);
347 }
348
349 /* Print TX Ring Summary */
350 if (!netdev || !netif_running(netdev))
351 goto exit;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
354 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
355 for (n = 0; n < adapter->num_tx_queues; n++) {
356 tx_ring = adapter->tx_ring[n];
357 tx_buffer_info =
358 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
359 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
360 n, tx_ring->next_to_use, tx_ring->next_to_clean,
361 (u64)tx_buffer_info->dma,
362 tx_buffer_info->length,
363 tx_buffer_info->next_to_watch,
364 (u64)tx_buffer_info->time_stamp);
365 }
366
367 /* Print TX Rings */
368 if (!netif_msg_tx_done(adapter))
369 goto rx_ring_summary;
370
371 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
372
373 /* Transmit Descriptor Formats
374 *
375 * Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
382 */
383
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 pr_info("------------------------------------\n");
387 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
388 pr_info("------------------------------------\n");
389 pr_info("T [desc] [address 63:0 ] "
390 "[PlPOIdStDDt Ln] [bi->dma ] "
391 "leng ntw timestamp bi->skb\n");
392
393 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
394 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
395 tx_buffer_info = &tx_ring->tx_buffer_info[i];
396 u0 = (struct my_u0 *)tx_desc;
397 pr_info("T [0x%03X] %016llX %016llX %016llX"
398 " %04X %3X %016llX %p", i,
399 le64_to_cpu(u0->a),
400 le64_to_cpu(u0->b),
401 (u64)tx_buffer_info->dma,
402 tx_buffer_info->length,
403 tx_buffer_info->next_to_watch,
404 (u64)tx_buffer_info->time_stamp,
405 tx_buffer_info->skb);
406 if (i == tx_ring->next_to_use &&
407 i == tx_ring->next_to_clean)
408 pr_cont(" NTC/U\n");
409 else if (i == tx_ring->next_to_use)
410 pr_cont(" NTU\n");
411 else if (i == tx_ring->next_to_clean)
412 pr_cont(" NTC\n");
413 else
414 pr_cont("\n");
415
416 if (netif_msg_pktdata(adapter) &&
417 tx_buffer_info->dma != 0)
418 print_hex_dump(KERN_INFO, "",
419 DUMP_PREFIX_ADDRESS, 16, 1,
420 phys_to_virt(tx_buffer_info->dma),
421 tx_buffer_info->length, true);
422 }
423 }
424
425 /* Print RX Rings Summary */
426 rx_ring_summary:
427 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
428 pr_info("Queue [NTU] [NTC]\n");
429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
431 pr_info("%5d %5X %5X\n",
432 n, rx_ring->next_to_use, rx_ring->next_to_clean);
433 }
434
435 /* Print RX Rings */
436 if (!netif_msg_rx_status(adapter))
437 goto exit;
438
439 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
440
441 /* Advanced Receive Descriptor (Read) Format
442 * 63 1 0
443 * +-----------------------------------------------------+
444 * 0 | Packet Buffer Address [63:1] |A0/NSE|
445 * +----------------------------------------------+------+
446 * 8 | Header Buffer Address [63:1] | DD |
447 * +-----------------------------------------------------+
448 *
449 *
450 * Advanced Receive Descriptor (Write-Back) Format
451 *
452 * 63 48 47 32 31 30 21 20 16 15 4 3 0
453 * +------------------------------------------------------+
454 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
455 * | Checksum Ident | | | | Type | Type |
456 * +------------------------------------------------------+
457 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
458 * +------------------------------------------------------+
459 * 63 48 47 32 31 20 19 0
460 */
461 for (n = 0; n < adapter->num_rx_queues; n++) {
462 rx_ring = adapter->rx_ring[n];
463 pr_info("------------------------------------\n");
464 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
465 pr_info("------------------------------------\n");
466 pr_info("R [desc] [ PktBuf A0] "
467 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
468 "<-- Adv Rx Read format\n");
469 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
470 "[vl er S cks ln] ---------------- [bi->skb] "
471 "<-- Adv Rx Write-Back format\n");
472
473 for (i = 0; i < rx_ring->count; i++) {
474 rx_buffer_info = &rx_ring->rx_buffer_info[i];
475 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
476 u0 = (struct my_u0 *)rx_desc;
477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
478 if (staterr & IXGBE_RXD_STAT_DD) {
479 /* Descriptor Done */
480 pr_info("RWB[0x%03X] %016llX "
481 "%016llX ---------------- %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 rx_buffer_info->skb);
485 } else {
486 pr_info("R [0x%03X] %016llX "
487 "%016llX %016llX %p", i,
488 le64_to_cpu(u0->a),
489 le64_to_cpu(u0->b),
490 (u64)rx_buffer_info->dma,
491 rx_buffer_info->skb);
492
493 if (netif_msg_pktdata(adapter)) {
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(rx_buffer_info->dma),
497 rx_ring->rx_buf_len, true);
498
499 if (rx_ring->rx_buf_len
500 < IXGBE_RXBUFFER_2048)
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
503 phys_to_virt(
504 rx_buffer_info->page_dma +
505 rx_buffer_info->page_offset
506 ),
507 PAGE_SIZE/2, true);
508 }
509 }
510
511 if (i == rx_ring->next_to_use)
512 pr_cont(" NTU\n");
513 else if (i == rx_ring->next_to_clean)
514 pr_cont(" NTC\n");
515 else
516 pr_cont("\n");
517
518 }
519 }
520
521 exit:
522 return;
523 }
524
525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
526 {
527 u32 ctrl_ext;
528
529 /* Let firmware take over control of h/w */
530 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
532 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
533 }
534
535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
536 {
537 u32 ctrl_ext;
538
539 /* Let firmware know the driver has taken over */
540 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
542 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
543 }
544
545 /*
546 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
547 * @adapter: pointer to adapter struct
548 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
549 * @queue: queue to map the corresponding interrupt to
550 * @msix_vector: the vector to map to the corresponding queue
551 *
552 */
553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
554 u8 queue, u8 msix_vector)
555 {
556 u32 ivar, index;
557 struct ixgbe_hw *hw = &adapter->hw;
558 switch (hw->mac.type) {
559 case ixgbe_mac_82598EB:
560 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
561 if (direction == -1)
562 direction = 0;
563 index = (((direction * 64) + queue) >> 2) & 0x1F;
564 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
565 ivar &= ~(0xFF << (8 * (queue & 0x3)));
566 ivar |= (msix_vector << (8 * (queue & 0x3)));
567 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
568 break;
569 case ixgbe_mac_82599EB:
570 case ixgbe_mac_X540:
571 if (direction == -1) {
572 /* other causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((queue & 1) * 8);
575 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
579 break;
580 } else {
581 /* tx or rx causes */
582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
583 index = ((16 * (queue & 1)) + (8 * direction));
584 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
585 ivar &= ~(0xFF << index);
586 ivar |= (msix_vector << index);
587 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 break;
589 }
590 default:
591 break;
592 }
593 }
594
595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
596 u64 qmask)
597 {
598 u32 mask;
599
600 switch (adapter->hw.mac.type) {
601 case ixgbe_mac_82598EB:
602 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
604 break;
605 case ixgbe_mac_82599EB:
606 case ixgbe_mac_X540:
607 mask = (qmask & 0xFFFFFFFF);
608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
609 mask = (qmask >> 32);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
611 break;
612 default:
613 break;
614 }
615 }
616
617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
618 struct ixgbe_tx_buffer *tx_buffer_info)
619 {
620 if (tx_buffer_info->dma) {
621 if (tx_buffer_info->mapped_as_page)
622 dma_unmap_page(tx_ring->dev,
623 tx_buffer_info->dma,
624 tx_buffer_info->length,
625 DMA_TO_DEVICE);
626 else
627 dma_unmap_single(tx_ring->dev,
628 tx_buffer_info->dma,
629 tx_buffer_info->length,
630 DMA_TO_DEVICE);
631 tx_buffer_info->dma = 0;
632 }
633 if (tx_buffer_info->skb) {
634 dev_kfree_skb_any(tx_buffer_info->skb);
635 tx_buffer_info->skb = NULL;
636 }
637 tx_buffer_info->time_stamp = 0;
638 /* tx_buffer_info must be completely set up in the transmit path */
639 }
640
641 /**
642 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
643 * @adapter: driver private struct
644 * @index: reg idx of queue to query (0-127)
645 *
646 * Helper function to determine the traffic index for a paticular
647 * register index.
648 *
649 * Returns : a tc index for use in range 0-7, or 0-3
650 */
651 u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
652 {
653 int tc = -1;
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
655
656 /* if DCB is not enabled the queues have no TC */
657 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
658 return tc;
659
660 /* check valid range */
661 if (reg_idx >= adapter->hw.mac.max_tx_queues)
662 return tc;
663
664 switch (adapter->hw.mac.type) {
665 case ixgbe_mac_82598EB:
666 tc = reg_idx >> 2;
667 break;
668 default:
669 if (dcb_i != 4 && dcb_i != 8)
670 break;
671
672 /* if VMDq is enabled the lowest order bits determine TC */
673 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
674 IXGBE_FLAG_VMDQ_ENABLED)) {
675 tc = reg_idx & (dcb_i - 1);
676 break;
677 }
678
679 /*
680 * Convert the reg_idx into the correct TC. This bitmask
681 * targets the last full 32 ring traffic class and assigns
682 * it a value of 1. From there the rest of the rings are
683 * based on shifting the mask further up to include the
684 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
685 * will only ever be 8 or 4 and that reg_idx will never
686 * be greater then 128. The code without the power of 2
687 * optimizations would be:
688 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
689 */
690 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
691 tc >>= 9 - (reg_idx >> 5);
692 }
693
694 return tc;
695 }
696
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698 {
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 data = 0;
702 u32 xoff[8] = {0};
703 int i;
704
705 if ((hw->fc.current_mode == ixgbe_fc_full) ||
706 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
707 switch (hw->mac.type) {
708 case ixgbe_mac_82598EB:
709 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
710 break;
711 default:
712 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
713 }
714 hwstats->lxoffrxc += data;
715
716 /* refill credits (no tx hang) if we received xoff */
717 if (!data)
718 return;
719
720 for (i = 0; i < adapter->num_tx_queues; i++)
721 clear_bit(__IXGBE_HANG_CHECK_ARMED,
722 &adapter->tx_ring[i]->state);
723 return;
724 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
725 return;
726
727 /* update stats for each tc, only valid with PFC enabled */
728 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
729 switch (hw->mac.type) {
730 case ixgbe_mac_82598EB:
731 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
732 break;
733 default:
734 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
735 }
736 hwstats->pxoffrxc[i] += xoff[i];
737 }
738
739 /* disarm tx queues that have received xoff frames */
740 for (i = 0; i < adapter->num_tx_queues; i++) {
741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
742 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
743
744 if (xoff[tc])
745 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
746 }
747 }
748
749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
750 {
751 return ring->tx_stats.completed;
752 }
753
754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
755 {
756 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
757 struct ixgbe_hw *hw = &adapter->hw;
758
759 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
760 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
761
762 if (head != tail)
763 return (head < tail) ?
764 tail - head : (tail + ring->count - head);
765
766 return 0;
767 }
768
769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
770 {
771 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
772 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
773 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
774 bool ret = false;
775
776 clear_check_for_tx_hang(tx_ring);
777
778 /*
779 * Check for a hung queue, but be thorough. This verifies
780 * that a transmit has been completed since the previous
781 * check AND there is at least one packet pending. The
782 * ARMED bit is set to indicate a potential hang. The
783 * bit is cleared if a pause frame is received to remove
784 * false hang detection due to PFC or 802.3x frames. By
785 * requiring this to fail twice we avoid races with
786 * pfc clearing the ARMED bit and conditions where we
787 * run the check_tx_hang logic with a transmit completion
788 * pending but without time to complete it yet.
789 */
790 if ((tx_done_old == tx_done) && tx_pending) {
791 /* make sure it is true for two checks in a row */
792 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
793 &tx_ring->state);
794 } else {
795 /* update completed stats and continue */
796 tx_ring->tx_stats.tx_done_old = tx_done;
797 /* reset the countdown */
798 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
799 }
800
801 return ret;
802 }
803
804 #define IXGBE_MAX_TXD_PWR 14
805 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
806
807 /* Tx Descriptors needed, worst case */
808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
809 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
811 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
812
813 static void ixgbe_tx_timeout(struct net_device *netdev);
814
815 /**
816 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
817 * @q_vector: structure containing interrupt and ring information
818 * @tx_ring: tx ring to clean
819 **/
820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
821 struct ixgbe_ring *tx_ring)
822 {
823 struct ixgbe_adapter *adapter = q_vector->adapter;
824 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
825 struct ixgbe_tx_buffer *tx_buffer_info;
826 unsigned int total_bytes = 0, total_packets = 0;
827 u16 i, eop, count = 0;
828
829 i = tx_ring->next_to_clean;
830 eop = tx_ring->tx_buffer_info[i].next_to_watch;
831 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
832
833 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
834 (count < tx_ring->work_limit)) {
835 bool cleaned = false;
836 rmb(); /* read buffer_info after eop_desc */
837 for ( ; !cleaned; count++) {
838 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
839 tx_buffer_info = &tx_ring->tx_buffer_info[i];
840
841 tx_desc->wb.status = 0;
842 cleaned = (i == eop);
843
844 i++;
845 if (i == tx_ring->count)
846 i = 0;
847
848 if (cleaned && tx_buffer_info->skb) {
849 total_bytes += tx_buffer_info->bytecount;
850 total_packets += tx_buffer_info->gso_segs;
851 }
852
853 ixgbe_unmap_and_free_tx_resource(tx_ring,
854 tx_buffer_info);
855 }
856
857 tx_ring->tx_stats.completed++;
858 eop = tx_ring->tx_buffer_info[i].next_to_watch;
859 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
860 }
861
862 tx_ring->next_to_clean = i;
863 tx_ring->total_bytes += total_bytes;
864 tx_ring->total_packets += total_packets;
865 u64_stats_update_begin(&tx_ring->syncp);
866 tx_ring->stats.packets += total_packets;
867 tx_ring->stats.bytes += total_bytes;
868 u64_stats_update_end(&tx_ring->syncp);
869
870 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
871 /* schedule immediate reset if we believe we hung */
872 struct ixgbe_hw *hw = &adapter->hw;
873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
874 e_err(drv, "Detected Tx Unit Hang\n"
875 " Tx Queue <%d>\n"
876 " TDH, TDT <%x>, <%x>\n"
877 " next_to_use <%x>\n"
878 " next_to_clean <%x>\n"
879 "tx_buffer_info[next_to_clean]\n"
880 " time_stamp <%lx>\n"
881 " jiffies <%lx>\n",
882 tx_ring->queue_index,
883 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
884 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
885 tx_ring->next_to_use, eop,
886 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
887
888 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
889
890 e_info(probe,
891 "tx hang %d detected on queue %d, resetting adapter\n",
892 adapter->tx_timeout_count + 1, tx_ring->queue_index);
893
894 /* schedule immediate reset if we believe we hung */
895 ixgbe_tx_timeout(adapter->netdev);
896
897 /* the adapter is about to reset, no point in enabling stuff */
898 return true;
899 }
900
901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
902 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
903 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
904 /* Make sure that anybody stopping the queue after this
905 * sees the new next_to_clean.
906 */
907 smp_mb();
908 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
909 !test_bit(__IXGBE_DOWN, &adapter->state)) {
910 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
911 ++tx_ring->tx_stats.restart_queue;
912 }
913 }
914
915 return count < tx_ring->work_limit;
916 }
917
918 #ifdef CONFIG_IXGBE_DCA
919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
920 struct ixgbe_ring *rx_ring,
921 int cpu)
922 {
923 struct ixgbe_hw *hw = &adapter->hw;
924 u32 rxctrl;
925 u8 reg_idx = rx_ring->reg_idx;
926
927 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
928 switch (hw->mac.type) {
929 case ixgbe_mac_82598EB:
930 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
931 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
932 break;
933 case ixgbe_mac_82599EB:
934 case ixgbe_mac_X540:
935 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
936 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
937 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
938 break;
939 default:
940 break;
941 }
942 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
943 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
944 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
946 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
948 }
949
950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
951 struct ixgbe_ring *tx_ring,
952 int cpu)
953 {
954 struct ixgbe_hw *hw = &adapter->hw;
955 u32 txctrl;
956 u8 reg_idx = tx_ring->reg_idx;
957
958 switch (hw->mac.type) {
959 case ixgbe_mac_82598EB:
960 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
961 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
962 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
966 break;
967 case ixgbe_mac_82599EB:
968 case ixgbe_mac_X540:
969 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
970 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
971 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
973 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
974 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
975 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
976 break;
977 default:
978 break;
979 }
980 }
981
982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
983 {
984 struct ixgbe_adapter *adapter = q_vector->adapter;
985 int cpu = get_cpu();
986 long r_idx;
987 int i;
988
989 if (q_vector->cpu == cpu)
990 goto out_no_update;
991
992 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
993 for (i = 0; i < q_vector->txr_count; i++) {
994 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
995 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
996 r_idx + 1);
997 }
998
999 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000 for (i = 0; i < q_vector->rxr_count; i++) {
1001 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003 r_idx + 1);
1004 }
1005
1006 q_vector->cpu = cpu;
1007 out_no_update:
1008 put_cpu();
1009 }
1010
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012 {
1013 int num_q_vectors;
1014 int i;
1015
1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017 return;
1018
1019 /* always use CB2 mode, difference is masked in the CB driver */
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
1022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024 else
1025 num_q_vectors = 1;
1026
1027 for (i = 0; i < num_q_vectors; i++) {
1028 adapter->q_vector[i]->cpu = -1;
1029 ixgbe_update_dca(adapter->q_vector[i]);
1030 }
1031 }
1032
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1034 {
1035 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036 unsigned long event = *(unsigned long *)data;
1037
1038 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039 return 0;
1040
1041 switch (event) {
1042 case DCA_PROVIDER_ADD:
1043 /* if we're already enabled, don't do it again */
1044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045 break;
1046 if (dca_add_requester(dev) == 0) {
1047 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048 ixgbe_setup_dca(adapter);
1049 break;
1050 }
1051 /* Fall Through since DCA is disabled. */
1052 case DCA_PROVIDER_REMOVE:
1053 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054 dca_remove_requester(dev);
1055 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057 }
1058 break;
1059 }
1060
1061 return 0;
1062 }
1063
1064 #endif /* CONFIG_IXGBE_DCA */
1065 /**
1066 * ixgbe_receive_skb - Send a completed packet up the stack
1067 * @adapter: board private structure
1068 * @skb: packet to send up
1069 * @status: hardware indication of status of receive
1070 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071 * @rx_desc: rx descriptor
1072 **/
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074 struct sk_buff *skb, u8 status,
1075 struct ixgbe_ring *ring,
1076 union ixgbe_adv_rx_desc *rx_desc)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct napi_struct *napi = &q_vector->napi;
1080 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1082
1083 if (is_vlan && (tag & VLAN_VID_MASK))
1084 __vlan_hwaccel_put_tag(skb, tag);
1085
1086 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087 napi_gro_receive(napi, skb);
1088 else
1089 netif_rx(skb);
1090 }
1091
1092 /**
1093 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094 * @adapter: address of board private structure
1095 * @status_err: hardware indication of status of receive
1096 * @skb: skb currently being received and modified
1097 **/
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
1104 skb_checksum_none_assert(skb);
1105
1106 /* Rx csum disabled */
1107 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1108 return;
1109
1110 /* if IP and error */
1111 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113 adapter->hw_csum_rx_error++;
1114 return;
1115 }
1116
1117 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118 return;
1119
1120 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123 /*
1124 * 82599 errata, UDP frames with a 0 checksum can be marked as
1125 * checksum errors.
1126 */
1127 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129 return;
1130
1131 adapter->hw_csum_rx_error++;
1132 return;
1133 }
1134
1135 /* It must be a TCP or UDP packet with a valid checksum */
1136 skb->ip_summed = CHECKSUM_UNNECESSARY;
1137 }
1138
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1140 {
1141 /*
1142 * Force memory writes to complete before letting h/w
1143 * know there are new descriptors to fetch. (Only
1144 * applicable for weak-ordered memory model archs,
1145 * such as IA-64).
1146 */
1147 wmb();
1148 writel(val, rx_ring->tail);
1149 }
1150
1151 /**
1152 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153 * @rx_ring: ring to place buffers on
1154 * @cleaned_count: number of buffers to replace
1155 **/
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1157 {
1158 union ixgbe_adv_rx_desc *rx_desc;
1159 struct ixgbe_rx_buffer *bi;
1160 struct sk_buff *skb;
1161 u16 i = rx_ring->next_to_use;
1162
1163 /* do nothing if no valid netdev defined */
1164 if (!rx_ring->netdev)
1165 return;
1166
1167 while (cleaned_count--) {
1168 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169 bi = &rx_ring->rx_buffer_info[i];
1170 skb = bi->skb;
1171
1172 if (!skb) {
1173 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174 rx_ring->rx_buf_len);
1175 if (!skb) {
1176 rx_ring->rx_stats.alloc_rx_buff_failed++;
1177 goto no_buffers;
1178 }
1179 /* initialize queue mapping */
1180 skb_record_rx_queue(skb, rx_ring->queue_index);
1181 bi->skb = skb;
1182 }
1183
1184 if (!bi->dma) {
1185 bi->dma = dma_map_single(rx_ring->dev,
1186 skb->data,
1187 rx_ring->rx_buf_len,
1188 DMA_FROM_DEVICE);
1189 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190 rx_ring->rx_stats.alloc_rx_buff_failed++;
1191 bi->dma = 0;
1192 goto no_buffers;
1193 }
1194 }
1195
1196 if (ring_is_ps_enabled(rx_ring)) {
1197 if (!bi->page) {
1198 bi->page = netdev_alloc_page(rx_ring->netdev);
1199 if (!bi->page) {
1200 rx_ring->rx_stats.alloc_rx_page_failed++;
1201 goto no_buffers;
1202 }
1203 }
1204
1205 if (!bi->page_dma) {
1206 /* use a half page if we're re-using */
1207 bi->page_offset ^= PAGE_SIZE / 2;
1208 bi->page_dma = dma_map_page(rx_ring->dev,
1209 bi->page,
1210 bi->page_offset,
1211 PAGE_SIZE / 2,
1212 DMA_FROM_DEVICE);
1213 if (dma_mapping_error(rx_ring->dev,
1214 bi->page_dma)) {
1215 rx_ring->rx_stats.alloc_rx_page_failed++;
1216 bi->page_dma = 0;
1217 goto no_buffers;
1218 }
1219 }
1220
1221 /* Refresh the desc even if buffer_addrs didn't change
1222 * because each write-back erases this info. */
1223 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1225 } else {
1226 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227 rx_desc->read.hdr_addr = 0;
1228 }
1229
1230 i++;
1231 if (i == rx_ring->count)
1232 i = 0;
1233 }
1234
1235 no_buffers:
1236 if (rx_ring->next_to_use != i) {
1237 rx_ring->next_to_use = i;
1238 ixgbe_release_rx_desc(rx_ring, i);
1239 }
1240 }
1241
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244 /* HW will not DMA in data larger than the given buffer, even if it
1245 * parses the (NFS, of course) header to be larger. In that case, it
1246 * fills the header buffer and spills the rest into the page.
1247 */
1248 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251 if (hlen > IXGBE_RX_HDR_SIZE)
1252 hlen = IXGBE_RX_HDR_SIZE;
1253 return hlen;
1254 }
1255
1256 /**
1257 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258 * @skb: pointer to the last skb in the rsc queue
1259 *
1260 * This function changes a queue full of hw rsc buffers into a completed
1261 * packet. It uses the ->prev pointers to find the first packet and then
1262 * turns it into the frag list owner.
1263 **/
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1265 {
1266 unsigned int frag_list_size = 0;
1267 unsigned int skb_cnt = 1;
1268
1269 while (skb->prev) {
1270 struct sk_buff *prev = skb->prev;
1271 frag_list_size += skb->len;
1272 skb->prev = NULL;
1273 skb = prev;
1274 skb_cnt++;
1275 }
1276
1277 skb_shinfo(skb)->frag_list = skb->next;
1278 skb->next = NULL;
1279 skb->len += frag_list_size;
1280 skb->data_len += frag_list_size;
1281 skb->truesize += frag_list_size;
1282 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
1284 return skb;
1285 }
1286
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288 {
1289 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290 IXGBE_RXDADV_RSCCNT_MASK);
1291 }
1292
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294 struct ixgbe_ring *rx_ring,
1295 int *work_done, int work_to_do)
1296 {
1297 struct ixgbe_adapter *adapter = q_vector->adapter;
1298 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300 struct sk_buff *skb;
1301 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302 const int current_node = numa_node_id();
1303 #ifdef IXGBE_FCOE
1304 int ddp_bytes = 0;
1305 #endif /* IXGBE_FCOE */
1306 u32 staterr;
1307 u16 i;
1308 u16 cleaned_count = 0;
1309 bool pkt_is_rsc = false;
1310
1311 i = rx_ring->next_to_clean;
1312 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1314
1315 while (staterr & IXGBE_RXD_STAT_DD) {
1316 u32 upper_len = 0;
1317
1318 rmb(); /* read descriptor and rx_buffer_info after status DD */
1319
1320 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
1322 skb = rx_buffer_info->skb;
1323 rx_buffer_info->skb = NULL;
1324 prefetch(skb->data);
1325
1326 if (ring_is_rsc_enabled(rx_ring))
1327 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1328
1329 /* if this is a skb from previous receive DMA will be 0 */
1330 if (rx_buffer_info->dma) {
1331 u16 hlen;
1332 if (pkt_is_rsc &&
1333 !(staterr & IXGBE_RXD_STAT_EOP) &&
1334 !skb->prev) {
1335 /*
1336 * When HWRSC is enabled, delay unmapping
1337 * of the first packet. It carries the
1338 * header information, HW may still
1339 * access the header after the writeback.
1340 * Only unmap it when EOP is reached
1341 */
1342 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1344 } else {
1345 dma_unmap_single(rx_ring->dev,
1346 rx_buffer_info->dma,
1347 rx_ring->rx_buf_len,
1348 DMA_FROM_DEVICE);
1349 }
1350 rx_buffer_info->dma = 0;
1351
1352 if (ring_is_ps_enabled(rx_ring)) {
1353 hlen = ixgbe_get_hlen(rx_desc);
1354 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355 } else {
1356 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357 }
1358
1359 skb_put(skb, hlen);
1360 } else {
1361 /* assume packet split since header is unmapped */
1362 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1363 }
1364
1365 if (upper_len) {
1366 dma_unmap_page(rx_ring->dev,
1367 rx_buffer_info->page_dma,
1368 PAGE_SIZE / 2,
1369 DMA_FROM_DEVICE);
1370 rx_buffer_info->page_dma = 0;
1371 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372 rx_buffer_info->page,
1373 rx_buffer_info->page_offset,
1374 upper_len);
1375
1376 if ((page_count(rx_buffer_info->page) == 1) &&
1377 (page_to_nid(rx_buffer_info->page) == current_node))
1378 get_page(rx_buffer_info->page);
1379 else
1380 rx_buffer_info->page = NULL;
1381
1382 skb->len += upper_len;
1383 skb->data_len += upper_len;
1384 skb->truesize += upper_len;
1385 }
1386
1387 i++;
1388 if (i == rx_ring->count)
1389 i = 0;
1390
1391 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392 prefetch(next_rxd);
1393 cleaned_count++;
1394
1395 if (pkt_is_rsc) {
1396 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397 IXGBE_RXDADV_NEXTP_SHIFT;
1398 next_buffer = &rx_ring->rx_buffer_info[nextp];
1399 } else {
1400 next_buffer = &rx_ring->rx_buffer_info[i];
1401 }
1402
1403 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404 if (ring_is_ps_enabled(rx_ring)) {
1405 rx_buffer_info->skb = next_buffer->skb;
1406 rx_buffer_info->dma = next_buffer->dma;
1407 next_buffer->skb = skb;
1408 next_buffer->dma = 0;
1409 } else {
1410 skb->next = next_buffer->skb;
1411 skb->next->prev = skb;
1412 }
1413 rx_ring->rx_stats.non_eop_descs++;
1414 goto next_desc;
1415 }
1416
1417 if (skb->prev) {
1418 skb = ixgbe_transform_rsc_queue(skb);
1419 /* if we got here without RSC the packet is invalid */
1420 if (!pkt_is_rsc) {
1421 __pskb_trim(skb, 0);
1422 rx_buffer_info->skb = skb;
1423 goto next_desc;
1424 }
1425 }
1426
1427 if (ring_is_rsc_enabled(rx_ring)) {
1428 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429 dma_unmap_single(rx_ring->dev,
1430 IXGBE_RSC_CB(skb)->dma,
1431 rx_ring->rx_buf_len,
1432 DMA_FROM_DEVICE);
1433 IXGBE_RSC_CB(skb)->dma = 0;
1434 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435 }
1436 }
1437 if (pkt_is_rsc) {
1438 if (ring_is_ps_enabled(rx_ring))
1439 rx_ring->rx_stats.rsc_count +=
1440 skb_shinfo(skb)->nr_frags;
1441 else
1442 rx_ring->rx_stats.rsc_count +=
1443 IXGBE_RSC_CB(skb)->skb_cnt;
1444 rx_ring->rx_stats.rsc_flush++;
1445 }
1446
1447 /* ERR_MASK will only have valid bits if EOP set */
1448 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449 /* trim packet back to size 0 and recycle it */
1450 __pskb_trim(skb, 0);
1451 rx_buffer_info->skb = skb;
1452 goto next_desc;
1453 }
1454
1455 ixgbe_rx_checksum(adapter, rx_desc, skb);
1456
1457 /* probably a little skewed due to removing CRC */
1458 total_rx_bytes += skb->len;
1459 total_rx_packets++;
1460
1461 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1462 #ifdef IXGBE_FCOE
1463 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466 if (!ddp_bytes)
1467 goto next_desc;
1468 }
1469 #endif /* IXGBE_FCOE */
1470 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1471
1472 next_desc:
1473 rx_desc->wb.upper.status_error = 0;
1474
1475 (*work_done)++;
1476 if (*work_done >= work_to_do)
1477 break;
1478
1479 /* return some buffers to hardware, one at a time is too slow */
1480 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482 cleaned_count = 0;
1483 }
1484
1485 /* use prefetched values */
1486 rx_desc = next_rxd;
1487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1488 }
1489
1490 rx_ring->next_to_clean = i;
1491 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493 if (cleaned_count)
1494 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1495
1496 #ifdef IXGBE_FCOE
1497 /* include DDPed FCoE data */
1498 if (ddp_bytes > 0) {
1499 unsigned int mss;
1500
1501 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502 sizeof(struct fc_frame_header) -
1503 sizeof(struct fcoe_crc_eof);
1504 if (mss > 512)
1505 mss &= ~511;
1506 total_rx_bytes += ddp_bytes;
1507 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508 }
1509 #endif /* IXGBE_FCOE */
1510
1511 rx_ring->total_packets += total_rx_packets;
1512 rx_ring->total_bytes += total_rx_bytes;
1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
1517 }
1518
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1520 /**
1521 * ixgbe_configure_msix - Configure MSI-X hardware
1522 * @adapter: board private structure
1523 *
1524 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525 * interrupts.
1526 **/
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528 {
1529 struct ixgbe_q_vector *q_vector;
1530 int i, q_vectors, v_idx, r_idx;
1531 u32 mask;
1532
1533 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535 /*
1536 * Populate the IVAR table and set the ITR values to the
1537 * corresponding register.
1538 */
1539 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540 q_vector = adapter->q_vector[v_idx];
1541 /* XXX for_each_set_bit(...) */
1542 r_idx = find_first_bit(q_vector->rxr_idx,
1543 adapter->num_rx_queues);
1544
1545 for (i = 0; i < q_vector->rxr_count; i++) {
1546 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548 r_idx = find_next_bit(q_vector->rxr_idx,
1549 adapter->num_rx_queues,
1550 r_idx + 1);
1551 }
1552 r_idx = find_first_bit(q_vector->txr_idx,
1553 adapter->num_tx_queues);
1554
1555 for (i = 0; i < q_vector->txr_count; i++) {
1556 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558 r_idx = find_next_bit(q_vector->txr_idx,
1559 adapter->num_tx_queues,
1560 r_idx + 1);
1561 }
1562
1563 if (q_vector->txr_count && !q_vector->rxr_count)
1564 /* tx only */
1565 q_vector->eitr = adapter->tx_eitr_param;
1566 else if (q_vector->rxr_count)
1567 /* rx or mixed */
1568 q_vector->eitr = adapter->rx_eitr_param;
1569
1570 ixgbe_write_eitr(q_vector);
1571 /* If Flow Director is enabled, set interrupt affinity */
1572 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574 /*
1575 * Allocate the affinity_hint cpumask, assign the mask
1576 * for this vector, and set our affinity_hint for
1577 * this irq.
1578 */
1579 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580 GFP_KERNEL))
1581 return;
1582 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584 q_vector->affinity_mask);
1585 }
1586 }
1587
1588 switch (adapter->hw.mac.type) {
1589 case ixgbe_mac_82598EB:
1590 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1591 v_idx);
1592 break;
1593 case ixgbe_mac_82599EB:
1594 case ixgbe_mac_X540:
1595 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1596 break;
1597
1598 default:
1599 break;
1600 }
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
1603 /* set up to autoclear timer, and the vectors */
1604 mask = IXGBE_EIMS_ENABLE_MASK;
1605 if (adapter->num_vfs)
1606 mask &= ~(IXGBE_EIMS_OTHER |
1607 IXGBE_EIMS_MAILBOX |
1608 IXGBE_EIMS_LSC);
1609 else
1610 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1612 }
1613
1614 enum latency_range {
1615 lowest_latency = 0,
1616 low_latency = 1,
1617 bulk_latency = 2,
1618 latency_invalid = 255
1619 };
1620
1621 /**
1622 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623 * @adapter: pointer to adapter
1624 * @eitr: eitr setting (ints per sec) to give last timeslice
1625 * @itr_setting: current throttle rate in ints/second
1626 * @packets: the number of packets during this measurement interval
1627 * @bytes: the number of bytes during this measurement interval
1628 *
1629 * Stores a new ITR value based on packets and byte
1630 * counts during the last interrupt. The advantage of per interrupt
1631 * computation is faster updates and more accurate ITR for the current
1632 * traffic pattern. Constants in this function were computed
1633 * based on theoretical maximum wire speed and thresholds were set based
1634 * on testing data as well as attempting to minimize response time
1635 * while increasing bulk throughput.
1636 * this functionality is controlled by the InterruptThrottleRate module
1637 * parameter (see ixgbe_param.c)
1638 **/
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640 u32 eitr, u8 itr_setting,
1641 int packets, int bytes)
1642 {
1643 unsigned int retval = itr_setting;
1644 u32 timepassed_us;
1645 u64 bytes_perint;
1646
1647 if (packets == 0)
1648 goto update_itr_done;
1649
1650
1651 /* simple throttlerate management
1652 * 0-20MB/s lowest (100000 ints/s)
1653 * 20-100MB/s low (20000 ints/s)
1654 * 100-1249MB/s bulk (8000 ints/s)
1655 */
1656 /* what was last interrupt timeslice? */
1657 timepassed_us = 1000000/eitr;
1658 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660 switch (itr_setting) {
1661 case lowest_latency:
1662 if (bytes_perint > adapter->eitr_low)
1663 retval = low_latency;
1664 break;
1665 case low_latency:
1666 if (bytes_perint > adapter->eitr_high)
1667 retval = bulk_latency;
1668 else if (bytes_perint <= adapter->eitr_low)
1669 retval = lowest_latency;
1670 break;
1671 case bulk_latency:
1672 if (bytes_perint <= adapter->eitr_high)
1673 retval = low_latency;
1674 break;
1675 }
1676
1677 update_itr_done:
1678 return retval;
1679 }
1680
1681 /**
1682 * ixgbe_write_eitr - write EITR register in hardware specific way
1683 * @q_vector: structure containing interrupt and ring information
1684 *
1685 * This function is made to be called by ethtool and by the driver
1686 * when it needs to update EITR registers at runtime. Hardware
1687 * specific quirks/differences are taken care of here.
1688 */
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1690 {
1691 struct ixgbe_adapter *adapter = q_vector->adapter;
1692 struct ixgbe_hw *hw = &adapter->hw;
1693 int v_idx = q_vector->v_idx;
1694 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
1696 switch (adapter->hw.mac.type) {
1697 case ixgbe_mac_82598EB:
1698 /* must write high and low 16 bits to reset counter */
1699 itr_reg |= (itr_reg << 16);
1700 break;
1701 case ixgbe_mac_82599EB:
1702 case ixgbe_mac_X540:
1703 /*
1704 * 82599 and X540 can support a value of zero, so allow it for
1705 * max interrupt rate, but there is an errata where it can
1706 * not be zero with RSC
1707 */
1708 if (itr_reg == 8 &&
1709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710 itr_reg = 0;
1711
1712 /*
1713 * set the WDIS bit to not clear the timer bits and cause an
1714 * immediate assertion of the interrupt
1715 */
1716 itr_reg |= IXGBE_EITR_CNT_WDIS;
1717 break;
1718 default:
1719 break;
1720 }
1721 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 }
1723
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725 {
1726 struct ixgbe_adapter *adapter = q_vector->adapter;
1727 int i, r_idx;
1728 u32 new_itr;
1729 u8 current_itr, ret_itr;
1730
1731 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732 for (i = 0; i < q_vector->txr_count; i++) {
1733 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1735 q_vector->tx_itr,
1736 tx_ring->total_packets,
1737 tx_ring->total_bytes);
1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
1740 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741 q_vector->tx_itr - 1 : ret_itr);
1742 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1743 r_idx + 1);
1744 }
1745
1746 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747 for (i = 0; i < q_vector->rxr_count; i++) {
1748 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1750 q_vector->rx_itr,
1751 rx_ring->total_packets,
1752 rx_ring->total_bytes);
1753 /* if the result for this queue would decrease interrupt
1754 * rate for this vector then use that result */
1755 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756 q_vector->rx_itr - 1 : ret_itr);
1757 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1758 r_idx + 1);
1759 }
1760
1761 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1762
1763 switch (current_itr) {
1764 /* counts and packets in update_itr are dependent on these numbers */
1765 case lowest_latency:
1766 new_itr = 100000;
1767 break;
1768 case low_latency:
1769 new_itr = 20000; /* aka hwitr = ~200 */
1770 break;
1771 case bulk_latency:
1772 default:
1773 new_itr = 8000;
1774 break;
1775 }
1776
1777 if (new_itr != q_vector->eitr) {
1778 /* do an exponential smoothing */
1779 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1780
1781 /* save the algorithm value here, not the smoothed one */
1782 q_vector->eitr = new_itr;
1783
1784 ixgbe_write_eitr(q_vector);
1785 }
1786 }
1787
1788 /**
1789 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790 * @work: pointer to work_struct containing our data
1791 **/
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1793 {
1794 struct ixgbe_adapter *adapter = container_of(work,
1795 struct ixgbe_adapter,
1796 check_overtemp_task);
1797 struct ixgbe_hw *hw = &adapter->hw;
1798 u32 eicr = adapter->interrupt_event;
1799
1800 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801 return;
1802
1803 switch (hw->device_id) {
1804 case IXGBE_DEV_ID_82599_T3_LOM: {
1805 u32 autoneg;
1806 bool link_up = false;
1807
1808 if (hw->mac.ops.check_link)
1809 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812 (eicr & IXGBE_EICR_LSC))
1813 /* Check if this is due to overtemp */
1814 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815 break;
1816 return;
1817 }
1818 default:
1819 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1820 return;
1821 break;
1822 }
1823 e_crit(drv,
1824 "Network adapter has been stopped because it has over heated. "
1825 "Restart the computer. If the problem persists, "
1826 "power off the system and replace the adapter\n");
1827 /* write to clear the interrupt */
1828 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1829 }
1830
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832 {
1833 struct ixgbe_hw *hw = &adapter->hw;
1834
1835 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836 (eicr & IXGBE_EICR_GPI_SDP1)) {
1837 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840 }
1841 }
1842
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844 {
1845 struct ixgbe_hw *hw = &adapter->hw;
1846
1847 if (eicr & IXGBE_EICR_GPI_SDP2) {
1848 /* Clear the interrupt */
1849 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851 schedule_work(&adapter->sfp_config_module_task);
1852 }
1853
1854 if (eicr & IXGBE_EICR_GPI_SDP1) {
1855 /* Clear the interrupt */
1856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858 schedule_work(&adapter->multispeed_fiber_task);
1859 }
1860 }
1861
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863 {
1864 struct ixgbe_hw *hw = &adapter->hw;
1865
1866 adapter->lsc_int++;
1867 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868 adapter->link_check_timeout = jiffies;
1869 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871 IXGBE_WRITE_FLUSH(hw);
1872 schedule_work(&adapter->watchdog_task);
1873 }
1874 }
1875
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877 {
1878 struct net_device *netdev = data;
1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880 struct ixgbe_hw *hw = &adapter->hw;
1881 u32 eicr;
1882
1883 /*
1884 * Workaround for Silicon errata. Use clear-by-write instead
1885 * of clear-by-read. Reading with EICS will return the
1886 * interrupt causes without clearing, which later be done
1887 * with the write to EICR.
1888 */
1889 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1891
1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
1894
1895 if (eicr & IXGBE_EICR_MAILBOX)
1896 ixgbe_msg_task(adapter);
1897
1898 switch (hw->mac.type) {
1899 case ixgbe_mac_82599EB:
1900 ixgbe_check_sfp_event(adapter, eicr);
1901 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903 adapter->interrupt_event = eicr;
1904 schedule_work(&adapter->check_overtemp_task);
1905 }
1906 /* now fallthrough to handle Flow Director */
1907 case ixgbe_mac_X540:
1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
1910 int i;
1911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912 /* Disable transmits before FDIR Re-initialization */
1913 netif_tx_stop_all_queues(netdev);
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *tx_ring =
1916 adapter->tx_ring[i];
1917 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1918 &tx_ring->state))
1919 schedule_work(&adapter->fdir_reinit_task);
1920 }
1921 }
1922 break;
1923 default:
1924 break;
1925 }
1926
1927 ixgbe_check_fan_failure(adapter, eicr);
1928
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1931
1932 return IRQ_HANDLED;
1933 }
1934
1935 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936 u64 qmask)
1937 {
1938 u32 mask;
1939 struct ixgbe_hw *hw = &adapter->hw;
1940
1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82598EB:
1943 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1945 break;
1946 case ixgbe_mac_82599EB:
1947 case ixgbe_mac_X540:
1948 mask = (qmask & 0xFFFFFFFF);
1949 if (mask)
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1951 mask = (qmask >> 32);
1952 if (mask)
1953 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1954 break;
1955 default:
1956 break;
1957 }
1958 /* skip the flush */
1959 }
1960
1961 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1962 u64 qmask)
1963 {
1964 u32 mask;
1965 struct ixgbe_hw *hw = &adapter->hw;
1966
1967 switch (hw->mac.type) {
1968 case ixgbe_mac_82598EB:
1969 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1970 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1971 break;
1972 case ixgbe_mac_82599EB:
1973 case ixgbe_mac_X540:
1974 mask = (qmask & 0xFFFFFFFF);
1975 if (mask)
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1977 mask = (qmask >> 32);
1978 if (mask)
1979 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1980 break;
1981 default:
1982 break;
1983 }
1984 /* skip the flush */
1985 }
1986
1987 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1988 {
1989 struct ixgbe_q_vector *q_vector = data;
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 struct ixgbe_ring *tx_ring;
1992 int i, r_idx;
1993
1994 if (!q_vector->txr_count)
1995 return IRQ_HANDLED;
1996
1997 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998 for (i = 0; i < q_vector->txr_count; i++) {
1999 tx_ring = adapter->tx_ring[r_idx];
2000 tx_ring->total_bytes = 0;
2001 tx_ring->total_packets = 0;
2002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2003 r_idx + 1);
2004 }
2005
2006 /* EIAM disabled interrupts (on this vector) for us */
2007 napi_schedule(&q_vector->napi);
2008
2009 return IRQ_HANDLED;
2010 }
2011
2012 /**
2013 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2014 * @irq: unused
2015 * @data: pointer to our q_vector struct for this interrupt vector
2016 **/
2017 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2018 {
2019 struct ixgbe_q_vector *q_vector = data;
2020 struct ixgbe_adapter *adapter = q_vector->adapter;
2021 struct ixgbe_ring *rx_ring;
2022 int r_idx;
2023 int i;
2024
2025 #ifdef CONFIG_IXGBE_DCA
2026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027 ixgbe_update_dca(q_vector);
2028 #endif
2029
2030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2031 for (i = 0; i < q_vector->rxr_count; i++) {
2032 rx_ring = adapter->rx_ring[r_idx];
2033 rx_ring->total_bytes = 0;
2034 rx_ring->total_packets = 0;
2035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2036 r_idx + 1);
2037 }
2038
2039 if (!q_vector->rxr_count)
2040 return IRQ_HANDLED;
2041
2042 /* EIAM disabled interrupts (on this vector) for us */
2043 napi_schedule(&q_vector->napi);
2044
2045 return IRQ_HANDLED;
2046 }
2047
2048 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2049 {
2050 struct ixgbe_q_vector *q_vector = data;
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 struct ixgbe_ring *ring;
2053 int r_idx;
2054 int i;
2055
2056 if (!q_vector->txr_count && !q_vector->rxr_count)
2057 return IRQ_HANDLED;
2058
2059 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060 for (i = 0; i < q_vector->txr_count; i++) {
2061 ring = adapter->tx_ring[r_idx];
2062 ring->total_bytes = 0;
2063 ring->total_packets = 0;
2064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2065 r_idx + 1);
2066 }
2067
2068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069 for (i = 0; i < q_vector->rxr_count; i++) {
2070 ring = adapter->rx_ring[r_idx];
2071 ring->total_bytes = 0;
2072 ring->total_packets = 0;
2073 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2074 r_idx + 1);
2075 }
2076
2077 /* EIAM disabled interrupts (on this vector) for us */
2078 napi_schedule(&q_vector->napi);
2079
2080 return IRQ_HANDLED;
2081 }
2082
2083 /**
2084 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085 * @napi: napi struct with our devices info in it
2086 * @budget: amount of work driver is allowed to do this pass, in packets
2087 *
2088 * This function is optimized for cleaning one queue only on a single
2089 * q_vector!!!
2090 **/
2091 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2092 {
2093 struct ixgbe_q_vector *q_vector =
2094 container_of(napi, struct ixgbe_q_vector, napi);
2095 struct ixgbe_adapter *adapter = q_vector->adapter;
2096 struct ixgbe_ring *rx_ring = NULL;
2097 int work_done = 0;
2098 long r_idx;
2099
2100 #ifdef CONFIG_IXGBE_DCA
2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2102 ixgbe_update_dca(q_vector);
2103 #endif
2104
2105 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106 rx_ring = adapter->rx_ring[r_idx];
2107
2108 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2109
2110 /* If all Rx work done, exit the polling mode */
2111 if (work_done < budget) {
2112 napi_complete(napi);
2113 if (adapter->rx_itr_setting & 1)
2114 ixgbe_set_itr_msix(q_vector);
2115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2116 ixgbe_irq_enable_queues(adapter,
2117 ((u64)1 << q_vector->v_idx));
2118 }
2119
2120 return work_done;
2121 }
2122
2123 /**
2124 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2125 * @napi: napi struct with our devices info in it
2126 * @budget: amount of work driver is allowed to do this pass, in packets
2127 *
2128 * This function will clean more than one rx queue associated with a
2129 * q_vector.
2130 **/
2131 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2132 {
2133 struct ixgbe_q_vector *q_vector =
2134 container_of(napi, struct ixgbe_q_vector, napi);
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_ring *ring = NULL;
2137 int work_done = 0, i;
2138 long r_idx;
2139 bool tx_clean_complete = true;
2140
2141 #ifdef CONFIG_IXGBE_DCA
2142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143 ixgbe_update_dca(q_vector);
2144 #endif
2145
2146 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147 for (i = 0; i < q_vector->txr_count; i++) {
2148 ring = adapter->tx_ring[r_idx];
2149 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2151 r_idx + 1);
2152 }
2153
2154 /* attempt to distribute budget to each queue fairly, but don't allow
2155 * the budget to go below 1 because we'll exit polling */
2156 budget /= (q_vector->rxr_count ?: 1);
2157 budget = max(budget, 1);
2158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159 for (i = 0; i < q_vector->rxr_count; i++) {
2160 ring = adapter->rx_ring[r_idx];
2161 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2162 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2163 r_idx + 1);
2164 }
2165
2166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2167 ring = adapter->rx_ring[r_idx];
2168 /* If all Rx work done, exit the polling mode */
2169 if (work_done < budget) {
2170 napi_complete(napi);
2171 if (adapter->rx_itr_setting & 1)
2172 ixgbe_set_itr_msix(q_vector);
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable_queues(adapter,
2175 ((u64)1 << q_vector->v_idx));
2176 return 0;
2177 }
2178
2179 return work_done;
2180 }
2181
2182 /**
2183 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184 * @napi: napi struct with our devices info in it
2185 * @budget: amount of work driver is allowed to do this pass, in packets
2186 *
2187 * This function is optimized for cleaning one queue only on a single
2188 * q_vector!!!
2189 **/
2190 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2191 {
2192 struct ixgbe_q_vector *q_vector =
2193 container_of(napi, struct ixgbe_q_vector, napi);
2194 struct ixgbe_adapter *adapter = q_vector->adapter;
2195 struct ixgbe_ring *tx_ring = NULL;
2196 int work_done = 0;
2197 long r_idx;
2198
2199 #ifdef CONFIG_IXGBE_DCA
2200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2201 ixgbe_update_dca(q_vector);
2202 #endif
2203
2204 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205 tx_ring = adapter->tx_ring[r_idx];
2206
2207 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2208 work_done = budget;
2209
2210 /* If all Tx work done, exit the polling mode */
2211 if (work_done < budget) {
2212 napi_complete(napi);
2213 if (adapter->tx_itr_setting & 1)
2214 ixgbe_set_itr_msix(q_vector);
2215 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216 ixgbe_irq_enable_queues(adapter,
2217 ((u64)1 << q_vector->v_idx));
2218 }
2219
2220 return work_done;
2221 }
2222
2223 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2224 int r_idx)
2225 {
2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2228
2229 set_bit(r_idx, q_vector->rxr_idx);
2230 q_vector->rxr_count++;
2231 rx_ring->q_vector = q_vector;
2232 }
2233
2234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2235 int t_idx)
2236 {
2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2239
2240 set_bit(t_idx, q_vector->txr_idx);
2241 q_vector->txr_count++;
2242 tx_ring->q_vector = q_vector;
2243 }
2244
2245 /**
2246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247 * @adapter: board private structure to initialize
2248 *
2249 * This function maps descriptor rings to the queue-specific vectors
2250 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2251 * one vector per ring/queue, but on a constrained vector budget, we
2252 * group the rings as "efficiently" as possible. You would add new
2253 * mapping configurations in here.
2254 **/
2255 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2256 {
2257 int q_vectors;
2258 int v_start = 0;
2259 int rxr_idx = 0, txr_idx = 0;
2260 int rxr_remaining = adapter->num_rx_queues;
2261 int txr_remaining = adapter->num_tx_queues;
2262 int i, j;
2263 int rqpv, tqpv;
2264 int err = 0;
2265
2266 /* No mapping required if MSI-X is disabled. */
2267 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2268 goto out;
2269
2270 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2271
2272 /*
2273 * The ideal configuration...
2274 * We have enough vectors to map one per queue.
2275 */
2276 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278 map_vector_to_rxq(adapter, v_start, rxr_idx);
2279
2280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281 map_vector_to_txq(adapter, v_start, txr_idx);
2282
2283 goto out;
2284 }
2285
2286 /*
2287 * If we don't have enough vectors for a 1-to-1
2288 * mapping, we'll have to group them so there are
2289 * multiple queues per vector.
2290 */
2291 /* Re-adjusting *qpv takes care of the remainder. */
2292 for (i = v_start; i < q_vectors; i++) {
2293 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2294 for (j = 0; j < rqpv; j++) {
2295 map_vector_to_rxq(adapter, i, rxr_idx);
2296 rxr_idx++;
2297 rxr_remaining--;
2298 }
2299 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2300 for (j = 0; j < tqpv; j++) {
2301 map_vector_to_txq(adapter, i, txr_idx);
2302 txr_idx++;
2303 txr_remaining--;
2304 }
2305 }
2306 out:
2307 return err;
2308 }
2309
2310 /**
2311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312 * @adapter: board private structure
2313 *
2314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315 * interrupts from the kernel.
2316 **/
2317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2318 {
2319 struct net_device *netdev = adapter->netdev;
2320 irqreturn_t (*handler)(int, void *);
2321 int i, vector, q_vectors, err;
2322 int ri = 0, ti = 0;
2323
2324 /* Decrement for Other and TCP Timer vectors */
2325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2326
2327 err = ixgbe_map_rings_to_vectors(adapter);
2328 if (err)
2329 return err;
2330
2331 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2332 ? &ixgbe_msix_clean_many : \
2333 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2334 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2335 NULL)
2336 for (vector = 0; vector < q_vectors; vector++) {
2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338 handler = SET_HANDLER(q_vector);
2339
2340 if (handler == &ixgbe_msix_clean_rx) {
2341 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342 "%s-%s-%d", netdev->name, "rx", ri++);
2343 } else if (handler == &ixgbe_msix_clean_tx) {
2344 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345 "%s-%s-%d", netdev->name, "tx", ti++);
2346 } else if (handler == &ixgbe_msix_clean_many) {
2347 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348 "%s-%s-%d", netdev->name, "TxRx", ri++);
2349 ti++;
2350 } else {
2351 /* skip this unused q_vector */
2352 continue;
2353 }
2354 err = request_irq(adapter->msix_entries[vector].vector,
2355 handler, 0, q_vector->name,
2356 q_vector);
2357 if (err) {
2358 e_err(probe, "request_irq failed for MSIX interrupt "
2359 "Error: %d\n", err);
2360 goto free_queue_irqs;
2361 }
2362 }
2363
2364 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2365 err = request_irq(adapter->msix_entries[vector].vector,
2366 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2367 if (err) {
2368 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2369 goto free_queue_irqs;
2370 }
2371
2372 return 0;
2373
2374 free_queue_irqs:
2375 for (i = vector - 1; i >= 0; i--)
2376 free_irq(adapter->msix_entries[--vector].vector,
2377 adapter->q_vector[i]);
2378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379 pci_disable_msix(adapter->pdev);
2380 kfree(adapter->msix_entries);
2381 adapter->msix_entries = NULL;
2382 return err;
2383 }
2384
2385 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2386 {
2387 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2388 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2390 u32 new_itr = q_vector->eitr;
2391 u8 current_itr;
2392
2393 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2394 q_vector->tx_itr,
2395 tx_ring->total_packets,
2396 tx_ring->total_bytes);
2397 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2398 q_vector->rx_itr,
2399 rx_ring->total_packets,
2400 rx_ring->total_bytes);
2401
2402 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2403
2404 switch (current_itr) {
2405 /* counts and packets in update_itr are dependent on these numbers */
2406 case lowest_latency:
2407 new_itr = 100000;
2408 break;
2409 case low_latency:
2410 new_itr = 20000; /* aka hwitr = ~200 */
2411 break;
2412 case bulk_latency:
2413 new_itr = 8000;
2414 break;
2415 default:
2416 break;
2417 }
2418
2419 if (new_itr != q_vector->eitr) {
2420 /* do an exponential smoothing */
2421 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2422
2423 /* save the algorithm value here */
2424 q_vector->eitr = new_itr;
2425
2426 ixgbe_write_eitr(q_vector);
2427 }
2428 }
2429
2430 /**
2431 * ixgbe_irq_enable - Enable default interrupt generation settings
2432 * @adapter: board private structure
2433 **/
2434 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2435 bool flush)
2436 {
2437 u32 mask;
2438
2439 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2440 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441 mask |= IXGBE_EIMS_GPI_SDP0;
2442 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443 mask |= IXGBE_EIMS_GPI_SDP1;
2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82599EB:
2446 case ixgbe_mac_X540:
2447 mask |= IXGBE_EIMS_ECC;
2448 mask |= IXGBE_EIMS_GPI_SDP1;
2449 mask |= IXGBE_EIMS_GPI_SDP2;
2450 if (adapter->num_vfs)
2451 mask |= IXGBE_EIMS_MAILBOX;
2452 break;
2453 default:
2454 break;
2455 }
2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458 mask |= IXGBE_EIMS_FLOW_DIR;
2459
2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2461 if (queues)
2462 ixgbe_irq_enable_queues(adapter, ~0);
2463 if (flush)
2464 IXGBE_WRITE_FLUSH(&adapter->hw);
2465
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469 }
2470 }
2471
2472 /**
2473 * ixgbe_intr - legacy mode Interrupt Handler
2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
2476 **/
2477 static irqreturn_t ixgbe_intr(int irq, void *data)
2478 {
2479 struct net_device *netdev = data;
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2483 u32 eicr;
2484
2485 /*
2486 * Workaround for silicon errata on 82598. Mask the interrupts
2487 * before the read of EICR.
2488 */
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2490
2491 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492 * therefore no explict interrupt disable is necessary */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2494 if (!eicr) {
2495 /*
2496 * shared interrupt alert!
2497 * make sure interrupts are enabled because the read will
2498 * have disabled interrupts due to EIAM
2499 * finish the workaround of silicon errata on 82598. Unmask
2500 * the interrupt that we masked before the EICR read.
2501 */
2502 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503 ixgbe_irq_enable(adapter, true, true);
2504 return IRQ_NONE; /* Not our interrupt */
2505 }
2506
2507 if (eicr & IXGBE_EICR_LSC)
2508 ixgbe_check_lsc(adapter);
2509
2510 switch (hw->mac.type) {
2511 case ixgbe_mac_82599EB:
2512 ixgbe_check_sfp_event(adapter, eicr);
2513 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515 adapter->interrupt_event = eicr;
2516 schedule_work(&adapter->check_overtemp_task);
2517 }
2518 break;
2519 default:
2520 break;
2521 }
2522
2523 ixgbe_check_fan_failure(adapter, eicr);
2524
2525 if (napi_schedule_prep(&(q_vector->napi))) {
2526 adapter->tx_ring[0]->total_packets = 0;
2527 adapter->tx_ring[0]->total_bytes = 0;
2528 adapter->rx_ring[0]->total_packets = 0;
2529 adapter->rx_ring[0]->total_bytes = 0;
2530 /* would disable interrupts here but EIAM disabled it */
2531 __napi_schedule(&(q_vector->napi));
2532 }
2533
2534 /*
2535 * re-enable link(maybe) and non-queue interrupts, no flush.
2536 * ixgbe_poll will re-enable the queue interrupts
2537 */
2538
2539 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540 ixgbe_irq_enable(adapter, false, false);
2541
2542 return IRQ_HANDLED;
2543 }
2544
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546 {
2547 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549 for (i = 0; i < q_vectors; i++) {
2550 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553 q_vector->rxr_count = 0;
2554 q_vector->txr_count = 0;
2555 }
2556 }
2557
2558 /**
2559 * ixgbe_request_irq - initialize interrupts
2560 * @adapter: board private structure
2561 *
2562 * Attempts to configure interrupts using the best available
2563 * capabilities of the hardware and kernel.
2564 **/
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2566 {
2567 struct net_device *netdev = adapter->netdev;
2568 int err;
2569
2570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571 err = ixgbe_request_msix_irqs(adapter);
2572 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574 netdev->name, netdev);
2575 } else {
2576 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577 netdev->name, netdev);
2578 }
2579
2580 if (err)
2581 e_err(probe, "request_irq failed, Error %d\n", err);
2582
2583 return err;
2584 }
2585
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587 {
2588 struct net_device *netdev = adapter->netdev;
2589
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591 int i, q_vectors;
2592
2593 q_vectors = adapter->num_msix_vectors;
2594
2595 i = q_vectors - 1;
2596 free_irq(adapter->msix_entries[i].vector, netdev);
2597
2598 i--;
2599 for (; i >= 0; i--) {
2600 free_irq(adapter->msix_entries[i].vector,
2601 adapter->q_vector[i]);
2602 }
2603
2604 ixgbe_reset_q_vectors(adapter);
2605 } else {
2606 free_irq(adapter->pdev->irq, netdev);
2607 }
2608 }
2609
2610 /**
2611 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612 * @adapter: board private structure
2613 **/
2614 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2615 {
2616 switch (adapter->hw.mac.type) {
2617 case ixgbe_mac_82598EB:
2618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2619 break;
2620 case ixgbe_mac_82599EB:
2621 case ixgbe_mac_X540:
2622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2625 if (adapter->num_vfs > 32)
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2627 break;
2628 default:
2629 break;
2630 }
2631 IXGBE_WRITE_FLUSH(&adapter->hw);
2632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2633 int i;
2634 for (i = 0; i < adapter->num_msix_vectors; i++)
2635 synchronize_irq(adapter->msix_entries[i].vector);
2636 } else {
2637 synchronize_irq(adapter->pdev->irq);
2638 }
2639 }
2640
2641 /**
2642 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2643 *
2644 **/
2645 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2646 {
2647 struct ixgbe_hw *hw = &adapter->hw;
2648
2649 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2650 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2651
2652 ixgbe_set_ivar(adapter, 0, 0, 0);
2653 ixgbe_set_ivar(adapter, 1, 0, 0);
2654
2655 map_vector_to_rxq(adapter, 0, 0);
2656 map_vector_to_txq(adapter, 0, 0);
2657
2658 e_info(hw, "Legacy interrupt IVAR setup done\n");
2659 }
2660
2661 /**
2662 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663 * @adapter: board private structure
2664 * @ring: structure containing ring specific data
2665 *
2666 * Configure the Tx descriptor ring after a reset.
2667 **/
2668 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
2670 {
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u64 tdba = ring->dma;
2673 int wait_loop = 10;
2674 u32 txdctl;
2675 u8 reg_idx = ring->reg_idx;
2676
2677 /* disable queue to avoid issues while updating state */
2678 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680 txdctl & ~IXGBE_TXDCTL_ENABLE);
2681 IXGBE_WRITE_FLUSH(hw);
2682
2683 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2684 (tdba & DMA_BIT_MASK(32)));
2685 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687 ring->count * sizeof(union ixgbe_adv_tx_desc));
2688 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2690 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2691
2692 /* configure fetching thresholds */
2693 if (adapter->rx_itr_setting == 0) {
2694 /* cannot set wthresh when itr==0 */
2695 txdctl &= ~0x007F0000;
2696 } else {
2697 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698 txdctl |= (8 << 16);
2699 }
2700 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701 /* PThresh workaround for Tx hang with DFP enabled. */
2702 txdctl |= 32;
2703 }
2704
2705 /* reinitialize flowdirector state */
2706 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707 adapter->atr_sample_rate) {
2708 ring->atr_sample_rate = adapter->atr_sample_rate;
2709 ring->atr_count = 0;
2710 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2711 } else {
2712 ring->atr_sample_rate = 0;
2713 }
2714
2715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2716
2717 /* enable queue */
2718 txdctl |= IXGBE_TXDCTL_ENABLE;
2719 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2720
2721 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* poll to verify queue is enabled */
2727 do {
2728 msleep(1);
2729 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2731 if (!wait_loop)
2732 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2733 }
2734
2735 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2736 {
2737 struct ixgbe_hw *hw = &adapter->hw;
2738 u32 rttdcs;
2739 u32 mask;
2740
2741 if (hw->mac.type == ixgbe_mac_82598EB)
2742 return;
2743
2744 /* disable the arbiter while setting MTQC */
2745 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748
2749 /* set transmit pool layout */
2750 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751 switch (adapter->flags & mask) {
2752
2753 case (IXGBE_FLAG_SRIOV_ENABLED):
2754 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2756 break;
2757
2758 case (IXGBE_FLAG_DCB_ENABLED):
2759 /* We enable 8 traffic classes, DCB only */
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2762 break;
2763
2764 default:
2765 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2766 break;
2767 }
2768
2769 /* re-enable the arbiter */
2770 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772 }
2773
2774 /**
2775 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2776 * @adapter: board private structure
2777 *
2778 * Configure the Tx unit of the MAC after a reset.
2779 **/
2780 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2781 {
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 u32 dmatxctl;
2784 u32 i;
2785
2786 ixgbe_setup_mtqc(adapter);
2787
2788 if (hw->mac.type != ixgbe_mac_82598EB) {
2789 /* DMATXCTL.EN must be before Tx queues are enabled */
2790 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791 dmatxctl |= IXGBE_DMATXCTL_TE;
2792 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2793 }
2794
2795 /* Setup the HW Tx Head and Tail descriptor pointers */
2796 for (i = 0; i < adapter->num_tx_queues; i++)
2797 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2798 }
2799
2800 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2801
2802 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *rx_ring)
2804 {
2805 u32 srrctl;
2806 u8 reg_idx = rx_ring->reg_idx;
2807
2808 switch (adapter->hw.mac.type) {
2809 case ixgbe_mac_82598EB: {
2810 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811 const int mask = feature[RING_F_RSS].mask;
2812 reg_idx = reg_idx & mask;
2813 }
2814 break;
2815 case ixgbe_mac_82599EB:
2816 case ixgbe_mac_X540:
2817 default:
2818 break;
2819 }
2820
2821 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2822
2823 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2825 if (adapter->num_vfs)
2826 srrctl |= IXGBE_SRRCTL_DROP_EN;
2827
2828 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829 IXGBE_SRRCTL_BSIZEHDR_MASK;
2830
2831 if (ring_is_ps_enabled(rx_ring)) {
2832 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2834 #else
2835 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2836 #endif
2837 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2838 } else {
2839 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2842 }
2843
2844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2845 }
2846
2847 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2848 {
2849 struct ixgbe_hw *hw = &adapter->hw;
2850 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2851 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2853 u32 mrqc = 0, reta = 0;
2854 u32 rxcsum;
2855 int i, j;
2856 int mask;
2857
2858 /* Fill out hash function seeds */
2859 for (i = 0; i < 10; i++)
2860 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2861
2862 /* Fill out redirection table */
2863 for (i = 0, j = 0; i < 128; i++, j++) {
2864 if (j == adapter->ring_feature[RING_F_RSS].indices)
2865 j = 0;
2866 /* reta = 4-byte sliding window of
2867 * 0x00..(indices-1)(indices-1)00..etc. */
2868 reta = (reta << 8) | (j * 0x11);
2869 if ((i & 3) == 3)
2870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2871 }
2872
2873 /* Disable indicating checksum in descriptor, enables RSS hash */
2874 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875 rxcsum |= IXGBE_RXCSUM_PCSD;
2876 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2877
2878 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2880 else
2881 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2882 #ifdef CONFIG_IXGBE_DCB
2883 | IXGBE_FLAG_DCB_ENABLED
2884 #endif
2885 | IXGBE_FLAG_SRIOV_ENABLED
2886 );
2887
2888 switch (mask) {
2889 case (IXGBE_FLAG_RSS_ENABLED):
2890 mrqc = IXGBE_MRQC_RSSEN;
2891 break;
2892 case (IXGBE_FLAG_SRIOV_ENABLED):
2893 mrqc = IXGBE_MRQC_VMDQEN;
2894 break;
2895 #ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED):
2897 mrqc = IXGBE_MRQC_RT8TCEN;
2898 break;
2899 #endif /* CONFIG_IXGBE_DCB */
2900 default:
2901 break;
2902 }
2903
2904 /* Perform hash on these packet types */
2905 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907 | IXGBE_MRQC_RSS_FIELD_IPV6
2908 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2909
2910 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2911 }
2912
2913 /**
2914 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915 * @adapter: address of board private structure
2916 * @ring: structure containing ring specific data
2917 **/
2918 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919 struct ixgbe_ring *ring)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 u32 rscctrl;
2923 u8 reg_idx = ring->reg_idx;
2924
2925 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2928 }
2929
2930 /**
2931 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932 * @adapter: address of board private structure
2933 * @index: index of ring to set
2934 **/
2935 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *ring)
2937 {
2938 struct ixgbe_hw *hw = &adapter->hw;
2939 u32 rscctrl;
2940 int rx_buf_len;
2941 u8 reg_idx = ring->reg_idx;
2942
2943 if (!ring_is_rsc_enabled(ring))
2944 return;
2945
2946 rx_buf_len = ring->rx_buf_len;
2947 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2948 rscctrl |= IXGBE_RSCCTL_RSCEN;
2949 /*
2950 * we must limit the number of descriptors so that the
2951 * total size of max desc * buf_len is not greater
2952 * than 65535
2953 */
2954 if (ring_is_ps_enabled(ring)) {
2955 #if (MAX_SKB_FRAGS > 16)
2956 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957 #elif (MAX_SKB_FRAGS > 8)
2958 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959 #elif (MAX_SKB_FRAGS > 4)
2960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2961 #else
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2963 #endif
2964 } else {
2965 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2969 else
2970 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971 }
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2973 }
2974
2975 /**
2976 * ixgbe_set_uta - Set unicast filter table address
2977 * @adapter: board private structure
2978 *
2979 * The unicast table address is a register array of 32-bit registers.
2980 * The table is meant to be used in a way similar to how the MTA is used
2981 * however due to certain limitations in the hardware it is necessary to
2982 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2984 **/
2985 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2986 {
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 int i;
2989
2990 /* The UTA table only exists on 82599 hardware and newer */
2991 if (hw->mac.type < ixgbe_mac_82599EB)
2992 return;
2993
2994 /* we only need to do this if VMDq is enabled */
2995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2996 return;
2997
2998 for (i = 0; i < 128; i++)
2999 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3000 }
3001
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3005 {
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008 u32 rxdctl;
3009 u8 reg_idx = ring->reg_idx;
3010
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014 return;
3015
3016 do {
3017 msleep(1);
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021 if (!wait_loop) {
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3024 }
3025 }
3026
3027 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029 {
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 u64 rdba = ring->dma;
3032 u32 rxdctl;
3033 u8 reg_idx = ring->reg_idx;
3034
3035 /* disable queue to avoid issues while updating state */
3036 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3037 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
3038 rxdctl & ~IXGBE_RXDCTL_ENABLE);
3039 IXGBE_WRITE_FLUSH(hw);
3040
3041 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3042 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3043 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3044 ring->count * sizeof(union ixgbe_adv_rx_desc));
3045 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3046 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3047 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3048
3049 ixgbe_configure_srrctl(adapter, ring);
3050 ixgbe_configure_rscctl(adapter, ring);
3051
3052 if (hw->mac.type == ixgbe_mac_82598EB) {
3053 /*
3054 * enable cache line friendly hardware writes:
3055 * PTHRESH=32 descriptors (half the internal cache),
3056 * this also removes ugly rx_no_buffer_count increment
3057 * HTHRESH=4 descriptors (to minimize latency on fetch)
3058 * WTHRESH=8 burst writeback up to two cache lines
3059 */
3060 rxdctl &= ~0x3FFFFF;
3061 rxdctl |= 0x080420;
3062 }
3063
3064 /* enable receive descriptor ring */
3065 rxdctl |= IXGBE_RXDCTL_ENABLE;
3066 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3067
3068 ixgbe_rx_desc_queue_enable(adapter, ring);
3069 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3070 }
3071
3072 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3073 {
3074 struct ixgbe_hw *hw = &adapter->hw;
3075 int p;
3076
3077 /* PSRTYPE must be initialized in non 82598 adapters */
3078 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3079 IXGBE_PSRTYPE_UDPHDR |
3080 IXGBE_PSRTYPE_IPV4HDR |
3081 IXGBE_PSRTYPE_L2HDR |
3082 IXGBE_PSRTYPE_IPV6HDR;
3083
3084 if (hw->mac.type == ixgbe_mac_82598EB)
3085 return;
3086
3087 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3088 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3089
3090 for (p = 0; p < adapter->num_rx_pools; p++)
3091 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3092 psrtype);
3093 }
3094
3095 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3096 {
3097 struct ixgbe_hw *hw = &adapter->hw;
3098 u32 gcr_ext;
3099 u32 vt_reg_bits;
3100 u32 reg_offset, vf_shift;
3101 u32 vmdctl;
3102
3103 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3104 return;
3105
3106 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3107 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3108 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3109 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3110
3111 vf_shift = adapter->num_vfs % 32;
3112 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3113
3114 /* Enable only the PF's pool for Tx/Rx */
3115 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3116 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3117 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3118 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3119 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3120
3121 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3122 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3123
3124 /*
3125 * Set up VF register offsets for selected VT Mode,
3126 * i.e. 32 or 64 VFs for SR-IOV
3127 */
3128 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3129 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3130 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3131 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3132
3133 /* enable Tx loopback for VF/PF communication */
3134 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3135 /* Enable MAC Anti-Spoofing */
3136 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3137 adapter->num_vfs);
3138 }
3139
3140 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3141 {
3142 struct ixgbe_hw *hw = &adapter->hw;
3143 struct net_device *netdev = adapter->netdev;
3144 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3145 int rx_buf_len;
3146 struct ixgbe_ring *rx_ring;
3147 int i;
3148 u32 mhadd, hlreg0;
3149
3150 /* Decide whether to use packet split mode or not */
3151 /* Do not use packet split if we're in SR-IOV Mode */
3152 if (!adapter->num_vfs)
3153 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3154
3155 /* Set the RX buffer length according to the mode */
3156 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3157 rx_buf_len = IXGBE_RX_HDR_SIZE;
3158 } else {
3159 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3160 (netdev->mtu <= ETH_DATA_LEN))
3161 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3162 else
3163 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3164 }
3165
3166 #ifdef IXGBE_FCOE
3167 /* adjust max frame to be able to do baby jumbo for FCoE */
3168 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3169 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3170 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3171
3172 #endif /* IXGBE_FCOE */
3173 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3174 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3175 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3176 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3177
3178 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3179 }
3180
3181 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3182 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3183 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3184 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3185
3186 /*
3187 * Setup the HW Rx Head and Tail Descriptor Pointers and
3188 * the Base and Length of the Rx Descriptor Ring
3189 */
3190 for (i = 0; i < adapter->num_rx_queues; i++) {
3191 rx_ring = adapter->rx_ring[i];
3192 rx_ring->rx_buf_len = rx_buf_len;
3193
3194 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3195 set_ring_ps_enabled(rx_ring);
3196 else
3197 clear_ring_ps_enabled(rx_ring);
3198
3199 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3200 set_ring_rsc_enabled(rx_ring);
3201 else
3202 clear_ring_rsc_enabled(rx_ring);
3203
3204 #ifdef IXGBE_FCOE
3205 if (netdev->features & NETIF_F_FCOE_MTU) {
3206 struct ixgbe_ring_feature *f;
3207 f = &adapter->ring_feature[RING_F_FCOE];
3208 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3209 clear_ring_ps_enabled(rx_ring);
3210 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3211 rx_ring->rx_buf_len =
3212 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3213 } else if (!ring_is_rsc_enabled(rx_ring) &&
3214 !ring_is_ps_enabled(rx_ring)) {
3215 rx_ring->rx_buf_len =
3216 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3217 }
3218 }
3219 #endif /* IXGBE_FCOE */
3220 }
3221 }
3222
3223 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3224 {
3225 struct ixgbe_hw *hw = &adapter->hw;
3226 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3227
3228 switch (hw->mac.type) {
3229 case ixgbe_mac_82598EB:
3230 /*
3231 * For VMDq support of different descriptor types or
3232 * buffer sizes through the use of multiple SRRCTL
3233 * registers, RDRXCTL.MVMEN must be set to 1
3234 *
3235 * also, the manual doesn't mention it clearly but DCA hints
3236 * will only use queue 0's tags unless this bit is set. Side
3237 * effects of setting this bit are only that SRRCTL must be
3238 * fully programmed [0..15]
3239 */
3240 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3241 break;
3242 case ixgbe_mac_82599EB:
3243 case ixgbe_mac_X540:
3244 /* Disable RSC for ACK packets */
3245 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3246 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3247 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3248 /* hardware requires some bits to be set by default */
3249 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3250 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3251 break;
3252 default:
3253 /* We should do nothing since we don't know this hardware */
3254 return;
3255 }
3256
3257 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3258 }
3259
3260 /**
3261 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3262 * @adapter: board private structure
3263 *
3264 * Configure the Rx unit of the MAC after a reset.
3265 **/
3266 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3267 {
3268 struct ixgbe_hw *hw = &adapter->hw;
3269 int i;
3270 u32 rxctrl;
3271
3272 /* disable receives while setting up the descriptors */
3273 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3274 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3275
3276 ixgbe_setup_psrtype(adapter);
3277 ixgbe_setup_rdrxctl(adapter);
3278
3279 /* Program registers for the distribution of queues */
3280 ixgbe_setup_mrqc(adapter);
3281
3282 ixgbe_set_uta(adapter);
3283
3284 /* set_rx_buffer_len must be called before ring initialization */
3285 ixgbe_set_rx_buffer_len(adapter);
3286
3287 /*
3288 * Setup the HW Rx Head and Tail Descriptor Pointers and
3289 * the Base and Length of the Rx Descriptor Ring
3290 */
3291 for (i = 0; i < adapter->num_rx_queues; i++)
3292 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3293
3294 /* disable drop enable for 82598 parts */
3295 if (hw->mac.type == ixgbe_mac_82598EB)
3296 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3297
3298 /* enable all receives */
3299 rxctrl |= IXGBE_RXCTRL_RXEN;
3300 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3301 }
3302
3303 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3304 {
3305 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3306 struct ixgbe_hw *hw = &adapter->hw;
3307 int pool_ndx = adapter->num_vfs;
3308
3309 /* add VID to filter table */
3310 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3311 set_bit(vid, adapter->active_vlans);
3312 }
3313
3314 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3315 {
3316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3317 struct ixgbe_hw *hw = &adapter->hw;
3318 int pool_ndx = adapter->num_vfs;
3319
3320 /* remove VID from filter table */
3321 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3322 clear_bit(vid, adapter->active_vlans);
3323 }
3324
3325 /**
3326 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3327 * @adapter: driver data
3328 */
3329 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3330 {
3331 struct ixgbe_hw *hw = &adapter->hw;
3332 u32 vlnctrl;
3333
3334 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3335 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3336 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3337 }
3338
3339 /**
3340 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3341 * @adapter: driver data
3342 */
3343 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3344 {
3345 struct ixgbe_hw *hw = &adapter->hw;
3346 u32 vlnctrl;
3347
3348 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3349 vlnctrl |= IXGBE_VLNCTRL_VFE;
3350 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3351 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3352 }
3353
3354 /**
3355 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3356 * @adapter: driver data
3357 */
3358 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3359 {
3360 struct ixgbe_hw *hw = &adapter->hw;
3361 u32 vlnctrl;
3362 int i, j;
3363
3364 switch (hw->mac.type) {
3365 case ixgbe_mac_82598EB:
3366 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3367 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3368 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3369 break;
3370 case ixgbe_mac_82599EB:
3371 case ixgbe_mac_X540:
3372 for (i = 0; i < adapter->num_rx_queues; i++) {
3373 j = adapter->rx_ring[i]->reg_idx;
3374 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3375 vlnctrl &= ~IXGBE_RXDCTL_VME;
3376 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3377 }
3378 break;
3379 default:
3380 break;
3381 }
3382 }
3383
3384 /**
3385 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3386 * @adapter: driver data
3387 */
3388 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3389 {
3390 struct ixgbe_hw *hw = &adapter->hw;
3391 u32 vlnctrl;
3392 int i, j;
3393
3394 switch (hw->mac.type) {
3395 case ixgbe_mac_82598EB:
3396 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3397 vlnctrl |= IXGBE_VLNCTRL_VME;
3398 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3399 break;
3400 case ixgbe_mac_82599EB:
3401 case ixgbe_mac_X540:
3402 for (i = 0; i < adapter->num_rx_queues; i++) {
3403 j = adapter->rx_ring[i]->reg_idx;
3404 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3405 vlnctrl |= IXGBE_RXDCTL_VME;
3406 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3407 }
3408 break;
3409 default:
3410 break;
3411 }
3412 }
3413
3414 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3415 {
3416 u16 vid;
3417
3418 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3419
3420 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3421 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3422 }
3423
3424 /**
3425 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3426 * @netdev: network interface device structure
3427 *
3428 * Writes unicast address list to the RAR table.
3429 * Returns: -ENOMEM on failure/insufficient address space
3430 * 0 on no addresses written
3431 * X on writing X addresses to the RAR table
3432 **/
3433 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3434 {
3435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3436 struct ixgbe_hw *hw = &adapter->hw;
3437 unsigned int vfn = adapter->num_vfs;
3438 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3439 int count = 0;
3440
3441 /* return ENOMEM indicating insufficient memory for addresses */
3442 if (netdev_uc_count(netdev) > rar_entries)
3443 return -ENOMEM;
3444
3445 if (!netdev_uc_empty(netdev) && rar_entries) {
3446 struct netdev_hw_addr *ha;
3447 /* return error if we do not support writing to RAR table */
3448 if (!hw->mac.ops.set_rar)
3449 return -ENOMEM;
3450
3451 netdev_for_each_uc_addr(ha, netdev) {
3452 if (!rar_entries)
3453 break;
3454 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3455 vfn, IXGBE_RAH_AV);
3456 count++;
3457 }
3458 }
3459 /* write the addresses in reverse order to avoid write combining */
3460 for (; rar_entries > 0 ; rar_entries--)
3461 hw->mac.ops.clear_rar(hw, rar_entries);
3462
3463 return count;
3464 }
3465
3466 /**
3467 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3468 * @netdev: network interface device structure
3469 *
3470 * The set_rx_method entry point is called whenever the unicast/multicast
3471 * address list or the network interface flags are updated. This routine is
3472 * responsible for configuring the hardware for proper unicast, multicast and
3473 * promiscuous mode.
3474 **/
3475 void ixgbe_set_rx_mode(struct net_device *netdev)
3476 {
3477 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3478 struct ixgbe_hw *hw = &adapter->hw;
3479 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3480 int count;
3481
3482 /* Check for Promiscuous and All Multicast modes */
3483
3484 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3485
3486 /* set all bits that we expect to always be set */
3487 fctrl |= IXGBE_FCTRL_BAM;
3488 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3489 fctrl |= IXGBE_FCTRL_PMCF;
3490
3491 /* clear the bits we are changing the status of */
3492 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3493
3494 if (netdev->flags & IFF_PROMISC) {
3495 hw->addr_ctrl.user_set_promisc = true;
3496 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3497 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3498 /* don't hardware filter vlans in promisc mode */
3499 ixgbe_vlan_filter_disable(adapter);
3500 } else {
3501 if (netdev->flags & IFF_ALLMULTI) {
3502 fctrl |= IXGBE_FCTRL_MPE;
3503 vmolr |= IXGBE_VMOLR_MPE;
3504 } else {
3505 /*
3506 * Write addresses to the MTA, if the attempt fails
3507 * then we should just turn on promiscous mode so
3508 * that we can at least receive multicast traffic
3509 */
3510 hw->mac.ops.update_mc_addr_list(hw, netdev);
3511 vmolr |= IXGBE_VMOLR_ROMPE;
3512 }
3513 ixgbe_vlan_filter_enable(adapter);
3514 hw->addr_ctrl.user_set_promisc = false;
3515 /*
3516 * Write addresses to available RAR registers, if there is not
3517 * sufficient space to store all the addresses then enable
3518 * unicast promiscous mode
3519 */
3520 count = ixgbe_write_uc_addr_list(netdev);
3521 if (count < 0) {
3522 fctrl |= IXGBE_FCTRL_UPE;
3523 vmolr |= IXGBE_VMOLR_ROPE;
3524 }
3525 }
3526
3527 if (adapter->num_vfs) {
3528 ixgbe_restore_vf_multicasts(adapter);
3529 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3530 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3531 IXGBE_VMOLR_ROPE);
3532 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3533 }
3534
3535 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3536
3537 if (netdev->features & NETIF_F_HW_VLAN_RX)
3538 ixgbe_vlan_strip_enable(adapter);
3539 else
3540 ixgbe_vlan_strip_disable(adapter);
3541 }
3542
3543 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3544 {
3545 int q_idx;
3546 struct ixgbe_q_vector *q_vector;
3547 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3548
3549 /* legacy and MSI only use one vector */
3550 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3551 q_vectors = 1;
3552
3553 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3554 struct napi_struct *napi;
3555 q_vector = adapter->q_vector[q_idx];
3556 napi = &q_vector->napi;
3557 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3558 if (!q_vector->rxr_count || !q_vector->txr_count) {
3559 if (q_vector->txr_count == 1)
3560 napi->poll = &ixgbe_clean_txonly;
3561 else if (q_vector->rxr_count == 1)
3562 napi->poll = &ixgbe_clean_rxonly;
3563 }
3564 }
3565
3566 napi_enable(napi);
3567 }
3568 }
3569
3570 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3571 {
3572 int q_idx;
3573 struct ixgbe_q_vector *q_vector;
3574 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3575
3576 /* legacy and MSI only use one vector */
3577 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3578 q_vectors = 1;
3579
3580 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3581 q_vector = adapter->q_vector[q_idx];
3582 napi_disable(&q_vector->napi);
3583 }
3584 }
3585
3586 #ifdef CONFIG_IXGBE_DCB
3587 /*
3588 * ixgbe_configure_dcb - Configure DCB hardware
3589 * @adapter: ixgbe adapter struct
3590 *
3591 * This is called by the driver on open to configure the DCB hardware.
3592 * This is also called by the gennetlink interface when reconfiguring
3593 * the DCB state.
3594 */
3595 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3596 {
3597 struct ixgbe_hw *hw = &adapter->hw;
3598 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3599
3600 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3601 if (hw->mac.type == ixgbe_mac_82598EB)
3602 netif_set_gso_max_size(adapter->netdev, 65536);
3603 return;
3604 }
3605
3606 if (hw->mac.type == ixgbe_mac_82598EB)
3607 netif_set_gso_max_size(adapter->netdev, 32768);
3608
3609 #ifdef CONFIG_FCOE
3610 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3611 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3612 #endif
3613
3614 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3615 DCB_TX_CONFIG);
3616 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3617 DCB_RX_CONFIG);
3618
3619 /* Enable VLAN tag insert/strip */
3620 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3621
3622 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3623
3624 /* reconfigure the hardware */
3625 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3626 }
3627
3628 #endif
3629 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3630 {
3631 struct net_device *netdev = adapter->netdev;
3632 struct ixgbe_hw *hw = &adapter->hw;
3633 int i;
3634
3635 #ifdef CONFIG_IXGBE_DCB
3636 ixgbe_configure_dcb(adapter);
3637 #endif
3638
3639 ixgbe_set_rx_mode(netdev);
3640 ixgbe_restore_vlan(adapter);
3641
3642 #ifdef IXGBE_FCOE
3643 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3644 ixgbe_configure_fcoe(adapter);
3645
3646 #endif /* IXGBE_FCOE */
3647 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3648 for (i = 0; i < adapter->num_tx_queues; i++)
3649 adapter->tx_ring[i]->atr_sample_rate =
3650 adapter->atr_sample_rate;
3651 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3652 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3653 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3654 }
3655 ixgbe_configure_virtualization(adapter);
3656
3657 ixgbe_configure_tx(adapter);
3658 ixgbe_configure_rx(adapter);
3659 }
3660
3661 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3662 {
3663 switch (hw->phy.type) {
3664 case ixgbe_phy_sfp_avago:
3665 case ixgbe_phy_sfp_ftl:
3666 case ixgbe_phy_sfp_intel:
3667 case ixgbe_phy_sfp_unknown:
3668 case ixgbe_phy_sfp_passive_tyco:
3669 case ixgbe_phy_sfp_passive_unknown:
3670 case ixgbe_phy_sfp_active_unknown:
3671 case ixgbe_phy_sfp_ftl_active:
3672 return true;
3673 default:
3674 return false;
3675 }
3676 }
3677
3678 /**
3679 * ixgbe_sfp_link_config - set up SFP+ link
3680 * @adapter: pointer to private adapter struct
3681 **/
3682 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3683 {
3684 struct ixgbe_hw *hw = &adapter->hw;
3685
3686 if (hw->phy.multispeed_fiber) {
3687 /*
3688 * In multispeed fiber setups, the device may not have
3689 * had a physical connection when the driver loaded.
3690 * If that's the case, the initial link configuration
3691 * couldn't get the MAC into 10G or 1G mode, so we'll
3692 * never have a link status change interrupt fire.
3693 * We need to try and force an autonegotiation
3694 * session, then bring up link.
3695 */
3696 hw->mac.ops.setup_sfp(hw);
3697 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3698 schedule_work(&adapter->multispeed_fiber_task);
3699 } else {
3700 /*
3701 * Direct Attach Cu and non-multispeed fiber modules
3702 * still need to be configured properly prior to
3703 * attempting link.
3704 */
3705 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3706 schedule_work(&adapter->sfp_config_module_task);
3707 }
3708 }
3709
3710 /**
3711 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3712 * @hw: pointer to private hardware struct
3713 *
3714 * Returns 0 on success, negative on failure
3715 **/
3716 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3717 {
3718 u32 autoneg;
3719 bool negotiation, link_up = false;
3720 u32 ret = IXGBE_ERR_LINK_SETUP;
3721
3722 if (hw->mac.ops.check_link)
3723 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3724
3725 if (ret)
3726 goto link_cfg_out;
3727
3728 if (hw->mac.ops.get_link_capabilities)
3729 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3730 &negotiation);
3731 if (ret)
3732 goto link_cfg_out;
3733
3734 if (hw->mac.ops.setup_link)
3735 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3736 link_cfg_out:
3737 return ret;
3738 }
3739
3740 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3741 {
3742 struct ixgbe_hw *hw = &adapter->hw;
3743 u32 gpie = 0;
3744
3745 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3746 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3747 IXGBE_GPIE_OCD;
3748 gpie |= IXGBE_GPIE_EIAME;
3749 /*
3750 * use EIAM to auto-mask when MSI-X interrupt is asserted
3751 * this saves a register write for every interrupt
3752 */
3753 switch (hw->mac.type) {
3754 case ixgbe_mac_82598EB:
3755 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3756 break;
3757 case ixgbe_mac_82599EB:
3758 case ixgbe_mac_X540:
3759 default:
3760 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3761 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3762 break;
3763 }
3764 } else {
3765 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3766 * specifically only auto mask tx and rx interrupts */
3767 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3768 }
3769
3770 /* XXX: to interrupt immediately for EICS writes, enable this */
3771 /* gpie |= IXGBE_GPIE_EIMEN; */
3772
3773 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3774 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3775 gpie |= IXGBE_GPIE_VTMODE_64;
3776 }
3777
3778 /* Enable fan failure interrupt */
3779 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3780 gpie |= IXGBE_SDP1_GPIEN;
3781
3782 if (hw->mac.type == ixgbe_mac_82599EB)
3783 gpie |= IXGBE_SDP1_GPIEN;
3784 gpie |= IXGBE_SDP2_GPIEN;
3785
3786 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3787 }
3788
3789 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3790 {
3791 struct ixgbe_hw *hw = &adapter->hw;
3792 int err;
3793 u32 ctrl_ext;
3794
3795 ixgbe_get_hw_control(adapter);
3796 ixgbe_setup_gpie(adapter);
3797
3798 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3799 ixgbe_configure_msix(adapter);
3800 else
3801 ixgbe_configure_msi_and_legacy(adapter);
3802
3803 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3804 if (hw->mac.ops.enable_tx_laser &&
3805 ((hw->phy.multispeed_fiber) ||
3806 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3807 (hw->mac.type == ixgbe_mac_82599EB))))
3808 hw->mac.ops.enable_tx_laser(hw);
3809
3810 clear_bit(__IXGBE_DOWN, &adapter->state);
3811 ixgbe_napi_enable_all(adapter);
3812
3813 if (ixgbe_is_sfp(hw)) {
3814 ixgbe_sfp_link_config(adapter);
3815 } else {
3816 err = ixgbe_non_sfp_link_config(hw);
3817 if (err)
3818 e_err(probe, "link_config FAILED %d\n", err);
3819 }
3820
3821 /* clear any pending interrupts, may auto mask */
3822 IXGBE_READ_REG(hw, IXGBE_EICR);
3823 ixgbe_irq_enable(adapter, true, true);
3824
3825 /*
3826 * If this adapter has a fan, check to see if we had a failure
3827 * before we enabled the interrupt.
3828 */
3829 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3830 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3831 if (esdp & IXGBE_ESDP_SDP1)
3832 e_crit(drv, "Fan has stopped, replace the adapter\n");
3833 }
3834
3835 /*
3836 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3837 * arrived before interrupts were enabled but after probe. Such
3838 * devices wouldn't have their type identified yet. We need to
3839 * kick off the SFP+ module setup first, then try to bring up link.
3840 * If we're not hot-pluggable SFP+, we just need to configure link
3841 * and bring it up.
3842 */
3843 if (hw->phy.type == ixgbe_phy_unknown)
3844 schedule_work(&adapter->sfp_config_module_task);
3845
3846 /* enable transmits */
3847 netif_tx_start_all_queues(adapter->netdev);
3848
3849 /* bring the link up in the watchdog, this could race with our first
3850 * link up interrupt but shouldn't be a problem */
3851 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3852 adapter->link_check_timeout = jiffies;
3853 mod_timer(&adapter->watchdog_timer, jiffies);
3854
3855 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3856 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3857 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3858 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3859
3860 return 0;
3861 }
3862
3863 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3864 {
3865 WARN_ON(in_interrupt());
3866 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3867 msleep(1);
3868 ixgbe_down(adapter);
3869 /*
3870 * If SR-IOV enabled then wait a bit before bringing the adapter
3871 * back up to give the VFs time to respond to the reset. The
3872 * two second wait is based upon the watchdog timer cycle in
3873 * the VF driver.
3874 */
3875 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3876 msleep(2000);
3877 ixgbe_up(adapter);
3878 clear_bit(__IXGBE_RESETTING, &adapter->state);
3879 }
3880
3881 int ixgbe_up(struct ixgbe_adapter *adapter)
3882 {
3883 /* hardware has been reset, we need to reload some things */
3884 ixgbe_configure(adapter);
3885
3886 return ixgbe_up_complete(adapter);
3887 }
3888
3889 void ixgbe_reset(struct ixgbe_adapter *adapter)
3890 {
3891 struct ixgbe_hw *hw = &adapter->hw;
3892 int err;
3893
3894 err = hw->mac.ops.init_hw(hw);
3895 switch (err) {
3896 case 0:
3897 case IXGBE_ERR_SFP_NOT_PRESENT:
3898 break;
3899 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3900 e_dev_err("master disable timed out\n");
3901 break;
3902 case IXGBE_ERR_EEPROM_VERSION:
3903 /* We are running on a pre-production device, log a warning */
3904 e_dev_warn("This device is a pre-production adapter/LOM. "
3905 "Please be aware there may be issuesassociated with "
3906 "your hardware. If you are experiencing problems "
3907 "please contact your Intel or hardware "
3908 "representative who provided you with this "
3909 "hardware.\n");
3910 break;
3911 default:
3912 e_dev_err("Hardware Error: %d\n", err);
3913 }
3914
3915 /* reprogram the RAR[0] in case user changed it. */
3916 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3917 IXGBE_RAH_AV);
3918 }
3919
3920 /**
3921 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3922 * @rx_ring: ring to free buffers from
3923 **/
3924 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3925 {
3926 struct device *dev = rx_ring->dev;
3927 unsigned long size;
3928 u16 i;
3929
3930 /* ring already cleared, nothing to do */
3931 if (!rx_ring->rx_buffer_info)
3932 return;
3933
3934 /* Free all the Rx ring sk_buffs */
3935 for (i = 0; i < rx_ring->count; i++) {
3936 struct ixgbe_rx_buffer *rx_buffer_info;
3937
3938 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3939 if (rx_buffer_info->dma) {
3940 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3941 rx_ring->rx_buf_len,
3942 DMA_FROM_DEVICE);
3943 rx_buffer_info->dma = 0;
3944 }
3945 if (rx_buffer_info->skb) {
3946 struct sk_buff *skb = rx_buffer_info->skb;
3947 rx_buffer_info->skb = NULL;
3948 do {
3949 struct sk_buff *this = skb;
3950 if (IXGBE_RSC_CB(this)->delay_unmap) {
3951 dma_unmap_single(dev,
3952 IXGBE_RSC_CB(this)->dma,
3953 rx_ring->rx_buf_len,
3954 DMA_FROM_DEVICE);
3955 IXGBE_RSC_CB(this)->dma = 0;
3956 IXGBE_RSC_CB(skb)->delay_unmap = false;
3957 }
3958 skb = skb->prev;
3959 dev_kfree_skb(this);
3960 } while (skb);
3961 }
3962 if (!rx_buffer_info->page)
3963 continue;
3964 if (rx_buffer_info->page_dma) {
3965 dma_unmap_page(dev, rx_buffer_info->page_dma,
3966 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3967 rx_buffer_info->page_dma = 0;
3968 }
3969 put_page(rx_buffer_info->page);
3970 rx_buffer_info->page = NULL;
3971 rx_buffer_info->page_offset = 0;
3972 }
3973
3974 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3975 memset(rx_ring->rx_buffer_info, 0, size);
3976
3977 /* Zero out the descriptor ring */
3978 memset(rx_ring->desc, 0, rx_ring->size);
3979
3980 rx_ring->next_to_clean = 0;
3981 rx_ring->next_to_use = 0;
3982 }
3983
3984 /**
3985 * ixgbe_clean_tx_ring - Free Tx Buffers
3986 * @tx_ring: ring to be cleaned
3987 **/
3988 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3989 {
3990 struct ixgbe_tx_buffer *tx_buffer_info;
3991 unsigned long size;
3992 u16 i;
3993
3994 /* ring already cleared, nothing to do */
3995 if (!tx_ring->tx_buffer_info)
3996 return;
3997
3998 /* Free all the Tx ring sk_buffs */
3999 for (i = 0; i < tx_ring->count; i++) {
4000 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4001 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4002 }
4003
4004 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4005 memset(tx_ring->tx_buffer_info, 0, size);
4006
4007 /* Zero out the descriptor ring */
4008 memset(tx_ring->desc, 0, tx_ring->size);
4009
4010 tx_ring->next_to_use = 0;
4011 tx_ring->next_to_clean = 0;
4012 }
4013
4014 /**
4015 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4016 * @adapter: board private structure
4017 **/
4018 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4019 {
4020 int i;
4021
4022 for (i = 0; i < adapter->num_rx_queues; i++)
4023 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4024 }
4025
4026 /**
4027 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4028 * @adapter: board private structure
4029 **/
4030 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4031 {
4032 int i;
4033
4034 for (i = 0; i < adapter->num_tx_queues; i++)
4035 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4036 }
4037
4038 void ixgbe_down(struct ixgbe_adapter *adapter)
4039 {
4040 struct net_device *netdev = adapter->netdev;
4041 struct ixgbe_hw *hw = &adapter->hw;
4042 u32 rxctrl;
4043 u32 txdctl;
4044 int i;
4045 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4046
4047 /* signal that we are down to the interrupt handler */
4048 set_bit(__IXGBE_DOWN, &adapter->state);
4049
4050 /* disable receive for all VFs and wait one second */
4051 if (adapter->num_vfs) {
4052 /* ping all the active vfs to let them know we are going down */
4053 ixgbe_ping_all_vfs(adapter);
4054
4055 /* Disable all VFTE/VFRE TX/RX */
4056 ixgbe_disable_tx_rx(adapter);
4057
4058 /* Mark all the VFs as inactive */
4059 for (i = 0 ; i < adapter->num_vfs; i++)
4060 adapter->vfinfo[i].clear_to_send = 0;
4061 }
4062
4063 /* disable receives */
4064 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4065 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4066
4067 IXGBE_WRITE_FLUSH(hw);
4068 msleep(10);
4069
4070 netif_tx_stop_all_queues(netdev);
4071
4072 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4073 del_timer_sync(&adapter->sfp_timer);
4074 del_timer_sync(&adapter->watchdog_timer);
4075 cancel_work_sync(&adapter->watchdog_task);
4076
4077 netif_carrier_off(netdev);
4078 netif_tx_disable(netdev);
4079
4080 ixgbe_irq_disable(adapter);
4081
4082 ixgbe_napi_disable_all(adapter);
4083
4084 /* Cleanup the affinity_hint CPU mask memory and callback */
4085 for (i = 0; i < num_q_vectors; i++) {
4086 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4087 /* clear the affinity_mask in the IRQ descriptor */
4088 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4089 /* release the CPU mask memory */
4090 free_cpumask_var(q_vector->affinity_mask);
4091 }
4092
4093 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4094 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4095 cancel_work_sync(&adapter->fdir_reinit_task);
4096
4097 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4098 cancel_work_sync(&adapter->check_overtemp_task);
4099
4100 /* disable transmits in the hardware now that interrupts are off */
4101 for (i = 0; i < adapter->num_tx_queues; i++) {
4102 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4103 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4104 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4105 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4106 }
4107 /* Disable the Tx DMA engine on 82599 */
4108 switch (hw->mac.type) {
4109 case ixgbe_mac_82599EB:
4110 case ixgbe_mac_X540:
4111 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4112 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4113 ~IXGBE_DMATXCTL_TE));
4114 break;
4115 default:
4116 break;
4117 }
4118
4119 /* clear n-tuple filters that are cached */
4120 ethtool_ntuple_flush(netdev);
4121
4122 if (!pci_channel_offline(adapter->pdev))
4123 ixgbe_reset(adapter);
4124
4125 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4126 if (hw->mac.ops.disable_tx_laser &&
4127 ((hw->phy.multispeed_fiber) ||
4128 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4129 (hw->mac.type == ixgbe_mac_82599EB))))
4130 hw->mac.ops.disable_tx_laser(hw);
4131
4132 ixgbe_clean_all_tx_rings(adapter);
4133 ixgbe_clean_all_rx_rings(adapter);
4134
4135 #ifdef CONFIG_IXGBE_DCA
4136 /* since we reset the hardware DCA settings were cleared */
4137 ixgbe_setup_dca(adapter);
4138 #endif
4139 }
4140
4141 /**
4142 * ixgbe_poll - NAPI Rx polling callback
4143 * @napi: structure for representing this polling device
4144 * @budget: how many packets driver is allowed to clean
4145 *
4146 * This function is used for legacy and MSI, NAPI mode
4147 **/
4148 static int ixgbe_poll(struct napi_struct *napi, int budget)
4149 {
4150 struct ixgbe_q_vector *q_vector =
4151 container_of(napi, struct ixgbe_q_vector, napi);
4152 struct ixgbe_adapter *adapter = q_vector->adapter;
4153 int tx_clean_complete, work_done = 0;
4154
4155 #ifdef CONFIG_IXGBE_DCA
4156 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4157 ixgbe_update_dca(q_vector);
4158 #endif
4159
4160 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4161 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4162
4163 if (!tx_clean_complete)
4164 work_done = budget;
4165
4166 /* If budget not fully consumed, exit the polling mode */
4167 if (work_done < budget) {
4168 napi_complete(napi);
4169 if (adapter->rx_itr_setting & 1)
4170 ixgbe_set_itr(adapter);
4171 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4172 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4173 }
4174 return work_done;
4175 }
4176
4177 /**
4178 * ixgbe_tx_timeout - Respond to a Tx Hang
4179 * @netdev: network interface device structure
4180 **/
4181 static void ixgbe_tx_timeout(struct net_device *netdev)
4182 {
4183 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4184
4185 adapter->tx_timeout_count++;
4186
4187 /* Do the reset outside of interrupt context */
4188 schedule_work(&adapter->reset_task);
4189 }
4190
4191 static void ixgbe_reset_task(struct work_struct *work)
4192 {
4193 struct ixgbe_adapter *adapter;
4194 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4195
4196 /* If we're already down or resetting, just bail */
4197 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4198 test_bit(__IXGBE_RESETTING, &adapter->state))
4199 return;
4200
4201 ixgbe_dump(adapter);
4202 netdev_err(adapter->netdev, "Reset adapter\n");
4203 ixgbe_reinit_locked(adapter);
4204 }
4205
4206 #ifdef CONFIG_IXGBE_DCB
4207 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4208 {
4209 bool ret = false;
4210 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4211
4212 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4213 return ret;
4214
4215 f->mask = 0x7 << 3;
4216 adapter->num_rx_queues = f->indices;
4217 adapter->num_tx_queues = f->indices;
4218 ret = true;
4219
4220 return ret;
4221 }
4222 #endif
4223
4224 /**
4225 * ixgbe_set_rss_queues: Allocate queues for RSS
4226 * @adapter: board private structure to initialize
4227 *
4228 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4229 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4230 *
4231 **/
4232 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4233 {
4234 bool ret = false;
4235 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4236
4237 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4238 f->mask = 0xF;
4239 adapter->num_rx_queues = f->indices;
4240 adapter->num_tx_queues = f->indices;
4241 ret = true;
4242 } else {
4243 ret = false;
4244 }
4245
4246 return ret;
4247 }
4248
4249 /**
4250 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4251 * @adapter: board private structure to initialize
4252 *
4253 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4254 * to the original CPU that initiated the Tx session. This runs in addition
4255 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4256 * Rx load across CPUs using RSS.
4257 *
4258 **/
4259 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4260 {
4261 bool ret = false;
4262 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4263
4264 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4265 f_fdir->mask = 0;
4266
4267 /* Flow Director must have RSS enabled */
4268 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4269 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4270 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4271 adapter->num_tx_queues = f_fdir->indices;
4272 adapter->num_rx_queues = f_fdir->indices;
4273 ret = true;
4274 } else {
4275 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4276 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4277 }
4278 return ret;
4279 }
4280
4281 #ifdef IXGBE_FCOE
4282 /**
4283 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4284 * @adapter: board private structure to initialize
4285 *
4286 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4287 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4288 * rx queues out of the max number of rx queues, instead, it is used as the
4289 * index of the first rx queue used by FCoE.
4290 *
4291 **/
4292 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4293 {
4294 bool ret = false;
4295 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4296
4297 f->indices = min((int)num_online_cpus(), f->indices);
4298 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4299 adapter->num_rx_queues = 1;
4300 adapter->num_tx_queues = 1;
4301 #ifdef CONFIG_IXGBE_DCB
4302 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4303 e_info(probe, "FCoE enabled with DCB\n");
4304 ixgbe_set_dcb_queues(adapter);
4305 }
4306 #endif
4307 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4308 e_info(probe, "FCoE enabled with RSS\n");
4309 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4310 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4311 ixgbe_set_fdir_queues(adapter);
4312 else
4313 ixgbe_set_rss_queues(adapter);
4314 }
4315 /* adding FCoE rx rings to the end */
4316 f->mask = adapter->num_rx_queues;
4317 adapter->num_rx_queues += f->indices;
4318 adapter->num_tx_queues += f->indices;
4319
4320 ret = true;
4321 }
4322
4323 return ret;
4324 }
4325
4326 #endif /* IXGBE_FCOE */
4327 /**
4328 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4329 * @adapter: board private structure to initialize
4330 *
4331 * IOV doesn't actually use anything, so just NAK the
4332 * request for now and let the other queue routines
4333 * figure out what to do.
4334 */
4335 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4336 {
4337 return false;
4338 }
4339
4340 /*
4341 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4342 * @adapter: board private structure to initialize
4343 *
4344 * This is the top level queue allocation routine. The order here is very
4345 * important, starting with the "most" number of features turned on at once,
4346 * and ending with the smallest set of features. This way large combinations
4347 * can be allocated if they're turned on, and smaller combinations are the
4348 * fallthrough conditions.
4349 *
4350 **/
4351 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4352 {
4353 /* Start with base case */
4354 adapter->num_rx_queues = 1;
4355 adapter->num_tx_queues = 1;
4356 adapter->num_rx_pools = adapter->num_rx_queues;
4357 adapter->num_rx_queues_per_pool = 1;
4358
4359 if (ixgbe_set_sriov_queues(adapter))
4360 goto done;
4361
4362 #ifdef IXGBE_FCOE
4363 if (ixgbe_set_fcoe_queues(adapter))
4364 goto done;
4365
4366 #endif /* IXGBE_FCOE */
4367 #ifdef CONFIG_IXGBE_DCB
4368 if (ixgbe_set_dcb_queues(adapter))
4369 goto done;
4370
4371 #endif
4372 if (ixgbe_set_fdir_queues(adapter))
4373 goto done;
4374
4375 if (ixgbe_set_rss_queues(adapter))
4376 goto done;
4377
4378 /* fallback to base case */
4379 adapter->num_rx_queues = 1;
4380 adapter->num_tx_queues = 1;
4381
4382 done:
4383 /* Notify the stack of the (possibly) reduced queue counts. */
4384 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4385 return netif_set_real_num_rx_queues(adapter->netdev,
4386 adapter->num_rx_queues);
4387 }
4388
4389 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4390 int vectors)
4391 {
4392 int err, vector_threshold;
4393
4394 /* We'll want at least 3 (vector_threshold):
4395 * 1) TxQ[0] Cleanup
4396 * 2) RxQ[0] Cleanup
4397 * 3) Other (Link Status Change, etc.)
4398 * 4) TCP Timer (optional)
4399 */
4400 vector_threshold = MIN_MSIX_COUNT;
4401
4402 /* The more we get, the more we will assign to Tx/Rx Cleanup
4403 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4404 * Right now, we simply care about how many we'll get; we'll
4405 * set them up later while requesting irq's.
4406 */
4407 while (vectors >= vector_threshold) {
4408 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4409 vectors);
4410 if (!err) /* Success in acquiring all requested vectors. */
4411 break;
4412 else if (err < 0)
4413 vectors = 0; /* Nasty failure, quit now */
4414 else /* err == number of vectors we should try again with */
4415 vectors = err;
4416 }
4417
4418 if (vectors < vector_threshold) {
4419 /* Can't allocate enough MSI-X interrupts? Oh well.
4420 * This just means we'll go with either a single MSI
4421 * vector or fall back to legacy interrupts.
4422 */
4423 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4424 "Unable to allocate MSI-X interrupts\n");
4425 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4426 kfree(adapter->msix_entries);
4427 adapter->msix_entries = NULL;
4428 } else {
4429 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4430 /*
4431 * Adjust for only the vectors we'll use, which is minimum
4432 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4433 * vectors we were allocated.
4434 */
4435 adapter->num_msix_vectors = min(vectors,
4436 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4437 }
4438 }
4439
4440 /**
4441 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4442 * @adapter: board private structure to initialize
4443 *
4444 * Cache the descriptor ring offsets for RSS to the assigned rings.
4445 *
4446 **/
4447 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4448 {
4449 int i;
4450
4451 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4452 return false;
4453
4454 for (i = 0; i < adapter->num_rx_queues; i++)
4455 adapter->rx_ring[i]->reg_idx = i;
4456 for (i = 0; i < adapter->num_tx_queues; i++)
4457 adapter->tx_ring[i]->reg_idx = i;
4458
4459 return true;
4460 }
4461
4462 #ifdef CONFIG_IXGBE_DCB
4463 /**
4464 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4465 * @adapter: board private structure to initialize
4466 *
4467 * Cache the descriptor ring offsets for DCB to the assigned rings.
4468 *
4469 **/
4470 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4471 {
4472 int i;
4473 bool ret = false;
4474 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4475
4476 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4477 return false;
4478
4479 /* the number of queues is assumed to be symmetric */
4480 switch (adapter->hw.mac.type) {
4481 case ixgbe_mac_82598EB:
4482 for (i = 0; i < dcb_i; i++) {
4483 adapter->rx_ring[i]->reg_idx = i << 3;
4484 adapter->tx_ring[i]->reg_idx = i << 2;
4485 }
4486 ret = true;
4487 break;
4488 case ixgbe_mac_82599EB:
4489 case ixgbe_mac_X540:
4490 if (dcb_i == 8) {
4491 /*
4492 * Tx TC0 starts at: descriptor queue 0
4493 * Tx TC1 starts at: descriptor queue 32
4494 * Tx TC2 starts at: descriptor queue 64
4495 * Tx TC3 starts at: descriptor queue 80
4496 * Tx TC4 starts at: descriptor queue 96
4497 * Tx TC5 starts at: descriptor queue 104
4498 * Tx TC6 starts at: descriptor queue 112
4499 * Tx TC7 starts at: descriptor queue 120
4500 *
4501 * Rx TC0-TC7 are offset by 16 queues each
4502 */
4503 for (i = 0; i < 3; i++) {
4504 adapter->tx_ring[i]->reg_idx = i << 5;
4505 adapter->rx_ring[i]->reg_idx = i << 4;
4506 }
4507 for ( ; i < 5; i++) {
4508 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4509 adapter->rx_ring[i]->reg_idx = i << 4;
4510 }
4511 for ( ; i < dcb_i; i++) {
4512 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4513 adapter->rx_ring[i]->reg_idx = i << 4;
4514 }
4515 ret = true;
4516 } else if (dcb_i == 4) {
4517 /*
4518 * Tx TC0 starts at: descriptor queue 0
4519 * Tx TC1 starts at: descriptor queue 64
4520 * Tx TC2 starts at: descriptor queue 96
4521 * Tx TC3 starts at: descriptor queue 112
4522 *
4523 * Rx TC0-TC3 are offset by 32 queues each
4524 */
4525 adapter->tx_ring[0]->reg_idx = 0;
4526 adapter->tx_ring[1]->reg_idx = 64;
4527 adapter->tx_ring[2]->reg_idx = 96;
4528 adapter->tx_ring[3]->reg_idx = 112;
4529 for (i = 0 ; i < dcb_i; i++)
4530 adapter->rx_ring[i]->reg_idx = i << 5;
4531 ret = true;
4532 }
4533 break;
4534 default:
4535 break;
4536 }
4537 return ret;
4538 }
4539 #endif
4540
4541 /**
4542 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4543 * @adapter: board private structure to initialize
4544 *
4545 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4546 *
4547 **/
4548 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4549 {
4550 int i;
4551 bool ret = false;
4552
4553 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4554 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4555 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4556 for (i = 0; i < adapter->num_rx_queues; i++)
4557 adapter->rx_ring[i]->reg_idx = i;
4558 for (i = 0; i < adapter->num_tx_queues; i++)
4559 adapter->tx_ring[i]->reg_idx = i;
4560 ret = true;
4561 }
4562
4563 return ret;
4564 }
4565
4566 #ifdef IXGBE_FCOE
4567 /**
4568 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4569 * @adapter: board private structure to initialize
4570 *
4571 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4572 *
4573 */
4574 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4575 {
4576 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4577 int i;
4578 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4579
4580 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4581 return false;
4582
4583 #ifdef CONFIG_IXGBE_DCB
4584 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4585 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4586
4587 ixgbe_cache_ring_dcb(adapter);
4588 /* find out queues in TC for FCoE */
4589 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4590 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4591 /*
4592 * In 82599, the number of Tx queues for each traffic
4593 * class for both 8-TC and 4-TC modes are:
4594 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4595 * 8 TCs: 32 32 16 16 8 8 8 8
4596 * 4 TCs: 64 64 32 32
4597 * We have max 8 queues for FCoE, where 8 the is
4598 * FCoE redirection table size. If TC for FCoE is
4599 * less than or equal to TC3, we have enough queues
4600 * to add max of 8 queues for FCoE, so we start FCoE
4601 * Tx queue from the next one, i.e., reg_idx + 1.
4602 * If TC for FCoE is above TC3, implying 8 TC mode,
4603 * and we need 8 for FCoE, we have to take all queues
4604 * in that traffic class for FCoE.
4605 */
4606 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4607 fcoe_tx_i--;
4608 }
4609 #endif /* CONFIG_IXGBE_DCB */
4610 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4611 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4612 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4613 ixgbe_cache_ring_fdir(adapter);
4614 else
4615 ixgbe_cache_ring_rss(adapter);
4616
4617 fcoe_rx_i = f->mask;
4618 fcoe_tx_i = f->mask;
4619 }
4620 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4621 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4622 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4623 }
4624 return true;
4625 }
4626
4627 #endif /* IXGBE_FCOE */
4628 /**
4629 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4630 * @adapter: board private structure to initialize
4631 *
4632 * SR-IOV doesn't use any descriptor rings but changes the default if
4633 * no other mapping is used.
4634 *
4635 */
4636 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4637 {
4638 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4639 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4640 if (adapter->num_vfs)
4641 return true;
4642 else
4643 return false;
4644 }
4645
4646 /**
4647 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4648 * @adapter: board private structure to initialize
4649 *
4650 * Once we know the feature-set enabled for the device, we'll cache
4651 * the register offset the descriptor ring is assigned to.
4652 *
4653 * Note, the order the various feature calls is important. It must start with
4654 * the "most" features enabled at the same time, then trickle down to the
4655 * least amount of features turned on at once.
4656 **/
4657 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4658 {
4659 /* start with default case */
4660 adapter->rx_ring[0]->reg_idx = 0;
4661 adapter->tx_ring[0]->reg_idx = 0;
4662
4663 if (ixgbe_cache_ring_sriov(adapter))
4664 return;
4665
4666 #ifdef IXGBE_FCOE
4667 if (ixgbe_cache_ring_fcoe(adapter))
4668 return;
4669
4670 #endif /* IXGBE_FCOE */
4671 #ifdef CONFIG_IXGBE_DCB
4672 if (ixgbe_cache_ring_dcb(adapter))
4673 return;
4674
4675 #endif
4676 if (ixgbe_cache_ring_fdir(adapter))
4677 return;
4678
4679 if (ixgbe_cache_ring_rss(adapter))
4680 return;
4681 }
4682
4683 /**
4684 * ixgbe_alloc_queues - Allocate memory for all rings
4685 * @adapter: board private structure to initialize
4686 *
4687 * We allocate one ring per queue at run-time since we don't know the
4688 * number of queues at compile-time. The polling_netdev array is
4689 * intended for Multiqueue, but should work fine with a single queue.
4690 **/
4691 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4692 {
4693 int rx = 0, tx = 0, nid = adapter->node;
4694
4695 if (nid < 0 || !node_online(nid))
4696 nid = first_online_node;
4697
4698 for (; tx < adapter->num_tx_queues; tx++) {
4699 struct ixgbe_ring *ring;
4700
4701 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4702 if (!ring)
4703 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4704 if (!ring)
4705 goto err_allocation;
4706 ring->count = adapter->tx_ring_count;
4707 ring->queue_index = tx;
4708 ring->numa_node = nid;
4709 ring->dev = &adapter->pdev->dev;
4710 ring->netdev = adapter->netdev;
4711
4712 adapter->tx_ring[tx] = ring;
4713 }
4714
4715 for (; rx < adapter->num_rx_queues; rx++) {
4716 struct ixgbe_ring *ring;
4717
4718 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4719 if (!ring)
4720 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4721 if (!ring)
4722 goto err_allocation;
4723 ring->count = adapter->rx_ring_count;
4724 ring->queue_index = rx;
4725 ring->numa_node = nid;
4726 ring->dev = &adapter->pdev->dev;
4727 ring->netdev = adapter->netdev;
4728
4729 adapter->rx_ring[rx] = ring;
4730 }
4731
4732 ixgbe_cache_ring_register(adapter);
4733
4734 return 0;
4735
4736 err_allocation:
4737 while (tx)
4738 kfree(adapter->tx_ring[--tx]);
4739
4740 while (rx)
4741 kfree(adapter->rx_ring[--rx]);
4742 return -ENOMEM;
4743 }
4744
4745 /**
4746 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4747 * @adapter: board private structure to initialize
4748 *
4749 * Attempt to configure the interrupts using the best available
4750 * capabilities of the hardware and the kernel.
4751 **/
4752 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4753 {
4754 struct ixgbe_hw *hw = &adapter->hw;
4755 int err = 0;
4756 int vector, v_budget;
4757
4758 /*
4759 * It's easy to be greedy for MSI-X vectors, but it really
4760 * doesn't do us much good if we have a lot more vectors
4761 * than CPU's. So let's be conservative and only ask for
4762 * (roughly) the same number of vectors as there are CPU's.
4763 */
4764 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4765 (int)num_online_cpus()) + NON_Q_VECTORS;
4766
4767 /*
4768 * At the same time, hardware can only support a maximum of
4769 * hw.mac->max_msix_vectors vectors. With features
4770 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4771 * descriptor queues supported by our device. Thus, we cap it off in
4772 * those rare cases where the cpu count also exceeds our vector limit.
4773 */
4774 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4775
4776 /* A failure in MSI-X entry allocation isn't fatal, but it does
4777 * mean we disable MSI-X capabilities of the adapter. */
4778 adapter->msix_entries = kcalloc(v_budget,
4779 sizeof(struct msix_entry), GFP_KERNEL);
4780 if (adapter->msix_entries) {
4781 for (vector = 0; vector < v_budget; vector++)
4782 adapter->msix_entries[vector].entry = vector;
4783
4784 ixgbe_acquire_msix_vectors(adapter, v_budget);
4785
4786 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4787 goto out;
4788 }
4789
4790 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4791 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4792 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4793 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4794 adapter->atr_sample_rate = 0;
4795 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4796 ixgbe_disable_sriov(adapter);
4797
4798 err = ixgbe_set_num_queues(adapter);
4799 if (err)
4800 return err;
4801
4802 err = pci_enable_msi(adapter->pdev);
4803 if (!err) {
4804 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4805 } else {
4806 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4807 "Unable to allocate MSI interrupt, "
4808 "falling back to legacy. Error: %d\n", err);
4809 /* reset err */
4810 err = 0;
4811 }
4812
4813 out:
4814 return err;
4815 }
4816
4817 /**
4818 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4819 * @adapter: board private structure to initialize
4820 *
4821 * We allocate one q_vector per queue interrupt. If allocation fails we
4822 * return -ENOMEM.
4823 **/
4824 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4825 {
4826 int q_idx, num_q_vectors;
4827 struct ixgbe_q_vector *q_vector;
4828 int napi_vectors;
4829 int (*poll)(struct napi_struct *, int);
4830
4831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4832 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4833 napi_vectors = adapter->num_rx_queues;
4834 poll = &ixgbe_clean_rxtx_many;
4835 } else {
4836 num_q_vectors = 1;
4837 napi_vectors = 1;
4838 poll = &ixgbe_poll;
4839 }
4840
4841 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4842 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4843 GFP_KERNEL, adapter->node);
4844 if (!q_vector)
4845 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4846 GFP_KERNEL);
4847 if (!q_vector)
4848 goto err_out;
4849 q_vector->adapter = adapter;
4850 if (q_vector->txr_count && !q_vector->rxr_count)
4851 q_vector->eitr = adapter->tx_eitr_param;
4852 else
4853 q_vector->eitr = adapter->rx_eitr_param;
4854 q_vector->v_idx = q_idx;
4855 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4856 adapter->q_vector[q_idx] = q_vector;
4857 }
4858
4859 return 0;
4860
4861 err_out:
4862 while (q_idx) {
4863 q_idx--;
4864 q_vector = adapter->q_vector[q_idx];
4865 netif_napi_del(&q_vector->napi);
4866 kfree(q_vector);
4867 adapter->q_vector[q_idx] = NULL;
4868 }
4869 return -ENOMEM;
4870 }
4871
4872 /**
4873 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4874 * @adapter: board private structure to initialize
4875 *
4876 * This function frees the memory allocated to the q_vectors. In addition if
4877 * NAPI is enabled it will delete any references to the NAPI struct prior
4878 * to freeing the q_vector.
4879 **/
4880 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4881 {
4882 int q_idx, num_q_vectors;
4883
4884 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4885 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4886 else
4887 num_q_vectors = 1;
4888
4889 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4890 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4891 adapter->q_vector[q_idx] = NULL;
4892 netif_napi_del(&q_vector->napi);
4893 kfree(q_vector);
4894 }
4895 }
4896
4897 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4898 {
4899 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4900 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4901 pci_disable_msix(adapter->pdev);
4902 kfree(adapter->msix_entries);
4903 adapter->msix_entries = NULL;
4904 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4905 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4906 pci_disable_msi(adapter->pdev);
4907 }
4908 }
4909
4910 /**
4911 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4912 * @adapter: board private structure to initialize
4913 *
4914 * We determine which interrupt scheme to use based on...
4915 * - Kernel support (MSI, MSI-X)
4916 * - which can be user-defined (via MODULE_PARAM)
4917 * - Hardware queue count (num_*_queues)
4918 * - defined by miscellaneous hardware support/features (RSS, etc.)
4919 **/
4920 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4921 {
4922 int err;
4923
4924 /* Number of supported queues */
4925 err = ixgbe_set_num_queues(adapter);
4926 if (err)
4927 return err;
4928
4929 err = ixgbe_set_interrupt_capability(adapter);
4930 if (err) {
4931 e_dev_err("Unable to setup interrupt capabilities\n");
4932 goto err_set_interrupt;
4933 }
4934
4935 err = ixgbe_alloc_q_vectors(adapter);
4936 if (err) {
4937 e_dev_err("Unable to allocate memory for queue vectors\n");
4938 goto err_alloc_q_vectors;
4939 }
4940
4941 err = ixgbe_alloc_queues(adapter);
4942 if (err) {
4943 e_dev_err("Unable to allocate memory for queues\n");
4944 goto err_alloc_queues;
4945 }
4946
4947 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4948 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4949 adapter->num_rx_queues, adapter->num_tx_queues);
4950
4951 set_bit(__IXGBE_DOWN, &adapter->state);
4952
4953 return 0;
4954
4955 err_alloc_queues:
4956 ixgbe_free_q_vectors(adapter);
4957 err_alloc_q_vectors:
4958 ixgbe_reset_interrupt_capability(adapter);
4959 err_set_interrupt:
4960 return err;
4961 }
4962
4963 static void ring_free_rcu(struct rcu_head *head)
4964 {
4965 kfree(container_of(head, struct ixgbe_ring, rcu));
4966 }
4967
4968 /**
4969 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4970 * @adapter: board private structure to clear interrupt scheme on
4971 *
4972 * We go through and clear interrupt specific resources and reset the structure
4973 * to pre-load conditions
4974 **/
4975 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4976 {
4977 int i;
4978
4979 for (i = 0; i < adapter->num_tx_queues; i++) {
4980 kfree(adapter->tx_ring[i]);
4981 adapter->tx_ring[i] = NULL;
4982 }
4983 for (i = 0; i < adapter->num_rx_queues; i++) {
4984 struct ixgbe_ring *ring = adapter->rx_ring[i];
4985
4986 /* ixgbe_get_stats64() might access this ring, we must wait
4987 * a grace period before freeing it.
4988 */
4989 call_rcu(&ring->rcu, ring_free_rcu);
4990 adapter->rx_ring[i] = NULL;
4991 }
4992
4993 adapter->num_tx_queues = 0;
4994 adapter->num_rx_queues = 0;
4995
4996 ixgbe_free_q_vectors(adapter);
4997 ixgbe_reset_interrupt_capability(adapter);
4998 }
4999
5000 /**
5001 * ixgbe_sfp_timer - worker thread to find a missing module
5002 * @data: pointer to our adapter struct
5003 **/
5004 static void ixgbe_sfp_timer(unsigned long data)
5005 {
5006 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5007
5008 /*
5009 * Do the sfp_timer outside of interrupt context due to the
5010 * delays that sfp+ detection requires
5011 */
5012 schedule_work(&adapter->sfp_task);
5013 }
5014
5015 /**
5016 * ixgbe_sfp_task - worker thread to find a missing module
5017 * @work: pointer to work_struct containing our data
5018 **/
5019 static void ixgbe_sfp_task(struct work_struct *work)
5020 {
5021 struct ixgbe_adapter *adapter = container_of(work,
5022 struct ixgbe_adapter,
5023 sfp_task);
5024 struct ixgbe_hw *hw = &adapter->hw;
5025
5026 if ((hw->phy.type == ixgbe_phy_nl) &&
5027 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5028 s32 ret = hw->phy.ops.identify_sfp(hw);
5029 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5030 goto reschedule;
5031 ret = hw->phy.ops.reset(hw);
5032 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5033 e_dev_err("failed to initialize because an unsupported "
5034 "SFP+ module type was detected.\n");
5035 e_dev_err("Reload the driver after installing a "
5036 "supported module.\n");
5037 unregister_netdev(adapter->netdev);
5038 } else {
5039 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5040 }
5041 /* don't need this routine any more */
5042 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5043 }
5044 return;
5045 reschedule:
5046 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5047 mod_timer(&adapter->sfp_timer,
5048 round_jiffies(jiffies + (2 * HZ)));
5049 }
5050
5051 /**
5052 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5053 * @adapter: board private structure to initialize
5054 *
5055 * ixgbe_sw_init initializes the Adapter private data structure.
5056 * Fields are initialized based on PCI device information and
5057 * OS network device settings (MTU size).
5058 **/
5059 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5060 {
5061 struct ixgbe_hw *hw = &adapter->hw;
5062 struct pci_dev *pdev = adapter->pdev;
5063 struct net_device *dev = adapter->netdev;
5064 unsigned int rss;
5065 #ifdef CONFIG_IXGBE_DCB
5066 int j;
5067 struct tc_configuration *tc;
5068 #endif
5069 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5070
5071 /* PCI config space info */
5072
5073 hw->vendor_id = pdev->vendor;
5074 hw->device_id = pdev->device;
5075 hw->revision_id = pdev->revision;
5076 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5077 hw->subsystem_device_id = pdev->subsystem_device;
5078
5079 /* Set capability flags */
5080 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5081 adapter->ring_feature[RING_F_RSS].indices = rss;
5082 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5083 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5084 switch (hw->mac.type) {
5085 case ixgbe_mac_82598EB:
5086 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5087 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5088 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5089 break;
5090 case ixgbe_mac_82599EB:
5091 case ixgbe_mac_X540:
5092 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5093 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5094 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5095 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5096 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5097 if (dev->features & NETIF_F_NTUPLE) {
5098 /* Flow Director perfect filter enabled */
5099 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5100 adapter->atr_sample_rate = 0;
5101 spin_lock_init(&adapter->fdir_perfect_lock);
5102 } else {
5103 /* Flow Director hash filters enabled */
5104 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5105 adapter->atr_sample_rate = 20;
5106 }
5107 adapter->ring_feature[RING_F_FDIR].indices =
5108 IXGBE_MAX_FDIR_INDICES;
5109 adapter->fdir_pballoc = 0;
5110 #ifdef IXGBE_FCOE
5111 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5112 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5113 adapter->ring_feature[RING_F_FCOE].indices = 0;
5114 #ifdef CONFIG_IXGBE_DCB
5115 /* Default traffic class to use for FCoE */
5116 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5117 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5118 #endif
5119 #endif /* IXGBE_FCOE */
5120 break;
5121 default:
5122 break;
5123 }
5124
5125 #ifdef CONFIG_IXGBE_DCB
5126 /* Configure DCB traffic classes */
5127 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5128 tc = &adapter->dcb_cfg.tc_config[j];
5129 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5130 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5131 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5132 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5133 tc->dcb_pfc = pfc_disabled;
5134 }
5135 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5136 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5137 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5138 adapter->dcb_cfg.pfc_mode_enable = false;
5139 adapter->dcb_cfg.round_robin_enable = false;
5140 adapter->dcb_set_bitmap = 0x00;
5141 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5142 adapter->ring_feature[RING_F_DCB].indices);
5143
5144 #endif
5145
5146 /* default flow control settings */
5147 hw->fc.requested_mode = ixgbe_fc_full;
5148 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5149 #ifdef CONFIG_DCB
5150 adapter->last_lfc_mode = hw->fc.current_mode;
5151 #endif
5152 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5153 hw->fc.low_water = FC_LOW_WATER(max_frame);
5154 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5155 hw->fc.send_xon = true;
5156 hw->fc.disable_fc_autoneg = false;
5157
5158 /* enable itr by default in dynamic mode */
5159 adapter->rx_itr_setting = 1;
5160 adapter->rx_eitr_param = 20000;
5161 adapter->tx_itr_setting = 1;
5162 adapter->tx_eitr_param = 10000;
5163
5164 /* set defaults for eitr in MegaBytes */
5165 adapter->eitr_low = 10;
5166 adapter->eitr_high = 20;
5167
5168 /* set default ring sizes */
5169 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5170 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5171
5172 /* initialize eeprom parameters */
5173 if (ixgbe_init_eeprom_params_generic(hw)) {
5174 e_dev_err("EEPROM initialization failed\n");
5175 return -EIO;
5176 }
5177
5178 /* enable rx csum by default */
5179 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5180
5181 /* get assigned NUMA node */
5182 adapter->node = dev_to_node(&pdev->dev);
5183
5184 set_bit(__IXGBE_DOWN, &adapter->state);
5185
5186 return 0;
5187 }
5188
5189 /**
5190 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5191 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5192 *
5193 * Return 0 on success, negative on failure
5194 **/
5195 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5196 {
5197 struct device *dev = tx_ring->dev;
5198 int size;
5199
5200 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5201 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5202 if (!tx_ring->tx_buffer_info)
5203 tx_ring->tx_buffer_info = vzalloc(size);
5204 if (!tx_ring->tx_buffer_info)
5205 goto err;
5206
5207 /* round up to nearest 4K */
5208 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5209 tx_ring->size = ALIGN(tx_ring->size, 4096);
5210
5211 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5212 &tx_ring->dma, GFP_KERNEL);
5213 if (!tx_ring->desc)
5214 goto err;
5215
5216 tx_ring->next_to_use = 0;
5217 tx_ring->next_to_clean = 0;
5218 tx_ring->work_limit = tx_ring->count;
5219 return 0;
5220
5221 err:
5222 vfree(tx_ring->tx_buffer_info);
5223 tx_ring->tx_buffer_info = NULL;
5224 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5225 return -ENOMEM;
5226 }
5227
5228 /**
5229 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5230 * @adapter: board private structure
5231 *
5232 * If this function returns with an error, then it's possible one or
5233 * more of the rings is populated (while the rest are not). It is the
5234 * callers duty to clean those orphaned rings.
5235 *
5236 * Return 0 on success, negative on failure
5237 **/
5238 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5239 {
5240 int i, err = 0;
5241
5242 for (i = 0; i < adapter->num_tx_queues; i++) {
5243 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5244 if (!err)
5245 continue;
5246 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5247 break;
5248 }
5249
5250 return err;
5251 }
5252
5253 /**
5254 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5255 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5256 *
5257 * Returns 0 on success, negative on failure
5258 **/
5259 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5260 {
5261 struct device *dev = rx_ring->dev;
5262 int size;
5263
5264 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5265 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5266 if (!rx_ring->rx_buffer_info)
5267 rx_ring->rx_buffer_info = vzalloc(size);
5268 if (!rx_ring->rx_buffer_info)
5269 goto err;
5270
5271 /* Round up to nearest 4K */
5272 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5273 rx_ring->size = ALIGN(rx_ring->size, 4096);
5274
5275 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5276 &rx_ring->dma, GFP_KERNEL);
5277
5278 if (!rx_ring->desc)
5279 goto err;
5280
5281 rx_ring->next_to_clean = 0;
5282 rx_ring->next_to_use = 0;
5283
5284 return 0;
5285 err:
5286 vfree(rx_ring->rx_buffer_info);
5287 rx_ring->rx_buffer_info = NULL;
5288 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5289 return -ENOMEM;
5290 }
5291
5292 /**
5293 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5294 * @adapter: board private structure
5295 *
5296 * If this function returns with an error, then it's possible one or
5297 * more of the rings is populated (while the rest are not). It is the
5298 * callers duty to clean those orphaned rings.
5299 *
5300 * Return 0 on success, negative on failure
5301 **/
5302 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5303 {
5304 int i, err = 0;
5305
5306 for (i = 0; i < adapter->num_rx_queues; i++) {
5307 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5308 if (!err)
5309 continue;
5310 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5311 break;
5312 }
5313
5314 return err;
5315 }
5316
5317 /**
5318 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5319 * @tx_ring: Tx descriptor ring for a specific queue
5320 *
5321 * Free all transmit software resources
5322 **/
5323 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5324 {
5325 ixgbe_clean_tx_ring(tx_ring);
5326
5327 vfree(tx_ring->tx_buffer_info);
5328 tx_ring->tx_buffer_info = NULL;
5329
5330 /* if not set, then don't free */
5331 if (!tx_ring->desc)
5332 return;
5333
5334 dma_free_coherent(tx_ring->dev, tx_ring->size,
5335 tx_ring->desc, tx_ring->dma);
5336
5337 tx_ring->desc = NULL;
5338 }
5339
5340 /**
5341 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5342 * @adapter: board private structure
5343 *
5344 * Free all transmit software resources
5345 **/
5346 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5347 {
5348 int i;
5349
5350 for (i = 0; i < adapter->num_tx_queues; i++)
5351 if (adapter->tx_ring[i]->desc)
5352 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5353 }
5354
5355 /**
5356 * ixgbe_free_rx_resources - Free Rx Resources
5357 * @rx_ring: ring to clean the resources from
5358 *
5359 * Free all receive software resources
5360 **/
5361 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5362 {
5363 ixgbe_clean_rx_ring(rx_ring);
5364
5365 vfree(rx_ring->rx_buffer_info);
5366 rx_ring->rx_buffer_info = NULL;
5367
5368 /* if not set, then don't free */
5369 if (!rx_ring->desc)
5370 return;
5371
5372 dma_free_coherent(rx_ring->dev, rx_ring->size,
5373 rx_ring->desc, rx_ring->dma);
5374
5375 rx_ring->desc = NULL;
5376 }
5377
5378 /**
5379 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5380 * @adapter: board private structure
5381 *
5382 * Free all receive software resources
5383 **/
5384 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5385 {
5386 int i;
5387
5388 for (i = 0; i < adapter->num_rx_queues; i++)
5389 if (adapter->rx_ring[i]->desc)
5390 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5391 }
5392
5393 /**
5394 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5395 * @netdev: network interface device structure
5396 * @new_mtu: new value for maximum frame size
5397 *
5398 * Returns 0 on success, negative on failure
5399 **/
5400 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5401 {
5402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5403 struct ixgbe_hw *hw = &adapter->hw;
5404 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5405
5406 /* MTU < 68 is an error and causes problems on some kernels */
5407 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5408 return -EINVAL;
5409
5410 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5411 /* must set new MTU before calling down or up */
5412 netdev->mtu = new_mtu;
5413
5414 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5415 hw->fc.low_water = FC_LOW_WATER(max_frame);
5416
5417 if (netif_running(netdev))
5418 ixgbe_reinit_locked(adapter);
5419
5420 return 0;
5421 }
5422
5423 /**
5424 * ixgbe_open - Called when a network interface is made active
5425 * @netdev: network interface device structure
5426 *
5427 * Returns 0 on success, negative value on failure
5428 *
5429 * The open entry point is called when a network interface is made
5430 * active by the system (IFF_UP). At this point all resources needed
5431 * for transmit and receive operations are allocated, the interrupt
5432 * handler is registered with the OS, the watchdog timer is started,
5433 * and the stack is notified that the interface is ready.
5434 **/
5435 static int ixgbe_open(struct net_device *netdev)
5436 {
5437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5438 int err;
5439
5440 /* disallow open during test */
5441 if (test_bit(__IXGBE_TESTING, &adapter->state))
5442 return -EBUSY;
5443
5444 netif_carrier_off(netdev);
5445
5446 /* allocate transmit descriptors */
5447 err = ixgbe_setup_all_tx_resources(adapter);
5448 if (err)
5449 goto err_setup_tx;
5450
5451 /* allocate receive descriptors */
5452 err = ixgbe_setup_all_rx_resources(adapter);
5453 if (err)
5454 goto err_setup_rx;
5455
5456 ixgbe_configure(adapter);
5457
5458 err = ixgbe_request_irq(adapter);
5459 if (err)
5460 goto err_req_irq;
5461
5462 err = ixgbe_up_complete(adapter);
5463 if (err)
5464 goto err_up;
5465
5466 netif_tx_start_all_queues(netdev);
5467
5468 return 0;
5469
5470 err_up:
5471 ixgbe_release_hw_control(adapter);
5472 ixgbe_free_irq(adapter);
5473 err_req_irq:
5474 err_setup_rx:
5475 ixgbe_free_all_rx_resources(adapter);
5476 err_setup_tx:
5477 ixgbe_free_all_tx_resources(adapter);
5478 ixgbe_reset(adapter);
5479
5480 return err;
5481 }
5482
5483 /**
5484 * ixgbe_close - Disables a network interface
5485 * @netdev: network interface device structure
5486 *
5487 * Returns 0, this is not allowed to fail
5488 *
5489 * The close entry point is called when an interface is de-activated
5490 * by the OS. The hardware is still under the drivers control, but
5491 * needs to be disabled. A global MAC reset is issued to stop the
5492 * hardware, and all transmit and receive resources are freed.
5493 **/
5494 static int ixgbe_close(struct net_device *netdev)
5495 {
5496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5497
5498 ixgbe_down(adapter);
5499 ixgbe_free_irq(adapter);
5500
5501 ixgbe_free_all_tx_resources(adapter);
5502 ixgbe_free_all_rx_resources(adapter);
5503
5504 ixgbe_release_hw_control(adapter);
5505
5506 return 0;
5507 }
5508
5509 #ifdef CONFIG_PM
5510 static int ixgbe_resume(struct pci_dev *pdev)
5511 {
5512 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5513 struct net_device *netdev = adapter->netdev;
5514 u32 err;
5515
5516 pci_set_power_state(pdev, PCI_D0);
5517 pci_restore_state(pdev);
5518 /*
5519 * pci_restore_state clears dev->state_saved so call
5520 * pci_save_state to restore it.
5521 */
5522 pci_save_state(pdev);
5523
5524 err = pci_enable_device_mem(pdev);
5525 if (err) {
5526 e_dev_err("Cannot enable PCI device from suspend\n");
5527 return err;
5528 }
5529 pci_set_master(pdev);
5530
5531 pci_wake_from_d3(pdev, false);
5532
5533 err = ixgbe_init_interrupt_scheme(adapter);
5534 if (err) {
5535 e_dev_err("Cannot initialize interrupts for device\n");
5536 return err;
5537 }
5538
5539 ixgbe_reset(adapter);
5540
5541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5542
5543 if (netif_running(netdev)) {
5544 err = ixgbe_open(netdev);
5545 if (err)
5546 return err;
5547 }
5548
5549 netif_device_attach(netdev);
5550
5551 return 0;
5552 }
5553 #endif /* CONFIG_PM */
5554
5555 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5556 {
5557 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5558 struct net_device *netdev = adapter->netdev;
5559 struct ixgbe_hw *hw = &adapter->hw;
5560 u32 ctrl, fctrl;
5561 u32 wufc = adapter->wol;
5562 #ifdef CONFIG_PM
5563 int retval = 0;
5564 #endif
5565
5566 netif_device_detach(netdev);
5567
5568 if (netif_running(netdev)) {
5569 ixgbe_down(adapter);
5570 ixgbe_free_irq(adapter);
5571 ixgbe_free_all_tx_resources(adapter);
5572 ixgbe_free_all_rx_resources(adapter);
5573 }
5574
5575 ixgbe_clear_interrupt_scheme(adapter);
5576
5577 #ifdef CONFIG_PM
5578 retval = pci_save_state(pdev);
5579 if (retval)
5580 return retval;
5581
5582 #endif
5583 if (wufc) {
5584 ixgbe_set_rx_mode(netdev);
5585
5586 /* turn on all-multi mode if wake on multicast is enabled */
5587 if (wufc & IXGBE_WUFC_MC) {
5588 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5589 fctrl |= IXGBE_FCTRL_MPE;
5590 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5591 }
5592
5593 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5594 ctrl |= IXGBE_CTRL_GIO_DIS;
5595 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5596
5597 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5598 } else {
5599 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5600 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5601 }
5602
5603 switch (hw->mac.type) {
5604 case ixgbe_mac_82598EB:
5605 pci_wake_from_d3(pdev, false);
5606 break;
5607 case ixgbe_mac_82599EB:
5608 case ixgbe_mac_X540:
5609 pci_wake_from_d3(pdev, !!wufc);
5610 break;
5611 default:
5612 break;
5613 }
5614
5615 *enable_wake = !!wufc;
5616
5617 ixgbe_release_hw_control(adapter);
5618
5619 pci_disable_device(pdev);
5620
5621 return 0;
5622 }
5623
5624 #ifdef CONFIG_PM
5625 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5626 {
5627 int retval;
5628 bool wake;
5629
5630 retval = __ixgbe_shutdown(pdev, &wake);
5631 if (retval)
5632 return retval;
5633
5634 if (wake) {
5635 pci_prepare_to_sleep(pdev);
5636 } else {
5637 pci_wake_from_d3(pdev, false);
5638 pci_set_power_state(pdev, PCI_D3hot);
5639 }
5640
5641 return 0;
5642 }
5643 #endif /* CONFIG_PM */
5644
5645 static void ixgbe_shutdown(struct pci_dev *pdev)
5646 {
5647 bool wake;
5648
5649 __ixgbe_shutdown(pdev, &wake);
5650
5651 if (system_state == SYSTEM_POWER_OFF) {
5652 pci_wake_from_d3(pdev, wake);
5653 pci_set_power_state(pdev, PCI_D3hot);
5654 }
5655 }
5656
5657 /**
5658 * ixgbe_update_stats - Update the board statistics counters.
5659 * @adapter: board private structure
5660 **/
5661 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5662 {
5663 struct net_device *netdev = adapter->netdev;
5664 struct ixgbe_hw *hw = &adapter->hw;
5665 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5666 u64 total_mpc = 0;
5667 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5668 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5669 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5670 u64 bytes = 0, packets = 0;
5671
5672 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5673 test_bit(__IXGBE_RESETTING, &adapter->state))
5674 return;
5675
5676 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5677 u64 rsc_count = 0;
5678 u64 rsc_flush = 0;
5679 for (i = 0; i < 16; i++)
5680 adapter->hw_rx_no_dma_resources +=
5681 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5682 for (i = 0; i < adapter->num_rx_queues; i++) {
5683 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5684 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5685 }
5686 adapter->rsc_total_count = rsc_count;
5687 adapter->rsc_total_flush = rsc_flush;
5688 }
5689
5690 for (i = 0; i < adapter->num_rx_queues; i++) {
5691 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5692 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5693 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5694 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5695 bytes += rx_ring->stats.bytes;
5696 packets += rx_ring->stats.packets;
5697 }
5698 adapter->non_eop_descs = non_eop_descs;
5699 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5700 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5701 netdev->stats.rx_bytes = bytes;
5702 netdev->stats.rx_packets = packets;
5703
5704 bytes = 0;
5705 packets = 0;
5706 /* gather some stats to the adapter struct that are per queue */
5707 for (i = 0; i < adapter->num_tx_queues; i++) {
5708 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5709 restart_queue += tx_ring->tx_stats.restart_queue;
5710 tx_busy += tx_ring->tx_stats.tx_busy;
5711 bytes += tx_ring->stats.bytes;
5712 packets += tx_ring->stats.packets;
5713 }
5714 adapter->restart_queue = restart_queue;
5715 adapter->tx_busy = tx_busy;
5716 netdev->stats.tx_bytes = bytes;
5717 netdev->stats.tx_packets = packets;
5718
5719 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5720 for (i = 0; i < 8; i++) {
5721 /* for packet buffers not used, the register should read 0 */
5722 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5723 missed_rx += mpc;
5724 hwstats->mpc[i] += mpc;
5725 total_mpc += hwstats->mpc[i];
5726 if (hw->mac.type == ixgbe_mac_82598EB)
5727 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5728 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5729 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5730 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5731 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5732 switch (hw->mac.type) {
5733 case ixgbe_mac_82598EB:
5734 hwstats->pxonrxc[i] +=
5735 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5736 break;
5737 case ixgbe_mac_82599EB:
5738 case ixgbe_mac_X540:
5739 hwstats->pxonrxc[i] +=
5740 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5741 break;
5742 default:
5743 break;
5744 }
5745 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5746 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5747 }
5748 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5749 /* work around hardware counting issue */
5750 hwstats->gprc -= missed_rx;
5751
5752 ixgbe_update_xoff_received(adapter);
5753
5754 /* 82598 hardware only has a 32 bit counter in the high register */
5755 switch (hw->mac.type) {
5756 case ixgbe_mac_82598EB:
5757 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5758 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5759 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5760 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5761 break;
5762 case ixgbe_mac_82599EB:
5763 case ixgbe_mac_X540:
5764 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5765 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5766 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5767 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5768 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5769 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5770 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5771 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5772 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5773 #ifdef IXGBE_FCOE
5774 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5775 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5776 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5777 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5778 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5779 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5780 #endif /* IXGBE_FCOE */
5781 break;
5782 default:
5783 break;
5784 }
5785 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5786 hwstats->bprc += bprc;
5787 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5788 if (hw->mac.type == ixgbe_mac_82598EB)
5789 hwstats->mprc -= bprc;
5790 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5791 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5792 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5793 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5794 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5795 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5796 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5797 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5798 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5799 hwstats->lxontxc += lxon;
5800 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5801 hwstats->lxofftxc += lxoff;
5802 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5803 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5804 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5805 /*
5806 * 82598 errata - tx of flow control packets is included in tx counters
5807 */
5808 xon_off_tot = lxon + lxoff;
5809 hwstats->gptc -= xon_off_tot;
5810 hwstats->mptc -= xon_off_tot;
5811 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5812 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5813 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5814 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5815 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5816 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5817 hwstats->ptc64 -= xon_off_tot;
5818 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5819 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5820 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5821 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5822 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5823 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5824
5825 /* Fill out the OS statistics structure */
5826 netdev->stats.multicast = hwstats->mprc;
5827
5828 /* Rx Errors */
5829 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5830 netdev->stats.rx_dropped = 0;
5831 netdev->stats.rx_length_errors = hwstats->rlec;
5832 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5833 netdev->stats.rx_missed_errors = total_mpc;
5834 }
5835
5836 /**
5837 * ixgbe_watchdog - Timer Call-back
5838 * @data: pointer to adapter cast into an unsigned long
5839 **/
5840 static void ixgbe_watchdog(unsigned long data)
5841 {
5842 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5843 struct ixgbe_hw *hw = &adapter->hw;
5844 u64 eics = 0;
5845 int i;
5846
5847 /*
5848 * Do the watchdog outside of interrupt context due to the lovely
5849 * delays that some of the newer hardware requires
5850 */
5851
5852 if (test_bit(__IXGBE_DOWN, &adapter->state))
5853 goto watchdog_short_circuit;
5854
5855 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5856 /*
5857 * for legacy and MSI interrupts don't set any bits
5858 * that are enabled for EIAM, because this operation
5859 * would set *both* EIMS and EICS for any bit in EIAM
5860 */
5861 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5862 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5863 goto watchdog_reschedule;
5864 }
5865
5866 /* get one bit for every active tx/rx interrupt vector */
5867 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5868 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5869 if (qv->rxr_count || qv->txr_count)
5870 eics |= ((u64)1 << i);
5871 }
5872
5873 /* Cause software interrupt to ensure rx rings are cleaned */
5874 ixgbe_irq_rearm_queues(adapter, eics);
5875
5876 watchdog_reschedule:
5877 /* Reset the timer */
5878 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5879
5880 watchdog_short_circuit:
5881 schedule_work(&adapter->watchdog_task);
5882 }
5883
5884 /**
5885 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5886 * @work: pointer to work_struct containing our data
5887 **/
5888 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5889 {
5890 struct ixgbe_adapter *adapter = container_of(work,
5891 struct ixgbe_adapter,
5892 multispeed_fiber_task);
5893 struct ixgbe_hw *hw = &adapter->hw;
5894 u32 autoneg;
5895 bool negotiation;
5896
5897 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5898 autoneg = hw->phy.autoneg_advertised;
5899 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5900 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5901 hw->mac.autotry_restart = false;
5902 if (hw->mac.ops.setup_link)
5903 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5904 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5905 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5906 }
5907
5908 /**
5909 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5910 * @work: pointer to work_struct containing our data
5911 **/
5912 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5913 {
5914 struct ixgbe_adapter *adapter = container_of(work,
5915 struct ixgbe_adapter,
5916 sfp_config_module_task);
5917 struct ixgbe_hw *hw = &adapter->hw;
5918 u32 err;
5919
5920 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5921
5922 /* Time for electrical oscillations to settle down */
5923 msleep(100);
5924 err = hw->phy.ops.identify_sfp(hw);
5925
5926 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5927 e_dev_err("failed to initialize because an unsupported SFP+ "
5928 "module type was detected.\n");
5929 e_dev_err("Reload the driver after installing a supported "
5930 "module.\n");
5931 unregister_netdev(adapter->netdev);
5932 return;
5933 }
5934 hw->mac.ops.setup_sfp(hw);
5935
5936 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5937 /* This will also work for DA Twinax connections */
5938 schedule_work(&adapter->multispeed_fiber_task);
5939 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5940 }
5941
5942 /**
5943 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5944 * @work: pointer to work_struct containing our data
5945 **/
5946 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5947 {
5948 struct ixgbe_adapter *adapter = container_of(work,
5949 struct ixgbe_adapter,
5950 fdir_reinit_task);
5951 struct ixgbe_hw *hw = &adapter->hw;
5952 int i;
5953
5954 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5955 for (i = 0; i < adapter->num_tx_queues; i++)
5956 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5957 &(adapter->tx_ring[i]->state));
5958 } else {
5959 e_err(probe, "failed to finish FDIR re-initialization, "
5960 "ignored adding FDIR ATR filters\n");
5961 }
5962 /* Done FDIR Re-initialization, enable transmits */
5963 netif_tx_start_all_queues(adapter->netdev);
5964 }
5965
5966 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5967 {
5968 u32 ssvpc;
5969
5970 /* Do not perform spoof check for 82598 */
5971 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5972 return;
5973
5974 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5975
5976 /*
5977 * ssvpc register is cleared on read, if zero then no
5978 * spoofed packets in the last interval.
5979 */
5980 if (!ssvpc)
5981 return;
5982
5983 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5984 }
5985
5986 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5987
5988 /**
5989 * ixgbe_watchdog_task - worker thread to bring link up
5990 * @work: pointer to work_struct containing our data
5991 **/
5992 static void ixgbe_watchdog_task(struct work_struct *work)
5993 {
5994 struct ixgbe_adapter *adapter = container_of(work,
5995 struct ixgbe_adapter,
5996 watchdog_task);
5997 struct net_device *netdev = adapter->netdev;
5998 struct ixgbe_hw *hw = &adapter->hw;
5999 u32 link_speed;
6000 bool link_up;
6001 int i;
6002 struct ixgbe_ring *tx_ring;
6003 int some_tx_pending = 0;
6004
6005 mutex_lock(&ixgbe_watchdog_lock);
6006
6007 link_up = adapter->link_up;
6008 link_speed = adapter->link_speed;
6009
6010 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6011 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6012 if (link_up) {
6013 #ifdef CONFIG_DCB
6014 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6015 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6016 hw->mac.ops.fc_enable(hw, i);
6017 } else {
6018 hw->mac.ops.fc_enable(hw, 0);
6019 }
6020 #else
6021 hw->mac.ops.fc_enable(hw, 0);
6022 #endif
6023 }
6024
6025 if (link_up ||
6026 time_after(jiffies, (adapter->link_check_timeout +
6027 IXGBE_TRY_LINK_TIMEOUT))) {
6028 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6029 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6030 }
6031 adapter->link_up = link_up;
6032 adapter->link_speed = link_speed;
6033 }
6034
6035 if (link_up) {
6036 if (!netif_carrier_ok(netdev)) {
6037 bool flow_rx, flow_tx;
6038
6039 switch (hw->mac.type) {
6040 case ixgbe_mac_82598EB: {
6041 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6042 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6043 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6044 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6045 }
6046 break;
6047 case ixgbe_mac_82599EB:
6048 case ixgbe_mac_X540: {
6049 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6050 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6051 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6052 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6053 }
6054 break;
6055 default:
6056 flow_tx = false;
6057 flow_rx = false;
6058 break;
6059 }
6060
6061 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6062 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6063 "10 Gbps" :
6064 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6065 "1 Gbps" : "unknown speed")),
6066 ((flow_rx && flow_tx) ? "RX/TX" :
6067 (flow_rx ? "RX" :
6068 (flow_tx ? "TX" : "None"))));
6069
6070 netif_carrier_on(netdev);
6071 } else {
6072 /* Force detection of hung controller */
6073 for (i = 0; i < adapter->num_tx_queues; i++) {
6074 tx_ring = adapter->tx_ring[i];
6075 set_check_for_tx_hang(tx_ring);
6076 }
6077 }
6078 } else {
6079 adapter->link_up = false;
6080 adapter->link_speed = 0;
6081 if (netif_carrier_ok(netdev)) {
6082 e_info(drv, "NIC Link is Down\n");
6083 netif_carrier_off(netdev);
6084 }
6085 }
6086
6087 if (!netif_carrier_ok(netdev)) {
6088 for (i = 0; i < adapter->num_tx_queues; i++) {
6089 tx_ring = adapter->tx_ring[i];
6090 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6091 some_tx_pending = 1;
6092 break;
6093 }
6094 }
6095
6096 if (some_tx_pending) {
6097 /* We've lost link, so the controller stops DMA,
6098 * but we've got queued Tx work that's never going
6099 * to get done, so reset controller to flush Tx.
6100 * (Do the reset outside of interrupt context).
6101 */
6102 schedule_work(&adapter->reset_task);
6103 }
6104 }
6105
6106 ixgbe_spoof_check(adapter);
6107 ixgbe_update_stats(adapter);
6108 mutex_unlock(&ixgbe_watchdog_lock);
6109 }
6110
6111 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6112 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6113 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6114 {
6115 struct ixgbe_adv_tx_context_desc *context_desc;
6116 unsigned int i;
6117 int err;
6118 struct ixgbe_tx_buffer *tx_buffer_info;
6119 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6120 u32 mss_l4len_idx, l4len;
6121
6122 if (skb_is_gso(skb)) {
6123 if (skb_header_cloned(skb)) {
6124 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6125 if (err)
6126 return err;
6127 }
6128 l4len = tcp_hdrlen(skb);
6129 *hdr_len += l4len;
6130
6131 if (protocol == htons(ETH_P_IP)) {
6132 struct iphdr *iph = ip_hdr(skb);
6133 iph->tot_len = 0;
6134 iph->check = 0;
6135 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6136 iph->daddr, 0,
6137 IPPROTO_TCP,
6138 0);
6139 } else if (skb_is_gso_v6(skb)) {
6140 ipv6_hdr(skb)->payload_len = 0;
6141 tcp_hdr(skb)->check =
6142 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6143 &ipv6_hdr(skb)->daddr,
6144 0, IPPROTO_TCP, 0);
6145 }
6146
6147 i = tx_ring->next_to_use;
6148
6149 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6150 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6151
6152 /* VLAN MACLEN IPLEN */
6153 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6154 vlan_macip_lens |=
6155 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6156 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6157 IXGBE_ADVTXD_MACLEN_SHIFT);
6158 *hdr_len += skb_network_offset(skb);
6159 vlan_macip_lens |=
6160 (skb_transport_header(skb) - skb_network_header(skb));
6161 *hdr_len +=
6162 (skb_transport_header(skb) - skb_network_header(skb));
6163 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6164 context_desc->seqnum_seed = 0;
6165
6166 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6167 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6168 IXGBE_ADVTXD_DTYP_CTXT);
6169
6170 if (protocol == htons(ETH_P_IP))
6171 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6172 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6173 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6174
6175 /* MSS L4LEN IDX */
6176 mss_l4len_idx =
6177 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6178 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6179 /* use index 1 for TSO */
6180 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6181 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6182
6183 tx_buffer_info->time_stamp = jiffies;
6184 tx_buffer_info->next_to_watch = i;
6185
6186 i++;
6187 if (i == tx_ring->count)
6188 i = 0;
6189 tx_ring->next_to_use = i;
6190
6191 return true;
6192 }
6193 return false;
6194 }
6195
6196 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6197 __be16 protocol)
6198 {
6199 u32 rtn = 0;
6200
6201 switch (protocol) {
6202 case cpu_to_be16(ETH_P_IP):
6203 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6204 switch (ip_hdr(skb)->protocol) {
6205 case IPPROTO_TCP:
6206 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6207 break;
6208 case IPPROTO_SCTP:
6209 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6210 break;
6211 }
6212 break;
6213 case cpu_to_be16(ETH_P_IPV6):
6214 /* XXX what about other V6 headers?? */
6215 switch (ipv6_hdr(skb)->nexthdr) {
6216 case IPPROTO_TCP:
6217 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6218 break;
6219 case IPPROTO_SCTP:
6220 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6221 break;
6222 }
6223 break;
6224 default:
6225 if (unlikely(net_ratelimit()))
6226 e_warn(probe, "partial checksum but proto=%x!\n",
6227 protocol);
6228 break;
6229 }
6230
6231 return rtn;
6232 }
6233
6234 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6235 struct ixgbe_ring *tx_ring,
6236 struct sk_buff *skb, u32 tx_flags,
6237 __be16 protocol)
6238 {
6239 struct ixgbe_adv_tx_context_desc *context_desc;
6240 unsigned int i;
6241 struct ixgbe_tx_buffer *tx_buffer_info;
6242 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6243
6244 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6245 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6246 i = tx_ring->next_to_use;
6247 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6248 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6249
6250 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6251 vlan_macip_lens |=
6252 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6253 vlan_macip_lens |= (skb_network_offset(skb) <<
6254 IXGBE_ADVTXD_MACLEN_SHIFT);
6255 if (skb->ip_summed == CHECKSUM_PARTIAL)
6256 vlan_macip_lens |= (skb_transport_header(skb) -
6257 skb_network_header(skb));
6258
6259 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6260 context_desc->seqnum_seed = 0;
6261
6262 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6263 IXGBE_ADVTXD_DTYP_CTXT);
6264
6265 if (skb->ip_summed == CHECKSUM_PARTIAL)
6266 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6267
6268 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6269 /* use index zero for tx checksum offload */
6270 context_desc->mss_l4len_idx = 0;
6271
6272 tx_buffer_info->time_stamp = jiffies;
6273 tx_buffer_info->next_to_watch = i;
6274
6275 i++;
6276 if (i == tx_ring->count)
6277 i = 0;
6278 tx_ring->next_to_use = i;
6279
6280 return true;
6281 }
6282
6283 return false;
6284 }
6285
6286 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6287 struct ixgbe_ring *tx_ring,
6288 struct sk_buff *skb, u32 tx_flags,
6289 unsigned int first, const u8 hdr_len)
6290 {
6291 struct device *dev = tx_ring->dev;
6292 struct ixgbe_tx_buffer *tx_buffer_info;
6293 unsigned int len;
6294 unsigned int total = skb->len;
6295 unsigned int offset = 0, size, count = 0, i;
6296 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6297 unsigned int f;
6298 unsigned int bytecount = skb->len;
6299 u16 gso_segs = 1;
6300
6301 i = tx_ring->next_to_use;
6302
6303 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6304 /* excluding fcoe_crc_eof for FCoE */
6305 total -= sizeof(struct fcoe_crc_eof);
6306
6307 len = min(skb_headlen(skb), total);
6308 while (len) {
6309 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6310 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6311
6312 tx_buffer_info->length = size;
6313 tx_buffer_info->mapped_as_page = false;
6314 tx_buffer_info->dma = dma_map_single(dev,
6315 skb->data + offset,
6316 size, DMA_TO_DEVICE);
6317 if (dma_mapping_error(dev, tx_buffer_info->dma))
6318 goto dma_error;
6319 tx_buffer_info->time_stamp = jiffies;
6320 tx_buffer_info->next_to_watch = i;
6321
6322 len -= size;
6323 total -= size;
6324 offset += size;
6325 count++;
6326
6327 if (len) {
6328 i++;
6329 if (i == tx_ring->count)
6330 i = 0;
6331 }
6332 }
6333
6334 for (f = 0; f < nr_frags; f++) {
6335 struct skb_frag_struct *frag;
6336
6337 frag = &skb_shinfo(skb)->frags[f];
6338 len = min((unsigned int)frag->size, total);
6339 offset = frag->page_offset;
6340
6341 while (len) {
6342 i++;
6343 if (i == tx_ring->count)
6344 i = 0;
6345
6346 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6347 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6348
6349 tx_buffer_info->length = size;
6350 tx_buffer_info->dma = dma_map_page(dev,
6351 frag->page,
6352 offset, size,
6353 DMA_TO_DEVICE);
6354 tx_buffer_info->mapped_as_page = true;
6355 if (dma_mapping_error(dev, tx_buffer_info->dma))
6356 goto dma_error;
6357 tx_buffer_info->time_stamp = jiffies;
6358 tx_buffer_info->next_to_watch = i;
6359
6360 len -= size;
6361 total -= size;
6362 offset += size;
6363 count++;
6364 }
6365 if (total == 0)
6366 break;
6367 }
6368
6369 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6370 gso_segs = skb_shinfo(skb)->gso_segs;
6371 #ifdef IXGBE_FCOE
6372 /* adjust for FCoE Sequence Offload */
6373 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6374 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6375 skb_shinfo(skb)->gso_size);
6376 #endif /* IXGBE_FCOE */
6377 bytecount += (gso_segs - 1) * hdr_len;
6378
6379 /* multiply data chunks by size of headers */
6380 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6381 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6382 tx_ring->tx_buffer_info[i].skb = skb;
6383 tx_ring->tx_buffer_info[first].next_to_watch = i;
6384
6385 return count;
6386
6387 dma_error:
6388 e_dev_err("TX DMA map failed\n");
6389
6390 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6391 tx_buffer_info->dma = 0;
6392 tx_buffer_info->time_stamp = 0;
6393 tx_buffer_info->next_to_watch = 0;
6394 if (count)
6395 count--;
6396
6397 /* clear timestamp and dma mappings for remaining portion of packet */
6398 while (count--) {
6399 if (i == 0)
6400 i += tx_ring->count;
6401 i--;
6402 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6403 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6404 }
6405
6406 return 0;
6407 }
6408
6409 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6410 int tx_flags, int count, u32 paylen, u8 hdr_len)
6411 {
6412 union ixgbe_adv_tx_desc *tx_desc = NULL;
6413 struct ixgbe_tx_buffer *tx_buffer_info;
6414 u32 olinfo_status = 0, cmd_type_len = 0;
6415 unsigned int i;
6416 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6417
6418 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6419
6420 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6421
6422 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6423 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6424
6425 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6426 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6427
6428 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6429 IXGBE_ADVTXD_POPTS_SHIFT;
6430
6431 /* use index 1 context for tso */
6432 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6433 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6434 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6435 IXGBE_ADVTXD_POPTS_SHIFT;
6436
6437 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6438 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6439 IXGBE_ADVTXD_POPTS_SHIFT;
6440
6441 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6442 olinfo_status |= IXGBE_ADVTXD_CC;
6443 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6444 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6445 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6446 }
6447
6448 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6449
6450 i = tx_ring->next_to_use;
6451 while (count--) {
6452 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6453 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6454 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6455 tx_desc->read.cmd_type_len =
6456 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6457 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6458 i++;
6459 if (i == tx_ring->count)
6460 i = 0;
6461 }
6462
6463 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6464
6465 /*
6466 * Force memory writes to complete before letting h/w
6467 * know there are new descriptors to fetch. (Only
6468 * applicable for weak-ordered memory model archs,
6469 * such as IA-64).
6470 */
6471 wmb();
6472
6473 tx_ring->next_to_use = i;
6474 writel(i, tx_ring->tail);
6475 }
6476
6477 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6478 u8 queue, u32 tx_flags, __be16 protocol)
6479 {
6480 struct ixgbe_atr_input atr_input;
6481 struct iphdr *iph = ip_hdr(skb);
6482 struct ethhdr *eth = (struct ethhdr *)skb->data;
6483 struct tcphdr *th;
6484 u16 vlan_id;
6485
6486 /* Right now, we support IPv4 w/ TCP only */
6487 if (protocol != htons(ETH_P_IP) ||
6488 iph->protocol != IPPROTO_TCP)
6489 return;
6490
6491 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6492
6493 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6494 IXGBE_TX_FLAGS_VLAN_SHIFT;
6495
6496 th = tcp_hdr(skb);
6497
6498 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6499 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6500 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6501 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6502 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6503 /* src and dst are inverted, think how the receiver sees them */
6504 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6505 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6506
6507 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6508 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6509 }
6510
6511 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6512 {
6513 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6514 /* Herbert's original patch had:
6515 * smp_mb__after_netif_stop_queue();
6516 * but since that doesn't exist yet, just open code it. */
6517 smp_mb();
6518
6519 /* We need to check again in a case another CPU has just
6520 * made room available. */
6521 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6522 return -EBUSY;
6523
6524 /* A reprieve! - use start_queue because it doesn't call schedule */
6525 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6526 ++tx_ring->tx_stats.restart_queue;
6527 return 0;
6528 }
6529
6530 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6531 {
6532 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6533 return 0;
6534 return __ixgbe_maybe_stop_tx(tx_ring, size);
6535 }
6536
6537 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6538 {
6539 struct ixgbe_adapter *adapter = netdev_priv(dev);
6540 int txq = smp_processor_id();
6541 #ifdef IXGBE_FCOE
6542 __be16 protocol;
6543
6544 protocol = vlan_get_protocol(skb);
6545
6546 if ((protocol == htons(ETH_P_FCOE)) ||
6547 (protocol == htons(ETH_P_FIP))) {
6548 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6549 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6550 txq += adapter->ring_feature[RING_F_FCOE].mask;
6551 return txq;
6552 #ifdef CONFIG_IXGBE_DCB
6553 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6554 txq = adapter->fcoe.up;
6555 return txq;
6556 #endif
6557 }
6558 }
6559 #endif
6560
6561 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6562 while (unlikely(txq >= dev->real_num_tx_queues))
6563 txq -= dev->real_num_tx_queues;
6564 return txq;
6565 }
6566
6567 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6568 if (skb->priority == TC_PRIO_CONTROL)
6569 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6570 else
6571 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6572 >> 13;
6573 return txq;
6574 }
6575
6576 return skb_tx_hash(dev, skb);
6577 }
6578
6579 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6580 struct ixgbe_adapter *adapter,
6581 struct ixgbe_ring *tx_ring)
6582 {
6583 struct net_device *netdev = tx_ring->netdev;
6584 struct netdev_queue *txq;
6585 unsigned int first;
6586 unsigned int tx_flags = 0;
6587 u8 hdr_len = 0;
6588 int tso;
6589 int count = 0;
6590 unsigned int f;
6591 __be16 protocol;
6592
6593 protocol = vlan_get_protocol(skb);
6594
6595 if (vlan_tx_tag_present(skb)) {
6596 tx_flags |= vlan_tx_tag_get(skb);
6597 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6598 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6599 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6600 }
6601 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6602 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6603 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6604 skb->priority != TC_PRIO_CONTROL) {
6605 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6606 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6607 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6608 }
6609
6610 #ifdef IXGBE_FCOE
6611 /* for FCoE with DCB, we force the priority to what
6612 * was specified by the switch */
6613 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6614 (protocol == htons(ETH_P_FCOE) ||
6615 protocol == htons(ETH_P_FIP))) {
6616 #ifdef CONFIG_IXGBE_DCB
6617 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6618 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6619 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6620 tx_flags |= ((adapter->fcoe.up << 13)
6621 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6622 }
6623 #endif
6624 /* flag for FCoE offloads */
6625 if (protocol == htons(ETH_P_FCOE))
6626 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6627 }
6628 #endif
6629
6630 /* four things can cause us to need a context descriptor */
6631 if (skb_is_gso(skb) ||
6632 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6633 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6634 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6635 count++;
6636
6637 count += TXD_USE_COUNT(skb_headlen(skb));
6638 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6639 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6640
6641 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6642 tx_ring->tx_stats.tx_busy++;
6643 return NETDEV_TX_BUSY;
6644 }
6645
6646 first = tx_ring->next_to_use;
6647 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6648 #ifdef IXGBE_FCOE
6649 /* setup tx offload for FCoE */
6650 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6651 if (tso < 0) {
6652 dev_kfree_skb_any(skb);
6653 return NETDEV_TX_OK;
6654 }
6655 if (tso)
6656 tx_flags |= IXGBE_TX_FLAGS_FSO;
6657 #endif /* IXGBE_FCOE */
6658 } else {
6659 if (protocol == htons(ETH_P_IP))
6660 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6661 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6662 protocol);
6663 if (tso < 0) {
6664 dev_kfree_skb_any(skb);
6665 return NETDEV_TX_OK;
6666 }
6667
6668 if (tso)
6669 tx_flags |= IXGBE_TX_FLAGS_TSO;
6670 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6671 protocol) &&
6672 (skb->ip_summed == CHECKSUM_PARTIAL))
6673 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6674 }
6675
6676 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6677 if (count) {
6678 /* add the ATR filter if ATR is on */
6679 if (tx_ring->atr_sample_rate) {
6680 ++tx_ring->atr_count;
6681 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6682 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6683 &tx_ring->state)) {
6684 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6685 tx_flags, protocol);
6686 tx_ring->atr_count = 0;
6687 }
6688 }
6689 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6690 txq->tx_bytes += skb->len;
6691 txq->tx_packets++;
6692 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6693 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6694
6695 } else {
6696 dev_kfree_skb_any(skb);
6697 tx_ring->tx_buffer_info[first].time_stamp = 0;
6698 tx_ring->next_to_use = first;
6699 }
6700
6701 return NETDEV_TX_OK;
6702 }
6703
6704 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6705 {
6706 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6707 struct ixgbe_ring *tx_ring;
6708
6709 tx_ring = adapter->tx_ring[skb->queue_mapping];
6710 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6711 }
6712
6713 /**
6714 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6715 * @netdev: network interface device structure
6716 * @p: pointer to an address structure
6717 *
6718 * Returns 0 on success, negative on failure
6719 **/
6720 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6721 {
6722 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6723 struct ixgbe_hw *hw = &adapter->hw;
6724 struct sockaddr *addr = p;
6725
6726 if (!is_valid_ether_addr(addr->sa_data))
6727 return -EADDRNOTAVAIL;
6728
6729 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6730 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6731
6732 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6733 IXGBE_RAH_AV);
6734
6735 return 0;
6736 }
6737
6738 static int
6739 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6740 {
6741 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6742 struct ixgbe_hw *hw = &adapter->hw;
6743 u16 value;
6744 int rc;
6745
6746 if (prtad != hw->phy.mdio.prtad)
6747 return -EINVAL;
6748 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6749 if (!rc)
6750 rc = value;
6751 return rc;
6752 }
6753
6754 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6755 u16 addr, u16 value)
6756 {
6757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6758 struct ixgbe_hw *hw = &adapter->hw;
6759
6760 if (prtad != hw->phy.mdio.prtad)
6761 return -EINVAL;
6762 return hw->phy.ops.write_reg(hw, addr, devad, value);
6763 }
6764
6765 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6766 {
6767 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6768
6769 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6770 }
6771
6772 /**
6773 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6774 * netdev->dev_addrs
6775 * @netdev: network interface device structure
6776 *
6777 * Returns non-zero on failure
6778 **/
6779 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6780 {
6781 int err = 0;
6782 struct ixgbe_adapter *adapter = netdev_priv(dev);
6783 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6784
6785 if (is_valid_ether_addr(mac->san_addr)) {
6786 rtnl_lock();
6787 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6788 rtnl_unlock();
6789 }
6790 return err;
6791 }
6792
6793 /**
6794 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6795 * netdev->dev_addrs
6796 * @netdev: network interface device structure
6797 *
6798 * Returns non-zero on failure
6799 **/
6800 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6801 {
6802 int err = 0;
6803 struct ixgbe_adapter *adapter = netdev_priv(dev);
6804 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6805
6806 if (is_valid_ether_addr(mac->san_addr)) {
6807 rtnl_lock();
6808 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6809 rtnl_unlock();
6810 }
6811 return err;
6812 }
6813
6814 #ifdef CONFIG_NET_POLL_CONTROLLER
6815 /*
6816 * Polling 'interrupt' - used by things like netconsole to send skbs
6817 * without having to re-enable interrupts. It's not called while
6818 * the interrupt routine is executing.
6819 */
6820 static void ixgbe_netpoll(struct net_device *netdev)
6821 {
6822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6823 int i;
6824
6825 /* if interface is down do nothing */
6826 if (test_bit(__IXGBE_DOWN, &adapter->state))
6827 return;
6828
6829 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6830 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6831 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6832 for (i = 0; i < num_q_vectors; i++) {
6833 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6834 ixgbe_msix_clean_many(0, q_vector);
6835 }
6836 } else {
6837 ixgbe_intr(adapter->pdev->irq, netdev);
6838 }
6839 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6840 }
6841 #endif
6842
6843 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6844 struct rtnl_link_stats64 *stats)
6845 {
6846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6847 int i;
6848
6849 /* accurate rx/tx bytes/packets stats */
6850 dev_txq_stats_fold(netdev, stats);
6851 rcu_read_lock();
6852 for (i = 0; i < adapter->num_rx_queues; i++) {
6853 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6854 u64 bytes, packets;
6855 unsigned int start;
6856
6857 if (ring) {
6858 do {
6859 start = u64_stats_fetch_begin_bh(&ring->syncp);
6860 packets = ring->stats.packets;
6861 bytes = ring->stats.bytes;
6862 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6863 stats->rx_packets += packets;
6864 stats->rx_bytes += bytes;
6865 }
6866 }
6867 rcu_read_unlock();
6868 /* following stats updated by ixgbe_watchdog_task() */
6869 stats->multicast = netdev->stats.multicast;
6870 stats->rx_errors = netdev->stats.rx_errors;
6871 stats->rx_length_errors = netdev->stats.rx_length_errors;
6872 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6873 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6874 return stats;
6875 }
6876
6877
6878 static const struct net_device_ops ixgbe_netdev_ops = {
6879 .ndo_open = ixgbe_open,
6880 .ndo_stop = ixgbe_close,
6881 .ndo_start_xmit = ixgbe_xmit_frame,
6882 .ndo_select_queue = ixgbe_select_queue,
6883 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6884 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6885 .ndo_validate_addr = eth_validate_addr,
6886 .ndo_set_mac_address = ixgbe_set_mac,
6887 .ndo_change_mtu = ixgbe_change_mtu,
6888 .ndo_tx_timeout = ixgbe_tx_timeout,
6889 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6890 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6891 .ndo_do_ioctl = ixgbe_ioctl,
6892 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6893 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6894 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6895 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6896 .ndo_get_stats64 = ixgbe_get_stats64,
6897 #ifdef CONFIG_NET_POLL_CONTROLLER
6898 .ndo_poll_controller = ixgbe_netpoll,
6899 #endif
6900 #ifdef IXGBE_FCOE
6901 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6902 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6903 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6904 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6905 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6906 #endif /* IXGBE_FCOE */
6907 };
6908
6909 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6910 const struct ixgbe_info *ii)
6911 {
6912 #ifdef CONFIG_PCI_IOV
6913 struct ixgbe_hw *hw = &adapter->hw;
6914 int err;
6915
6916 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
6917 return;
6918
6919 /* The 82599 supports up to 64 VFs per physical function
6920 * but this implementation limits allocation to 63 so that
6921 * basic networking resources are still available to the
6922 * physical function
6923 */
6924 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6925 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6926 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6927 if (err) {
6928 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6929 goto err_novfs;
6930 }
6931 /* If call to enable VFs succeeded then allocate memory
6932 * for per VF control structures.
6933 */
6934 adapter->vfinfo =
6935 kcalloc(adapter->num_vfs,
6936 sizeof(struct vf_data_storage), GFP_KERNEL);
6937 if (adapter->vfinfo) {
6938 /* Now that we're sure SR-IOV is enabled
6939 * and memory allocated set up the mailbox parameters
6940 */
6941 ixgbe_init_mbx_params_pf(hw);
6942 memcpy(&hw->mbx.ops, ii->mbx_ops,
6943 sizeof(hw->mbx.ops));
6944
6945 /* Disable RSC when in SR-IOV mode */
6946 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6947 IXGBE_FLAG2_RSC_ENABLED);
6948 return;
6949 }
6950
6951 /* Oh oh */
6952 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6953 "SRIOV disabled\n");
6954 pci_disable_sriov(adapter->pdev);
6955
6956 err_novfs:
6957 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6958 adapter->num_vfs = 0;
6959 #endif /* CONFIG_PCI_IOV */
6960 }
6961
6962 /**
6963 * ixgbe_probe - Device Initialization Routine
6964 * @pdev: PCI device information struct
6965 * @ent: entry in ixgbe_pci_tbl
6966 *
6967 * Returns 0 on success, negative on failure
6968 *
6969 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6970 * The OS initialization, configuring of the adapter private structure,
6971 * and a hardware reset occur.
6972 **/
6973 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6974 const struct pci_device_id *ent)
6975 {
6976 struct net_device *netdev;
6977 struct ixgbe_adapter *adapter = NULL;
6978 struct ixgbe_hw *hw;
6979 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6980 static int cards_found;
6981 int i, err, pci_using_dac;
6982 u8 part_str[IXGBE_PBANUM_LENGTH];
6983 unsigned int indices = num_possible_cpus();
6984 #ifdef IXGBE_FCOE
6985 u16 device_caps;
6986 #endif
6987 u32 eec;
6988
6989 /* Catch broken hardware that put the wrong VF device ID in
6990 * the PCIe SR-IOV capability.
6991 */
6992 if (pdev->is_virtfn) {
6993 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6994 pci_name(pdev), pdev->vendor, pdev->device);
6995 return -EINVAL;
6996 }
6997
6998 err = pci_enable_device_mem(pdev);
6999 if (err)
7000 return err;
7001
7002 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7003 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7004 pci_using_dac = 1;
7005 } else {
7006 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7007 if (err) {
7008 err = dma_set_coherent_mask(&pdev->dev,
7009 DMA_BIT_MASK(32));
7010 if (err) {
7011 dev_err(&pdev->dev,
7012 "No usable DMA configuration, aborting\n");
7013 goto err_dma;
7014 }
7015 }
7016 pci_using_dac = 0;
7017 }
7018
7019 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7020 IORESOURCE_MEM), ixgbe_driver_name);
7021 if (err) {
7022 dev_err(&pdev->dev,
7023 "pci_request_selected_regions failed 0x%x\n", err);
7024 goto err_pci_reg;
7025 }
7026
7027 pci_enable_pcie_error_reporting(pdev);
7028
7029 pci_set_master(pdev);
7030 pci_save_state(pdev);
7031
7032 if (ii->mac == ixgbe_mac_82598EB)
7033 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7034 else
7035 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7036
7037 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7038 #ifdef IXGBE_FCOE
7039 indices += min_t(unsigned int, num_possible_cpus(),
7040 IXGBE_MAX_FCOE_INDICES);
7041 #endif
7042 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7043 if (!netdev) {
7044 err = -ENOMEM;
7045 goto err_alloc_etherdev;
7046 }
7047
7048 SET_NETDEV_DEV(netdev, &pdev->dev);
7049
7050 adapter = netdev_priv(netdev);
7051 pci_set_drvdata(pdev, adapter);
7052
7053 adapter->netdev = netdev;
7054 adapter->pdev = pdev;
7055 hw = &adapter->hw;
7056 hw->back = adapter;
7057 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7058
7059 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7060 pci_resource_len(pdev, 0));
7061 if (!hw->hw_addr) {
7062 err = -EIO;
7063 goto err_ioremap;
7064 }
7065
7066 for (i = 1; i <= 5; i++) {
7067 if (pci_resource_len(pdev, i) == 0)
7068 continue;
7069 }
7070
7071 netdev->netdev_ops = &ixgbe_netdev_ops;
7072 ixgbe_set_ethtool_ops(netdev);
7073 netdev->watchdog_timeo = 5 * HZ;
7074 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7075
7076 adapter->bd_number = cards_found;
7077
7078 /* Setup hw api */
7079 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7080 hw->mac.type = ii->mac;
7081
7082 /* EEPROM */
7083 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7084 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7085 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7086 if (!(eec & (1 << 8)))
7087 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7088
7089 /* PHY */
7090 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7091 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7092 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7093 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7094 hw->phy.mdio.mmds = 0;
7095 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7096 hw->phy.mdio.dev = netdev;
7097 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7098 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7099
7100 /* set up this timer and work struct before calling get_invariants
7101 * which might start the timer
7102 */
7103 init_timer(&adapter->sfp_timer);
7104 adapter->sfp_timer.function = ixgbe_sfp_timer;
7105 adapter->sfp_timer.data = (unsigned long) adapter;
7106
7107 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7108
7109 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7110 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7111
7112 /* a new SFP+ module arrival, called from GPI SDP2 context */
7113 INIT_WORK(&adapter->sfp_config_module_task,
7114 ixgbe_sfp_config_module_task);
7115
7116 ii->get_invariants(hw);
7117
7118 /* setup the private structure */
7119 err = ixgbe_sw_init(adapter);
7120 if (err)
7121 goto err_sw_init;
7122
7123 /* Make it possible the adapter to be woken up via WOL */
7124 switch (adapter->hw.mac.type) {
7125 case ixgbe_mac_82599EB:
7126 case ixgbe_mac_X540:
7127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7128 break;
7129 default:
7130 break;
7131 }
7132
7133 /*
7134 * If there is a fan on this device and it has failed log the
7135 * failure.
7136 */
7137 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7138 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7139 if (esdp & IXGBE_ESDP_SDP1)
7140 e_crit(probe, "Fan has stopped, replace the adapter\n");
7141 }
7142
7143 /* reset_hw fills in the perm_addr as well */
7144 hw->phy.reset_if_overtemp = true;
7145 err = hw->mac.ops.reset_hw(hw);
7146 hw->phy.reset_if_overtemp = false;
7147 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7148 hw->mac.type == ixgbe_mac_82598EB) {
7149 /*
7150 * Start a kernel thread to watch for a module to arrive.
7151 * Only do this for 82598, since 82599 will generate
7152 * interrupts on module arrival.
7153 */
7154 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7155 mod_timer(&adapter->sfp_timer,
7156 round_jiffies(jiffies + (2 * HZ)));
7157 err = 0;
7158 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7159 e_dev_err("failed to initialize because an unsupported SFP+ "
7160 "module type was detected.\n");
7161 e_dev_err("Reload the driver after installing a supported "
7162 "module.\n");
7163 goto err_sw_init;
7164 } else if (err) {
7165 e_dev_err("HW Init failed: %d\n", err);
7166 goto err_sw_init;
7167 }
7168
7169 ixgbe_probe_vf(adapter, ii);
7170
7171 netdev->features = NETIF_F_SG |
7172 NETIF_F_IP_CSUM |
7173 NETIF_F_HW_VLAN_TX |
7174 NETIF_F_HW_VLAN_RX |
7175 NETIF_F_HW_VLAN_FILTER;
7176
7177 netdev->features |= NETIF_F_IPV6_CSUM;
7178 netdev->features |= NETIF_F_TSO;
7179 netdev->features |= NETIF_F_TSO6;
7180 netdev->features |= NETIF_F_GRO;
7181
7182 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7183 netdev->features |= NETIF_F_SCTP_CSUM;
7184
7185 netdev->vlan_features |= NETIF_F_TSO;
7186 netdev->vlan_features |= NETIF_F_TSO6;
7187 netdev->vlan_features |= NETIF_F_IP_CSUM;
7188 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7189 netdev->vlan_features |= NETIF_F_SG;
7190
7191 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7192 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7193 IXGBE_FLAG_DCB_ENABLED);
7194 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7195 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7196
7197 #ifdef CONFIG_IXGBE_DCB
7198 netdev->dcbnl_ops = &dcbnl_ops;
7199 #endif
7200
7201 #ifdef IXGBE_FCOE
7202 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7203 if (hw->mac.ops.get_device_caps) {
7204 hw->mac.ops.get_device_caps(hw, &device_caps);
7205 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7206 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7207 }
7208 }
7209 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7210 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7211 netdev->vlan_features |= NETIF_F_FSO;
7212 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7213 }
7214 #endif /* IXGBE_FCOE */
7215 if (pci_using_dac) {
7216 netdev->features |= NETIF_F_HIGHDMA;
7217 netdev->vlan_features |= NETIF_F_HIGHDMA;
7218 }
7219
7220 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7221 netdev->features |= NETIF_F_LRO;
7222
7223 /* make sure the EEPROM is good */
7224 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7225 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7226 err = -EIO;
7227 goto err_eeprom;
7228 }
7229
7230 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7231 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7232
7233 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7234 e_dev_err("invalid MAC address\n");
7235 err = -EIO;
7236 goto err_eeprom;
7237 }
7238
7239 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7240 if (hw->mac.ops.disable_tx_laser &&
7241 ((hw->phy.multispeed_fiber) ||
7242 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7243 (hw->mac.type == ixgbe_mac_82599EB))))
7244 hw->mac.ops.disable_tx_laser(hw);
7245
7246 init_timer(&adapter->watchdog_timer);
7247 adapter->watchdog_timer.function = ixgbe_watchdog;
7248 adapter->watchdog_timer.data = (unsigned long)adapter;
7249
7250 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7251 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7252
7253 err = ixgbe_init_interrupt_scheme(adapter);
7254 if (err)
7255 goto err_sw_init;
7256
7257 switch (pdev->device) {
7258 case IXGBE_DEV_ID_82599_SFP:
7259 /* Only this subdevice supports WOL */
7260 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7261 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7262 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7263 break;
7264 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7265 /* All except this subdevice support WOL */
7266 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7267 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7268 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7269 break;
7270 case IXGBE_DEV_ID_82599_KX4:
7271 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7272 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7273 break;
7274 default:
7275 adapter->wol = 0;
7276 break;
7277 }
7278 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7279
7280 /* pick up the PCI bus settings for reporting later */
7281 hw->mac.ops.get_bus_info(hw);
7282
7283 /* print bus type/speed/width info */
7284 e_dev_info("(PCI Express:%s:%s) %pM\n",
7285 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7286 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7287 "Unknown"),
7288 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7289 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7290 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7291 "Unknown"),
7292 netdev->dev_addr);
7293
7294 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7295 if (err)
7296 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7297 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7298 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7299 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7300 part_str);
7301 else
7302 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7303 hw->mac.type, hw->phy.type, part_str);
7304
7305 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7306 e_dev_warn("PCI-Express bandwidth available for this card is "
7307 "not sufficient for optimal performance.\n");
7308 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7309 "is required.\n");
7310 }
7311
7312 /* save off EEPROM version number */
7313 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7314
7315 /* reset the hardware with the new settings */
7316 err = hw->mac.ops.start_hw(hw);
7317
7318 if (err == IXGBE_ERR_EEPROM_VERSION) {
7319 /* We are running on a pre-production device, log a warning */
7320 e_dev_warn("This device is a pre-production adapter/LOM. "
7321 "Please be aware there may be issues associated "
7322 "with your hardware. If you are experiencing "
7323 "problems please contact your Intel or hardware "
7324 "representative who provided you with this "
7325 "hardware.\n");
7326 }
7327 strcpy(netdev->name, "eth%d");
7328 err = register_netdev(netdev);
7329 if (err)
7330 goto err_register;
7331
7332 /* carrier off reporting is important to ethtool even BEFORE open */
7333 netif_carrier_off(netdev);
7334
7335 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7336 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7337 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7338
7339 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7340 INIT_WORK(&adapter->check_overtemp_task,
7341 ixgbe_check_overtemp_task);
7342 #ifdef CONFIG_IXGBE_DCA
7343 if (dca_add_requester(&pdev->dev) == 0) {
7344 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7345 ixgbe_setup_dca(adapter);
7346 }
7347 #endif
7348 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7349 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7350 for (i = 0; i < adapter->num_vfs; i++)
7351 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7352 }
7353
7354 /* add san mac addr to netdev */
7355 ixgbe_add_sanmac_netdev(netdev);
7356
7357 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7358 cards_found++;
7359 return 0;
7360
7361 err_register:
7362 ixgbe_release_hw_control(adapter);
7363 ixgbe_clear_interrupt_scheme(adapter);
7364 err_sw_init:
7365 err_eeprom:
7366 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7367 ixgbe_disable_sriov(adapter);
7368 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7369 del_timer_sync(&adapter->sfp_timer);
7370 cancel_work_sync(&adapter->sfp_task);
7371 cancel_work_sync(&adapter->multispeed_fiber_task);
7372 cancel_work_sync(&adapter->sfp_config_module_task);
7373 iounmap(hw->hw_addr);
7374 err_ioremap:
7375 free_netdev(netdev);
7376 err_alloc_etherdev:
7377 pci_release_selected_regions(pdev,
7378 pci_select_bars(pdev, IORESOURCE_MEM));
7379 err_pci_reg:
7380 err_dma:
7381 pci_disable_device(pdev);
7382 return err;
7383 }
7384
7385 /**
7386 * ixgbe_remove - Device Removal Routine
7387 * @pdev: PCI device information struct
7388 *
7389 * ixgbe_remove is called by the PCI subsystem to alert the driver
7390 * that it should release a PCI device. The could be caused by a
7391 * Hot-Plug event, or because the driver is going to be removed from
7392 * memory.
7393 **/
7394 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7395 {
7396 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7397 struct net_device *netdev = adapter->netdev;
7398
7399 set_bit(__IXGBE_DOWN, &adapter->state);
7400
7401 /*
7402 * The timers may be rescheduled, so explicitly disable them
7403 * from being rescheduled.
7404 */
7405 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7406 del_timer_sync(&adapter->watchdog_timer);
7407 del_timer_sync(&adapter->sfp_timer);
7408
7409 cancel_work_sync(&adapter->watchdog_task);
7410 cancel_work_sync(&adapter->sfp_task);
7411 cancel_work_sync(&adapter->multispeed_fiber_task);
7412 cancel_work_sync(&adapter->sfp_config_module_task);
7413 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7414 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7415 cancel_work_sync(&adapter->fdir_reinit_task);
7416 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7417 cancel_work_sync(&adapter->check_overtemp_task);
7418
7419 #ifdef CONFIG_IXGBE_DCA
7420 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7421 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7422 dca_remove_requester(&pdev->dev);
7423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7424 }
7425
7426 #endif
7427 #ifdef IXGBE_FCOE
7428 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7429 ixgbe_cleanup_fcoe(adapter);
7430
7431 #endif /* IXGBE_FCOE */
7432
7433 /* remove the added san mac */
7434 ixgbe_del_sanmac_netdev(netdev);
7435
7436 if (netdev->reg_state == NETREG_REGISTERED)
7437 unregister_netdev(netdev);
7438
7439 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7440 ixgbe_disable_sriov(adapter);
7441
7442 ixgbe_clear_interrupt_scheme(adapter);
7443
7444 ixgbe_release_hw_control(adapter);
7445
7446 iounmap(adapter->hw.hw_addr);
7447 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7448 IORESOURCE_MEM));
7449
7450 e_dev_info("complete\n");
7451
7452 free_netdev(netdev);
7453
7454 pci_disable_pcie_error_reporting(pdev);
7455
7456 pci_disable_device(pdev);
7457 }
7458
7459 /**
7460 * ixgbe_io_error_detected - called when PCI error is detected
7461 * @pdev: Pointer to PCI device
7462 * @state: The current pci connection state
7463 *
7464 * This function is called after a PCI bus error affecting
7465 * this device has been detected.
7466 */
7467 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7468 pci_channel_state_t state)
7469 {
7470 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7471 struct net_device *netdev = adapter->netdev;
7472
7473 netif_device_detach(netdev);
7474
7475 if (state == pci_channel_io_perm_failure)
7476 return PCI_ERS_RESULT_DISCONNECT;
7477
7478 if (netif_running(netdev))
7479 ixgbe_down(adapter);
7480 pci_disable_device(pdev);
7481
7482 /* Request a slot reset. */
7483 return PCI_ERS_RESULT_NEED_RESET;
7484 }
7485
7486 /**
7487 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7488 * @pdev: Pointer to PCI device
7489 *
7490 * Restart the card from scratch, as if from a cold-boot.
7491 */
7492 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7493 {
7494 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7495 pci_ers_result_t result;
7496 int err;
7497
7498 if (pci_enable_device_mem(pdev)) {
7499 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7500 result = PCI_ERS_RESULT_DISCONNECT;
7501 } else {
7502 pci_set_master(pdev);
7503 pci_restore_state(pdev);
7504 pci_save_state(pdev);
7505
7506 pci_wake_from_d3(pdev, false);
7507
7508 ixgbe_reset(adapter);
7509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7510 result = PCI_ERS_RESULT_RECOVERED;
7511 }
7512
7513 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7514 if (err) {
7515 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7516 "failed 0x%0x\n", err);
7517 /* non-fatal, continue */
7518 }
7519
7520 return result;
7521 }
7522
7523 /**
7524 * ixgbe_io_resume - called when traffic can start flowing again.
7525 * @pdev: Pointer to PCI device
7526 *
7527 * This callback is called when the error recovery driver tells us that
7528 * its OK to resume normal operation.
7529 */
7530 static void ixgbe_io_resume(struct pci_dev *pdev)
7531 {
7532 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7533 struct net_device *netdev = adapter->netdev;
7534
7535 if (netif_running(netdev)) {
7536 if (ixgbe_up(adapter)) {
7537 e_info(probe, "ixgbe_up failed after reset\n");
7538 return;
7539 }
7540 }
7541
7542 netif_device_attach(netdev);
7543 }
7544
7545 static struct pci_error_handlers ixgbe_err_handler = {
7546 .error_detected = ixgbe_io_error_detected,
7547 .slot_reset = ixgbe_io_slot_reset,
7548 .resume = ixgbe_io_resume,
7549 };
7550
7551 static struct pci_driver ixgbe_driver = {
7552 .name = ixgbe_driver_name,
7553 .id_table = ixgbe_pci_tbl,
7554 .probe = ixgbe_probe,
7555 .remove = __devexit_p(ixgbe_remove),
7556 #ifdef CONFIG_PM
7557 .suspend = ixgbe_suspend,
7558 .resume = ixgbe_resume,
7559 #endif
7560 .shutdown = ixgbe_shutdown,
7561 .err_handler = &ixgbe_err_handler
7562 };
7563
7564 /**
7565 * ixgbe_init_module - Driver Registration Routine
7566 *
7567 * ixgbe_init_module is the first routine called when the driver is
7568 * loaded. All it does is register with the PCI subsystem.
7569 **/
7570 static int __init ixgbe_init_module(void)
7571 {
7572 int ret;
7573 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7574 pr_info("%s\n", ixgbe_copyright);
7575
7576 #ifdef CONFIG_IXGBE_DCA
7577 dca_register_notify(&dca_notifier);
7578 #endif
7579
7580 ret = pci_register_driver(&ixgbe_driver);
7581 return ret;
7582 }
7583
7584 module_init(ixgbe_init_module);
7585
7586 /**
7587 * ixgbe_exit_module - Driver Exit Cleanup Routine
7588 *
7589 * ixgbe_exit_module is called just before the driver is removed
7590 * from memory.
7591 **/
7592 static void __exit ixgbe_exit_module(void)
7593 {
7594 #ifdef CONFIG_IXGBE_DCA
7595 dca_unregister_notify(&dca_notifier);
7596 #endif
7597 pci_unregister_driver(&ixgbe_driver);
7598 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7599 }
7600
7601 #ifdef CONFIG_IXGBE_DCA
7602 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7603 void *p)
7604 {
7605 int ret_val;
7606
7607 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7608 __ixgbe_notify_dca);
7609
7610 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7611 }
7612
7613 #endif /* CONFIG_IXGBE_DCA */
7614
7615 /**
7616 * ixgbe_get_hw_dev return device
7617 * used by hardware layer to print debugging information
7618 **/
7619 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7620 {
7621 struct ixgbe_adapter *adapter = hw->back;
7622 return adapter->netdev;
7623 }
7624
7625 module_exit(ixgbe_exit_module);
7626
7627 /* ixgbe_main.c */
Linus' kernel tree