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ARM: 6621/1: bitops: remove condition code clobber for CLZ
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
blobbfd3c227cd4aefe14be928ee4df953612b4d5c10
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
64
65 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
66 {
67 struct ixgbe_mac_info *mac = &hw->mac;
68
69 /* enable the laser control functions for SFP+ fiber */
70 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
71 mac->ops.disable_tx_laser =
72 &ixgbe_disable_tx_laser_multispeed_fiber;
73 mac->ops.enable_tx_laser =
74 &ixgbe_enable_tx_laser_multispeed_fiber;
75 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
76 } else {
77 mac->ops.disable_tx_laser = NULL;
78 mac->ops.enable_tx_laser = NULL;
79 mac->ops.flap_tx_laser = NULL;
80 }
81
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
85 } else {
86 if ((mac->ops.get_media_type(hw) ==
87 ixgbe_media_type_backplane) &&
88 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
89 hw->phy.smart_speed == ixgbe_smart_speed_on))
90 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
91 else
92 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
93 }
94 }
95
96 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98 s32 ret_val = 0;
99 u32 reg_anlp1 = 0;
100 u32 i = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
105
106 hw->phy.ops.reset = NULL;
107
108 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
109 &data_offset);
110
111 if (ret_val != 0)
112 goto setup_sfp_out;
113
114 /* PHY config will finish before releasing the semaphore */
115 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
116 if (ret_val != 0) {
117 ret_val = IXGBE_ERR_SWFW_SYNC;
118 goto setup_sfp_out;
119 }
120
121 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
122 while (data_value != 0xffff) {
123 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
124 IXGBE_WRITE_FLUSH(hw);
125 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
126 }
127
128 /* Release the semaphore */
129 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
130 /* Delay obtaining semaphore again to allow FW access */
131 msleep(hw->eeprom.semaphore_delay);
132
133 /* Now restart DSP by setting Restart_AN and clearing LMS */
134 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
135 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
136 IXGBE_AUTOC_AN_RESTART));
137
138 /* Wait for AN to leave state 0 */
139 for (i = 0; i < 10; i++) {
140 msleep(4);
141 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
142 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
143 break;
144 }
145 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
146 hw_dbg(hw, "sfp module setup not complete\n");
147 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
148 goto setup_sfp_out;
149 }
150
151 /* Restart DSP by setting Restart_AN and return to SFI mode */
152 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
153 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
154 IXGBE_AUTOC_AN_RESTART));
155 }
156
157 setup_sfp_out:
158 return ret_val;
159 }
160
161 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
162 {
163 struct ixgbe_mac_info *mac = &hw->mac;
164
165 ixgbe_init_mac_link_ops_82599(hw);
166
167 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
168 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
169 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
170 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
171 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
172 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
173
174 return 0;
175 }
176
177 /**
178 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
179 * @hw: pointer to hardware structure
180 *
181 * Initialize any function pointers that were not able to be
182 * set during get_invariants because the PHY/SFP type was
183 * not known. Perform the SFP init if necessary.
184 *
185 **/
186 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
187 {
188 struct ixgbe_mac_info *mac = &hw->mac;
189 struct ixgbe_phy_info *phy = &hw->phy;
190 s32 ret_val = 0;
191
192 /* Identify the PHY or SFP module */
193 ret_val = phy->ops.identify(hw);
194
195 /* Setup function pointers based on detected SFP module and speeds */
196 ixgbe_init_mac_link_ops_82599(hw);
197
198 /* If copper media, overwrite with copper function pointers */
199 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
200 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
201 mac->ops.get_link_capabilities =
202 &ixgbe_get_copper_link_capabilities_generic;
203 }
204
205 /* Set necessary function pointers based on phy type */
206 switch (hw->phy.type) {
207 case ixgbe_phy_tn:
208 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
209 phy->ops.get_firmware_version =
210 &ixgbe_get_phy_firmware_version_tnx;
211 break;
212 case ixgbe_phy_aq:
213 phy->ops.get_firmware_version =
214 &ixgbe_get_phy_firmware_version_generic;
215 break;
216 default:
217 break;
218 }
219
220 return ret_val;
221 }
222
223 /**
224 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
225 * @hw: pointer to hardware structure
226 * @speed: pointer to link speed
227 * @negotiation: true when autoneg or autotry is enabled
228 *
229 * Determines the link capabilities by reading the AUTOC register.
230 **/
231 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
232 ixgbe_link_speed *speed,
233 bool *negotiation)
234 {
235 s32 status = 0;
236 u32 autoc = 0;
237
238 /* Determine 1G link capabilities off of SFP+ type */
239 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
240 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
242 *negotiation = true;
243 goto out;
244 }
245
246 /*
247 * Determine link capabilities based on the stored value of AUTOC,
248 * which represents EEPROM defaults. If AUTOC value has not been
249 * stored, use the current register value.
250 */
251 if (hw->mac.orig_link_settings_stored)
252 autoc = hw->mac.orig_autoc;
253 else
254 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
255
256 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
257 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
258 *speed = IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = false;
260 break;
261
262 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
263 *speed = IXGBE_LINK_SPEED_10GB_FULL;
264 *negotiation = false;
265 break;
266
267 case IXGBE_AUTOC_LMS_1G_AN:
268 *speed = IXGBE_LINK_SPEED_1GB_FULL;
269 *negotiation = true;
270 break;
271
272 case IXGBE_AUTOC_LMS_10G_SERIAL:
273 *speed = IXGBE_LINK_SPEED_10GB_FULL;
274 *negotiation = false;
275 break;
276
277 case IXGBE_AUTOC_LMS_KX4_KX_KR:
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
279 *speed = IXGBE_LINK_SPEED_UNKNOWN;
280 if (autoc & IXGBE_AUTOC_KR_SUPP)
281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
284 if (autoc & IXGBE_AUTOC_KX_SUPP)
285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 break;
288
289 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
290 *speed = IXGBE_LINK_SPEED_100_FULL;
291 if (autoc & IXGBE_AUTOC_KR_SUPP)
292 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
293 if (autoc & IXGBE_AUTOC_KX4_SUPP)
294 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
295 if (autoc & IXGBE_AUTOC_KX_SUPP)
296 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
297 *negotiation = true;
298 break;
299
300 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
301 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
302 *negotiation = false;
303 break;
304
305 default:
306 status = IXGBE_ERR_LINK_SETUP;
307 goto out;
308 break;
309 }
310
311 if (hw->phy.multispeed_fiber) {
312 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
313 IXGBE_LINK_SPEED_1GB_FULL;
314 *negotiation = true;
315 }
316
317 out:
318 return status;
319 }
320
321 /**
322 * ixgbe_get_media_type_82599 - Get media type
323 * @hw: pointer to hardware structure
324 *
325 * Returns the media type (fiber, copper, backplane)
326 **/
327 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
328 {
329 enum ixgbe_media_type media_type;
330
331 /* Detect if there is a copper PHY attached. */
332 if (hw->phy.type == ixgbe_phy_cu_unknown ||
333 hw->phy.type == ixgbe_phy_tn ||
334 hw->phy.type == ixgbe_phy_aq) {
335 media_type = ixgbe_media_type_copper;
336 goto out;
337 }
338
339 switch (hw->device_id) {
340 case IXGBE_DEV_ID_82599_KX4:
341 case IXGBE_DEV_ID_82599_KX4_MEZZ:
342 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
343 case IXGBE_DEV_ID_82599_KR:
344 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
345 case IXGBE_DEV_ID_82599_XAUI_LOM:
346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
350 case IXGBE_DEV_ID_82599_SFP_FCOE:
351 case IXGBE_DEV_ID_82599_SFP_EM:
352 media_type = ixgbe_media_type_fiber;
353 break;
354 case IXGBE_DEV_ID_82599_CX4:
355 media_type = ixgbe_media_type_cx4;
356 break;
357 default:
358 media_type = ixgbe_media_type_unknown;
359 break;
360 }
361 out:
362 return media_type;
363 }
364
365 /**
366 * ixgbe_start_mac_link_82599 - Setup MAC link settings
367 * @hw: pointer to hardware structure
368 * @autoneg_wait_to_complete: true when waiting for completion is needed
369 *
370 * Configures link settings based on values in the ixgbe_hw struct.
371 * Restarts the link. Performs autonegotiation if needed.
372 **/
373 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
374 bool autoneg_wait_to_complete)
375 {
376 u32 autoc_reg;
377 u32 links_reg;
378 u32 i;
379 s32 status = 0;
380
381 /* Restart link */
382 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
383 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
384 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
385
386 /* Only poll for autoneg to complete if specified to do so */
387 if (autoneg_wait_to_complete) {
388 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
389 IXGBE_AUTOC_LMS_KX4_KX_KR ||
390 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
391 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
392 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
393 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
394 links_reg = 0; /* Just in case Autoneg time = 0 */
395 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
396 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
397 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
398 break;
399 msleep(100);
400 }
401 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
402 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
403 hw_dbg(hw, "Autoneg did not complete.\n");
404 }
405 }
406 }
407
408 /* Add delay to filter out noises during initial link setup */
409 msleep(50);
410
411 return status;
412 }
413
414 /**
415 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
416 * @hw: pointer to hardware structure
417 *
418 * The base drivers may require better control over SFP+ module
419 * PHY states. This includes selectively shutting down the Tx
420 * laser on the PHY, effectively halting physical link.
421 **/
422 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
423 {
424 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
425
426 /* Disable tx laser; allow 100us to go dark per spec */
427 esdp_reg |= IXGBE_ESDP_SDP3;
428 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
429 IXGBE_WRITE_FLUSH(hw);
430 udelay(100);
431 }
432
433 /**
434 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
435 * @hw: pointer to hardware structure
436 *
437 * The base drivers may require better control over SFP+ module
438 * PHY states. This includes selectively turning on the Tx
439 * laser on the PHY, effectively starting physical link.
440 **/
441 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
442 {
443 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
444
445 /* Enable tx laser; allow 100ms to light up */
446 esdp_reg &= ~IXGBE_ESDP_SDP3;
447 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
448 IXGBE_WRITE_FLUSH(hw);
449 msleep(100);
450 }
451
452 /**
453 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
454 * @hw: pointer to hardware structure
455 *
456 * When the driver changes the link speeds that it can support,
457 * it sets autotry_restart to true to indicate that we need to
458 * initiate a new autotry session with the link partner. To do
459 * so, we set the speed then disable and re-enable the tx laser, to
460 * alert the link partner that it also needs to restart autotry on its
461 * end. This is consistent with true clause 37 autoneg, which also
462 * involves a loss of signal.
463 **/
464 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
465 {
466 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
467
468 if (hw->mac.autotry_restart) {
469 ixgbe_disable_tx_laser_multispeed_fiber(hw);
470 ixgbe_enable_tx_laser_multispeed_fiber(hw);
471 hw->mac.autotry_restart = false;
472 }
473 }
474
475 /**
476 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
477 * @hw: pointer to hardware structure
478 * @speed: new link speed
479 * @autoneg: true if autonegotiation enabled
480 * @autoneg_wait_to_complete: true when waiting for completion is needed
481 *
482 * Set the link speed in the AUTOC register and restarts link.
483 **/
484 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
485 ixgbe_link_speed speed,
486 bool autoneg,
487 bool autoneg_wait_to_complete)
488 {
489 s32 status = 0;
490 ixgbe_link_speed phy_link_speed;
491 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
492 u32 speedcnt = 0;
493 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
494 bool link_up = false;
495 bool negotiation;
496 int i;
497
498 /* Mask off requested but non-supported speeds */
499 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
500 speed &= phy_link_speed;
501
502 /*
503 * Try each speed one by one, highest priority first. We do this in
504 * software because 10gb fiber doesn't support speed autonegotiation.
505 */
506 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
507 speedcnt++;
508 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
509
510 /* If we already have link at this speed, just jump out */
511 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
512
513 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
514 goto out;
515
516 /* Set the module link speed */
517 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
518 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
519 IXGBE_WRITE_FLUSH(hw);
520
521 /* Allow module to change analog characteristics (1G->10G) */
522 msleep(40);
523
524 status = ixgbe_setup_mac_link_82599(hw,
525 IXGBE_LINK_SPEED_10GB_FULL,
526 autoneg,
527 autoneg_wait_to_complete);
528 if (status != 0)
529 return status;
530
531 /* Flap the tx laser if it has not already been done */
532 hw->mac.ops.flap_tx_laser(hw);
533
534 /*
535 * Wait for the controller to acquire link. Per IEEE 802.3ap,
536 * Section 73.10.2, we may have to wait up to 500ms if KR is
537 * attempted. 82599 uses the same timing for 10g SFI.
538 */
539
540 for (i = 0; i < 5; i++) {
541 /* Wait for the link partner to also set speed */
542 msleep(100);
543
544 /* If we have link, just jump out */
545 hw->mac.ops.check_link(hw, &phy_link_speed,
546 &link_up, false);
547 if (link_up)
548 goto out;
549 }
550 }
551
552 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
553 speedcnt++;
554 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
555 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
556
557 /* If we already have link at this speed, just jump out */
558 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
559
560 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
561 goto out;
562
563 /* Set the module link speed */
564 esdp_reg &= ~IXGBE_ESDP_SDP5;
565 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
567 IXGBE_WRITE_FLUSH(hw);
568
569 /* Allow module to change analog characteristics (10G->1G) */
570 msleep(40);
571
572 status = ixgbe_setup_mac_link_82599(hw,
573 IXGBE_LINK_SPEED_1GB_FULL,
574 autoneg,
575 autoneg_wait_to_complete);
576 if (status != 0)
577 return status;
578
579 /* Flap the tx laser if it has not already been done */
580 hw->mac.ops.flap_tx_laser(hw);
581
582 /* Wait for the link partner to also set speed */
583 msleep(100);
584
585 /* If we have link, just jump out */
586 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
587 if (link_up)
588 goto out;
589 }
590
591 /*
592 * We didn't get link. Configure back to the highest speed we tried,
593 * (if there was more than one). We call ourselves back with just the
594 * single highest speed that the user requested.
595 */
596 if (speedcnt > 1)
597 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
598 highest_link_speed,
599 autoneg,
600 autoneg_wait_to_complete);
601
602 out:
603 /* Set autoneg_advertised value based on input link speed */
604 hw->phy.autoneg_advertised = 0;
605
606 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
607 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
608
609 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
610 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
611
612 return status;
613 }
614
615 /**
616 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
617 * @hw: pointer to hardware structure
618 * @speed: new link speed
619 * @autoneg: true if autonegotiation enabled
620 * @autoneg_wait_to_complete: true when waiting for completion is needed
621 *
622 * Implements the Intel SmartSpeed algorithm.
623 **/
624 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
625 ixgbe_link_speed speed, bool autoneg,
626 bool autoneg_wait_to_complete)
627 {
628 s32 status = 0;
629 ixgbe_link_speed link_speed;
630 s32 i, j;
631 bool link_up = false;
632 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
633 struct ixgbe_adapter *adapter = hw->back;
634
635 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
636
637 /* Set autoneg_advertised value based on input link speed */
638 hw->phy.autoneg_advertised = 0;
639
640 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
641 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
642
643 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
644 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
645
646 if (speed & IXGBE_LINK_SPEED_100_FULL)
647 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
648
649 /*
650 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
651 * autoneg advertisement if link is unable to be established at the
652 * highest negotiated rate. This can sometimes happen due to integrity
653 * issues with the physical media connection.
654 */
655
656 /* First, try to get link with full advertisement */
657 hw->phy.smart_speed_active = false;
658 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
659 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
660 autoneg_wait_to_complete);
661 if (status)
662 goto out;
663
664 /*
665 * Wait for the controller to acquire link. Per IEEE 802.3ap,
666 * Section 73.10.2, we may have to wait up to 500ms if KR is
667 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
668 * Table 9 in the AN MAS.
669 */
670 for (i = 0; i < 5; i++) {
671 mdelay(100);
672
673 /* If we have link, just jump out */
674 hw->mac.ops.check_link(hw, &link_speed,
675 &link_up, false);
676 if (link_up)
677 goto out;
678 }
679 }
680
681 /*
682 * We didn't get link. If we advertised KR plus one of KX4/KX
683 * (or BX4/BX), then disable KR and try again.
684 */
685 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
686 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
687 goto out;
688
689 /* Turn SmartSpeed on to disable KR support */
690 hw->phy.smart_speed_active = true;
691 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
692 autoneg_wait_to_complete);
693 if (status)
694 goto out;
695
696 /*
697 * Wait for the controller to acquire link. 600ms will allow for
698 * the AN link_fail_inhibit_timer as well for multiple cycles of
699 * parallel detect, both 10g and 1g. This allows for the maximum
700 * connect attempts as defined in the AN MAS table 73-7.
701 */
702 for (i = 0; i < 6; i++) {
703 mdelay(100);
704
705 /* If we have link, just jump out */
706 hw->mac.ops.check_link(hw, &link_speed,
707 &link_up, false);
708 if (link_up)
709 goto out;
710 }
711
712 /* We didn't get link. Turn SmartSpeed back off. */
713 hw->phy.smart_speed_active = false;
714 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
715 autoneg_wait_to_complete);
716
717 out:
718 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
719 e_info(hw, "Smartspeed has downgraded the link speed from "
720 "the maximum advertised\n");
721 return status;
722 }
723
724 /**
725 * ixgbe_setup_mac_link_82599 - Set MAC link speed
726 * @hw: pointer to hardware structure
727 * @speed: new link speed
728 * @autoneg: true if autonegotiation enabled
729 * @autoneg_wait_to_complete: true when waiting for completion is needed
730 *
731 * Set the link speed in the AUTOC register and restarts link.
732 **/
733 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
734 ixgbe_link_speed speed, bool autoneg,
735 bool autoneg_wait_to_complete)
736 {
737 s32 status = 0;
738 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
739 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
740 u32 start_autoc = autoc;
741 u32 orig_autoc = 0;
742 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
743 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
744 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
745 u32 links_reg;
746 u32 i;
747 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
748
749 /* Check to see if speed passed in is supported. */
750 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
751 speed &= link_capabilities;
752
753 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
754 status = IXGBE_ERR_LINK_SETUP;
755 goto out;
756 }
757
758 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
759 if (hw->mac.orig_link_settings_stored)
760 orig_autoc = hw->mac.orig_autoc;
761 else
762 orig_autoc = autoc;
763
764
765 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
767 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
768 /* Set KX4/KX/KR support according to speed requested */
769 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
770 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
771 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
772 autoc |= IXGBE_AUTOC_KX4_SUPP;
773 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
774 (hw->phy.smart_speed_active == false))
775 autoc |= IXGBE_AUTOC_KR_SUPP;
776 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
777 autoc |= IXGBE_AUTOC_KX_SUPP;
778 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
779 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
780 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
781 /* Switch from 1G SFI to 10G SFI if requested */
782 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
783 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
784 autoc &= ~IXGBE_AUTOC_LMS_MASK;
785 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
786 }
787 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
788 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
789 /* Switch from 10G SFI to 1G SFI if requested */
790 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
791 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
792 autoc &= ~IXGBE_AUTOC_LMS_MASK;
793 if (autoneg)
794 autoc |= IXGBE_AUTOC_LMS_1G_AN;
795 else
796 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
797 }
798 }
799
800 if (autoc != start_autoc) {
801 /* Restart link */
802 autoc |= IXGBE_AUTOC_AN_RESTART;
803 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
804
805 /* Only poll for autoneg to complete if specified to do so */
806 if (autoneg_wait_to_complete) {
807 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
808 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
809 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
810 links_reg = 0; /*Just in case Autoneg time=0*/
811 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
812 links_reg =
813 IXGBE_READ_REG(hw, IXGBE_LINKS);
814 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
815 break;
816 msleep(100);
817 }
818 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
819 status =
820 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
821 hw_dbg(hw, "Autoneg did not "
822 "complete.\n");
823 }
824 }
825 }
826
827 /* Add delay to filter out noises during initial link setup */
828 msleep(50);
829 }
830
831 out:
832 return status;
833 }
834
835 /**
836 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
837 * @hw: pointer to hardware structure
838 * @speed: new link speed
839 * @autoneg: true if autonegotiation enabled
840 * @autoneg_wait_to_complete: true if waiting is needed to complete
841 *
842 * Restarts link on PHY and MAC based on settings passed in.
843 **/
844 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
845 ixgbe_link_speed speed,
846 bool autoneg,
847 bool autoneg_wait_to_complete)
848 {
849 s32 status;
850
851 /* Setup the PHY according to input speed */
852 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
853 autoneg_wait_to_complete);
854 /* Set up MAC */
855 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
856
857 return status;
858 }
859
860 /**
861 * ixgbe_reset_hw_82599 - Perform hardware reset
862 * @hw: pointer to hardware structure
863 *
864 * Resets the hardware by resetting the transmit and receive units, masks
865 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
866 * reset.
867 **/
868 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
869 {
870 s32 status = 0;
871 u32 ctrl;
872 u32 i;
873 u32 autoc;
874 u32 autoc2;
875
876 /* Call adapter stop to disable tx/rx and clear interrupts */
877 hw->mac.ops.stop_adapter(hw);
878
879 /* PHY ops must be identified and initialized prior to reset */
880
881 /* Init PHY and function pointers, perform SFP setup */
882 status = hw->phy.ops.init(hw);
883
884 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
885 goto reset_hw_out;
886
887 /* Setup SFP module if there is one present. */
888 if (hw->phy.sfp_setup_needed) {
889 status = hw->mac.ops.setup_sfp(hw);
890 hw->phy.sfp_setup_needed = false;
891 }
892
893 /* Reset PHY */
894 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
895 hw->phy.ops.reset(hw);
896
897 /*
898 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
899 * access and verify no pending requests before reset
900 */
901 status = ixgbe_disable_pcie_master(hw);
902 if (status != 0) {
903 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
904 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
905 }
906
907 /*
908 * Issue global reset to the MAC. This needs to be a SW reset.
909 * If link reset is used, it might reset the MAC when mng is using it
910 */
911 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
912 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
913 IXGBE_WRITE_FLUSH(hw);
914
915 /* Poll for reset bit to self-clear indicating reset is complete */
916 for (i = 0; i < 10; i++) {
917 udelay(1);
918 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
919 if (!(ctrl & IXGBE_CTRL_RST))
920 break;
921 }
922 if (ctrl & IXGBE_CTRL_RST) {
923 status = IXGBE_ERR_RESET_FAILED;
924 hw_dbg(hw, "Reset polling failed to complete.\n");
925 }
926
927 msleep(50);
928
929 /*
930 * Store the original AUTOC/AUTOC2 values if they have not been
931 * stored off yet. Otherwise restore the stored original
932 * values since the reset operation sets back to defaults.
933 */
934 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
935 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
936 if (hw->mac.orig_link_settings_stored == false) {
937 hw->mac.orig_autoc = autoc;
938 hw->mac.orig_autoc2 = autoc2;
939 hw->mac.orig_link_settings_stored = true;
940 } else {
941 if (autoc != hw->mac.orig_autoc)
942 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
943 IXGBE_AUTOC_AN_RESTART));
944
945 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
946 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
947 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
948 autoc2 |= (hw->mac.orig_autoc2 &
949 IXGBE_AUTOC2_UPPER_MASK);
950 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
951 }
952 }
953
954 /*
955 * Store MAC address from RAR0, clear receive address registers, and
956 * clear the multicast table. Also reset num_rar_entries to 128,
957 * since we modify this value when programming the SAN MAC address.
958 */
959 hw->mac.num_rar_entries = 128;
960 hw->mac.ops.init_rx_addrs(hw);
961
962 /* Store the permanent mac address */
963 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
964
965 /* Store the permanent SAN mac address */
966 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
967
968 /* Add the SAN MAC address to the RAR only if it's a valid address */
969 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
970 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
971 hw->mac.san_addr, 0, IXGBE_RAH_AV);
972
973 /* Reserve the last RAR for the SAN MAC address */
974 hw->mac.num_rar_entries--;
975 }
976
977 /* Store the alternative WWNN/WWPN prefix */
978 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
979 &hw->mac.wwpn_prefix);
980
981 reset_hw_out:
982 return status;
983 }
984
985 /**
986 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
987 * @hw: pointer to hardware structure
988 **/
989 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
990 {
991 int i;
992 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
993 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
994
995 /*
996 * Before starting reinitialization process,
997 * FDIRCMD.CMD must be zero.
998 */
999 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1000 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1001 IXGBE_FDIRCMD_CMD_MASK))
1002 break;
1003 udelay(10);
1004 }
1005 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1006 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1007 "aborting table re-initialization.\n");
1008 return IXGBE_ERR_FDIR_REINIT_FAILED;
1009 }
1010
1011 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1012 IXGBE_WRITE_FLUSH(hw);
1013 /*
1014 * 82599 adapters flow director init flow cannot be restarted,
1015 * Workaround 82599 silicon errata by performing the following steps
1016 * before re-writing the FDIRCTRL control register with the same value.
1017 * - write 1 to bit 8 of FDIRCMD register &
1018 * - write 0 to bit 8 of FDIRCMD register
1019 */
1020 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1021 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1022 IXGBE_FDIRCMD_CLEARHT));
1023 IXGBE_WRITE_FLUSH(hw);
1024 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1025 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1026 ~IXGBE_FDIRCMD_CLEARHT));
1027 IXGBE_WRITE_FLUSH(hw);
1028 /*
1029 * Clear FDIR Hash register to clear any leftover hashes
1030 * waiting to be programmed.
1031 */
1032 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1033 IXGBE_WRITE_FLUSH(hw);
1034
1035 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1036 IXGBE_WRITE_FLUSH(hw);
1037
1038 /* Poll init-done after we write FDIRCTRL register */
1039 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1040 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1041 IXGBE_FDIRCTRL_INIT_DONE)
1042 break;
1043 udelay(10);
1044 }
1045 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1046 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1047 return IXGBE_ERR_FDIR_REINIT_FAILED;
1048 }
1049
1050 /* Clear FDIR statistics registers (read to clear) */
1051 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1052 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1053 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1054 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1055 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1056
1057 return 0;
1058 }
1059
1060 /**
1061 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1062 * @hw: pointer to hardware structure
1063 * @pballoc: which mode to allocate filters with
1064 **/
1065 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1066 {
1067 u32 fdirctrl = 0;
1068 u32 pbsize;
1069 int i;
1070
1071 /*
1072 * Before enabling Flow Director, the Rx Packet Buffer size
1073 * must be reduced. The new value is the current size minus
1074 * flow director memory usage size.
1075 */
1076 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1077 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1078 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1079
1080 /*
1081 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1082 * intialized to zero for non DCB mode otherwise actual total RX PB
1083 * would be bigger than programmed and filter space would run into
1084 * the PB 0 region.
1085 */
1086 for (i = 1; i < 8; i++)
1087 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1088
1089 /* Send interrupt when 64 filters are left */
1090 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1091
1092 /* Set the maximum length per hash bucket to 0xA filters */
1093 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1094
1095 switch (pballoc) {
1096 case IXGBE_FDIR_PBALLOC_64K:
1097 /* 8k - 1 signature filters */
1098 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1099 break;
1100 case IXGBE_FDIR_PBALLOC_128K:
1101 /* 16k - 1 signature filters */
1102 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1103 break;
1104 case IXGBE_FDIR_PBALLOC_256K:
1105 /* 32k - 1 signature filters */
1106 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1107 break;
1108 default:
1109 /* bad value */
1110 return IXGBE_ERR_CONFIG;
1111 };
1112
1113 /* Move the flexible bytes to use the ethertype - shift 6 words */
1114 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1115
1116 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1117
1118 /* Prime the keys for hashing */
1119 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1120 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1121 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1122 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1123
1124 /*
1125 * Poll init-done after we write the register. Estimated times:
1126 * 10G: PBALLOC = 11b, timing is 60us
1127 * 1G: PBALLOC = 11b, timing is 600us
1128 * 100M: PBALLOC = 11b, timing is 6ms
1129 *
1130 * Multiple these timings by 4 if under full Rx load
1131 *
1132 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1133 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1134 * this might not finish in our poll time, but we can live with that
1135 * for now.
1136 */
1137 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1138 IXGBE_WRITE_FLUSH(hw);
1139 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1140 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1141 IXGBE_FDIRCTRL_INIT_DONE)
1142 break;
1143 msleep(1);
1144 }
1145 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1146 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1147
1148 return 0;
1149 }
1150
1151 /**
1152 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1153 * @hw: pointer to hardware structure
1154 * @pballoc: which mode to allocate filters with
1155 **/
1156 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1157 {
1158 u32 fdirctrl = 0;
1159 u32 pbsize;
1160 int i;
1161
1162 /*
1163 * Before enabling Flow Director, the Rx Packet Buffer size
1164 * must be reduced. The new value is the current size minus
1165 * flow director memory usage size.
1166 */
1167 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1168 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1169 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1170
1171 /*
1172 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1173 * intialized to zero for non DCB mode otherwise actual total RX PB
1174 * would be bigger than programmed and filter space would run into
1175 * the PB 0 region.
1176 */
1177 for (i = 1; i < 8; i++)
1178 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1179
1180 /* Send interrupt when 64 filters are left */
1181 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1182
1183 /* Initialize the drop queue to Rx queue 127 */
1184 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1185
1186 switch (pballoc) {
1187 case IXGBE_FDIR_PBALLOC_64K:
1188 /* 2k - 1 perfect filters */
1189 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1190 break;
1191 case IXGBE_FDIR_PBALLOC_128K:
1192 /* 4k - 1 perfect filters */
1193 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1194 break;
1195 case IXGBE_FDIR_PBALLOC_256K:
1196 /* 8k - 1 perfect filters */
1197 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1198 break;
1199 default:
1200 /* bad value */
1201 return IXGBE_ERR_CONFIG;
1202 };
1203
1204 /* Turn perfect match filtering on */
1205 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1206 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1207
1208 /* Move the flexible bytes to use the ethertype - shift 6 words */
1209 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1210
1211 /* Prime the keys for hashing */
1212 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1213 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1214 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1215 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1216
1217 /*
1218 * Poll init-done after we write the register. Estimated times:
1219 * 10G: PBALLOC = 11b, timing is 60us
1220 * 1G: PBALLOC = 11b, timing is 600us
1221 * 100M: PBALLOC = 11b, timing is 6ms
1222 *
1223 * Multiple these timings by 4 if under full Rx load
1224 *
1225 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1226 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1227 * this might not finish in our poll time, but we can live with that
1228 * for now.
1229 */
1230
1231 /* Set the maximum length per hash bucket to 0xA filters */
1232 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1233
1234 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1235 IXGBE_WRITE_FLUSH(hw);
1236 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1237 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1238 IXGBE_FDIRCTRL_INIT_DONE)
1239 break;
1240 msleep(1);
1241 }
1242 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1243 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1244
1245 return 0;
1246 }
1247
1248
1249 /**
1250 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1251 * @stream: input bitstream to compute the hash on
1252 * @key: 32-bit hash key
1253 **/
1254 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1255 u32 key)
1256 {
1257 /*
1258 * The algorithm is as follows:
1259 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1260 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1261 * and A[n] x B[n] is bitwise AND between same length strings
1262 *
1263 * K[n] is 16 bits, defined as:
1264 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1265 * for n modulo 32 < 15, K[n] =
1266 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1267 *
1268 * S[n] is 16 bits, defined as:
1269 * for n >= 15, S[n] = S[n:n - 15]
1270 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1271 *
1272 * To simplify for programming, the algorithm is implemented
1273 * in software this way:
1274 *
1275 * Key[31:0], Stream[335:0]
1276 *
1277 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1278 * int_key[350:0] = tmp_key[351:1]
1279 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1280 *
1281 * hash[15:0] = 0;
1282 * for (i = 0; i < 351; i++) {
1283 * if (int_key[i])
1284 * hash ^= int_stream[(i + 15):i];
1285 * }
1286 */
1287
1288 union {
1289 u64 fill[6];
1290 u32 key[11];
1291 u8 key_stream[44];
1292 } tmp_key;
1293
1294 u8 *stream = (u8 *)atr_input;
1295 u8 int_key[44]; /* upper-most bit unused */
1296 u8 hash_str[46]; /* upper-most 2 bits unused */
1297 u16 hash_result = 0;
1298 int i, j, k, h;
1299
1300 /*
1301 * Initialize the fill member to prevent warnings
1302 * on some compilers
1303 */
1304 tmp_key.fill[0] = 0;
1305
1306 /* First load the temporary key stream */
1307 for (i = 0; i < 6; i++) {
1308 u64 fillkey = ((u64)key << 32) | key;
1309 tmp_key.fill[i] = fillkey;
1310 }
1311
1312 /*
1313 * Set the interim key for the hashing. Bit 352 is unused, so we must
1314 * shift and compensate when building the key.
1315 */
1316
1317 int_key[0] = tmp_key.key_stream[0] >> 1;
1318 for (i = 1, j = 0; i < 44; i++) {
1319 unsigned int this_key = tmp_key.key_stream[j] << 7;
1320 j++;
1321 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1322 }
1323
1324 /*
1325 * Set the interim bit string for the hashing. Bits 368 and 367 are
1326 * unused, so shift and compensate when building the string.
1327 */
1328 hash_str[0] = (stream[40] & 0x7f) >> 1;
1329 for (i = 1, j = 40; i < 46; i++) {
1330 unsigned int this_str = stream[j] << 7;
1331 j++;
1332 if (j > 41)
1333 j = 0;
1334 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1335 }
1336
1337 /*
1338 * Now compute the hash. i is the index into hash_str, j is into our
1339 * key stream, k is counting the number of bits, and h interates within
1340 * each byte.
1341 */
1342 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1343 for (h = 0; h < 8 && k < 351; h++, k++) {
1344 if (int_key[j] & (1 << h)) {
1345 /*
1346 * Key bit is set, XOR in the current 16-bit
1347 * string. Example of processing:
1348 * h = 0,
1349 * tmp = (hash_str[i - 2] & 0 << 16) |
1350 * (hash_str[i - 1] & 0xff << 8) |
1351 * (hash_str[i] & 0xff >> 0)
1352 * So tmp = hash_str[15 + k:k], since the
1353 * i + 2 clause rolls off the 16-bit value
1354 * h = 7,
1355 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1356 * (hash_str[i - 1] & 0xff << 1) |
1357 * (hash_str[i] & 0x80 >> 7)
1358 */
1359 int tmp = (hash_str[i] >> h);
1360 tmp |= (hash_str[i - 1] << (8 - h));
1361 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1362 << (16 - h);
1363 hash_result ^= (u16)tmp;
1364 }
1365 }
1366 }
1367
1368 return hash_result;
1369 }
1370
1371 /**
1372 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1373 * @input: input stream to modify
1374 * @vlan: the VLAN id to load
1375 **/
1376 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1377 {
1378 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1379 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1380
1381 return 0;
1382 }
1383
1384 /**
1385 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1386 * @input: input stream to modify
1387 * @src_addr: the IP address to load
1388 **/
1389 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1390 {
1391 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1392 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1393 (src_addr >> 16) & 0xff;
1394 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1395 (src_addr >> 8) & 0xff;
1396 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1397
1398 return 0;
1399 }
1400
1401 /**
1402 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1403 * @input: input stream to modify
1404 * @dst_addr: the IP address to load
1405 **/
1406 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1407 {
1408 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1409 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1410 (dst_addr >> 16) & 0xff;
1411 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1412 (dst_addr >> 8) & 0xff;
1413 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1414
1415 return 0;
1416 }
1417
1418 /**
1419 * ixgbe_atr_set_src_port_82599 - Sets the source port
1420 * @input: input stream to modify
1421 * @src_port: the source port to load
1422 **/
1423 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1424 {
1425 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1426 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1427
1428 return 0;
1429 }
1430
1431 /**
1432 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1433 * @input: input stream to modify
1434 * @dst_port: the destination port to load
1435 **/
1436 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1437 {
1438 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1439 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1440
1441 return 0;
1442 }
1443
1444 /**
1445 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1446 * @input: input stream to modify
1447 * @flex_bytes: the flexible bytes to load
1448 **/
1449 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1450 {
1451 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1452 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1453
1454 return 0;
1455 }
1456
1457 /**
1458 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1459 * @input: input stream to modify
1460 * @l4type: the layer 4 type value to load
1461 **/
1462 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1463 {
1464 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1465
1466 return 0;
1467 }
1468
1469 /**
1470 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1471 * @input: input stream to search
1472 * @vlan: the VLAN id to load
1473 **/
1474 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1475 {
1476 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1477 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1478
1479 return 0;
1480 }
1481
1482 /**
1483 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1484 * @input: input stream to search
1485 * @src_addr: the IP address to load
1486 **/
1487 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1488 u32 *src_addr)
1489 {
1490 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1491 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1492 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1493 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1494
1495 return 0;
1496 }
1497
1498 /**
1499 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1500 * @input: input stream to search
1501 * @dst_addr: the IP address to load
1502 **/
1503 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1504 u32 *dst_addr)
1505 {
1506 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1507 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1508 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1509 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1510
1511 return 0;
1512 }
1513
1514 /**
1515 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1516 * @input: input stream to search
1517 * @src_addr_1: the first 4 bytes of the IP address to load
1518 * @src_addr_2: the second 4 bytes of the IP address to load
1519 * @src_addr_3: the third 4 bytes of the IP address to load
1520 * @src_addr_4: the fourth 4 bytes of the IP address to load
1521 **/
1522 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1523 u32 *src_addr_1, u32 *src_addr_2,
1524 u32 *src_addr_3, u32 *src_addr_4)
1525 {
1526 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1527 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1528 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1529 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1530
1531 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1532 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1533 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1534 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1535
1536 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1537 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1538 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1539 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1540
1541 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1542 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1543 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1544 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1545
1546 return 0;
1547 }
1548
1549 /**
1550 * ixgbe_atr_get_src_port_82599 - Gets the source port
1551 * @input: input stream to modify
1552 * @src_port: the source port to load
1553 *
1554 * Even though the input is given in big-endian, the FDIRPORT registers
1555 * expect the ports to be programmed in little-endian. Hence the need to swap
1556 * endianness when retrieving the data. This can be confusing since the
1557 * internal hash engine expects it to be big-endian.
1558 **/
1559 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1560 u16 *src_port)
1561 {
1562 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1563 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1564
1565 return 0;
1566 }
1567
1568 /**
1569 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1570 * @input: input stream to modify
1571 * @dst_port: the destination port to load
1572 *
1573 * Even though the input is given in big-endian, the FDIRPORT registers
1574 * expect the ports to be programmed in little-endian. Hence the need to swap
1575 * endianness when retrieving the data. This can be confusing since the
1576 * internal hash engine expects it to be big-endian.
1577 **/
1578 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1579 u16 *dst_port)
1580 {
1581 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1582 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1583
1584 return 0;
1585 }
1586
1587 /**
1588 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1589 * @input: input stream to modify
1590 * @flex_bytes: the flexible bytes to load
1591 **/
1592 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1593 u16 *flex_byte)
1594 {
1595 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1596 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1597
1598 return 0;
1599 }
1600
1601 /**
1602 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1603 * @input: input stream to modify
1604 * @l4type: the layer 4 type value to load
1605 **/
1606 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1607 u8 *l4type)
1608 {
1609 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1610
1611 return 0;
1612 }
1613
1614 /**
1615 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1616 * @hw: pointer to hardware structure
1617 * @stream: input bitstream
1618 * @queue: queue index to direct traffic to
1619 **/
1620 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1621 struct ixgbe_atr_input *input,
1622 u8 queue)
1623 {
1624 u64 fdirhashcmd;
1625 u64 fdircmd;
1626 u32 fdirhash;
1627 u16 bucket_hash, sig_hash;
1628 u8 l4type;
1629
1630 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1631 IXGBE_ATR_BUCKET_HASH_KEY);
1632
1633 /* bucket_hash is only 15 bits */
1634 bucket_hash &= IXGBE_ATR_HASH_MASK;
1635
1636 sig_hash = ixgbe_atr_compute_hash_82599(input,
1637 IXGBE_ATR_SIGNATURE_HASH_KEY);
1638
1639 /* Get the l4type in order to program FDIRCMD properly */
1640 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1641 ixgbe_atr_get_l4type_82599(input, &l4type);
1642
1643 /*
1644 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1645 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1646 */
1647 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1648
1649 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1650 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1651
1652 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1653 case IXGBE_ATR_L4TYPE_TCP:
1654 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1655 break;
1656 case IXGBE_ATR_L4TYPE_UDP:
1657 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1658 break;
1659 case IXGBE_ATR_L4TYPE_SCTP:
1660 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1661 break;
1662 default:
1663 hw_dbg(hw, "Error on l4type input\n");
1664 return IXGBE_ERR_CONFIG;
1665 }
1666
1667 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1668 fdircmd |= IXGBE_FDIRCMD_IPV6;
1669
1670 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1671 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1672
1673 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1674
1675 return 0;
1676 }
1677
1678 /**
1679 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1680 * @hw: pointer to hardware structure
1681 * @input: input bitstream
1682 * @input_masks: bitwise masks for relevant fields
1683 * @soft_id: software index into the silicon hash tables for filter storage
1684 * @queue: queue index to direct traffic to
1685 *
1686 * Note that the caller to this function must lock before calling, since the
1687 * hardware writes must be protected from one another.
1688 **/
1689 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1690 struct ixgbe_atr_input *input,
1691 struct ixgbe_atr_input_masks *input_masks,
1692 u16 soft_id, u8 queue)
1693 {
1694 u32 fdircmd = 0;
1695 u32 fdirhash;
1696 u32 src_ipv4 = 0, dst_ipv4 = 0;
1697 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1698 u16 src_port, dst_port, vlan_id, flex_bytes;
1699 u16 bucket_hash;
1700 u8 l4type;
1701 u8 fdirm = 0;
1702
1703 /* Get our input values */
1704 ixgbe_atr_get_l4type_82599(input, &l4type);
1705
1706 /*
1707 * Check l4type formatting, and bail out before we touch the hardware
1708 * if there's a configuration issue
1709 */
1710 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1711 case IXGBE_ATR_L4TYPE_TCP:
1712 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1713 break;
1714 case IXGBE_ATR_L4TYPE_UDP:
1715 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1716 break;
1717 case IXGBE_ATR_L4TYPE_SCTP:
1718 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1719 break;
1720 default:
1721 hw_dbg(hw, "Error on l4type input\n");
1722 return IXGBE_ERR_CONFIG;
1723 }
1724
1725 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1726 IXGBE_ATR_BUCKET_HASH_KEY);
1727
1728 /* bucket_hash is only 15 bits */
1729 bucket_hash &= IXGBE_ATR_HASH_MASK;
1730
1731 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1732 ixgbe_atr_get_src_port_82599(input, &src_port);
1733 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1734 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1735
1736 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1737
1738 /* Now figure out if we're IPv4 or IPv6 */
1739 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1740 /* IPv6 */
1741 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1742 &src_ipv6_3, &src_ipv6_4);
1743
1744 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1745 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1746 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1747 /* The last 4 bytes is the same register as IPv4 */
1748 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1749
1750 fdircmd |= IXGBE_FDIRCMD_IPV6;
1751 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1752 } else {
1753 /* IPv4 */
1754 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1755 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
1756 }
1757
1758 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1759 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1760
1761 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1762 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1763 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
1764 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1765
1766 /*
1767 * Program the relevant mask registers. L4type cannot be
1768 * masked out in this implementation.
1769 *
1770 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1771 * point in time.
1772 */
1773 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1774 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1775
1776 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1777 case IXGBE_ATR_L4TYPE_TCP:
1778 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
1779 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1780 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1781 (input_masks->dst_port_mask << 16)));
1782 break;
1783 case IXGBE_ATR_L4TYPE_UDP:
1784 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
1785 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1786 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1787 (input_masks->src_port_mask << 16)));
1788 break;
1789 default:
1790 /* this already would have failed above */
1791 break;
1792 }
1793
1794 /* Program the last mask register, FDIRM */
1795 if (input_masks->vlan_id_mask)
1796 /* Mask both VLAN and VLANP - bits 0 and 1 */
1797 fdirm |= 0x3;
1798
1799 if (input_masks->data_mask)
1800 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1801 fdirm |= 0x10;
1802
1803 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1804 fdirm |= 0x24;
1805
1806 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1807
1808 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1809 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1810 fdircmd |= IXGBE_FDIRCMD_LAST;
1811 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1812 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1813
1814 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1815 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1816
1817 return 0;
1818 }
1819 /**
1820 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1821 * @hw: pointer to hardware structure
1822 * @reg: analog register to read
1823 * @val: read value
1824 *
1825 * Performs read operation to Omer analog register specified.
1826 **/
1827 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1828 {
1829 u32 core_ctl;
1830
1831 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1832 (reg << 8));
1833 IXGBE_WRITE_FLUSH(hw);
1834 udelay(10);
1835 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1836 *val = (u8)core_ctl;
1837
1838 return 0;
1839 }
1840
1841 /**
1842 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1843 * @hw: pointer to hardware structure
1844 * @reg: atlas register to write
1845 * @val: value to write
1846 *
1847 * Performs write operation to Omer analog register specified.
1848 **/
1849 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1850 {
1851 u32 core_ctl;
1852
1853 core_ctl = (reg << 8) | val;
1854 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1855 IXGBE_WRITE_FLUSH(hw);
1856 udelay(10);
1857
1858 return 0;
1859 }
1860
1861 /**
1862 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1863 * @hw: pointer to hardware structure
1864 *
1865 * Starts the hardware using the generic start_hw function.
1866 * Then performs device-specific:
1867 * Clears the rate limiter registers.
1868 **/
1869 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1870 {
1871 u32 q_num;
1872 s32 ret_val;
1873
1874 ret_val = ixgbe_start_hw_generic(hw);
1875
1876 /* Clear the rate limiters */
1877 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1878 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1879 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1880 }
1881 IXGBE_WRITE_FLUSH(hw);
1882
1883 /* We need to run link autotry after the driver loads */
1884 hw->mac.autotry_restart = true;
1885
1886 if (ret_val == 0)
1887 ret_val = ixgbe_verify_fw_version_82599(hw);
1888
1889 return ret_val;
1890 }
1891
1892 /**
1893 * ixgbe_identify_phy_82599 - Get physical layer module
1894 * @hw: pointer to hardware structure
1895 *
1896 * Determines the physical layer module found on the current adapter.
1897 **/
1898 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1899 {
1900 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1901 status = ixgbe_identify_phy_generic(hw);
1902 if (status != 0)
1903 status = ixgbe_identify_sfp_module_generic(hw);
1904 return status;
1905 }
1906
1907 /**
1908 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1909 * @hw: pointer to hardware structure
1910 *
1911 * Determines physical layer capabilities of the current configuration.
1912 **/
1913 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1914 {
1915 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1916 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1917 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1918 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1919 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1920 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1921 u16 ext_ability = 0;
1922 u8 comp_codes_10g = 0;
1923 u8 comp_codes_1g = 0;
1924
1925 hw->phy.ops.identify(hw);
1926
1927 if (hw->phy.type == ixgbe_phy_tn ||
1928 hw->phy.type == ixgbe_phy_aq ||
1929 hw->phy.type == ixgbe_phy_cu_unknown) {
1930 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1931 &ext_ability);
1932 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1933 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1934 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1935 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1936 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1937 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1938 goto out;
1939 }
1940
1941 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1942 case IXGBE_AUTOC_LMS_1G_AN:
1943 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1944 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1945 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1946 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1947 goto out;
1948 } else
1949 /* SFI mode so read SFP module */
1950 goto sfp_check;
1951 break;
1952 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1953 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1954 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1955 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1956 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1957 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1958 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1959 goto out;
1960 break;
1961 case IXGBE_AUTOC_LMS_10G_SERIAL:
1962 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1963 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1964 goto out;
1965 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1966 goto sfp_check;
1967 break;
1968 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1969 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1970 if (autoc & IXGBE_AUTOC_KX_SUPP)
1971 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1972 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1973 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1974 if (autoc & IXGBE_AUTOC_KR_SUPP)
1975 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1976 goto out;
1977 break;
1978 default:
1979 goto out;
1980 break;
1981 }
1982
1983 sfp_check:
1984 /* SFP check must be done last since DA modules are sometimes used to
1985 * test KR mode - we need to id KR mode correctly before SFP module.
1986 * Call identify_sfp because the pluggable module may have changed */
1987 hw->phy.ops.identify_sfp(hw);
1988 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1989 goto out;
1990
1991 switch (hw->phy.type) {
1992 case ixgbe_phy_sfp_passive_tyco:
1993 case ixgbe_phy_sfp_passive_unknown:
1994 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1995 break;
1996 case ixgbe_phy_sfp_ftl_active:
1997 case ixgbe_phy_sfp_active_unknown:
1998 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1999 break;
2000 case ixgbe_phy_sfp_avago:
2001 case ixgbe_phy_sfp_ftl:
2002 case ixgbe_phy_sfp_intel:
2003 case ixgbe_phy_sfp_unknown:
2004 hw->phy.ops.read_i2c_eeprom(hw,
2005 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2006 hw->phy.ops.read_i2c_eeprom(hw,
2007 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2008 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2009 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2010 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2011 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2012 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2013 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2014 break;
2015 default:
2016 break;
2017 }
2018
2019 out:
2020 return physical_layer;
2021 }
2022
2023 /**
2024 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2025 * @hw: pointer to hardware structure
2026 * @regval: register value to write to RXCTRL
2027 *
2028 * Enables the Rx DMA unit for 82599
2029 **/
2030 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2031 {
2032 #define IXGBE_MAX_SECRX_POLL 30
2033 int i;
2034 int secrxreg;
2035
2036 /*
2037 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2038 * If traffic is incoming before we enable the Rx unit, it could hang
2039 * the Rx DMA unit. Therefore, make sure the security engine is
2040 * completely disabled prior to enabling the Rx unit.
2041 */
2042 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2043 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2044 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2045 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2046 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2047 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2048 break;
2049 else
2050 udelay(10);
2051 }
2052
2053 /* For informational purposes only */
2054 if (i >= IXGBE_MAX_SECRX_POLL)
2055 hw_dbg(hw, "Rx unit being enabled before security "
2056 "path fully disabled. Continuing with init.\n");
2057
2058 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2059 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2060 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2061 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2062 IXGBE_WRITE_FLUSH(hw);
2063
2064 return 0;
2065 }
2066
2067 /**
2068 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2069 * @hw: pointer to hardware structure
2070 * @device_caps: the EEPROM word with the extra device capabilities
2071 *
2072 * This function will read the EEPROM location for the device capabilities,
2073 * and return the word through device_caps.
2074 **/
2075 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2076 {
2077 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2078
2079 return 0;
2080 }
2081
2082 /**
2083 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2084 * @hw: pointer to hardware structure
2085 *
2086 * Verifies that installed the firmware version is 0.6 or higher
2087 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2088 *
2089 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2090 * if the FW version is not supported.
2091 **/
2092 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2093 {
2094 s32 status = IXGBE_ERR_EEPROM_VERSION;
2095 u16 fw_offset, fw_ptp_cfg_offset;
2096 u16 fw_version = 0;
2097
2098 /* firmware check is only necessary for SFI devices */
2099 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2100 status = 0;
2101 goto fw_version_out;
2102 }
2103
2104 /* get the offset to the Firmware Module block */
2105 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2106
2107 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2108 goto fw_version_out;
2109
2110 /* get the offset to the Pass Through Patch Configuration block */
2111 hw->eeprom.ops.read(hw, (fw_offset +
2112 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2113 &fw_ptp_cfg_offset);
2114
2115 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2116 goto fw_version_out;
2117
2118 /* get the firmware version */
2119 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2120 IXGBE_FW_PATCH_VERSION_4),
2121 &fw_version);
2122
2123 if (fw_version > 0x5)
2124 status = 0;
2125
2126 fw_version_out:
2127 return status;
2128 }
2129
2130 static struct ixgbe_mac_operations mac_ops_82599 = {
2131 .init_hw = &ixgbe_init_hw_generic,
2132 .reset_hw = &ixgbe_reset_hw_82599,
2133 .start_hw = &ixgbe_start_hw_82599,
2134 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2135 .get_media_type = &ixgbe_get_media_type_82599,
2136 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2137 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2138 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2139 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2140 .get_device_caps = &ixgbe_get_device_caps_82599,
2141 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2142 .stop_adapter = &ixgbe_stop_adapter_generic,
2143 .get_bus_info = &ixgbe_get_bus_info_generic,
2144 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2145 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2146 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2147 .setup_link = &ixgbe_setup_mac_link_82599,
2148 .check_link = &ixgbe_check_mac_link_generic,
2149 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2150 .led_on = &ixgbe_led_on_generic,
2151 .led_off = &ixgbe_led_off_generic,
2152 .blink_led_start = &ixgbe_blink_led_start_generic,
2153 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2154 .set_rar = &ixgbe_set_rar_generic,
2155 .clear_rar = &ixgbe_clear_rar_generic,
2156 .set_vmdq = &ixgbe_set_vmdq_generic,
2157 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2158 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2159 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2160 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2161 .enable_mc = &ixgbe_enable_mc_generic,
2162 .disable_mc = &ixgbe_disable_mc_generic,
2163 .clear_vfta = &ixgbe_clear_vfta_generic,
2164 .set_vfta = &ixgbe_set_vfta_generic,
2165 .fc_enable = &ixgbe_fc_enable_generic,
2166 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2167 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2168 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2169 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2170 };
2171
2172 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2173 .init_params = &ixgbe_init_eeprom_params_generic,
2174 .read = &ixgbe_read_eerd_generic,
2175 .write = &ixgbe_write_eeprom_generic,
2176 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2177 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2178 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2179 };
2180
2181 static struct ixgbe_phy_operations phy_ops_82599 = {
2182 .identify = &ixgbe_identify_phy_82599,
2183 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2184 .init = &ixgbe_init_phy_ops_82599,
2185 .reset = &ixgbe_reset_phy_generic,
2186 .read_reg = &ixgbe_read_phy_reg_generic,
2187 .write_reg = &ixgbe_write_phy_reg_generic,
2188 .setup_link = &ixgbe_setup_phy_link_generic,
2189 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2190 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2191 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2192 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2193 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2194 .check_overtemp = &ixgbe_tn_check_overtemp,
2195 };
2196
2197 struct ixgbe_info ixgbe_82599_info = {
2198 .mac = ixgbe_mac_82599EB,
2199 .get_invariants = &ixgbe_get_invariants_82599,
2200 .mac_ops = &mac_ops_82599,
2201 .eeprom_ops = &eeprom_ops_82599,
2202 .phy_ops = &phy_ops_82599,
2203 .mbx_ops = &mbx_ops_generic,
2204 };
Linus' kernel tree