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cciss: Fix race between disk-adding code and interrupt handler
[linux-2.6.git] / include / asm-x86 / processor.h
blob6e26c7c717a23a15255869f2b864350faf21d597
1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* migration helper, for KVM - will be removed in 2.6.25: */
7 #define Xgt_desc_struct desc_ptr
8
9 /* Forward declaration, a strange C thing */
10 struct task_struct;
11 struct mm_struct;
12
13 #include <asm/vm86.h>
14 #include <asm/math_emu.h>
15 #include <asm/segment.h>
16 #include <asm/types.h>
17 #include <asm/sigcontext.h>
18 #include <asm/current.h>
19 #include <asm/cpufeature.h>
20 #include <asm/system.h>
21 #include <asm/page.h>
22 #include <asm/percpu.h>
23 #include <asm/msr.h>
24 #include <asm/desc_defs.h>
25 #include <asm/nops.h>
26
27 #include <linux/personality.h>
28 #include <linux/cpumask.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/init.h>
32
33 /*
34 * Default implementation of macro that returns current
35 * instruction pointer ("program counter").
36 */
37 static inline void *current_text_addr(void)
38 {
39 void *pc;
40
41 asm volatile("mov $1f, %0; 1:":"=r" (pc));
42
43 return pc;
44 }
45
46 #ifdef CONFIG_X86_VSMP
47 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
49 #else
50 # define ARCH_MIN_TASKALIGN 16
51 # define ARCH_MIN_MMSTRUCT_ALIGN 0
52 #endif
53
54 /*
55 * CPU type and hardware bug flags. Kept separately for each CPU.
56 * Members of this structure are referenced in head.S, so think twice
57 * before touching them. [mj]
58 */
59
60 struct cpuinfo_x86 {
61 __u8 x86; /* CPU family */
62 __u8 x86_vendor; /* CPU vendor */
63 __u8 x86_model;
64 __u8 x86_mask;
65 #ifdef CONFIG_X86_32
66 char wp_works_ok; /* It doesn't on 386's */
67
68 /* Problems on some 486Dx4's and old 386's: */
69 char hlt_works_ok;
70 char hard_math;
71 char rfu;
72 char fdiv_bug;
73 char f00f_bug;
74 char coma_bug;
75 char pad0;
76 #else
77 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
78 int x86_tlbsize;
79 __u8 x86_virt_bits;
80 __u8 x86_phys_bits;
81 /* CPUID returned core id bits: */
82 __u8 x86_coreid_bits;
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
85 #endif
86 /* Maximum supported CPUID level, -1=no CPUID: */
87 int cpuid_level;
88 __u32 x86_capability[NCAPINTS];
89 char x86_vendor_id[16];
90 char x86_model_id[64];
91 /* in KB - valid for CPUS which support this call: */
92 int x86_cache_size;
93 int x86_cache_alignment; /* In bytes */
94 int x86_power;
95 unsigned long loops_per_jiffy;
96 #ifdef CONFIG_SMP
97 /* cpus sharing the last level cache: */
98 cpumask_t llc_shared_map;
99 #endif
100 /* cpuid returned max cores value: */
101 u16 x86_max_cores;
102 u16 apicid;
103 u16 initial_apicid;
104 u16 x86_clflush_size;
105 #ifdef CONFIG_SMP
106 /* number of cores as seen by the OS: */
107 u16 booted_cores;
108 /* Physical processor id: */
109 u16 phys_proc_id;
110 /* Core id: */
111 u16 cpu_core_id;
112 /* Index into per_cpu list: */
113 u16 cpu_index;
114 #endif
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
116
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_NEXGEN 4
122 #define X86_VENDOR_CENTAUR 5
123 #define X86_VENDOR_TRANSMETA 7
124 #define X86_VENDOR_NSC 8
125 #define X86_VENDOR_NUM 9
126
127 #define X86_VENDOR_UNKNOWN 0xff
128
129 /*
130 * capabilities of CPUs
131 */
132 extern struct cpuinfo_x86 boot_cpu_data;
133 extern struct cpuinfo_x86 new_cpu_data;
134
135 extern struct tss_struct doublefault_tss;
136 extern __u32 cleared_cpu_caps[NCAPINTS];
137
138 #ifdef CONFIG_SMP
139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
141 #define current_cpu_data cpu_data(smp_processor_id())
142 #else
143 #define cpu_data(cpu) boot_cpu_data
144 #define current_cpu_data boot_cpu_data
145 #endif
146
147 static inline int hlt_works(int cpu)
148 {
149 #ifdef CONFIG_X86_32
150 return cpu_data(cpu).hlt_works_ok;
151 #else
152 return 1;
153 #endif
154 }
155
156 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157
158 extern void cpu_detect(struct cpuinfo_x86 *c);
159
160 extern void identify_cpu(struct cpuinfo_x86 *);
161 extern void identify_boot_cpu(void);
162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
163 extern void print_cpu_info(struct cpuinfo_x86 *);
164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
166 extern unsigned short num_cache_leaves;
167
168 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
169 extern void detect_ht(struct cpuinfo_x86 *c);
170 #else
171 static inline void detect_ht(struct cpuinfo_x86 *c) {}
172 #endif
173
174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
175 unsigned int *ecx, unsigned int *edx)
176 {
177 /* ecx is often an input as well as an output. */
178 asm("cpuid"
179 : "=a" (*eax),
180 "=b" (*ebx),
181 "=c" (*ecx),
182 "=d" (*edx)
183 : "0" (*eax), "2" (*ecx));
184 }
185
186 static inline void load_cr3(pgd_t *pgdir)
187 {
188 write_cr3(__pa(pgdir));
189 }
190
191 #ifdef CONFIG_X86_32
192 /* This is the TSS defined by the hardware. */
193 struct x86_hw_tss {
194 unsigned short back_link, __blh;
195 unsigned long sp0;
196 unsigned short ss0, __ss0h;
197 unsigned long sp1;
198 /* ss1 caches MSR_IA32_SYSENTER_CS: */
199 unsigned short ss1, __ss1h;
200 unsigned long sp2;
201 unsigned short ss2, __ss2h;
202 unsigned long __cr3;
203 unsigned long ip;
204 unsigned long flags;
205 unsigned long ax;
206 unsigned long cx;
207 unsigned long dx;
208 unsigned long bx;
209 unsigned long sp;
210 unsigned long bp;
211 unsigned long si;
212 unsigned long di;
213 unsigned short es, __esh;
214 unsigned short cs, __csh;
215 unsigned short ss, __ssh;
216 unsigned short ds, __dsh;
217 unsigned short fs, __fsh;
218 unsigned short gs, __gsh;
219 unsigned short ldt, __ldth;
220 unsigned short trace;
221 unsigned short io_bitmap_base;
222
223 } __attribute__((packed));
224 #else
225 struct x86_hw_tss {
226 u32 reserved1;
227 u64 sp0;
228 u64 sp1;
229 u64 sp2;
230 u64 reserved2;
231 u64 ist[7];
232 u32 reserved3;
233 u32 reserved4;
234 u16 reserved5;
235 u16 io_bitmap_base;
236
237 } __attribute__((packed)) ____cacheline_aligned;
238 #endif
239
240 /*
241 * IO-bitmap sizes:
242 */
243 #define IO_BITMAP_BITS 65536
244 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
245 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
246 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
247 #define INVALID_IO_BITMAP_OFFSET 0x8000
248 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
249
250 struct tss_struct {
251 /*
252 * The hardware state:
253 */
254 struct x86_hw_tss x86_tss;
255
256 /*
257 * The extra 1 is there because the CPU will access an
258 * additional byte beyond the end of the IO permission
259 * bitmap. The extra byte must be all 1 bits, and must
260 * be within the limit.
261 */
262 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
263 /*
264 * Cache the current maximum and the last task that used the bitmap:
265 */
266 unsigned long io_bitmap_max;
267 struct thread_struct *io_bitmap_owner;
268
269 /*
270 * Pad the TSS to be cacheline-aligned (size is 0x100):
271 */
272 unsigned long __cacheline_filler[35];
273 /*
274 * .. and then another 0x100 bytes for the emergency kernel stack:
275 */
276 unsigned long stack[64];
277
278 } __attribute__((packed));
279
280 DECLARE_PER_CPU(struct tss_struct, init_tss);
281
282 /*
283 * Save the original ist values for checking stack pointers during debugging
284 */
285 struct orig_ist {
286 unsigned long ist[7];
287 };
288
289 #define MXCSR_DEFAULT 0x1f80
290
291 struct i387_fsave_struct {
292 u32 cwd; /* FPU Control Word */
293 u32 swd; /* FPU Status Word */
294 u32 twd; /* FPU Tag Word */
295 u32 fip; /* FPU IP Offset */
296 u32 fcs; /* FPU IP Selector */
297 u32 foo; /* FPU Operand Pointer Offset */
298 u32 fos; /* FPU Operand Pointer Selector */
299
300 /* 8*10 bytes for each FP-reg = 80 bytes: */
301 u32 st_space[20];
302
303 /* Software status information [not touched by FSAVE ]: */
304 u32 status;
305 };
306
307 struct i387_fxsave_struct {
308 u16 cwd; /* Control Word */
309 u16 swd; /* Status Word */
310 u16 twd; /* Tag Word */
311 u16 fop; /* Last Instruction Opcode */
312 union {
313 struct {
314 u64 rip; /* Instruction Pointer */
315 u64 rdp; /* Data Pointer */
316 };
317 struct {
318 u32 fip; /* FPU IP Offset */
319 u32 fcs; /* FPU IP Selector */
320 u32 foo; /* FPU Operand Offset */
321 u32 fos; /* FPU Operand Selector */
322 };
323 };
324 u32 mxcsr; /* MXCSR Register State */
325 u32 mxcsr_mask; /* MXCSR Mask */
326
327 /* 8*16 bytes for each FP-reg = 128 bytes: */
328 u32 st_space[32];
329
330 /* 16*16 bytes for each XMM-reg = 256 bytes: */
331 u32 xmm_space[64];
332
333 u32 padding[24];
334
335 } __attribute__((aligned(16)));
336
337 struct i387_soft_struct {
338 u32 cwd;
339 u32 swd;
340 u32 twd;
341 u32 fip;
342 u32 fcs;
343 u32 foo;
344 u32 fos;
345 /* 8*10 bytes for each FP-reg = 80 bytes: */
346 u32 st_space[20];
347 u8 ftop;
348 u8 changed;
349 u8 lookahead;
350 u8 no_update;
351 u8 rm;
352 u8 alimit;
353 struct info *info;
354 u32 entry_eip;
355 };
356
357 union i387_union {
358 struct i387_fsave_struct fsave;
359 struct i387_fxsave_struct fxsave;
360 struct i387_soft_struct soft;
361 };
362
363 #ifdef CONFIG_X86_64
364 DECLARE_PER_CPU(struct orig_ist, orig_ist);
365 #endif
366
367 extern void print_cpu_info(struct cpuinfo_x86 *);
368 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
369 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
370 extern unsigned short num_cache_leaves;
371
372 struct thread_struct {
373 /* Cached TLS descriptors: */
374 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
375 unsigned long sp0;
376 unsigned long sp;
377 #ifdef CONFIG_X86_32
378 unsigned long sysenter_cs;
379 #else
380 unsigned long usersp; /* Copy from PDA */
381 unsigned short es;
382 unsigned short ds;
383 unsigned short fsindex;
384 unsigned short gsindex;
385 #endif
386 unsigned long ip;
387 unsigned long fs;
388 unsigned long gs;
389 /* Hardware debugging registers: */
390 unsigned long debugreg0;
391 unsigned long debugreg1;
392 unsigned long debugreg2;
393 unsigned long debugreg3;
394 unsigned long debugreg6;
395 unsigned long debugreg7;
396 /* Fault info: */
397 unsigned long cr2;
398 unsigned long trap_no;
399 unsigned long error_code;
400 /* Floating point info: */
401 union i387_union i387 __attribute__((aligned(16)));;
402 #ifdef CONFIG_X86_32
403 /* Virtual 86 mode info */
404 struct vm86_struct __user *vm86_info;
405 unsigned long screen_bitmap;
406 unsigned long v86flags;
407 unsigned long v86mask;
408 unsigned long saved_sp0;
409 unsigned int saved_fs;
410 unsigned int saved_gs;
411 #endif
412 /* IO permissions: */
413 unsigned long *io_bitmap_ptr;
414 unsigned long iopl;
415 /* Max allowed port in the bitmap, in bytes: */
416 unsigned io_bitmap_max;
417 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
418 unsigned long debugctlmsr;
419 /* Debug Store - if not 0 points to a DS Save Area configuration;
420 * goes into MSR_IA32_DS_AREA */
421 unsigned long ds_area_msr;
422 };
423
424 static inline unsigned long native_get_debugreg(int regno)
425 {
426 unsigned long val = 0; /* Damn you, gcc! */
427
428 switch (regno) {
429 case 0:
430 asm("mov %%db0, %0" :"=r" (val));
431 break;
432 case 1:
433 asm("mov %%db1, %0" :"=r" (val));
434 break;
435 case 2:
436 asm("mov %%db2, %0" :"=r" (val));
437 break;
438 case 3:
439 asm("mov %%db3, %0" :"=r" (val));
440 break;
441 case 6:
442 asm("mov %%db6, %0" :"=r" (val));
443 break;
444 case 7:
445 asm("mov %%db7, %0" :"=r" (val));
446 break;
447 default:
448 BUG();
449 }
450 return val;
451 }
452
453 static inline void native_set_debugreg(int regno, unsigned long value)
454 {
455 switch (regno) {
456 case 0:
457 asm("mov %0, %%db0" ::"r" (value));
458 break;
459 case 1:
460 asm("mov %0, %%db1" ::"r" (value));
461 break;
462 case 2:
463 asm("mov %0, %%db2" ::"r" (value));
464 break;
465 case 3:
466 asm("mov %0, %%db3" ::"r" (value));
467 break;
468 case 6:
469 asm("mov %0, %%db6" ::"r" (value));
470 break;
471 case 7:
472 asm("mov %0, %%db7" ::"r" (value));
473 break;
474 default:
475 BUG();
476 }
477 }
478
479 /*
480 * Set IOPL bits in EFLAGS from given mask
481 */
482 static inline void native_set_iopl_mask(unsigned mask)
483 {
484 #ifdef CONFIG_X86_32
485 unsigned int reg;
486
487 asm volatile ("pushfl;"
488 "popl %0;"
489 "andl %1, %0;"
490 "orl %2, %0;"
491 "pushl %0;"
492 "popfl"
493 : "=&r" (reg)
494 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
495 #endif
496 }
497
498 static inline void
499 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
500 {
501 tss->x86_tss.sp0 = thread->sp0;
502 #ifdef CONFIG_X86_32
503 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
504 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
505 tss->x86_tss.ss1 = thread->sysenter_cs;
506 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
507 }
508 #endif
509 }
510
511 static inline void native_swapgs(void)
512 {
513 #ifdef CONFIG_X86_64
514 asm volatile("swapgs" ::: "memory");
515 #endif
516 }
517
518 #ifdef CONFIG_PARAVIRT
519 #include <asm/paravirt.h>
520 #else
521 #define __cpuid native_cpuid
522 #define paravirt_enabled() 0
523
524 /*
525 * These special macros can be used to get or set a debugging register
526 */
527 #define get_debugreg(var, register) \
528 (var) = native_get_debugreg(register)
529 #define set_debugreg(value, register) \
530 native_set_debugreg(register, value)
531
532 static inline void load_sp0(struct tss_struct *tss,
533 struct thread_struct *thread)
534 {
535 native_load_sp0(tss, thread);
536 }
537
538 #define set_iopl_mask native_set_iopl_mask
539 #define SWAPGS swapgs
540 #endif /* CONFIG_PARAVIRT */
541
542 /*
543 * Save the cr4 feature set we're using (ie
544 * Pentium 4MB enable and PPro Global page
545 * enable), so that any CPU's that boot up
546 * after us can get the correct flags.
547 */
548 extern unsigned long mmu_cr4_features;
549
550 static inline void set_in_cr4(unsigned long mask)
551 {
552 unsigned cr4;
553
554 mmu_cr4_features |= mask;
555 cr4 = read_cr4();
556 cr4 |= mask;
557 write_cr4(cr4);
558 }
559
560 static inline void clear_in_cr4(unsigned long mask)
561 {
562 unsigned cr4;
563
564 mmu_cr4_features &= ~mask;
565 cr4 = read_cr4();
566 cr4 &= ~mask;
567 write_cr4(cr4);
568 }
569
570 struct microcode_header {
571 unsigned int hdrver;
572 unsigned int rev;
573 unsigned int date;
574 unsigned int sig;
575 unsigned int cksum;
576 unsigned int ldrver;
577 unsigned int pf;
578 unsigned int datasize;
579 unsigned int totalsize;
580 unsigned int reserved[3];
581 };
582
583 struct microcode {
584 struct microcode_header hdr;
585 unsigned int bits[0];
586 };
587
588 typedef struct microcode microcode_t;
589 typedef struct microcode_header microcode_header_t;
590
591 /* microcode format is extended from prescott processors */
592 struct extended_signature {
593 unsigned int sig;
594 unsigned int pf;
595 unsigned int cksum;
596 };
597
598 struct extended_sigtable {
599 unsigned int count;
600 unsigned int cksum;
601 unsigned int reserved[3];
602 struct extended_signature sigs[0];
603 };
604
605 typedef struct {
606 unsigned long seg;
607 } mm_segment_t;
608
609
610 /*
611 * create a kernel thread without removing it from tasklists
612 */
613 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
614
615 /* Free all resources held by a thread. */
616 extern void release_thread(struct task_struct *);
617
618 /* Prepare to copy thread state - unlazy all lazy state */
619 extern void prepare_to_copy(struct task_struct *tsk);
620
621 unsigned long get_wchan(struct task_struct *p);
622
623 /*
624 * Generic CPUID function
625 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
626 * resulting in stale register contents being returned.
627 */
628 static inline void cpuid(unsigned int op,
629 unsigned int *eax, unsigned int *ebx,
630 unsigned int *ecx, unsigned int *edx)
631 {
632 *eax = op;
633 *ecx = 0;
634 __cpuid(eax, ebx, ecx, edx);
635 }
636
637 /* Some CPUID calls want 'count' to be placed in ecx */
638 static inline void cpuid_count(unsigned int op, int count,
639 unsigned int *eax, unsigned int *ebx,
640 unsigned int *ecx, unsigned int *edx)
641 {
642 *eax = op;
643 *ecx = count;
644 __cpuid(eax, ebx, ecx, edx);
645 }
646
647 /*
648 * CPUID functions returning a single datum
649 */
650 static inline unsigned int cpuid_eax(unsigned int op)
651 {
652 unsigned int eax, ebx, ecx, edx;
653
654 cpuid(op, &eax, &ebx, &ecx, &edx);
655
656 return eax;
657 }
658
659 static inline unsigned int cpuid_ebx(unsigned int op)
660 {
661 unsigned int eax, ebx, ecx, edx;
662
663 cpuid(op, &eax, &ebx, &ecx, &edx);
664
665 return ebx;
666 }
667
668 static inline unsigned int cpuid_ecx(unsigned int op)
669 {
670 unsigned int eax, ebx, ecx, edx;
671
672 cpuid(op, &eax, &ebx, &ecx, &edx);
673
674 return ecx;
675 }
676
677 static inline unsigned int cpuid_edx(unsigned int op)
678 {
679 unsigned int eax, ebx, ecx, edx;
680
681 cpuid(op, &eax, &ebx, &ecx, &edx);
682
683 return edx;
684 }
685
686 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
687 static inline void rep_nop(void)
688 {
689 asm volatile("rep; nop" ::: "memory");
690 }
691
692 static inline void cpu_relax(void)
693 {
694 rep_nop();
695 }
696
697 /* Stop speculative execution: */
698 static inline void sync_core(void)
699 {
700 int tmp;
701
702 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
703 : "ebx", "ecx", "edx", "memory");
704 }
705
706 static inline void __monitor(const void *eax, unsigned long ecx,
707 unsigned long edx)
708 {
709 /* "monitor %eax, %ecx, %edx;" */
710 asm volatile(".byte 0x0f, 0x01, 0xc8;"
711 :: "a" (eax), "c" (ecx), "d"(edx));
712 }
713
714 static inline void __mwait(unsigned long eax, unsigned long ecx)
715 {
716 /* "mwait %eax, %ecx;" */
717 asm volatile(".byte 0x0f, 0x01, 0xc9;"
718 :: "a" (eax), "c" (ecx));
719 }
720
721 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
722 {
723 /* "mwait %eax, %ecx;" */
724 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
725 :: "a" (eax), "c" (ecx));
726 }
727
728 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
729
730 extern int force_mwait;
731
732 extern void select_idle_routine(const struct cpuinfo_x86 *c);
733
734 extern unsigned long boot_option_idle_override;
735
736 extern void enable_sep_cpu(void);
737 extern int sysenter_setup(void);
738
739 /* Defined in head.S */
740 extern struct desc_ptr early_gdt_descr;
741
742 extern void cpu_set_gdt(int);
743 extern void switch_to_new_gdt(void);
744 extern void cpu_init(void);
745 extern void init_gdt(int cpu);
746
747 static inline void update_debugctlmsr(unsigned long debugctlmsr)
748 {
749 #ifndef CONFIG_X86_DEBUGCTLMSR
750 if (boot_cpu_data.x86 < 6)
751 return;
752 #endif
753 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
754 }
755
756 /*
757 * from system description table in BIOS. Mostly for MCA use, but
758 * others may find it useful:
759 */
760 extern unsigned int machine_id;
761 extern unsigned int machine_submodel_id;
762 extern unsigned int BIOS_revision;
763
764 /* Boot loader type from the setup header: */
765 extern int bootloader_type;
766
767 extern char ignore_fpu_irq;
768
769 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
770 #define ARCH_HAS_PREFETCHW
771 #define ARCH_HAS_SPINLOCK_PREFETCH
772
773 #ifdef CONFIG_X86_32
774 # define BASE_PREFETCH ASM_NOP4
775 # define ARCH_HAS_PREFETCH
776 #else
777 # define BASE_PREFETCH "prefetcht0 (%1)"
778 #endif
779
780 /*
781 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
782 *
783 * It's not worth to care about 3dnow prefetches for the K6
784 * because they are microcoded there and very slow.
785 */
786 static inline void prefetch(const void *x)
787 {
788 alternative_input(BASE_PREFETCH,
789 "prefetchnta (%1)",
790 X86_FEATURE_XMM,
791 "r" (x));
792 }
793
794 /*
795 * 3dnow prefetch to get an exclusive cache line.
796 * Useful for spinlocks to avoid one state transition in the
797 * cache coherency protocol:
798 */
799 static inline void prefetchw(const void *x)
800 {
801 alternative_input(BASE_PREFETCH,
802 "prefetchw (%1)",
803 X86_FEATURE_3DNOW,
804 "r" (x));
805 }
806
807 static inline void spin_lock_prefetch(const void *x)
808 {
809 prefetchw(x);
810 }
811
812 #ifdef CONFIG_X86_32
813 /*
814 * User space process size: 3GB (default).
815 */
816 #define TASK_SIZE PAGE_OFFSET
817 #define STACK_TOP TASK_SIZE
818 #define STACK_TOP_MAX STACK_TOP
819
820 #define INIT_THREAD { \
821 .sp0 = sizeof(init_stack) + (long)&init_stack, \
822 .vm86_info = NULL, \
823 .sysenter_cs = __KERNEL_CS, \
824 .io_bitmap_ptr = NULL, \
825 .fs = __KERNEL_PERCPU, \
826 }
827
828 /*
829 * Note that the .io_bitmap member must be extra-big. This is because
830 * the CPU will access an additional byte beyond the end of the IO
831 * permission bitmap. The extra byte must be all 1 bits, and must
832 * be within the limit.
833 */
834 #define INIT_TSS { \
835 .x86_tss = { \
836 .sp0 = sizeof(init_stack) + (long)&init_stack, \
837 .ss0 = __KERNEL_DS, \
838 .ss1 = __KERNEL_CS, \
839 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
840 }, \
841 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
842 }
843
844 extern unsigned long thread_saved_pc(struct task_struct *tsk);
845
846 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
847 #define KSTK_TOP(info) \
848 ({ \
849 unsigned long *__ptr = (unsigned long *)(info); \
850 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
851 })
852
853 /*
854 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
855 * This is necessary to guarantee that the entire "struct pt_regs"
856 * is accessable even if the CPU haven't stored the SS/ESP registers
857 * on the stack (interrupt gate does not save these registers
858 * when switching to the same priv ring).
859 * Therefore beware: accessing the ss/esp fields of the
860 * "struct pt_regs" is possible, but they may contain the
861 * completely wrong values.
862 */
863 #define task_pt_regs(task) \
864 ({ \
865 struct pt_regs *__regs__; \
866 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
867 __regs__ - 1; \
868 })
869
870 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
871
872 #else
873 /*
874 * User space process size. 47bits minus one guard page.
875 */
876 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
877
878 /* This decides where the kernel will search for a free chunk of vm
879 * space during mmap's.
880 */
881 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
882 0xc0000000 : 0xFFFFe000)
883
884 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
885 IA32_PAGE_OFFSET : TASK_SIZE64)
886 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
887 IA32_PAGE_OFFSET : TASK_SIZE64)
888
889 #define STACK_TOP TASK_SIZE
890 #define STACK_TOP_MAX TASK_SIZE64
891
892 #define INIT_THREAD { \
893 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
894 }
895
896 #define INIT_TSS { \
897 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
898 }
899
900 /*
901 * Return saved PC of a blocked thread.
902 * What is this good for? it will be always the scheduler or ret_from_fork.
903 */
904 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
905
906 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
907 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
908 #endif /* CONFIG_X86_64 */
909
910 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
911 unsigned long new_sp);
912
913 /*
914 * This decides where the kernel will search for a free chunk of vm
915 * space during mmap's.
916 */
917 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
918
919 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
920
921 #endif
Linus' kernel tree