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r8169: remove erroneous processing of always set bit.
[linux-2.6.git] / drivers / tty / serial / 8250.c
blob7f50999eebc22f00fb482d2fda62d62f11262be5
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69 /*
70 * Debugging.
71 */
72 #if 0
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #else
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 #endif
77
78 #if 0
79 #define DEBUG_INTR(fmt...) printk(fmt)
80 #else
81 #define DEBUG_INTR(fmt...) do { } while (0)
82 #endif
83
84 #define PASS_LIMIT 512
85
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89 /*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94 #define is_real_interrupt(irq) ((irq) != 0)
95
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
98 #endif
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102
103 /*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107 #define CONFIG_HUB6 1
108
109 #include <asm/serial.h>
110 /*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125 #ifdef CONFIG_SERIAL_8250_RSA
126
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
131
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
312 };
313
314 #if defined(CONFIG_MIPS_ALCHEMY)
315
316 /* Au1x00 UART hardware has a weird register layout */
317 static const u8 au_io_in_map[] = {
318 [UART_RX] = 0,
319 [UART_IER] = 2,
320 [UART_IIR] = 3,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323 [UART_LSR] = 7,
324 [UART_MSR] = 8,
325 };
326
327 static const u8 au_io_out_map[] = {
328 [UART_TX] = 1,
329 [UART_IER] = 2,
330 [UART_FCR] = 4,
331 [UART_LCR] = 5,
332 [UART_MCR] = 6,
333 };
334
335 /* sane hardware needs no mapping */
336 static inline int map_8250_in_reg(struct uart_port *p, int offset)
337 {
338 if (p->iotype != UPIO_AU)
339 return offset;
340 return au_io_in_map[offset];
341 }
342
343 static inline int map_8250_out_reg(struct uart_port *p, int offset)
344 {
345 if (p->iotype != UPIO_AU)
346 return offset;
347 return au_io_out_map[offset];
348 }
349
350 #elif defined(CONFIG_SERIAL_8250_RM9K)
351
352 static const u8
353 regmap_in[8] = {
354 [UART_RX] = 0x00,
355 [UART_IER] = 0x0c,
356 [UART_IIR] = 0x14,
357 [UART_LCR] = 0x1c,
358 [UART_MCR] = 0x20,
359 [UART_LSR] = 0x24,
360 [UART_MSR] = 0x28,
361 [UART_SCR] = 0x2c
362 },
363 regmap_out[8] = {
364 [UART_TX] = 0x04,
365 [UART_IER] = 0x0c,
366 [UART_FCR] = 0x18,
367 [UART_LCR] = 0x1c,
368 [UART_MCR] = 0x20,
369 [UART_LSR] = 0x24,
370 [UART_MSR] = 0x28,
371 [UART_SCR] = 0x2c
372 };
373
374 static inline int map_8250_in_reg(struct uart_port *p, int offset)
375 {
376 if (p->iotype != UPIO_RM9000)
377 return offset;
378 return regmap_in[offset];
379 }
380
381 static inline int map_8250_out_reg(struct uart_port *p, int offset)
382 {
383 if (p->iotype != UPIO_RM9000)
384 return offset;
385 return regmap_out[offset];
386 }
387
388 #else
389
390 /* sane hardware needs no mapping */
391 #define map_8250_in_reg(up, offset) (offset)
392 #define map_8250_out_reg(up, offset) (offset)
393
394 #endif
395
396 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 {
398 offset = map_8250_in_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 return inb(p->iobase + 1);
401 }
402
403 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 {
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 outb(value, p->iobase + 1);
408 }
409
410 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 {
412 offset = map_8250_in_reg(p, offset) << p->regshift;
413 return readb(p->membase + offset);
414 }
415
416 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 {
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writeb(value, p->membase + offset);
420 }
421
422 static void mem32_serial_out(struct uart_port *p, int offset, int value)
423 {
424 offset = map_8250_out_reg(p, offset) << p->regshift;
425 writel(value, p->membase + offset);
426 }
427
428 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429 {
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return readl(p->membase + offset);
432 }
433
434 static unsigned int au_serial_in(struct uart_port *p, int offset)
435 {
436 offset = map_8250_in_reg(p, offset) << p->regshift;
437 return __raw_readl(p->membase + offset);
438 }
439
440 static void au_serial_out(struct uart_port *p, int offset, int value)
441 {
442 offset = map_8250_out_reg(p, offset) << p->regshift;
443 __raw_writel(value, p->membase + offset);
444 }
445
446 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
447 {
448 unsigned int tmp;
449 offset = map_8250_in_reg(p, offset) << p->regshift;
450 if (offset == UART_IIR) {
451 tmp = readl(p->membase + (UART_IIR & ~3));
452 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
453 } else
454 return readb(p->membase + offset);
455 }
456
457 static void tsi_serial_out(struct uart_port *p, int offset, int value)
458 {
459 offset = map_8250_out_reg(p, offset) << p->regshift;
460 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
461 writeb(value, p->membase + offset);
462 }
463
464 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
465 static inline void dwapb_save_out_value(struct uart_port *p, int offset,
466 int value)
467 {
468 struct uart_8250_port *up =
469 container_of(p, struct uart_8250_port, port);
470
471 if (offset == UART_LCR)
472 up->lcr = value;
473 }
474
475 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */
476 static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
477 {
478 if (offset == UART_TX || offset == UART_IER)
479 p->serial_in(p, UART_IER);
480 }
481
482 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
483 {
484 int save_offset = offset;
485 offset = map_8250_out_reg(p, offset) << p->regshift;
486 dwapb_save_out_value(p, save_offset, value);
487 writeb(value, p->membase + offset);
488 dwapb_check_clear_ier(p, save_offset);
489 }
490
491 static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
492 {
493 int save_offset = offset;
494 offset = map_8250_out_reg(p, offset) << p->regshift;
495 dwapb_save_out_value(p, save_offset, value);
496 writel(value, p->membase + offset);
497 dwapb_check_clear_ier(p, save_offset);
498 }
499
500 static unsigned int io_serial_in(struct uart_port *p, int offset)
501 {
502 offset = map_8250_in_reg(p, offset) << p->regshift;
503 return inb(p->iobase + offset);
504 }
505
506 static void io_serial_out(struct uart_port *p, int offset, int value)
507 {
508 offset = map_8250_out_reg(p, offset) << p->regshift;
509 outb(value, p->iobase + offset);
510 }
511
512 static void set_io_from_upio(struct uart_port *p)
513 {
514 struct uart_8250_port *up =
515 container_of(p, struct uart_8250_port, port);
516 switch (p->iotype) {
517 case UPIO_HUB6:
518 p->serial_in = hub6_serial_in;
519 p->serial_out = hub6_serial_out;
520 break;
521
522 case UPIO_MEM:
523 p->serial_in = mem_serial_in;
524 p->serial_out = mem_serial_out;
525 break;
526
527 case UPIO_RM9000:
528 case UPIO_MEM32:
529 p->serial_in = mem32_serial_in;
530 p->serial_out = mem32_serial_out;
531 break;
532
533 case UPIO_AU:
534 p->serial_in = au_serial_in;
535 p->serial_out = au_serial_out;
536 break;
537
538 case UPIO_TSI:
539 p->serial_in = tsi_serial_in;
540 p->serial_out = tsi_serial_out;
541 break;
542
543 case UPIO_DWAPB:
544 p->serial_in = mem_serial_in;
545 p->serial_out = dwapb_serial_out;
546 break;
547
548 case UPIO_DWAPB32:
549 p->serial_in = mem32_serial_in;
550 p->serial_out = dwapb32_serial_out;
551 break;
552
553 default:
554 p->serial_in = io_serial_in;
555 p->serial_out = io_serial_out;
556 break;
557 }
558 /* Remember loaded iotype */
559 up->cur_iotype = p->iotype;
560 }
561
562 static void
563 serial_out_sync(struct uart_8250_port *up, int offset, int value)
564 {
565 struct uart_port *p = &up->port;
566 switch (p->iotype) {
567 case UPIO_MEM:
568 case UPIO_MEM32:
569 case UPIO_AU:
570 case UPIO_DWAPB:
571 case UPIO_DWAPB32:
572 p->serial_out(p, offset, value);
573 p->serial_in(p, UART_LCR); /* safe, no side-effects */
574 break;
575 default:
576 p->serial_out(p, offset, value);
577 }
578 }
579
580 #define serial_in(up, offset) \
581 (up->port.serial_in(&(up)->port, (offset)))
582 #define serial_out(up, offset, value) \
583 (up->port.serial_out(&(up)->port, (offset), (value)))
584 /*
585 * We used to support using pause I/O for certain machines. We
586 * haven't supported this for a while, but just in case it's badly
587 * needed for certain old 386 machines, I've left these #define's
588 * in....
589 */
590 #define serial_inp(up, offset) serial_in(up, offset)
591 #define serial_outp(up, offset, value) serial_out(up, offset, value)
592
593 /* Uart divisor latch read */
594 static inline int _serial_dl_read(struct uart_8250_port *up)
595 {
596 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
597 }
598
599 /* Uart divisor latch write */
600 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
601 {
602 serial_outp(up, UART_DLL, value & 0xff);
603 serial_outp(up, UART_DLM, value >> 8 & 0xff);
604 }
605
606 #if defined(CONFIG_MIPS_ALCHEMY)
607 /* Au1x00 haven't got a standard divisor latch */
608 static int serial_dl_read(struct uart_8250_port *up)
609 {
610 if (up->port.iotype == UPIO_AU)
611 return __raw_readl(up->port.membase + 0x28);
612 else
613 return _serial_dl_read(up);
614 }
615
616 static void serial_dl_write(struct uart_8250_port *up, int value)
617 {
618 if (up->port.iotype == UPIO_AU)
619 __raw_writel(value, up->port.membase + 0x28);
620 else
621 _serial_dl_write(up, value);
622 }
623 #elif defined(CONFIG_SERIAL_8250_RM9K)
624 static int serial_dl_read(struct uart_8250_port *up)
625 {
626 return (up->port.iotype == UPIO_RM9000) ?
627 (((__raw_readl(up->port.membase + 0x10) << 8) |
628 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
629 _serial_dl_read(up);
630 }
631
632 static void serial_dl_write(struct uart_8250_port *up, int value)
633 {
634 if (up->port.iotype == UPIO_RM9000) {
635 __raw_writel(value, up->port.membase + 0x08);
636 __raw_writel(value >> 8, up->port.membase + 0x10);
637 } else {
638 _serial_dl_write(up, value);
639 }
640 }
641 #else
642 #define serial_dl_read(up) _serial_dl_read(up)
643 #define serial_dl_write(up, value) _serial_dl_write(up, value)
644 #endif
645
646 /*
647 * For the 16C950
648 */
649 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
650 {
651 serial_out(up, UART_SCR, offset);
652 serial_out(up, UART_ICR, value);
653 }
654
655 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
656 {
657 unsigned int value;
658
659 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
660 serial_out(up, UART_SCR, offset);
661 value = serial_in(up, UART_ICR);
662 serial_icr_write(up, UART_ACR, up->acr);
663
664 return value;
665 }
666
667 /*
668 * FIFO support.
669 */
670 static void serial8250_clear_fifos(struct uart_8250_port *p)
671 {
672 if (p->capabilities & UART_CAP_FIFO) {
673 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
674 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
675 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
676 serial_outp(p, UART_FCR, 0);
677 }
678 }
679
680 /*
681 * IER sleep support. UARTs which have EFRs need the "extended
682 * capability" bit enabled. Note that on XR16C850s, we need to
683 * reset LCR to write to IER.
684 */
685 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
686 {
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
689 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
690 serial_outp(p, UART_EFR, UART_EFR_ECB);
691 serial_outp(p, UART_LCR, 0);
692 }
693 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
694 if (p->capabilities & UART_CAP_EFR) {
695 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
696 serial_outp(p, UART_EFR, 0);
697 serial_outp(p, UART_LCR, 0);
698 }
699 }
700 }
701
702 #ifdef CONFIG_SERIAL_8250_RSA
703 /*
704 * Attempts to turn on the RSA FIFO. Returns zero on failure.
705 * We set the port uart clock rate if we succeed.
706 */
707 static int __enable_rsa(struct uart_8250_port *up)
708 {
709 unsigned char mode;
710 int result;
711
712 mode = serial_inp(up, UART_RSA_MSR);
713 result = mode & UART_RSA_MSR_FIFO;
714
715 if (!result) {
716 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
717 mode = serial_inp(up, UART_RSA_MSR);
718 result = mode & UART_RSA_MSR_FIFO;
719 }
720
721 if (result)
722 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
723
724 return result;
725 }
726
727 static void enable_rsa(struct uart_8250_port *up)
728 {
729 if (up->port.type == PORT_RSA) {
730 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
731 spin_lock_irq(&up->port.lock);
732 __enable_rsa(up);
733 spin_unlock_irq(&up->port.lock);
734 }
735 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
736 serial_outp(up, UART_RSA_FRR, 0);
737 }
738 }
739
740 /*
741 * Attempts to turn off the RSA FIFO. Returns zero on failure.
742 * It is unknown why interrupts were disabled in here. However,
743 * the caller is expected to preserve this behaviour by grabbing
744 * the spinlock before calling this function.
745 */
746 static void disable_rsa(struct uart_8250_port *up)
747 {
748 unsigned char mode;
749 int result;
750
751 if (up->port.type == PORT_RSA &&
752 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
753 spin_lock_irq(&up->port.lock);
754
755 mode = serial_inp(up, UART_RSA_MSR);
756 result = !(mode & UART_RSA_MSR_FIFO);
757
758 if (!result) {
759 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
760 mode = serial_inp(up, UART_RSA_MSR);
761 result = !(mode & UART_RSA_MSR_FIFO);
762 }
763
764 if (result)
765 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
766 spin_unlock_irq(&up->port.lock);
767 }
768 }
769 #endif /* CONFIG_SERIAL_8250_RSA */
770
771 /*
772 * This is a quickie test to see how big the FIFO is.
773 * It doesn't work at all the time, more's the pity.
774 */
775 static int size_fifo(struct uart_8250_port *up)
776 {
777 unsigned char old_fcr, old_mcr, old_lcr;
778 unsigned short old_dl;
779 int count;
780
781 old_lcr = serial_inp(up, UART_LCR);
782 serial_outp(up, UART_LCR, 0);
783 old_fcr = serial_inp(up, UART_FCR);
784 old_mcr = serial_inp(up, UART_MCR);
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
786 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
787 serial_outp(up, UART_MCR, UART_MCR_LOOP);
788 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
789 old_dl = serial_dl_read(up);
790 serial_dl_write(up, 0x0001);
791 serial_outp(up, UART_LCR, 0x03);
792 for (count = 0; count < 256; count++)
793 serial_outp(up, UART_TX, count);
794 mdelay(20);/* FIXME - schedule_timeout */
795 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
796 (count < 256); count++)
797 serial_inp(up, UART_RX);
798 serial_outp(up, UART_FCR, old_fcr);
799 serial_outp(up, UART_MCR, old_mcr);
800 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
801 serial_dl_write(up, old_dl);
802 serial_outp(up, UART_LCR, old_lcr);
803
804 return count;
805 }
806
807 /*
808 * Read UART ID using the divisor method - set DLL and DLM to zero
809 * and the revision will be in DLL and device type in DLM. We
810 * preserve the device state across this.
811 */
812 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
813 {
814 unsigned char old_dll, old_dlm, old_lcr;
815 unsigned int id;
816
817 old_lcr = serial_inp(p, UART_LCR);
818 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
819
820 old_dll = serial_inp(p, UART_DLL);
821 old_dlm = serial_inp(p, UART_DLM);
822
823 serial_outp(p, UART_DLL, 0);
824 serial_outp(p, UART_DLM, 0);
825
826 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
827
828 serial_outp(p, UART_DLL, old_dll);
829 serial_outp(p, UART_DLM, old_dlm);
830 serial_outp(p, UART_LCR, old_lcr);
831
832 return id;
833 }
834
835 /*
836 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
837 * When this function is called we know it is at least a StarTech
838 * 16650 V2, but it might be one of several StarTech UARTs, or one of
839 * its clones. (We treat the broken original StarTech 16650 V1 as a
840 * 16550, and why not? Startech doesn't seem to even acknowledge its
841 * existence.)
842 *
843 * What evil have men's minds wrought...
844 */
845 static void autoconfig_has_efr(struct uart_8250_port *up)
846 {
847 unsigned int id1, id2, id3, rev;
848
849 /*
850 * Everything with an EFR has SLEEP
851 */
852 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
853
854 /*
855 * First we check to see if it's an Oxford Semiconductor UART.
856 *
857 * If we have to do this here because some non-National
858 * Semiconductor clone chips lock up if you try writing to the
859 * LSR register (which serial_icr_read does)
860 */
861
862 /*
863 * Check for Oxford Semiconductor 16C950.
864 *
865 * EFR [4] must be set else this test fails.
866 *
867 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
868 * claims that it's needed for 952 dual UART's (which are not
869 * recommended for new designs).
870 */
871 up->acr = 0;
872 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
873 serial_out(up, UART_EFR, UART_EFR_ECB);
874 serial_out(up, UART_LCR, 0x00);
875 id1 = serial_icr_read(up, UART_ID1);
876 id2 = serial_icr_read(up, UART_ID2);
877 id3 = serial_icr_read(up, UART_ID3);
878 rev = serial_icr_read(up, UART_REV);
879
880 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
881
882 if (id1 == 0x16 && id2 == 0xC9 &&
883 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
884 up->port.type = PORT_16C950;
885
886 /*
887 * Enable work around for the Oxford Semiconductor 952 rev B
888 * chip which causes it to seriously miscalculate baud rates
889 * when DLL is 0.
890 */
891 if (id3 == 0x52 && rev == 0x01)
892 up->bugs |= UART_BUG_QUOT;
893 return;
894 }
895
896 /*
897 * We check for a XR16C850 by setting DLL and DLM to 0, and then
898 * reading back DLL and DLM. The chip type depends on the DLM
899 * value read back:
900 * 0x10 - XR16C850 and the DLL contains the chip revision.
901 * 0x12 - XR16C2850.
902 * 0x14 - XR16C854.
903 */
904 id1 = autoconfig_read_divisor_id(up);
905 DEBUG_AUTOCONF("850id=%04x ", id1);
906
907 id2 = id1 >> 8;
908 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
909 up->port.type = PORT_16850;
910 return;
911 }
912
913 /*
914 * It wasn't an XR16C850.
915 *
916 * We distinguish between the '654 and the '650 by counting
917 * how many bytes are in the FIFO. I'm using this for now,
918 * since that's the technique that was sent to me in the
919 * serial driver update, but I'm not convinced this works.
920 * I've had problems doing this in the past. -TYT
921 */
922 if (size_fifo(up) == 64)
923 up->port.type = PORT_16654;
924 else
925 up->port.type = PORT_16650V2;
926 }
927
928 /*
929 * We detected a chip without a FIFO. Only two fall into
930 * this category - the original 8250 and the 16450. The
931 * 16450 has a scratch register (accessible with LCR=0)
932 */
933 static void autoconfig_8250(struct uart_8250_port *up)
934 {
935 unsigned char scratch, status1, status2;
936
937 up->port.type = PORT_8250;
938
939 scratch = serial_in(up, UART_SCR);
940 serial_outp(up, UART_SCR, 0xa5);
941 status1 = serial_in(up, UART_SCR);
942 serial_outp(up, UART_SCR, 0x5a);
943 status2 = serial_in(up, UART_SCR);
944 serial_outp(up, UART_SCR, scratch);
945
946 if (status1 == 0xa5 && status2 == 0x5a)
947 up->port.type = PORT_16450;
948 }
949
950 static int broken_efr(struct uart_8250_port *up)
951 {
952 /*
953 * Exar ST16C2550 "A2" devices incorrectly detect as
954 * having an EFR, and report an ID of 0x0201. See
955 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
956 */
957 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
958 return 1;
959
960 return 0;
961 }
962
963 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
964 {
965 unsigned char status;
966
967 status = serial_in(up, 0x04); /* EXCR2 */
968 #define PRESL(x) ((x) & 0x30)
969 if (PRESL(status) == 0x10) {
970 /* already in high speed mode */
971 return 0;
972 } else {
973 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
974 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
975 serial_outp(up, 0x04, status);
976 }
977 return 1;
978 }
979
980 /*
981 * We know that the chip has FIFOs. Does it have an EFR? The
982 * EFR is located in the same register position as the IIR and
983 * we know the top two bits of the IIR are currently set. The
984 * EFR should contain zero. Try to read the EFR.
985 */
986 static void autoconfig_16550a(struct uart_8250_port *up)
987 {
988 unsigned char status1, status2;
989 unsigned int iersave;
990
991 up->port.type = PORT_16550A;
992 up->capabilities |= UART_CAP_FIFO;
993
994 /*
995 * Check for presence of the EFR when DLAB is set.
996 * Only ST16C650V1 UARTs pass this test.
997 */
998 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
999 if (serial_in(up, UART_EFR) == 0) {
1000 serial_outp(up, UART_EFR, 0xA8);
1001 if (serial_in(up, UART_EFR) != 0) {
1002 DEBUG_AUTOCONF("EFRv1 ");
1003 up->port.type = PORT_16650;
1004 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1005 } else {
1006 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1007 }
1008 serial_outp(up, UART_EFR, 0);
1009 return;
1010 }
1011
1012 /*
1013 * Maybe it requires 0xbf to be written to the LCR.
1014 * (other ST16C650V2 UARTs, TI16C752A, etc)
1015 */
1016 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1017 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1018 DEBUG_AUTOCONF("EFRv2 ");
1019 autoconfig_has_efr(up);
1020 return;
1021 }
1022
1023 /*
1024 * Check for a National Semiconductor SuperIO chip.
1025 * Attempt to switch to bank 2, read the value of the LOOP bit
1026 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1027 * switch back to bank 2, read it from EXCR1 again and check
1028 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1029 */
1030 serial_outp(up, UART_LCR, 0);
1031 status1 = serial_in(up, UART_MCR);
1032 serial_outp(up, UART_LCR, 0xE0);
1033 status2 = serial_in(up, 0x02); /* EXCR1 */
1034
1035 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1036 serial_outp(up, UART_LCR, 0);
1037 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1038 serial_outp(up, UART_LCR, 0xE0);
1039 status2 = serial_in(up, 0x02); /* EXCR1 */
1040 serial_outp(up, UART_LCR, 0);
1041 serial_outp(up, UART_MCR, status1);
1042
1043 if ((status2 ^ status1) & UART_MCR_LOOP) {
1044 unsigned short quot;
1045
1046 serial_outp(up, UART_LCR, 0xE0);
1047
1048 quot = serial_dl_read(up);
1049 quot <<= 3;
1050
1051 if (ns16550a_goto_highspeed(up))
1052 serial_dl_write(up, quot);
1053
1054 serial_outp(up, UART_LCR, 0);
1055
1056 up->port.uartclk = 921600*16;
1057 up->port.type = PORT_NS16550A;
1058 up->capabilities |= UART_NATSEMI;
1059 return;
1060 }
1061 }
1062
1063 /*
1064 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1065 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1066 * Try setting it with and without DLAB set. Cheap clones
1067 * set bit 5 without DLAB set.
1068 */
1069 serial_outp(up, UART_LCR, 0);
1070 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1071 status1 = serial_in(up, UART_IIR) >> 5;
1072 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1073 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1074 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1075 status2 = serial_in(up, UART_IIR) >> 5;
1076 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1077 serial_outp(up, UART_LCR, 0);
1078
1079 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1080
1081 if (status1 == 6 && status2 == 7) {
1082 up->port.type = PORT_16750;
1083 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1084 return;
1085 }
1086
1087 /*
1088 * Try writing and reading the UART_IER_UUE bit (b6).
1089 * If it works, this is probably one of the Xscale platform's
1090 * internal UARTs.
1091 * We're going to explicitly set the UUE bit to 0 before
1092 * trying to write and read a 1 just to make sure it's not
1093 * already a 1 and maybe locked there before we even start start.
1094 */
1095 iersave = serial_in(up, UART_IER);
1096 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1097 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1098 /*
1099 * OK it's in a known zero state, try writing and reading
1100 * without disturbing the current state of the other bits.
1101 */
1102 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1103 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1104 /*
1105 * It's an Xscale.
1106 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1107 */
1108 DEBUG_AUTOCONF("Xscale ");
1109 up->port.type = PORT_XSCALE;
1110 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1111 return;
1112 }
1113 } else {
1114 /*
1115 * If we got here we couldn't force the IER_UUE bit to 0.
1116 * Log it and continue.
1117 */
1118 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1119 }
1120 serial_outp(up, UART_IER, iersave);
1121
1122 /*
1123 * We distinguish between 16550A and U6 16550A by counting
1124 * how many bytes are in the FIFO.
1125 */
1126 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1127 up->port.type = PORT_U6_16550A;
1128 up->capabilities |= UART_CAP_AFE;
1129 }
1130 }
1131
1132 /*
1133 * This routine is called by rs_init() to initialize a specific serial
1134 * port. It determines what type of UART chip this serial port is
1135 * using: 8250, 16450, 16550, 16550A. The important question is
1136 * whether or not this UART is a 16550A or not, since this will
1137 * determine whether or not we can use its FIFO features or not.
1138 */
1139 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1140 {
1141 unsigned char status1, scratch, scratch2, scratch3;
1142 unsigned char save_lcr, save_mcr;
1143 unsigned long flags;
1144
1145 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1146 return;
1147
1148 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1149 serial_index(&up->port), up->port.iobase, up->port.membase);
1150
1151 /*
1152 * We really do need global IRQs disabled here - we're going to
1153 * be frobbing the chips IRQ enable register to see if it exists.
1154 */
1155 spin_lock_irqsave(&up->port.lock, flags);
1156
1157 up->capabilities = 0;
1158 up->bugs = 0;
1159
1160 if (!(up->port.flags & UPF_BUGGY_UART)) {
1161 /*
1162 * Do a simple existence test first; if we fail this,
1163 * there's no point trying anything else.
1164 *
1165 * 0x80 is used as a nonsense port to prevent against
1166 * false positives due to ISA bus float. The
1167 * assumption is that 0x80 is a non-existent port;
1168 * which should be safe since include/asm/io.h also
1169 * makes this assumption.
1170 *
1171 * Note: this is safe as long as MCR bit 4 is clear
1172 * and the device is in "PC" mode.
1173 */
1174 scratch = serial_inp(up, UART_IER);
1175 serial_outp(up, UART_IER, 0);
1176 #ifdef __i386__
1177 outb(0xff, 0x080);
1178 #endif
1179 /*
1180 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1181 * 16C754B) allow only to modify them if an EFR bit is set.
1182 */
1183 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1184 serial_outp(up, UART_IER, 0x0F);
1185 #ifdef __i386__
1186 outb(0, 0x080);
1187 #endif
1188 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1189 serial_outp(up, UART_IER, scratch);
1190 if (scratch2 != 0 || scratch3 != 0x0F) {
1191 /*
1192 * We failed; there's nothing here
1193 */
1194 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1195 scratch2, scratch3);
1196 goto out;
1197 }
1198 }
1199
1200 save_mcr = serial_in(up, UART_MCR);
1201 save_lcr = serial_in(up, UART_LCR);
1202
1203 /*
1204 * Check to see if a UART is really there. Certain broken
1205 * internal modems based on the Rockwell chipset fail this
1206 * test, because they apparently don't implement the loopback
1207 * test mode. So this test is skipped on the COM 1 through
1208 * COM 4 ports. This *should* be safe, since no board
1209 * manufacturer would be stupid enough to design a board
1210 * that conflicts with COM 1-4 --- we hope!
1211 */
1212 if (!(up->port.flags & UPF_SKIP_TEST)) {
1213 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1214 status1 = serial_inp(up, UART_MSR) & 0xF0;
1215 serial_outp(up, UART_MCR, save_mcr);
1216 if (status1 != 0x90) {
1217 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1218 status1);
1219 goto out;
1220 }
1221 }
1222
1223 /*
1224 * We're pretty sure there's a port here. Lets find out what
1225 * type of port it is. The IIR top two bits allows us to find
1226 * out if it's 8250 or 16450, 16550, 16550A or later. This
1227 * determines what we test for next.
1228 *
1229 * We also initialise the EFR (if any) to zero for later. The
1230 * EFR occupies the same register location as the FCR and IIR.
1231 */
1232 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1233 serial_outp(up, UART_EFR, 0);
1234 serial_outp(up, UART_LCR, 0);
1235
1236 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1237 scratch = serial_in(up, UART_IIR) >> 6;
1238
1239 DEBUG_AUTOCONF("iir=%d ", scratch);
1240
1241 switch (scratch) {
1242 case 0:
1243 autoconfig_8250(up);
1244 break;
1245 case 1:
1246 up->port.type = PORT_UNKNOWN;
1247 break;
1248 case 2:
1249 up->port.type = PORT_16550;
1250 break;
1251 case 3:
1252 autoconfig_16550a(up);
1253 break;
1254 }
1255
1256 #ifdef CONFIG_SERIAL_8250_RSA
1257 /*
1258 * Only probe for RSA ports if we got the region.
1259 */
1260 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1261 int i;
1262
1263 for (i = 0 ; i < probe_rsa_count; ++i) {
1264 if (probe_rsa[i] == up->port.iobase &&
1265 __enable_rsa(up)) {
1266 up->port.type = PORT_RSA;
1267 break;
1268 }
1269 }
1270 }
1271 #endif
1272
1273 serial_outp(up, UART_LCR, save_lcr);
1274
1275 if (up->capabilities != uart_config[up->port.type].flags) {
1276 printk(KERN_WARNING
1277 "ttyS%d: detected caps %08x should be %08x\n",
1278 serial_index(&up->port), up->capabilities,
1279 uart_config[up->port.type].flags);
1280 }
1281
1282 up->port.fifosize = uart_config[up->port.type].fifo_size;
1283 up->capabilities = uart_config[up->port.type].flags;
1284 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1285
1286 if (up->port.type == PORT_UNKNOWN)
1287 goto out;
1288
1289 /*
1290 * Reset the UART.
1291 */
1292 #ifdef CONFIG_SERIAL_8250_RSA
1293 if (up->port.type == PORT_RSA)
1294 serial_outp(up, UART_RSA_FRR, 0);
1295 #endif
1296 serial_outp(up, UART_MCR, save_mcr);
1297 serial8250_clear_fifos(up);
1298 serial_in(up, UART_RX);
1299 if (up->capabilities & UART_CAP_UUE)
1300 serial_outp(up, UART_IER, UART_IER_UUE);
1301 else
1302 serial_outp(up, UART_IER, 0);
1303
1304 out:
1305 spin_unlock_irqrestore(&up->port.lock, flags);
1306 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1307 }
1308
1309 static void autoconfig_irq(struct uart_8250_port *up)
1310 {
1311 unsigned char save_mcr, save_ier;
1312 unsigned char save_ICP = 0;
1313 unsigned int ICP = 0;
1314 unsigned long irqs;
1315 int irq;
1316
1317 if (up->port.flags & UPF_FOURPORT) {
1318 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1319 save_ICP = inb_p(ICP);
1320 outb_p(0x80, ICP);
1321 (void) inb_p(ICP);
1322 }
1323
1324 /* forget possible initially masked and pending IRQ */
1325 probe_irq_off(probe_irq_on());
1326 save_mcr = serial_inp(up, UART_MCR);
1327 save_ier = serial_inp(up, UART_IER);
1328 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1329
1330 irqs = probe_irq_on();
1331 serial_outp(up, UART_MCR, 0);
1332 udelay(10);
1333 if (up->port.flags & UPF_FOURPORT) {
1334 serial_outp(up, UART_MCR,
1335 UART_MCR_DTR | UART_MCR_RTS);
1336 } else {
1337 serial_outp(up, UART_MCR,
1338 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1339 }
1340 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1341 (void)serial_inp(up, UART_LSR);
1342 (void)serial_inp(up, UART_RX);
1343 (void)serial_inp(up, UART_IIR);
1344 (void)serial_inp(up, UART_MSR);
1345 serial_outp(up, UART_TX, 0xFF);
1346 udelay(20);
1347 irq = probe_irq_off(irqs);
1348
1349 serial_outp(up, UART_MCR, save_mcr);
1350 serial_outp(up, UART_IER, save_ier);
1351
1352 if (up->port.flags & UPF_FOURPORT)
1353 outb_p(save_ICP, ICP);
1354
1355 up->port.irq = (irq > 0) ? irq : 0;
1356 }
1357
1358 static inline void __stop_tx(struct uart_8250_port *p)
1359 {
1360 if (p->ier & UART_IER_THRI) {
1361 p->ier &= ~UART_IER_THRI;
1362 serial_out(p, UART_IER, p->ier);
1363 }
1364 }
1365
1366 static void serial8250_stop_tx(struct uart_port *port)
1367 {
1368 struct uart_8250_port *up =
1369 container_of(port, struct uart_8250_port, port);
1370
1371 __stop_tx(up);
1372
1373 /*
1374 * We really want to stop the transmitter from sending.
1375 */
1376 if (up->port.type == PORT_16C950) {
1377 up->acr |= UART_ACR_TXDIS;
1378 serial_icr_write(up, UART_ACR, up->acr);
1379 }
1380 }
1381
1382 static void transmit_chars(struct uart_8250_port *up);
1383
1384 static void serial8250_start_tx(struct uart_port *port)
1385 {
1386 struct uart_8250_port *up =
1387 container_of(port, struct uart_8250_port, port);
1388
1389 if (!(up->ier & UART_IER_THRI)) {
1390 up->ier |= UART_IER_THRI;
1391 serial_out(up, UART_IER, up->ier);
1392
1393 if (up->bugs & UART_BUG_TXEN) {
1394 unsigned char lsr;
1395 lsr = serial_in(up, UART_LSR);
1396 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1397 if ((up->port.type == PORT_RM9000) ?
1398 (lsr & UART_LSR_THRE) :
1399 (lsr & UART_LSR_TEMT))
1400 transmit_chars(up);
1401 }
1402 }
1403
1404 /*
1405 * Re-enable the transmitter if we disabled it.
1406 */
1407 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1408 up->acr &= ~UART_ACR_TXDIS;
1409 serial_icr_write(up, UART_ACR, up->acr);
1410 }
1411 }
1412
1413 static void serial8250_stop_rx(struct uart_port *port)
1414 {
1415 struct uart_8250_port *up =
1416 container_of(port, struct uart_8250_port, port);
1417
1418 up->ier &= ~UART_IER_RLSI;
1419 up->port.read_status_mask &= ~UART_LSR_DR;
1420 serial_out(up, UART_IER, up->ier);
1421 }
1422
1423 static void serial8250_enable_ms(struct uart_port *port)
1424 {
1425 struct uart_8250_port *up =
1426 container_of(port, struct uart_8250_port, port);
1427
1428 /* no MSR capabilities */
1429 if (up->bugs & UART_BUG_NOMSR)
1430 return;
1431
1432 up->ier |= UART_IER_MSI;
1433 serial_out(up, UART_IER, up->ier);
1434 }
1435
1436 /*
1437 * Clear the Tegra rx fifo after a break
1438 *
1439 * FIXME: This needs to become a port specific callback once we have a
1440 * framework for this
1441 */
1442 static void clear_rx_fifo(struct uart_8250_port *up)
1443 {
1444 unsigned int status, tmout = 10000;
1445 do {
1446 status = serial_in(up, UART_LSR);
1447 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1448 status = serial_in(up, UART_RX);
1449 else
1450 break;
1451 if (--tmout == 0)
1452 break;
1453 udelay(1);
1454 } while (1);
1455 }
1456
1457 static void
1458 receive_chars(struct uart_8250_port *up, unsigned int *status)
1459 {
1460 struct tty_struct *tty = up->port.state->port.tty;
1461 unsigned char ch, lsr = *status;
1462 int max_count = 256;
1463 char flag;
1464
1465 do {
1466 if (likely(lsr & UART_LSR_DR))
1467 ch = serial_inp(up, UART_RX);
1468 else
1469 /*
1470 * Intel 82571 has a Serial Over Lan device that will
1471 * set UART_LSR_BI without setting UART_LSR_DR when
1472 * it receives a break. To avoid reading from the
1473 * receive buffer without UART_LSR_DR bit set, we
1474 * just force the read character to be 0
1475 */
1476 ch = 0;
1477
1478 flag = TTY_NORMAL;
1479 up->port.icount.rx++;
1480
1481 lsr |= up->lsr_saved_flags;
1482 up->lsr_saved_flags = 0;
1483
1484 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1485 /*
1486 * For statistics only
1487 */
1488 if (lsr & UART_LSR_BI) {
1489 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1490 up->port.icount.brk++;
1491 /*
1492 * If tegra port then clear the rx fifo to
1493 * accept another break/character.
1494 */
1495 if (up->port.type == PORT_TEGRA)
1496 clear_rx_fifo(up);
1497
1498 /*
1499 * We do the SysRQ and SAK checking
1500 * here because otherwise the break
1501 * may get masked by ignore_status_mask
1502 * or read_status_mask.
1503 */
1504 if (uart_handle_break(&up->port))
1505 goto ignore_char;
1506 } else if (lsr & UART_LSR_PE)
1507 up->port.icount.parity++;
1508 else if (lsr & UART_LSR_FE)
1509 up->port.icount.frame++;
1510 if (lsr & UART_LSR_OE)
1511 up->port.icount.overrun++;
1512
1513 /*
1514 * Mask off conditions which should be ignored.
1515 */
1516 lsr &= up->port.read_status_mask;
1517
1518 if (lsr & UART_LSR_BI) {
1519 DEBUG_INTR("handling break....");
1520 flag = TTY_BREAK;
1521 } else if (lsr & UART_LSR_PE)
1522 flag = TTY_PARITY;
1523 else if (lsr & UART_LSR_FE)
1524 flag = TTY_FRAME;
1525 }
1526 if (uart_handle_sysrq_char(&up->port, ch))
1527 goto ignore_char;
1528
1529 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1530
1531 ignore_char:
1532 lsr = serial_inp(up, UART_LSR);
1533 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1534 spin_unlock(&up->port.lock);
1535 tty_flip_buffer_push(tty);
1536 spin_lock(&up->port.lock);
1537 *status = lsr;
1538 }
1539
1540 static void transmit_chars(struct uart_8250_port *up)
1541 {
1542 struct circ_buf *xmit = &up->port.state->xmit;
1543 int count;
1544
1545 if (up->port.x_char) {
1546 serial_outp(up, UART_TX, up->port.x_char);
1547 up->port.icount.tx++;
1548 up->port.x_char = 0;
1549 return;
1550 }
1551 if (uart_tx_stopped(&up->port)) {
1552 serial8250_stop_tx(&up->port);
1553 return;
1554 }
1555 if (uart_circ_empty(xmit)) {
1556 __stop_tx(up);
1557 return;
1558 }
1559
1560 count = up->tx_loadsz;
1561 do {
1562 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1563 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1564 up->port.icount.tx++;
1565 if (uart_circ_empty(xmit))
1566 break;
1567 } while (--count > 0);
1568
1569 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1570 uart_write_wakeup(&up->port);
1571
1572 DEBUG_INTR("THRE...");
1573
1574 if (uart_circ_empty(xmit))
1575 __stop_tx(up);
1576 }
1577
1578 static unsigned int check_modem_status(struct uart_8250_port *up)
1579 {
1580 unsigned int status = serial_in(up, UART_MSR);
1581
1582 status |= up->msr_saved_flags;
1583 up->msr_saved_flags = 0;
1584 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1585 up->port.state != NULL) {
1586 if (status & UART_MSR_TERI)
1587 up->port.icount.rng++;
1588 if (status & UART_MSR_DDSR)
1589 up->port.icount.dsr++;
1590 if (status & UART_MSR_DDCD)
1591 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1592 if (status & UART_MSR_DCTS)
1593 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1594
1595 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1596 }
1597
1598 return status;
1599 }
1600
1601 /*
1602 * This handles the interrupt from one port.
1603 */
1604 static void serial8250_handle_port(struct uart_8250_port *up)
1605 {
1606 unsigned int status;
1607 unsigned long flags;
1608
1609 spin_lock_irqsave(&up->port.lock, flags);
1610
1611 status = serial_inp(up, UART_LSR);
1612
1613 DEBUG_INTR("status = %x...", status);
1614
1615 if (status & (UART_LSR_DR | UART_LSR_BI))
1616 receive_chars(up, &status);
1617 check_modem_status(up);
1618 if (status & UART_LSR_THRE)
1619 transmit_chars(up);
1620
1621 spin_unlock_irqrestore(&up->port.lock, flags);
1622 }
1623
1624 /*
1625 * This is the serial driver's interrupt routine.
1626 *
1627 * Arjan thinks the old way was overly complex, so it got simplified.
1628 * Alan disagrees, saying that need the complexity to handle the weird
1629 * nature of ISA shared interrupts. (This is a special exception.)
1630 *
1631 * In order to handle ISA shared interrupts properly, we need to check
1632 * that all ports have been serviced, and therefore the ISA interrupt
1633 * line has been de-asserted.
1634 *
1635 * This means we need to loop through all ports. checking that they
1636 * don't have an interrupt pending.
1637 */
1638 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1639 {
1640 struct irq_info *i = dev_id;
1641 struct list_head *l, *end = NULL;
1642 int pass_counter = 0, handled = 0;
1643
1644 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1645
1646 spin_lock(&i->lock);
1647
1648 l = i->head;
1649 do {
1650 struct uart_8250_port *up;
1651 unsigned int iir;
1652
1653 up = list_entry(l, struct uart_8250_port, list);
1654
1655 iir = serial_in(up, UART_IIR);
1656 if (!(iir & UART_IIR_NO_INT)) {
1657 serial8250_handle_port(up);
1658
1659 handled = 1;
1660
1661 end = NULL;
1662 } else if ((up->port.iotype == UPIO_DWAPB ||
1663 up->port.iotype == UPIO_DWAPB32) &&
1664 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1665 /* The DesignWare APB UART has an Busy Detect (0x07)
1666 * interrupt meaning an LCR write attempt occurred while the
1667 * UART was busy. The interrupt must be cleared by reading
1668 * the UART status register (USR) and the LCR re-written. */
1669 unsigned int status;
1670 status = *(volatile u32 *)up->port.private_data;
1671 serial_out(up, UART_LCR, up->lcr);
1672
1673 handled = 1;
1674
1675 end = NULL;
1676 } else if (end == NULL)
1677 end = l;
1678
1679 l = l->next;
1680
1681 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1682 /* If we hit this, we're dead. */
1683 printk_ratelimited(KERN_ERR
1684 "serial8250: too much work for irq%d\n", irq);
1685 break;
1686 }
1687 } while (l != end);
1688
1689 spin_unlock(&i->lock);
1690
1691 DEBUG_INTR("end.\n");
1692
1693 return IRQ_RETVAL(handled);
1694 }
1695
1696 /*
1697 * To support ISA shared interrupts, we need to have one interrupt
1698 * handler that ensures that the IRQ line has been deasserted
1699 * before returning. Failing to do this will result in the IRQ
1700 * line being stuck active, and, since ISA irqs are edge triggered,
1701 * no more IRQs will be seen.
1702 */
1703 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1704 {
1705 spin_lock_irq(&i->lock);
1706
1707 if (!list_empty(i->head)) {
1708 if (i->head == &up->list)
1709 i->head = i->head->next;
1710 list_del(&up->list);
1711 } else {
1712 BUG_ON(i->head != &up->list);
1713 i->head = NULL;
1714 }
1715 spin_unlock_irq(&i->lock);
1716 /* List empty so throw away the hash node */
1717 if (i->head == NULL) {
1718 hlist_del(&i->node);
1719 kfree(i);
1720 }
1721 }
1722
1723 static int serial_link_irq_chain(struct uart_8250_port *up)
1724 {
1725 struct hlist_head *h;
1726 struct hlist_node *n;
1727 struct irq_info *i;
1728 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1729
1730 mutex_lock(&hash_mutex);
1731
1732 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1733
1734 hlist_for_each(n, h) {
1735 i = hlist_entry(n, struct irq_info, node);
1736 if (i->irq == up->port.irq)
1737 break;
1738 }
1739
1740 if (n == NULL) {
1741 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1742 if (i == NULL) {
1743 mutex_unlock(&hash_mutex);
1744 return -ENOMEM;
1745 }
1746 spin_lock_init(&i->lock);
1747 i->irq = up->port.irq;
1748 hlist_add_head(&i->node, h);
1749 }
1750 mutex_unlock(&hash_mutex);
1751
1752 spin_lock_irq(&i->lock);
1753
1754 if (i->head) {
1755 list_add(&up->list, i->head);
1756 spin_unlock_irq(&i->lock);
1757
1758 ret = 0;
1759 } else {
1760 INIT_LIST_HEAD(&up->list);
1761 i->head = &up->list;
1762 spin_unlock_irq(&i->lock);
1763 irq_flags |= up->port.irqflags;
1764 ret = request_irq(up->port.irq, serial8250_interrupt,
1765 irq_flags, "serial", i);
1766 if (ret < 0)
1767 serial_do_unlink(i, up);
1768 }
1769
1770 return ret;
1771 }
1772
1773 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1774 {
1775 struct irq_info *i;
1776 struct hlist_node *n;
1777 struct hlist_head *h;
1778
1779 mutex_lock(&hash_mutex);
1780
1781 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1782
1783 hlist_for_each(n, h) {
1784 i = hlist_entry(n, struct irq_info, node);
1785 if (i->irq == up->port.irq)
1786 break;
1787 }
1788
1789 BUG_ON(n == NULL);
1790 BUG_ON(i->head == NULL);
1791
1792 if (list_empty(i->head))
1793 free_irq(up->port.irq, i);
1794
1795 serial_do_unlink(i, up);
1796 mutex_unlock(&hash_mutex);
1797 }
1798
1799 /*
1800 * This function is used to handle ports that do not have an
1801 * interrupt. This doesn't work very well for 16450's, but gives
1802 * barely passable results for a 16550A. (Although at the expense
1803 * of much CPU overhead).
1804 */
1805 static void serial8250_timeout(unsigned long data)
1806 {
1807 struct uart_8250_port *up = (struct uart_8250_port *)data;
1808 unsigned int iir;
1809
1810 iir = serial_in(up, UART_IIR);
1811 if (!(iir & UART_IIR_NO_INT))
1812 serial8250_handle_port(up);
1813 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1814 }
1815
1816 static void serial8250_backup_timeout(unsigned long data)
1817 {
1818 struct uart_8250_port *up = (struct uart_8250_port *)data;
1819 unsigned int iir, ier = 0, lsr;
1820 unsigned long flags;
1821
1822 spin_lock_irqsave(&up->port.lock, flags);
1823
1824 /*
1825 * Must disable interrupts or else we risk racing with the interrupt
1826 * based handler.
1827 */
1828 if (is_real_interrupt(up->port.irq)) {
1829 ier = serial_in(up, UART_IER);
1830 serial_out(up, UART_IER, 0);
1831 }
1832
1833 iir = serial_in(up, UART_IIR);
1834
1835 /*
1836 * This should be a safe test for anyone who doesn't trust the
1837 * IIR bits on their UART, but it's specifically designed for
1838 * the "Diva" UART used on the management processor on many HP
1839 * ia64 and parisc boxes.
1840 */
1841 lsr = serial_in(up, UART_LSR);
1842 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1843 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1844 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1845 (lsr & UART_LSR_THRE)) {
1846 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1847 iir |= UART_IIR_THRI;
1848 }
1849
1850 if (!(iir & UART_IIR_NO_INT))
1851 transmit_chars(up);
1852
1853 if (is_real_interrupt(up->port.irq))
1854 serial_out(up, UART_IER, ier);
1855
1856 spin_unlock_irqrestore(&up->port.lock, flags);
1857
1858 /* Standard timer interval plus 0.2s to keep the port running */
1859 mod_timer(&up->timer,
1860 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1861 }
1862
1863 static unsigned int serial8250_tx_empty(struct uart_port *port)
1864 {
1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
1867 unsigned long flags;
1868 unsigned int lsr;
1869
1870 spin_lock_irqsave(&up->port.lock, flags);
1871 lsr = serial_in(up, UART_LSR);
1872 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1873 spin_unlock_irqrestore(&up->port.lock, flags);
1874
1875 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1876 }
1877
1878 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1879 {
1880 struct uart_8250_port *up =
1881 container_of(port, struct uart_8250_port, port);
1882 unsigned int status;
1883 unsigned int ret;
1884
1885 status = check_modem_status(up);
1886
1887 ret = 0;
1888 if (status & UART_MSR_DCD)
1889 ret |= TIOCM_CAR;
1890 if (status & UART_MSR_RI)
1891 ret |= TIOCM_RNG;
1892 if (status & UART_MSR_DSR)
1893 ret |= TIOCM_DSR;
1894 if (status & UART_MSR_CTS)
1895 ret |= TIOCM_CTS;
1896 return ret;
1897 }
1898
1899 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1900 {
1901 struct uart_8250_port *up =
1902 container_of(port, struct uart_8250_port, port);
1903 unsigned char mcr = 0;
1904
1905 if (mctrl & TIOCM_RTS)
1906 mcr |= UART_MCR_RTS;
1907 if (mctrl & TIOCM_DTR)
1908 mcr |= UART_MCR_DTR;
1909 if (mctrl & TIOCM_OUT1)
1910 mcr |= UART_MCR_OUT1;
1911 if (mctrl & TIOCM_OUT2)
1912 mcr |= UART_MCR_OUT2;
1913 if (mctrl & TIOCM_LOOP)
1914 mcr |= UART_MCR_LOOP;
1915
1916 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1917
1918 serial_out(up, UART_MCR, mcr);
1919 }
1920
1921 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1922 {
1923 struct uart_8250_port *up =
1924 container_of(port, struct uart_8250_port, port);
1925 unsigned long flags;
1926
1927 spin_lock_irqsave(&up->port.lock, flags);
1928 if (break_state == -1)
1929 up->lcr |= UART_LCR_SBC;
1930 else
1931 up->lcr &= ~UART_LCR_SBC;
1932 serial_out(up, UART_LCR, up->lcr);
1933 spin_unlock_irqrestore(&up->port.lock, flags);
1934 }
1935
1936 /*
1937 * Wait for transmitter & holding register to empty
1938 */
1939 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1940 {
1941 unsigned int status, tmout = 10000;
1942
1943 /* Wait up to 10ms for the character(s) to be sent. */
1944 for (;;) {
1945 status = serial_in(up, UART_LSR);
1946
1947 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1948
1949 if ((status & bits) == bits)
1950 break;
1951 if (--tmout == 0)
1952 break;
1953 udelay(1);
1954 }
1955
1956 /* Wait up to 1s for flow control if necessary */
1957 if (up->port.flags & UPF_CONS_FLOW) {
1958 unsigned int tmout;
1959 for (tmout = 1000000; tmout; tmout--) {
1960 unsigned int msr = serial_in(up, UART_MSR);
1961 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1962 if (msr & UART_MSR_CTS)
1963 break;
1964 udelay(1);
1965 touch_nmi_watchdog();
1966 }
1967 }
1968 }
1969
1970 #ifdef CONFIG_CONSOLE_POLL
1971 /*
1972 * Console polling routines for writing and reading from the uart while
1973 * in an interrupt or debug context.
1974 */
1975
1976 static int serial8250_get_poll_char(struct uart_port *port)
1977 {
1978 struct uart_8250_port *up =
1979 container_of(port, struct uart_8250_port, port);
1980 unsigned char lsr = serial_inp(up, UART_LSR);
1981
1982 if (!(lsr & UART_LSR_DR))
1983 return NO_POLL_CHAR;
1984
1985 return serial_inp(up, UART_RX);
1986 }
1987
1988
1989 static void serial8250_put_poll_char(struct uart_port *port,
1990 unsigned char c)
1991 {
1992 unsigned int ier;
1993 struct uart_8250_port *up =
1994 container_of(port, struct uart_8250_port, port);
1995
1996 /*
1997 * First save the IER then disable the interrupts
1998 */
1999 ier = serial_in(up, UART_IER);
2000 if (up->capabilities & UART_CAP_UUE)
2001 serial_out(up, UART_IER, UART_IER_UUE);
2002 else
2003 serial_out(up, UART_IER, 0);
2004
2005 wait_for_xmitr(up, BOTH_EMPTY);
2006 /*
2007 * Send the character out.
2008 * If a LF, also do CR...
2009 */
2010 serial_out(up, UART_TX, c);
2011 if (c == 10) {
2012 wait_for_xmitr(up, BOTH_EMPTY);
2013 serial_out(up, UART_TX, 13);
2014 }
2015
2016 /*
2017 * Finally, wait for transmitter to become empty
2018 * and restore the IER
2019 */
2020 wait_for_xmitr(up, BOTH_EMPTY);
2021 serial_out(up, UART_IER, ier);
2022 }
2023
2024 #endif /* CONFIG_CONSOLE_POLL */
2025
2026 static int serial8250_startup(struct uart_port *port)
2027 {
2028 struct uart_8250_port *up =
2029 container_of(port, struct uart_8250_port, port);
2030 unsigned long flags;
2031 unsigned char lsr, iir;
2032 int retval;
2033
2034 up->port.fifosize = uart_config[up->port.type].fifo_size;
2035 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2036 up->capabilities = uart_config[up->port.type].flags;
2037 up->mcr = 0;
2038
2039 if (up->port.iotype != up->cur_iotype)
2040 set_io_from_upio(port);
2041
2042 if (up->port.type == PORT_16C950) {
2043 /* Wake up and initialize UART */
2044 up->acr = 0;
2045 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2046 serial_outp(up, UART_EFR, UART_EFR_ECB);
2047 serial_outp(up, UART_IER, 0);
2048 serial_outp(up, UART_LCR, 0);
2049 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2050 serial_outp(up, UART_LCR, 0xBF);
2051 serial_outp(up, UART_EFR, UART_EFR_ECB);
2052 serial_outp(up, UART_LCR, 0);
2053 }
2054
2055 #ifdef CONFIG_SERIAL_8250_RSA
2056 /*
2057 * If this is an RSA port, see if we can kick it up to the
2058 * higher speed clock.
2059 */
2060 enable_rsa(up);
2061 #endif
2062
2063 /*
2064 * Clear the FIFO buffers and disable them.
2065 * (they will be reenabled in set_termios())
2066 */
2067 serial8250_clear_fifos(up);
2068
2069 /*
2070 * Clear the interrupt registers.
2071 */
2072 (void) serial_inp(up, UART_LSR);
2073 (void) serial_inp(up, UART_RX);
2074 (void) serial_inp(up, UART_IIR);
2075 (void) serial_inp(up, UART_MSR);
2076
2077 /*
2078 * At this point, there's no way the LSR could still be 0xff;
2079 * if it is, then bail out, because there's likely no UART
2080 * here.
2081 */
2082 if (!(up->port.flags & UPF_BUGGY_UART) &&
2083 (serial_inp(up, UART_LSR) == 0xff)) {
2084 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2085 serial_index(&up->port));
2086 return -ENODEV;
2087 }
2088
2089 /*
2090 * For a XR16C850, we need to set the trigger levels
2091 */
2092 if (up->port.type == PORT_16850) {
2093 unsigned char fctr;
2094
2095 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2096
2097 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2098 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2099 serial_outp(up, UART_TRG, UART_TRG_96);
2100 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2101 serial_outp(up, UART_TRG, UART_TRG_96);
2102
2103 serial_outp(up, UART_LCR, 0);
2104 }
2105
2106 if (is_real_interrupt(up->port.irq)) {
2107 unsigned char iir1;
2108 /*
2109 * Test for UARTs that do not reassert THRE when the
2110 * transmitter is idle and the interrupt has already
2111 * been cleared. Real 16550s should always reassert
2112 * this interrupt whenever the transmitter is idle and
2113 * the interrupt is enabled. Delays are necessary to
2114 * allow register changes to become visible.
2115 */
2116 spin_lock_irqsave(&up->port.lock, flags);
2117 if (up->port.irqflags & IRQF_SHARED)
2118 disable_irq_nosync(up->port.irq);
2119
2120 wait_for_xmitr(up, UART_LSR_THRE);
2121 serial_out_sync(up, UART_IER, UART_IER_THRI);
2122 udelay(1); /* allow THRE to set */
2123 iir1 = serial_in(up, UART_IIR);
2124 serial_out(up, UART_IER, 0);
2125 serial_out_sync(up, UART_IER, UART_IER_THRI);
2126 udelay(1); /* allow a working UART time to re-assert THRE */
2127 iir = serial_in(up, UART_IIR);
2128 serial_out(up, UART_IER, 0);
2129
2130 if (up->port.irqflags & IRQF_SHARED)
2131 enable_irq(up->port.irq);
2132 spin_unlock_irqrestore(&up->port.lock, flags);
2133
2134 /*
2135 * If the interrupt is not reasserted, setup a timer to
2136 * kick the UART on a regular basis.
2137 */
2138 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2139 up->bugs |= UART_BUG_THRE;
2140 pr_debug("ttyS%d - using backup timer\n",
2141 serial_index(port));
2142 }
2143 }
2144
2145 /*
2146 * The above check will only give an accurate result the first time
2147 * the port is opened so this value needs to be preserved.
2148 */
2149 if (up->bugs & UART_BUG_THRE) {
2150 up->timer.function = serial8250_backup_timeout;
2151 up->timer.data = (unsigned long)up;
2152 mod_timer(&up->timer, jiffies +
2153 uart_poll_timeout(port) + HZ / 5);
2154 }
2155
2156 /*
2157 * If the "interrupt" for this port doesn't correspond with any
2158 * hardware interrupt, we use a timer-based system. The original
2159 * driver used to do this with IRQ0.
2160 */
2161 if (!is_real_interrupt(up->port.irq)) {
2162 up->timer.data = (unsigned long)up;
2163 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2164 } else {
2165 retval = serial_link_irq_chain(up);
2166 if (retval)
2167 return retval;
2168 }
2169
2170 /*
2171 * Now, initialize the UART
2172 */
2173 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2174
2175 spin_lock_irqsave(&up->port.lock, flags);
2176 if (up->port.flags & UPF_FOURPORT) {
2177 if (!is_real_interrupt(up->port.irq))
2178 up->port.mctrl |= TIOCM_OUT1;
2179 } else
2180 /*
2181 * Most PC uarts need OUT2 raised to enable interrupts.
2182 */
2183 if (is_real_interrupt(up->port.irq))
2184 up->port.mctrl |= TIOCM_OUT2;
2185
2186 serial8250_set_mctrl(&up->port, up->port.mctrl);
2187
2188 /* Serial over Lan (SoL) hack:
2189 Intel 8257x Gigabit ethernet chips have a
2190 16550 emulation, to be used for Serial Over Lan.
2191 Those chips take a longer time than a normal
2192 serial device to signalize that a transmission
2193 data was queued. Due to that, the above test generally
2194 fails. One solution would be to delay the reading of
2195 iir. However, this is not reliable, since the timeout
2196 is variable. So, let's just don't test if we receive
2197 TX irq. This way, we'll never enable UART_BUG_TXEN.
2198 */
2199 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2200 goto dont_test_tx_en;
2201
2202 /*
2203 * Do a quick test to see if we receive an
2204 * interrupt when we enable the TX irq.
2205 */
2206 serial_outp(up, UART_IER, UART_IER_THRI);
2207 lsr = serial_in(up, UART_LSR);
2208 iir = serial_in(up, UART_IIR);
2209 serial_outp(up, UART_IER, 0);
2210
2211 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2212 if (!(up->bugs & UART_BUG_TXEN)) {
2213 up->bugs |= UART_BUG_TXEN;
2214 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2215 serial_index(port));
2216 }
2217 } else {
2218 up->bugs &= ~UART_BUG_TXEN;
2219 }
2220
2221 dont_test_tx_en:
2222 spin_unlock_irqrestore(&up->port.lock, flags);
2223
2224 /*
2225 * Clear the interrupt registers again for luck, and clear the
2226 * saved flags to avoid getting false values from polling
2227 * routines or the previous session.
2228 */
2229 serial_inp(up, UART_LSR);
2230 serial_inp(up, UART_RX);
2231 serial_inp(up, UART_IIR);
2232 serial_inp(up, UART_MSR);
2233 up->lsr_saved_flags = 0;
2234 up->msr_saved_flags = 0;
2235
2236 /*
2237 * Finally, enable interrupts. Note: Modem status interrupts
2238 * are set via set_termios(), which will be occurring imminently
2239 * anyway, so we don't enable them here.
2240 */
2241 up->ier = UART_IER_RLSI | UART_IER_RDI;
2242 serial_outp(up, UART_IER, up->ier);
2243
2244 if (up->port.flags & UPF_FOURPORT) {
2245 unsigned int icp;
2246 /*
2247 * Enable interrupts on the AST Fourport board
2248 */
2249 icp = (up->port.iobase & 0xfe0) | 0x01f;
2250 outb_p(0x80, icp);
2251 (void) inb_p(icp);
2252 }
2253
2254 return 0;
2255 }
2256
2257 static void serial8250_shutdown(struct uart_port *port)
2258 {
2259 struct uart_8250_port *up =
2260 container_of(port, struct uart_8250_port, port);
2261 unsigned long flags;
2262
2263 /*
2264 * Disable interrupts from this port
2265 */
2266 up->ier = 0;
2267 serial_outp(up, UART_IER, 0);
2268
2269 spin_lock_irqsave(&up->port.lock, flags);
2270 if (up->port.flags & UPF_FOURPORT) {
2271 /* reset interrupts on the AST Fourport board */
2272 inb((up->port.iobase & 0xfe0) | 0x1f);
2273 up->port.mctrl |= TIOCM_OUT1;
2274 } else
2275 up->port.mctrl &= ~TIOCM_OUT2;
2276
2277 serial8250_set_mctrl(&up->port, up->port.mctrl);
2278 spin_unlock_irqrestore(&up->port.lock, flags);
2279
2280 /*
2281 * Disable break condition and FIFOs
2282 */
2283 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2284 serial8250_clear_fifos(up);
2285
2286 #ifdef CONFIG_SERIAL_8250_RSA
2287 /*
2288 * Reset the RSA board back to 115kbps compat mode.
2289 */
2290 disable_rsa(up);
2291 #endif
2292
2293 /*
2294 * Read data port to reset things, and then unlink from
2295 * the IRQ chain.
2296 */
2297 (void) serial_in(up, UART_RX);
2298
2299 del_timer_sync(&up->timer);
2300 up->timer.function = serial8250_timeout;
2301 if (is_real_interrupt(up->port.irq))
2302 serial_unlink_irq_chain(up);
2303 }
2304
2305 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2306 {
2307 unsigned int quot;
2308
2309 /*
2310 * Handle magic divisors for baud rates above baud_base on
2311 * SMSC SuperIO chips.
2312 */
2313 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2314 baud == (port->uartclk/4))
2315 quot = 0x8001;
2316 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2317 baud == (port->uartclk/8))
2318 quot = 0x8002;
2319 else
2320 quot = uart_get_divisor(port, baud);
2321
2322 return quot;
2323 }
2324
2325 void
2326 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2327 struct ktermios *old)
2328 {
2329 struct uart_8250_port *up =
2330 container_of(port, struct uart_8250_port, port);
2331 unsigned char cval, fcr = 0;
2332 unsigned long flags;
2333 unsigned int baud, quot;
2334
2335 switch (termios->c_cflag & CSIZE) {
2336 case CS5:
2337 cval = UART_LCR_WLEN5;
2338 break;
2339 case CS6:
2340 cval = UART_LCR_WLEN6;
2341 break;
2342 case CS7:
2343 cval = UART_LCR_WLEN7;
2344 break;
2345 default:
2346 case CS8:
2347 cval = UART_LCR_WLEN8;
2348 break;
2349 }
2350
2351 if (termios->c_cflag & CSTOPB)
2352 cval |= UART_LCR_STOP;
2353 if (termios->c_cflag & PARENB)
2354 cval |= UART_LCR_PARITY;
2355 if (!(termios->c_cflag & PARODD))
2356 cval |= UART_LCR_EPAR;
2357 #ifdef CMSPAR
2358 if (termios->c_cflag & CMSPAR)
2359 cval |= UART_LCR_SPAR;
2360 #endif
2361
2362 /*
2363 * Ask the core to calculate the divisor for us.
2364 */
2365 baud = uart_get_baud_rate(port, termios, old,
2366 port->uartclk / 16 / 0xffff,
2367 port->uartclk / 16);
2368 quot = serial8250_get_divisor(port, baud);
2369
2370 /*
2371 * Oxford Semi 952 rev B workaround
2372 */
2373 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2374 quot++;
2375
2376 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2377 if (baud < 2400)
2378 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2379 else
2380 fcr = uart_config[up->port.type].fcr;
2381 }
2382
2383 /*
2384 * MCR-based auto flow control. When AFE is enabled, RTS will be
2385 * deasserted when the receive FIFO contains more characters than
2386 * the trigger, or the MCR RTS bit is cleared. In the case where
2387 * the remote UART is not using CTS auto flow control, we must
2388 * have sufficient FIFO entries for the latency of the remote
2389 * UART to respond. IOW, at least 32 bytes of FIFO.
2390 */
2391 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2392 up->mcr &= ~UART_MCR_AFE;
2393 if (termios->c_cflag & CRTSCTS)
2394 up->mcr |= UART_MCR_AFE;
2395 }
2396
2397 /*
2398 * Ok, we're now changing the port state. Do it with
2399 * interrupts disabled.
2400 */
2401 spin_lock_irqsave(&up->port.lock, flags);
2402
2403 /*
2404 * Update the per-port timeout.
2405 */
2406 uart_update_timeout(port, termios->c_cflag, baud);
2407
2408 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2409 if (termios->c_iflag & INPCK)
2410 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2411 if (termios->c_iflag & (BRKINT | PARMRK))
2412 up->port.read_status_mask |= UART_LSR_BI;
2413
2414 /*
2415 * Characteres to ignore
2416 */
2417 up->port.ignore_status_mask = 0;
2418 if (termios->c_iflag & IGNPAR)
2419 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2420 if (termios->c_iflag & IGNBRK) {
2421 up->port.ignore_status_mask |= UART_LSR_BI;
2422 /*
2423 * If we're ignoring parity and break indicators,
2424 * ignore overruns too (for real raw support).
2425 */
2426 if (termios->c_iflag & IGNPAR)
2427 up->port.ignore_status_mask |= UART_LSR_OE;
2428 }
2429
2430 /*
2431 * ignore all characters if CREAD is not set
2432 */
2433 if ((termios->c_cflag & CREAD) == 0)
2434 up->port.ignore_status_mask |= UART_LSR_DR;
2435
2436 /*
2437 * CTS flow control flag and modem status interrupts
2438 */
2439 up->ier &= ~UART_IER_MSI;
2440 if (!(up->bugs & UART_BUG_NOMSR) &&
2441 UART_ENABLE_MS(&up->port, termios->c_cflag))
2442 up->ier |= UART_IER_MSI;
2443 if (up->capabilities & UART_CAP_UUE)
2444 up->ier |= UART_IER_UUE;
2445 if (up->capabilities & UART_CAP_RTOIE)
2446 up->ier |= UART_IER_RTOIE;
2447
2448 serial_out(up, UART_IER, up->ier);
2449
2450 if (up->capabilities & UART_CAP_EFR) {
2451 unsigned char efr = 0;
2452 /*
2453 * TI16C752/Startech hardware flow control. FIXME:
2454 * - TI16C752 requires control thresholds to be set.
2455 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2456 */
2457 if (termios->c_cflag & CRTSCTS)
2458 efr |= UART_EFR_CTS;
2459
2460 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2461 serial_outp(up, UART_EFR, efr);
2462 }
2463
2464 #ifdef CONFIG_ARCH_OMAP
2465 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2466 if (cpu_is_omap1510() && is_omap_port(up)) {
2467 if (baud == 115200) {
2468 quot = 1;
2469 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2470 } else
2471 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2472 }
2473 #endif
2474
2475 if (up->capabilities & UART_NATSEMI) {
2476 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2477 serial_outp(up, UART_LCR, 0xe0);
2478 } else {
2479 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2480 }
2481
2482 serial_dl_write(up, quot);
2483
2484 /*
2485 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2486 * is written without DLAB set, this mode will be disabled.
2487 */
2488 if (up->port.type == PORT_16750)
2489 serial_outp(up, UART_FCR, fcr);
2490
2491 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2492 up->lcr = cval; /* Save LCR */
2493 if (up->port.type != PORT_16750) {
2494 if (fcr & UART_FCR_ENABLE_FIFO) {
2495 /* emulated UARTs (Lucent Venus 167x) need two steps */
2496 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2497 }
2498 serial_outp(up, UART_FCR, fcr); /* set fcr */
2499 }
2500 serial8250_set_mctrl(&up->port, up->port.mctrl);
2501 spin_unlock_irqrestore(&up->port.lock, flags);
2502 /* Don't rewrite B0 */
2503 if (tty_termios_baud_rate(termios))
2504 tty_termios_encode_baud_rate(termios, baud, baud);
2505 }
2506 EXPORT_SYMBOL(serial8250_do_set_termios);
2507
2508 static void
2509 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2510 struct ktermios *old)
2511 {
2512 if (port->set_termios)
2513 port->set_termios(port, termios, old);
2514 else
2515 serial8250_do_set_termios(port, termios, old);
2516 }
2517
2518 static void
2519 serial8250_set_ldisc(struct uart_port *port, int new)
2520 {
2521 if (new == N_PPS) {
2522 port->flags |= UPF_HARDPPS_CD;
2523 serial8250_enable_ms(port);
2524 } else
2525 port->flags &= ~UPF_HARDPPS_CD;
2526 }
2527
2528
2529 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2530 unsigned int oldstate)
2531 {
2532 struct uart_8250_port *p =
2533 container_of(port, struct uart_8250_port, port);
2534
2535 serial8250_set_sleep(p, state != 0);
2536 }
2537 EXPORT_SYMBOL(serial8250_do_pm);
2538
2539 static void
2540 serial8250_pm(struct uart_port *port, unsigned int state,
2541 unsigned int oldstate)
2542 {
2543 if (port->pm)
2544 port->pm(port, state, oldstate);
2545 else
2546 serial8250_do_pm(port, state, oldstate);
2547 }
2548
2549 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2550 {
2551 if (pt->port.iotype == UPIO_AU)
2552 return 0x1000;
2553 #ifdef CONFIG_ARCH_OMAP
2554 if (is_omap_port(pt))
2555 return 0x16 << pt->port.regshift;
2556 #endif
2557 return 8 << pt->port.regshift;
2558 }
2559
2560 /*
2561 * Resource handling.
2562 */
2563 static int serial8250_request_std_resource(struct uart_8250_port *up)
2564 {
2565 unsigned int size = serial8250_port_size(up);
2566 int ret = 0;
2567
2568 switch (up->port.iotype) {
2569 case UPIO_AU:
2570 case UPIO_TSI:
2571 case UPIO_MEM32:
2572 case UPIO_MEM:
2573 case UPIO_DWAPB:
2574 case UPIO_DWAPB32:
2575 if (!up->port.mapbase)
2576 break;
2577
2578 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2579 ret = -EBUSY;
2580 break;
2581 }
2582
2583 if (up->port.flags & UPF_IOREMAP) {
2584 up->port.membase = ioremap_nocache(up->port.mapbase,
2585 size);
2586 if (!up->port.membase) {
2587 release_mem_region(up->port.mapbase, size);
2588 ret = -ENOMEM;
2589 }
2590 }
2591 break;
2592
2593 case UPIO_HUB6:
2594 case UPIO_PORT:
2595 if (!request_region(up->port.iobase, size, "serial"))
2596 ret = -EBUSY;
2597 break;
2598 }
2599 return ret;
2600 }
2601
2602 static void serial8250_release_std_resource(struct uart_8250_port *up)
2603 {
2604 unsigned int size = serial8250_port_size(up);
2605
2606 switch (up->port.iotype) {
2607 case UPIO_AU:
2608 case UPIO_TSI:
2609 case UPIO_MEM32:
2610 case UPIO_MEM:
2611 case UPIO_DWAPB:
2612 case UPIO_DWAPB32:
2613 if (!up->port.mapbase)
2614 break;
2615
2616 if (up->port.flags & UPF_IOREMAP) {
2617 iounmap(up->port.membase);
2618 up->port.membase = NULL;
2619 }
2620
2621 release_mem_region(up->port.mapbase, size);
2622 break;
2623
2624 case UPIO_HUB6:
2625 case UPIO_PORT:
2626 release_region(up->port.iobase, size);
2627 break;
2628 }
2629 }
2630
2631 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2632 {
2633 unsigned long start = UART_RSA_BASE << up->port.regshift;
2634 unsigned int size = 8 << up->port.regshift;
2635 int ret = -EINVAL;
2636
2637 switch (up->port.iotype) {
2638 case UPIO_HUB6:
2639 case UPIO_PORT:
2640 start += up->port.iobase;
2641 if (request_region(start, size, "serial-rsa"))
2642 ret = 0;
2643 else
2644 ret = -EBUSY;
2645 break;
2646 }
2647
2648 return ret;
2649 }
2650
2651 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2652 {
2653 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2654 unsigned int size = 8 << up->port.regshift;
2655
2656 switch (up->port.iotype) {
2657 case UPIO_HUB6:
2658 case UPIO_PORT:
2659 release_region(up->port.iobase + offset, size);
2660 break;
2661 }
2662 }
2663
2664 static void serial8250_release_port(struct uart_port *port)
2665 {
2666 struct uart_8250_port *up =
2667 container_of(port, struct uart_8250_port, port);
2668
2669 serial8250_release_std_resource(up);
2670 if (up->port.type == PORT_RSA)
2671 serial8250_release_rsa_resource(up);
2672 }
2673
2674 static int serial8250_request_port(struct uart_port *port)
2675 {
2676 struct uart_8250_port *up =
2677 container_of(port, struct uart_8250_port, port);
2678 int ret = 0;
2679
2680 ret = serial8250_request_std_resource(up);
2681 if (ret == 0 && up->port.type == PORT_RSA) {
2682 ret = serial8250_request_rsa_resource(up);
2683 if (ret < 0)
2684 serial8250_release_std_resource(up);
2685 }
2686
2687 return ret;
2688 }
2689
2690 static void serial8250_config_port(struct uart_port *port, int flags)
2691 {
2692 struct uart_8250_port *up =
2693 container_of(port, struct uart_8250_port, port);
2694 int probeflags = PROBE_ANY;
2695 int ret;
2696
2697 /*
2698 * Find the region that we can probe for. This in turn
2699 * tells us whether we can probe for the type of port.
2700 */
2701 ret = serial8250_request_std_resource(up);
2702 if (ret < 0)
2703 return;
2704
2705 ret = serial8250_request_rsa_resource(up);
2706 if (ret < 0)
2707 probeflags &= ~PROBE_RSA;
2708
2709 if (up->port.iotype != up->cur_iotype)
2710 set_io_from_upio(port);
2711
2712 if (flags & UART_CONFIG_TYPE)
2713 autoconfig(up, probeflags);
2714
2715 /* if access method is AU, it is a 16550 with a quirk */
2716 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2717 up->bugs |= UART_BUG_NOMSR;
2718
2719 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2720 autoconfig_irq(up);
2721
2722 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2723 serial8250_release_rsa_resource(up);
2724 if (up->port.type == PORT_UNKNOWN)
2725 serial8250_release_std_resource(up);
2726 }
2727
2728 static int
2729 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2730 {
2731 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2732 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2733 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2734 ser->type == PORT_STARTECH)
2735 return -EINVAL;
2736 return 0;
2737 }
2738
2739 static const char *
2740 serial8250_type(struct uart_port *port)
2741 {
2742 int type = port->type;
2743
2744 if (type >= ARRAY_SIZE(uart_config))
2745 type = 0;
2746 return uart_config[type].name;
2747 }
2748
2749 static struct uart_ops serial8250_pops = {
2750 .tx_empty = serial8250_tx_empty,
2751 .set_mctrl = serial8250_set_mctrl,
2752 .get_mctrl = serial8250_get_mctrl,
2753 .stop_tx = serial8250_stop_tx,
2754 .start_tx = serial8250_start_tx,
2755 .stop_rx = serial8250_stop_rx,
2756 .enable_ms = serial8250_enable_ms,
2757 .break_ctl = serial8250_break_ctl,
2758 .startup = serial8250_startup,
2759 .shutdown = serial8250_shutdown,
2760 .set_termios = serial8250_set_termios,
2761 .set_ldisc = serial8250_set_ldisc,
2762 .pm = serial8250_pm,
2763 .type = serial8250_type,
2764 .release_port = serial8250_release_port,
2765 .request_port = serial8250_request_port,
2766 .config_port = serial8250_config_port,
2767 .verify_port = serial8250_verify_port,
2768 #ifdef CONFIG_CONSOLE_POLL
2769 .poll_get_char = serial8250_get_poll_char,
2770 .poll_put_char = serial8250_put_poll_char,
2771 #endif
2772 };
2773
2774 static struct uart_8250_port serial8250_ports[UART_NR];
2775
2776 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2777 unsigned short *capabilities);
2778
2779 void serial8250_set_isa_configurator(
2780 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2781 {
2782 serial8250_isa_config = v;
2783 }
2784 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2785
2786 static void __init serial8250_isa_init_ports(void)
2787 {
2788 struct uart_8250_port *up;
2789 static int first = 1;
2790 int i, irqflag = 0;
2791
2792 if (!first)
2793 return;
2794 first = 0;
2795
2796 for (i = 0; i < nr_uarts; i++) {
2797 struct uart_8250_port *up = &serial8250_ports[i];
2798
2799 up->port.line = i;
2800 spin_lock_init(&up->port.lock);
2801
2802 init_timer(&up->timer);
2803 up->timer.function = serial8250_timeout;
2804
2805 /*
2806 * ALPHA_KLUDGE_MCR needs to be killed.
2807 */
2808 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2809 up->mcr_force = ALPHA_KLUDGE_MCR;
2810
2811 up->port.ops = &serial8250_pops;
2812 }
2813
2814 if (share_irqs)
2815 irqflag = IRQF_SHARED;
2816
2817 for (i = 0, up = serial8250_ports;
2818 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2819 i++, up++) {
2820 up->port.iobase = old_serial_port[i].port;
2821 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2822 up->port.irqflags = old_serial_port[i].irqflags;
2823 up->port.uartclk = old_serial_port[i].baud_base * 16;
2824 up->port.flags = old_serial_port[i].flags;
2825 up->port.hub6 = old_serial_port[i].hub6;
2826 up->port.membase = old_serial_port[i].iomem_base;
2827 up->port.iotype = old_serial_port[i].io_type;
2828 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2829 set_io_from_upio(&up->port);
2830 up->port.irqflags |= irqflag;
2831 if (serial8250_isa_config != NULL)
2832 serial8250_isa_config(i, &up->port, &up->capabilities);
2833
2834 }
2835 }
2836
2837 static void
2838 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2839 {
2840 up->port.type = type;
2841 up->port.fifosize = uart_config[type].fifo_size;
2842 up->capabilities = uart_config[type].flags;
2843 up->tx_loadsz = uart_config[type].tx_loadsz;
2844 }
2845
2846 static void __init
2847 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2848 {
2849 int i;
2850
2851 for (i = 0; i < nr_uarts; i++) {
2852 struct uart_8250_port *up = &serial8250_ports[i];
2853 up->cur_iotype = 0xFF;
2854 }
2855
2856 serial8250_isa_init_ports();
2857
2858 for (i = 0; i < nr_uarts; i++) {
2859 struct uart_8250_port *up = &serial8250_ports[i];
2860
2861 up->port.dev = dev;
2862
2863 if (up->port.flags & UPF_FIXED_TYPE)
2864 serial8250_init_fixed_type_port(up, up->port.type);
2865
2866 uart_add_one_port(drv, &up->port);
2867 }
2868 }
2869
2870 #ifdef CONFIG_SERIAL_8250_CONSOLE
2871
2872 static void serial8250_console_putchar(struct uart_port *port, int ch)
2873 {
2874 struct uart_8250_port *up =
2875 container_of(port, struct uart_8250_port, port);
2876
2877 wait_for_xmitr(up, UART_LSR_THRE);
2878 serial_out(up, UART_TX, ch);
2879 }
2880
2881 /*
2882 * Print a string to the serial port trying not to disturb
2883 * any possible real use of the port...
2884 *
2885 * The console_lock must be held when we get here.
2886 */
2887 static void
2888 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2889 {
2890 struct uart_8250_port *up = &serial8250_ports[co->index];
2891 unsigned long flags;
2892 unsigned int ier;
2893 int locked = 1;
2894
2895 touch_nmi_watchdog();
2896
2897 local_irq_save(flags);
2898 if (up->port.sysrq) {
2899 /* serial8250_handle_port() already took the lock */
2900 locked = 0;
2901 } else if (oops_in_progress) {
2902 locked = spin_trylock(&up->port.lock);
2903 } else
2904 spin_lock(&up->port.lock);
2905
2906 /*
2907 * First save the IER then disable the interrupts
2908 */
2909 ier = serial_in(up, UART_IER);
2910
2911 if (up->capabilities & UART_CAP_UUE)
2912 serial_out(up, UART_IER, UART_IER_UUE);
2913 else
2914 serial_out(up, UART_IER, 0);
2915
2916 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2917
2918 /*
2919 * Finally, wait for transmitter to become empty
2920 * and restore the IER
2921 */
2922 wait_for_xmitr(up, BOTH_EMPTY);
2923 serial_out(up, UART_IER, ier);
2924
2925 /*
2926 * The receive handling will happen properly because the
2927 * receive ready bit will still be set; it is not cleared
2928 * on read. However, modem control will not, we must
2929 * call it if we have saved something in the saved flags
2930 * while processing with interrupts off.
2931 */
2932 if (up->msr_saved_flags)
2933 check_modem_status(up);
2934
2935 if (locked)
2936 spin_unlock(&up->port.lock);
2937 local_irq_restore(flags);
2938 }
2939
2940 static int __init serial8250_console_setup(struct console *co, char *options)
2941 {
2942 struct uart_port *port;
2943 int baud = 9600;
2944 int bits = 8;
2945 int parity = 'n';
2946 int flow = 'n';
2947
2948 /*
2949 * Check whether an invalid uart number has been specified, and
2950 * if so, search for the first available port that does have
2951 * console support.
2952 */
2953 if (co->index >= nr_uarts)
2954 co->index = 0;
2955 port = &serial8250_ports[co->index].port;
2956 if (!port->iobase && !port->membase)
2957 return -ENODEV;
2958
2959 if (options)
2960 uart_parse_options(options, &baud, &parity, &bits, &flow);
2961
2962 return uart_set_options(port, co, baud, parity, bits, flow);
2963 }
2964
2965 static int serial8250_console_early_setup(void)
2966 {
2967 return serial8250_find_port_for_earlycon();
2968 }
2969
2970 static struct console serial8250_console = {
2971 .name = "ttyS",
2972 .write = serial8250_console_write,
2973 .device = uart_console_device,
2974 .setup = serial8250_console_setup,
2975 .early_setup = serial8250_console_early_setup,
2976 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2977 .index = -1,
2978 .data = &serial8250_reg,
2979 };
2980
2981 static int __init serial8250_console_init(void)
2982 {
2983 if (nr_uarts > UART_NR)
2984 nr_uarts = UART_NR;
2985
2986 serial8250_isa_init_ports();
2987 register_console(&serial8250_console);
2988 return 0;
2989 }
2990 console_initcall(serial8250_console_init);
2991
2992 int serial8250_find_port(struct uart_port *p)
2993 {
2994 int line;
2995 struct uart_port *port;
2996
2997 for (line = 0; line < nr_uarts; line++) {
2998 port = &serial8250_ports[line].port;
2999 if (uart_match_port(p, port))
3000 return line;
3001 }
3002 return -ENODEV;
3003 }
3004
3005 #define SERIAL8250_CONSOLE &serial8250_console
3006 #else
3007 #define SERIAL8250_CONSOLE NULL
3008 #endif
3009
3010 static struct uart_driver serial8250_reg = {
3011 .owner = THIS_MODULE,
3012 .driver_name = "serial",
3013 .dev_name = "ttyS",
3014 .major = TTY_MAJOR,
3015 .minor = 64,
3016 .cons = SERIAL8250_CONSOLE,
3017 };
3018
3019 /*
3020 * early_serial_setup - early registration for 8250 ports
3021 *
3022 * Setup an 8250 port structure prior to console initialisation. Use
3023 * after console initialisation will cause undefined behaviour.
3024 */
3025 int __init early_serial_setup(struct uart_port *port)
3026 {
3027 struct uart_port *p;
3028
3029 if (port->line >= ARRAY_SIZE(serial8250_ports))
3030 return -ENODEV;
3031
3032 serial8250_isa_init_ports();
3033 p = &serial8250_ports[port->line].port;
3034 p->iobase = port->iobase;
3035 p->membase = port->membase;
3036 p->irq = port->irq;
3037 p->irqflags = port->irqflags;
3038 p->uartclk = port->uartclk;
3039 p->fifosize = port->fifosize;
3040 p->regshift = port->regshift;
3041 p->iotype = port->iotype;
3042 p->flags = port->flags;
3043 p->mapbase = port->mapbase;
3044 p->private_data = port->private_data;
3045 p->type = port->type;
3046 p->line = port->line;
3047
3048 set_io_from_upio(p);
3049 if (port->serial_in)
3050 p->serial_in = port->serial_in;
3051 if (port->serial_out)
3052 p->serial_out = port->serial_out;
3053
3054 return 0;
3055 }
3056
3057 /**
3058 * serial8250_suspend_port - suspend one serial port
3059 * @line: serial line number
3060 *
3061 * Suspend one serial port.
3062 */
3063 void serial8250_suspend_port(int line)
3064 {
3065 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3066 }
3067
3068 /**
3069 * serial8250_resume_port - resume one serial port
3070 * @line: serial line number
3071 *
3072 * Resume one serial port.
3073 */
3074 void serial8250_resume_port(int line)
3075 {
3076 struct uart_8250_port *up = &serial8250_ports[line];
3077
3078 if (up->capabilities & UART_NATSEMI) {
3079 /* Ensure it's still in high speed mode */
3080 serial_outp(up, UART_LCR, 0xE0);
3081
3082 ns16550a_goto_highspeed(up);
3083
3084 serial_outp(up, UART_LCR, 0);
3085 up->port.uartclk = 921600*16;
3086 }
3087 uart_resume_port(&serial8250_reg, &up->port);
3088 }
3089
3090 /*
3091 * Register a set of serial devices attached to a platform device. The
3092 * list is terminated with a zero flags entry, which means we expect
3093 * all entries to have at least UPF_BOOT_AUTOCONF set.
3094 */
3095 static int __devinit serial8250_probe(struct platform_device *dev)
3096 {
3097 struct plat_serial8250_port *p = dev->dev.platform_data;
3098 struct uart_port port;
3099 int ret, i, irqflag = 0;
3100
3101 memset(&port, 0, sizeof(struct uart_port));
3102
3103 if (share_irqs)
3104 irqflag = IRQF_SHARED;
3105
3106 for (i = 0; p && p->flags != 0; p++, i++) {
3107 port.iobase = p->iobase;
3108 port.membase = p->membase;
3109 port.irq = p->irq;
3110 port.irqflags = p->irqflags;
3111 port.uartclk = p->uartclk;
3112 port.regshift = p->regshift;
3113 port.iotype = p->iotype;
3114 port.flags = p->flags;
3115 port.mapbase = p->mapbase;
3116 port.hub6 = p->hub6;
3117 port.private_data = p->private_data;
3118 port.type = p->type;
3119 port.serial_in = p->serial_in;
3120 port.serial_out = p->serial_out;
3121 port.set_termios = p->set_termios;
3122 port.pm = p->pm;
3123 port.dev = &dev->dev;
3124 port.irqflags |= irqflag;
3125 ret = serial8250_register_port(&port);
3126 if (ret < 0) {
3127 dev_err(&dev->dev, "unable to register port at index %d "
3128 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3129 p->iobase, (unsigned long long)p->mapbase,
3130 p->irq, ret);
3131 }
3132 }
3133 return 0;
3134 }
3135
3136 /*
3137 * Remove serial ports registered against a platform device.
3138 */
3139 static int __devexit serial8250_remove(struct platform_device *dev)
3140 {
3141 int i;
3142
3143 for (i = 0; i < nr_uarts; i++) {
3144 struct uart_8250_port *up = &serial8250_ports[i];
3145
3146 if (up->port.dev == &dev->dev)
3147 serial8250_unregister_port(i);
3148 }
3149 return 0;
3150 }
3151
3152 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3153 {
3154 int i;
3155
3156 for (i = 0; i < UART_NR; i++) {
3157 struct uart_8250_port *up = &serial8250_ports[i];
3158
3159 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3160 uart_suspend_port(&serial8250_reg, &up->port);
3161 }
3162
3163 return 0;
3164 }
3165
3166 static int serial8250_resume(struct platform_device *dev)
3167 {
3168 int i;
3169
3170 for (i = 0; i < UART_NR; i++) {
3171 struct uart_8250_port *up = &serial8250_ports[i];
3172
3173 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3174 serial8250_resume_port(i);
3175 }
3176
3177 return 0;
3178 }
3179
3180 static struct platform_driver serial8250_isa_driver = {
3181 .probe = serial8250_probe,
3182 .remove = __devexit_p(serial8250_remove),
3183 .suspend = serial8250_suspend,
3184 .resume = serial8250_resume,
3185 .driver = {
3186 .name = "serial8250",
3187 .owner = THIS_MODULE,
3188 },
3189 };
3190
3191 /*
3192 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3193 * in the table in include/asm/serial.h
3194 */
3195 static struct platform_device *serial8250_isa_devs;
3196
3197 /*
3198 * serial8250_register_port and serial8250_unregister_port allows for
3199 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3200 * modems and PCI multiport cards.
3201 */
3202 static DEFINE_MUTEX(serial_mutex);
3203
3204 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3205 {
3206 int i;
3207
3208 /*
3209 * First, find a port entry which matches.
3210 */
3211 for (i = 0; i < nr_uarts; i++)
3212 if (uart_match_port(&serial8250_ports[i].port, port))
3213 return &serial8250_ports[i];
3214
3215 /*
3216 * We didn't find a matching entry, so look for the first
3217 * free entry. We look for one which hasn't been previously
3218 * used (indicated by zero iobase).
3219 */
3220 for (i = 0; i < nr_uarts; i++)
3221 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3222 serial8250_ports[i].port.iobase == 0)
3223 return &serial8250_ports[i];
3224
3225 /*
3226 * That also failed. Last resort is to find any entry which
3227 * doesn't have a real port associated with it.
3228 */
3229 for (i = 0; i < nr_uarts; i++)
3230 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3231 return &serial8250_ports[i];
3232
3233 return NULL;
3234 }
3235
3236 /**
3237 * serial8250_register_port - register a serial port
3238 * @port: serial port template
3239 *
3240 * Configure the serial port specified by the request. If the
3241 * port exists and is in use, it is hung up and unregistered
3242 * first.
3243 *
3244 * The port is then probed and if necessary the IRQ is autodetected
3245 * If this fails an error is returned.
3246 *
3247 * On success the port is ready to use and the line number is returned.
3248 */
3249 int serial8250_register_port(struct uart_port *port)
3250 {
3251 struct uart_8250_port *uart;
3252 int ret = -ENOSPC;
3253
3254 if (port->uartclk == 0)
3255 return -EINVAL;
3256
3257 mutex_lock(&serial_mutex);
3258
3259 uart = serial8250_find_match_or_unused(port);
3260 if (uart) {
3261 uart_remove_one_port(&serial8250_reg, &uart->port);
3262
3263 uart->port.iobase = port->iobase;
3264 uart->port.membase = port->membase;
3265 uart->port.irq = port->irq;
3266 uart->port.irqflags = port->irqflags;
3267 uart->port.uartclk = port->uartclk;
3268 uart->port.fifosize = port->fifosize;
3269 uart->port.regshift = port->regshift;
3270 uart->port.iotype = port->iotype;
3271 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3272 uart->port.mapbase = port->mapbase;
3273 uart->port.private_data = port->private_data;
3274 if (port->dev)
3275 uart->port.dev = port->dev;
3276
3277 if (port->flags & UPF_FIXED_TYPE)
3278 serial8250_init_fixed_type_port(uart, port->type);
3279
3280 set_io_from_upio(&uart->port);
3281 /* Possibly override default I/O functions. */
3282 if (port->serial_in)
3283 uart->port.serial_in = port->serial_in;
3284 if (port->serial_out)
3285 uart->port.serial_out = port->serial_out;
3286 /* Possibly override set_termios call */
3287 if (port->set_termios)
3288 uart->port.set_termios = port->set_termios;
3289 if (port->pm)
3290 uart->port.pm = port->pm;
3291
3292 if (serial8250_isa_config != NULL)
3293 serial8250_isa_config(0, &uart->port,
3294 &uart->capabilities);
3295
3296 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3297 if (ret == 0)
3298 ret = uart->port.line;
3299 }
3300 mutex_unlock(&serial_mutex);
3301
3302 return ret;
3303 }
3304 EXPORT_SYMBOL(serial8250_register_port);
3305
3306 /**
3307 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3308 * @line: serial line number
3309 *
3310 * Remove one serial port. This may not be called from interrupt
3311 * context. We hand the port back to the our control.
3312 */
3313 void serial8250_unregister_port(int line)
3314 {
3315 struct uart_8250_port *uart = &serial8250_ports[line];
3316
3317 mutex_lock(&serial_mutex);
3318 uart_remove_one_port(&serial8250_reg, &uart->port);
3319 if (serial8250_isa_devs) {
3320 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3321 uart->port.type = PORT_UNKNOWN;
3322 uart->port.dev = &serial8250_isa_devs->dev;
3323 uart->capabilities = uart_config[uart->port.type].flags;
3324 uart_add_one_port(&serial8250_reg, &uart->port);
3325 } else {
3326 uart->port.dev = NULL;
3327 }
3328 mutex_unlock(&serial_mutex);
3329 }
3330 EXPORT_SYMBOL(serial8250_unregister_port);
3331
3332 static int __init serial8250_init(void)
3333 {
3334 int ret;
3335
3336 if (nr_uarts > UART_NR)
3337 nr_uarts = UART_NR;
3338
3339 printk(KERN_INFO "Serial: 8250/16550 driver, "
3340 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3341 share_irqs ? "en" : "dis");
3342
3343 #ifdef CONFIG_SPARC
3344 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3345 #else
3346 serial8250_reg.nr = UART_NR;
3347 ret = uart_register_driver(&serial8250_reg);
3348 #endif
3349 if (ret)
3350 goto out;
3351
3352 serial8250_isa_devs = platform_device_alloc("serial8250",
3353 PLAT8250_DEV_LEGACY);
3354 if (!serial8250_isa_devs) {
3355 ret = -ENOMEM;
3356 goto unreg_uart_drv;
3357 }
3358
3359 ret = platform_device_add(serial8250_isa_devs);
3360 if (ret)
3361 goto put_dev;
3362
3363 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3364
3365 ret = platform_driver_register(&serial8250_isa_driver);
3366 if (ret == 0)
3367 goto out;
3368
3369 platform_device_del(serial8250_isa_devs);
3370 put_dev:
3371 platform_device_put(serial8250_isa_devs);
3372 unreg_uart_drv:
3373 #ifdef CONFIG_SPARC
3374 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3375 #else
3376 uart_unregister_driver(&serial8250_reg);
3377 #endif
3378 out:
3379 return ret;
3380 }
3381
3382 static void __exit serial8250_exit(void)
3383 {
3384 struct platform_device *isa_dev = serial8250_isa_devs;
3385
3386 /*
3387 * This tells serial8250_unregister_port() not to re-register
3388 * the ports (thereby making serial8250_isa_driver permanently
3389 * in use.)
3390 */
3391 serial8250_isa_devs = NULL;
3392
3393 platform_driver_unregister(&serial8250_isa_driver);
3394 platform_device_unregister(isa_dev);
3395
3396 #ifdef CONFIG_SPARC
3397 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3398 #else
3399 uart_unregister_driver(&serial8250_reg);
3400 #endif
3401 }
3402
3403 module_init(serial8250_init);
3404 module_exit(serial8250_exit);
3405
3406 EXPORT_SYMBOL(serial8250_suspend_port);
3407 EXPORT_SYMBOL(serial8250_resume_port);
3408
3409 MODULE_LICENSE("GPL");
3410 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3411
3412 module_param(share_irqs, uint, 0644);
3413 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3414 " (unsafe)");
3415
3416 module_param(nr_uarts, uint, 0644);
3417 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3418
3419 module_param(skip_txen_test, uint, 0644);
3420 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3421
3422 #ifdef CONFIG_SERIAL_8250_RSA
3423 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3424 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3425 #endif
3426 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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