arch/arm/mach-tegra/board-dt-tegra30.c

   1 /*
   2  * arch/arm/mach-tegra/board-dt-tegra30.c
   3  *
   4  * NVIDIA Tegra30 device tree board support
   5  *
   6  * Copyright (C) 2011 NVIDIA Corporation
   7  *
   8  * Derived from:
   9  *
  10  * arch/arm/mach-tegra/board-dt-tegra20.c
  11  *
  12  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  13  * Copyright (C) 2010 Google, Inc.
  14  *
  15  * This software is licensed under the terms of the GNU General Public
  16  * License version 2, as published by the Free Software Foundation, and
  17  * may be copied, distributed, and modified under those terms.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  */
  25
  26 #include <linux/clocksource.h>
  27 #include <linux/kernel.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_fdt.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_platform.h>
  33
  34 #include <asm/mach/arch.h>
  35 #include <asm/hardware/gic.h>
  36
  37 #include "board.h"
  38 #include "clock.h"
  39 #include "common.h"
  40 #include "iomap.h"
  41
  42 static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
  43         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
  44         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
  45         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
  46         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
  47         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
  48         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
  49         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
  50         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
  51         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
  52         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
  53         OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
  54         OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
  55         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
  56         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
  57         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
  58         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
  59         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
  60         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
  61         OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
  62         OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
  63         OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
  64         OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
  65         OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
  66         OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
  67         {}
  68 };
  69
  70 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
  71         /* name         parent          rate            enabled */
  72         { "uarta",      "pll_p",        408000000,      true },
  73         { "pll_a",      "pll_p_out1",   564480000,      true },
  74         { "pll_a_out0", "pll_a",        11289600,       true },
  75         { "extern1",    "pll_a_out0",   0,              true },
  76         { "clk_out_1",  "extern1",      0,              true },
  77         { "blink",      "clk_32k",      32768,          true },
  78         { "i2s0",       "pll_a_out0",   11289600,       false},
  79         { "i2s1",       "pll_a_out0",   11289600,       false},
  80         { "i2s2",       "pll_a_out0",   11289600,       false},
  81         { "i2s3",       "pll_a_out0",   11289600,       false},
  82         { "i2s4",       "pll_a_out0",   11289600,       false},
  83         { "sdmmc1",     "pll_p",        48000000,       false},
  84         { "sdmmc3",     "pll_p",        48000000,       false},
  85         { "sdmmc4",     "pll_p",        48000000,       false},
  86         { "sbc1",       "pll_p",        100000000,      false},
  87         { "sbc2",       "pll_p",        100000000,      false},
  88         { "sbc3",       "pll_p",        100000000,      false},
  89         { "sbc4",       "pll_p",        100000000,      false},
  90         { "sbc5",       "pll_p",        100000000,      false},
  91         { "sbc6",       "pll_p",        100000000,      false},
  92         { "host1x",     "pll_c",        150000000,      false},
  93         { "disp1",      "pll_p",        600000000,      false},
  94         { "disp2",      "pll_p",        600000000,      false},
  95         { NULL,         NULL,           0,              0},
  96 };
  97
  98 static void __init tegra30_dt_init(void)
  99 {
 100         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 101
 102         of_platform_populate(NULL, of_default_bus_match_table,
 103                                 tegra30_auxdata_lookup, NULL);
 104 }
 105
 106 static const char *tegra30_dt_board_compat[] = {
 107         "nvidia,tegra30",
 108         NULL
 109 };
 110
 111 DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
 112         .smp            = smp_ops(tegra_smp_ops),
 113         .map_io         = tegra_map_common_io,
 114         .init_early     = tegra30_init_early,
 115         .init_irq       = tegra_dt_init_irq,
 116         .handle_irq     = gic_handle_irq,
 117         .init_time      = clocksource_of_init,
 118         .init_machine   = tegra30_dt_init,
 119         .init_late      = tegra_init_late,
 120         .restart        = tegra_assert_system_reset,
 121         .dt_compat      = tegra30_dt_board_compat,
 122 MACHINE_END