2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
45 #include <asm/mach/time.h>
46 #include <asm/smp_twd.h>
47 #include <asm/sched_clock.h>
49 #include <asm/arch_timer.h>
50 #include "omap_hwmod.h"
51 #include "omap_device.h"
52 #include <plat/counter-32k.h>
53 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
60 /* Parent clocks, eventually these will come from the clock framework */
62 #define OMAP2_MPU_SOURCE "sys_ck"
63 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
64 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
65 #define OMAP2_32K_SOURCE "func_32k_ck"
66 #define OMAP3_32K_SOURCE "omap_32k_fck"
67 #define OMAP4_32K_SOURCE "sys_32k_ck"
69 #define REALTIME_COUNTER_BASE 0x48243200
70 #define INCREMENTER_NUMERATOR_OFFSET 0x10
71 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
72 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
76 static struct omap_dm_timer clkev
;
77 static struct clock_event_device clockevent_gpt
;
79 static irqreturn_t
omap2_gp_timer_interrupt(int irq
, void *dev_id
)
81 struct clock_event_device
*evt
= &clockevent_gpt
;
83 __omap_dm_timer_write_status(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
85 evt
->event_handler(evt
);
89 static struct irqaction omap2_gp_timer_irq
= {
91 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
92 .handler
= omap2_gp_timer_interrupt
,
95 static int omap2_gp_timer_set_next_event(unsigned long cycles
,
96 struct clock_event_device
*evt
)
98 __omap_dm_timer_load_start(&clkev
, OMAP_TIMER_CTRL_ST
,
99 0xffffffff - cycles
, OMAP_TIMER_POSTED
);
104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode
,
105 struct clock_event_device
*evt
)
109 __omap_dm_timer_stop(&clkev
, OMAP_TIMER_POSTED
, clkev
.rate
);
112 case CLOCK_EVT_MODE_PERIODIC
:
113 period
= clkev
.rate
/ HZ
;
115 /* Looks like we need to first set the load value separately */
116 __omap_dm_timer_write(&clkev
, OMAP_TIMER_LOAD_REG
,
117 0xffffffff - period
, OMAP_TIMER_POSTED
);
118 __omap_dm_timer_load_start(&clkev
,
119 OMAP_TIMER_CTRL_AR
| OMAP_TIMER_CTRL_ST
,
120 0xffffffff - period
, OMAP_TIMER_POSTED
);
122 case CLOCK_EVT_MODE_ONESHOT
:
124 case CLOCK_EVT_MODE_UNUSED
:
125 case CLOCK_EVT_MODE_SHUTDOWN
:
126 case CLOCK_EVT_MODE_RESUME
:
131 static struct clock_event_device clockevent_gpt
= {
133 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
136 .set_next_event
= omap2_gp_timer_set_next_event
,
137 .set_mode
= omap2_gp_timer_set_mode
,
140 static struct property device_disabled
= {
142 .length
= sizeof("disabled"),
146 static struct of_device_id omap_timer_match
[] __initdata
= {
147 { .compatible
= "ti,omap2-timer", },
152 * omap_get_timer_dt - get a timer using device-tree
153 * @match - device-tree match structure for matching a device type
154 * @property - optional timer property to match
156 * Helper function to get a timer during early boot using device-tree for use
157 * as kernel system timer. Optionally, the property argument can be used to
158 * select a timer with a specific property. Once a timer is found then mark
159 * the timer node in device-tree as disabled, to prevent the kernel from
160 * registering this timer as a platform device and so no one else can use it.
162 static struct device_node
* __init
omap_get_timer_dt(struct of_device_id
*match
,
163 const char *property
)
165 struct device_node
*np
;
167 for_each_matching_node(np
, match
) {
168 if (!of_device_is_available(np
)) {
173 if (property
&& !of_get_property(np
, property
, NULL
)) {
178 of_add_property(np
, &device_disabled
);
186 * omap_dmtimer_init - initialisation function when device tree is used
188 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
189 * be used by the kernel as they are reserved. Therefore, to prevent the
190 * kernel registering these devices remove them dynamically from the device
193 static void __init
omap_dmtimer_init(void)
195 struct device_node
*np
;
197 if (!cpu_is_omap34xx())
200 /* If we are a secure device, remove any secure timer nodes */
201 if ((omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
202 np
= omap_get_timer_dt(omap_timer_match
, "ti,timer-secure");
209 * omap_dm_timer_get_errata - get errata flags for a timer
211 * Get the timer errata flags that are specific to the OMAP device being used.
213 static u32 __init
omap_dm_timer_get_errata(void)
215 if (cpu_is_omap24xx())
218 return OMAP_TIMER_ERRATA_I103_I767
;
221 static int __init
omap_dm_timer_init_one(struct omap_dm_timer
*timer
,
223 const char *fck_source
,
224 const char *property
,
227 char name
[10]; /* 10 = sizeof("gptXX_Xck0") */
229 struct device_node
*np
;
230 struct omap_hwmod
*oh
;
231 struct resource irq
, mem
;
234 if (of_have_populated_dt()) {
235 np
= omap_get_timer_dt(omap_timer_match
, NULL
);
239 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
243 timer
->irq
= irq_of_parse_and_map(np
, 0);
247 timer
->io_base
= of_iomap(np
, 0);
251 if (omap_dm_timer_reserve_systimer(gptimer_id
))
254 sprintf(name
, "timer%d", gptimer_id
);
258 oh
= omap_hwmod_lookup(oh_name
);
262 if (!of_have_populated_dt()) {
263 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_IRQ
, NULL
,
267 timer
->irq
= irq
.start
;
269 r
= omap_hwmod_get_resource_byname(oh
, IORESOURCE_MEM
, NULL
,
274 /* Static mapping, never released */
275 timer
->io_base
= ioremap(mem
.start
, mem
.end
- mem
.start
);
281 /* After the dmtimer is using hwmod these clocks won't be needed */
282 timer
->fclk
= clk_get(NULL
, omap_hwmod_get_main_clk(oh
));
283 if (IS_ERR(timer
->fclk
))
286 /* FIXME: Need to remove hard-coded test on timer ID */
287 if (gptimer_id
!= 12) {
290 src
= clk_get(NULL
, fck_source
);
294 r
= clk_set_parent(timer
->fclk
, src
);
296 pr_warn("%s: %s cannot set source\n",
302 omap_hwmod_setup_one(oh_name
);
303 omap_hwmod_enable(oh
);
304 __omap_dm_timer_init_regs(timer
);
307 __omap_dm_timer_enable_posted(timer
);
309 /* Check that the intended posted configuration matches the actual */
310 if (posted
!= timer
->posted
)
313 timer
->rate
= clk_get_rate(timer
->fclk
);
319 static void __init
omap2_gp_clockevent_init(int gptimer_id
,
320 const char *fck_source
,
321 const char *property
)
325 clkev
.errata
= omap_dm_timer_get_errata();
328 * For clock-event timers we never read the timer counter and
329 * so we are not impacted by errata i103 and i767. Therefore,
330 * we can safely ignore this errata for clock-event timers.
332 __omap_dm_timer_override_errata(&clkev
, OMAP_TIMER_ERRATA_I103_I767
);
334 res
= omap_dm_timer_init_one(&clkev
, gptimer_id
, fck_source
, property
,
338 omap2_gp_timer_irq
.dev_id
= &clkev
;
339 setup_irq(clkev
.irq
, &omap2_gp_timer_irq
);
341 __omap_dm_timer_int_enable(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
343 clockevent_gpt
.mult
= div_sc(clkev
.rate
, NSEC_PER_SEC
,
344 clockevent_gpt
.shift
);
345 clockevent_gpt
.max_delta_ns
=
346 clockevent_delta2ns(0xffffffff, &clockevent_gpt
);
347 clockevent_gpt
.min_delta_ns
=
348 clockevent_delta2ns(3, &clockevent_gpt
);
349 /* Timer internal resynch latency. */
351 clockevent_gpt
.cpumask
= cpu_possible_mask
;
352 clockevent_gpt
.irq
= omap_dm_timer_get_irq(&clkev
);
353 clockevents_register_device(&clockevent_gpt
);
355 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
356 gptimer_id
, clkev
.rate
);
359 /* Clocksource code */
360 static struct omap_dm_timer clksrc
;
361 static bool use_gptimer_clksrc
;
366 static cycle_t
clocksource_read_cycles(struct clocksource
*cs
)
368 return (cycle_t
)__omap_dm_timer_read_counter(&clksrc
,
369 OMAP_TIMER_NONPOSTED
);
372 static struct clocksource clocksource_gpt
= {
375 .read
= clocksource_read_cycles
,
376 .mask
= CLOCKSOURCE_MASK(32),
377 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
380 static u32 notrace
dmtimer_read_sched_clock(void)
383 return __omap_dm_timer_read_counter(&clksrc
,
384 OMAP_TIMER_NONPOSTED
);
389 static struct of_device_id omap_counter_match
[] __initdata
= {
390 { .compatible
= "ti,omap-counter32k", },
394 /* Setup free-running counter for clocksource */
395 static int __init __maybe_unused
omap2_sync32k_clocksource_init(void)
398 struct device_node
*np
= NULL
;
399 struct omap_hwmod
*oh
;
401 const char *oh_name
= "counter_32k";
404 * If device-tree is present, then search the DT blob
405 * to see if the 32kHz counter is supported.
407 if (of_have_populated_dt()) {
408 np
= omap_get_timer_dt(omap_counter_match
, NULL
);
412 of_property_read_string_index(np
, "ti,hwmods", 0, &oh_name
);
418 * First check hwmod data is available for sync32k counter
420 oh
= omap_hwmod_lookup(oh_name
);
421 if (!oh
|| oh
->slaves_cnt
== 0)
424 omap_hwmod_setup_one(oh_name
);
427 vbase
= of_iomap(np
, 0);
430 vbase
= omap_hwmod_get_mpu_rt_va(oh
);
434 pr_warn("%s: failed to get counter_32k resource\n", __func__
);
438 ret
= omap_hwmod_enable(oh
);
440 pr_warn("%s: failed to enable counter_32k module (%d)\n",
445 ret
= omap_init_clocksource_32k(vbase
);
447 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
455 static void __init
omap2_gptimer_clocksource_init(int gptimer_id
,
456 const char *fck_source
)
460 clksrc
.errata
= omap_dm_timer_get_errata();
462 res
= omap_dm_timer_init_one(&clksrc
, gptimer_id
, fck_source
, NULL
,
463 OMAP_TIMER_NONPOSTED
);
466 __omap_dm_timer_load_start(&clksrc
,
467 OMAP_TIMER_CTRL_ST
| OMAP_TIMER_CTRL_AR
, 0,
468 OMAP_TIMER_NONPOSTED
);
469 setup_sched_clock(dmtimer_read_sched_clock
, 32, clksrc
.rate
);
471 if (clocksource_register_hz(&clocksource_gpt
, clksrc
.rate
))
472 pr_err("Could not register clocksource %s\n",
473 clocksource_gpt
.name
);
475 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
476 gptimer_id
, clksrc
.rate
);
479 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
481 * The realtime counter also called master counter, is a free-running
482 * counter, which is related to real time. It produces the count used
483 * by the CPU local timer peripherals in the MPU cluster. The timer counts
484 * at a rate of 6.144 MHz. Because the device operates on different clocks
485 * in different power modes, the master counter shifts operation between
486 * clocks, adjusting the increment per clock in hardware accordingly to
487 * maintain a constant count rate.
489 static void __init
realtime_counter_init(void)
492 static struct clk
*sys_clk
;
494 unsigned int reg
, num
, den
;
496 base
= ioremap(REALTIME_COUNTER_BASE
, SZ_32
);
498 pr_err("%s: ioremap failed\n", __func__
);
501 sys_clk
= clk_get(NULL
, "sys_clkin_ck");
502 if (IS_ERR(sys_clk
)) {
503 pr_err("%s: failed to get system clock handle\n", __func__
);
508 rate
= clk_get_rate(sys_clk
);
509 /* Numerator/denumerator values refer TRM Realtime Counter section */
533 /* Program it for 38.4 MHz */
539 /* Program numerator and denumerator registers */
540 reg
= __raw_readl(base
+ INCREMENTER_NUMERATOR_OFFSET
) &
541 NUMERATOR_DENUMERATOR_MASK
;
543 __raw_writel(reg
, base
+ INCREMENTER_NUMERATOR_OFFSET
);
545 reg
= __raw_readl(base
+ INCREMENTER_NUMERATOR_OFFSET
) &
546 NUMERATOR_DENUMERATOR_MASK
;
548 __raw_writel(reg
, base
+ INCREMENTER_DENUMERATOR_RELOAD_OFFSET
);
553 static inline void __init
realtime_counter_init(void)
557 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
558 clksrc_nr, clksrc_src) \
559 void __init omap##name##_gptimer_timer_init(void) \
561 omap_dmtimer_init(); \
562 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
563 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
566 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
567 clksrc_nr, clksrc_src) \
568 void __init omap##name##_sync32k_timer_init(void) \
570 omap_dmtimer_init(); \
571 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
572 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
573 if (use_gptimer_clksrc) \
574 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
576 omap2_sync32k_clocksource_init(); \
579 #ifdef CONFIG_ARCH_OMAP2
580 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE
, "ti,timer-alwon",
581 2, OMAP2_MPU_SOURCE
);
582 #endif /* CONFIG_ARCH_OMAP2 */
584 #ifdef CONFIG_ARCH_OMAP3
585 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE
, "ti,timer-alwon",
586 2, OMAP3_MPU_SOURCE
);
587 OMAP_SYS_32K_TIMER_INIT(3_secure
, 12, OMAP3_32K_SOURCE
, "ti,timer-secure",
588 2, OMAP3_MPU_SOURCE
);
589 OMAP_SYS_GP_TIMER_INIT(3_gp
, 1, OMAP3_MPU_SOURCE
, "ti,timer-alwon",
590 2, OMAP3_MPU_SOURCE
);
591 #endif /* CONFIG_ARCH_OMAP3 */
593 #ifdef CONFIG_SOC_AM33XX
594 OMAP_SYS_GP_TIMER_INIT(3_am33xx
, 1, OMAP4_MPU_SOURCE
, "ti,timer-alwon",
595 2, OMAP4_MPU_SOURCE
);
596 #endif /* CONFIG_SOC_AM33XX */
598 #ifdef CONFIG_ARCH_OMAP4
599 OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE
, "ti,timer-alwon",
600 2, OMAP4_MPU_SOURCE
);
601 #ifdef CONFIG_LOCAL_TIMERS
602 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer
, OMAP44XX_LOCAL_TWD_BASE
, 29);
603 void __init
omap4_local_timer_init(void)
605 omap4_sync32k_timer_init();
606 /* Local timers are not supprted on OMAP4430 ES1.0 */
607 if (omap_rev() != OMAP4430_REV_ES1_0
) {
610 if (of_have_populated_dt()) {
611 twd_local_timer_of_register();
615 err
= twd_local_timer_register(&twd_local_timer
);
617 pr_err("twd_local_timer_register failed %d\n", err
);
620 #else /* CONFIG_LOCAL_TIMERS */
621 void __init
omap4_local_timer_init(void)
623 omap4_sync32k_timer_init();
625 #endif /* CONFIG_LOCAL_TIMERS */
626 #endif /* CONFIG_ARCH_OMAP4 */
628 #ifdef CONFIG_SOC_OMAP5
629 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE
, "ti,timer-alwon",
630 2, OMAP4_MPU_SOURCE
);
631 void __init
omap5_realtime_timer_init(void)
635 omap5_sync32k_timer_init();
636 realtime_counter_init();
638 err
= arch_timer_of_register();
640 pr_err("%s: arch_timer_register failed %d\n", __func__
, err
);
642 #endif /* CONFIG_SOC_OMAP5 */
645 * omap_timer_init - build and register timer device with an
646 * associated timer hwmod
647 * @oh: timer hwmod pointer to be used to build timer device
648 * @user: parameter that can be passed from calling hwmod API
650 * Called by omap_hwmod_for_each_by_class to register each of the timer
651 * devices present in the system. The number of timer devices is known
652 * by parsing through the hwmod database for a given class name. At the
653 * end of function call memory is allocated for timer device and it is
654 * registered to the framework ready to be proved by the driver.
656 static int __init
omap_timer_init(struct omap_hwmod
*oh
, void *unused
)
660 char *name
= "omap_timer";
661 struct dmtimer_platform_data
*pdata
;
662 struct platform_device
*pdev
;
663 struct omap_timer_capability_dev_attr
*timer_dev_attr
;
665 pr_debug("%s: %s\n", __func__
, oh
->name
);
667 /* on secure device, do not register secure timer */
668 timer_dev_attr
= oh
->dev_attr
;
669 if (omap_type() != OMAP2_DEVICE_TYPE_GP
&& timer_dev_attr
)
670 if (timer_dev_attr
->timer_capability
== OMAP_TIMER_SECURE
)
673 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
675 pr_err("%s: No memory for [%s]\n", __func__
, oh
->name
);
680 * Extract the IDs from name field in hwmod database
681 * and use the same for constructing ids' for the
682 * timer devices. In a way, we are avoiding usage of
683 * static variable witin the function to do the same.
684 * CAUTION: We have to be careful and make sure the
685 * name in hwmod database does not change in which case
686 * we might either make corresponding change here or
687 * switch back static variable mechanism.
689 sscanf(oh
->name
, "timer%2d", &id
);
692 pdata
->timer_capability
= timer_dev_attr
->timer_capability
;
694 pdata
->timer_errata
= omap_dm_timer_get_errata();
695 pdata
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
697 pdev
= omap_device_build(name
, id
, oh
, pdata
, sizeof(*pdata
),
701 pr_err("%s: Can't build omap_device for %s: %s.\n",
702 __func__
, name
, oh
->name
);
712 * omap2_dm_timer_init - top level regular device initialization
714 * Uses dedicated hwmod api to parse through hwmod database for
715 * given class name and then build and register the timer device.
717 static int __init
omap2_dm_timer_init(void)
721 /* If dtb is there, the devices will be created dynamically */
722 if (of_have_populated_dt())
725 ret
= omap_hwmod_for_each_by_class("timer", omap_timer_init
, NULL
);
727 pr_err("%s: device registration failed.\n", __func__
);
733 arch_initcall(omap2_dm_timer_init
);
736 * omap2_override_clocksource - clocksource override with user configuration
738 * Allows user to override default clocksource, using kernel parameter
739 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
741 * Note that, here we are using same standard kernel parameter "clocksource=",
742 * and not introducing any OMAP specific interface.
744 static int __init
omap2_override_clocksource(char *str
)
749 * For OMAP architecture, we only have two options
750 * - sync_32k (default)
751 * - gp_timer (sys_clk based)
753 if (!strcmp(str
, "gp_timer"))
754 use_gptimer_clksrc
= true;
758 early_param("clocksource", omap2_override_clocksource
);