arch/arm/mach-omap2/prminst44xx.c

   1 /*
   2  * OMAP4 PRM instance functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2011 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "prcm-common.h"
  22 #include "prm44xx.h"
  23 #include "prminst44xx.h"
  24 #include "prm-regbits-44xx.h"
  25 #include "prcm44xx.h"
  26 #include "prcm_mpu44xx.h"
  27
  28 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
  29
  30 /**
  31  * omap_prm_base_init - Populates the prm partitions
  32  *
  33  * Populates the base addresses of the _prm_bases
  34  * array used for read/write of prm module registers.
  35  */
  36 void omap_prm_base_init(void)
  37 {
  38         _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
  39         _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
  40 }
  41
  42 /* Read a register in a PRM instance */
  43 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
  44 {
  45         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  46                part == OMAP4430_INVALID_PRCM_PARTITION ||
  47                !_prm_bases[part]);
  48         return __raw_readl(_prm_bases[part] + inst + idx);
  49 }
  50
  51 /* Write into a register in a PRM instance */
  52 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
  53 {
  54         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  55                part == OMAP4430_INVALID_PRCM_PARTITION ||
  56                !_prm_bases[part]);
  57         __raw_writel(val, _prm_bases[part] + inst + idx);
  58 }
  59
  60 /* Read-modify-write a register in PRM. Caller must lock */
  61 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
  62                                     u16 idx)
  63 {
  64         u32 v;
  65
  66         v = omap4_prminst_read_inst_reg(part, inst, idx);
  67         v &= ~mask;
  68         v |= bits;
  69         omap4_prminst_write_inst_reg(v, part, inst, idx);
  70
  71         return v;
  72 }
  73
  74 /*
  75  * Address offset (in bytes) between the reset control and the reset
  76  * status registers: 4 bytes on OMAP4
  77  */
  78 #define OMAP4_RST_CTRL_ST_OFFSET                4
  79
  80 /**
  81  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
  82  * submodules contained in the hwmod module
  83  * @rstctrl_reg: RM_RSTCTRL register address for this module
  84  * @shift: register bit shift corresponding to the reset line to check
  85  *
  86  * Returns 1 if the (sub)module hardreset line is currently asserted,
  87  * 0 if the (sub)module hardreset line is not currently asserted, or
  88  * -EINVAL upon parameter error.
  89  */
  90 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
  91                                         u16 rstctrl_offs)
  92 {
  93         u32 v;
  94
  95         v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
  96         v &= 1 << shift;
  97         v >>= shift;
  98
  99         return v;
 100 }
 101
 102 /**
 103  * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
 104  * @rstctrl_reg: RM_RSTCTRL register address for this module
 105  * @shift: register bit shift corresponding to the reset line to assert
 106  *
 107  * Some IPs like dsp, ipu or iva contain processors that require an HW
 108  * reset line to be asserted / deasserted in order to fully enable the
 109  * IP.  These modules may have multiple hard-reset lines that reset
 110  * different 'submodules' inside the IP block.  This function will
 111  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 112  * upon an argument error.
 113  */
 114 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 115                                    u16 rstctrl_offs)
 116 {
 117         u32 mask = 1 << shift;
 118
 119         omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
 120
 121         return 0;
 122 }
 123
 124 /**
 125  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 126  * wait
 127  * @rstctrl_reg: RM_RSTCTRL register address for this module
 128  * @shift: register bit shift corresponding to the reset line to deassert
 129  *
 130  * Some IPs like dsp, ipu or iva contain processors that require an HW
 131  * reset line to be asserted / deasserted in order to fully enable the
 132  * IP.  These modules may have multiple hard-reset lines that reset
 133  * different 'submodules' inside the IP block.  This function will
 134  * take the submodule out of reset and wait until the PRCM indicates
 135  * that the reset has completed before returning.  Returns 0 upon success or
 136  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 137  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 138  */
 139 int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 140                                      u16 rstctrl_offs)
 141 {
 142         int c;
 143         u32 mask = 1 << shift;
 144         u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
 145
 146         /* Check the current status to avoid de-asserting the line twice */
 147         if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
 148                                                 rstctrl_offs) == 0)
 149                 return -EEXIST;
 150
 151         /* Clear the reset status by writing 1 to the status bit */
 152         omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
 153                                         rstst_offs);
 154         /* de-assert the reset control line */
 155         omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
 156         /* wait the status to be set */
 157         omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
 158                                                               rstst_offs),
 159                           MAX_MODULE_HARDRESET_WAIT, c);
 160
 161         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 162 }
 163
 164
 165 void omap4_prminst_global_warm_sw_reset(void)
 166 {
 167         u32 v;
 168
 169         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 170                                     OMAP4430_PRM_DEVICE_INST,
 171                                     OMAP4_PRM_RSTCTRL_OFFSET);
 172         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 173         omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
 174                                  OMAP4430_PRM_DEVICE_INST,
 175                                  OMAP4_PRM_RSTCTRL_OFFSET);
 176
 177         /* OCP barrier */
 178         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 179                                     OMAP4430_PRM_DEVICE_INST,
 180                                     OMAP4_PRM_RSTCTRL_OFFSET);
 181 }