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r8169: move the netpoll handler after the irq handler.
[linux-2.6.git] / drivers / net / ethernet / realtek / r8169.c
blob12329c5e1ede3085e24e49722567d693c56812a6
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48
49 #ifdef RTL8169_DEBUG
50 #define assert(expr) \
51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
54 }
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #else
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
61
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
71
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
87
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
99
100 enum mac_version {
101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
134 RTL_GIGA_MAC_VER_34,
135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
137 RTL_GIGA_MAC_NONE = 0xff,
138 };
139
140 enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143 };
144
145 #define JUMBO_1K ETH_DATA_LEN
146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151 #define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157 }
158
159 static const struct {
160 const char *name;
161 enum rtl_tx_desc_version txd_version;
162 const char *fw_name;
163 u16 jumbo_max;
164 bool jumbo_tx_csum;
165 } rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
169 [RTL_GIGA_MAC_VER_02] =
170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
171 [RTL_GIGA_MAC_VER_03] =
172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
173 [RTL_GIGA_MAC_VER_04] =
174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
175 [RTL_GIGA_MAC_VER_05] =
176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
177 [RTL_GIGA_MAC_VER_06] =
178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
182 [RTL_GIGA_MAC_VER_08] =
183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
184 [RTL_GIGA_MAC_VER_09] =
185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
186 [RTL_GIGA_MAC_VER_10] =
187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
188 [RTL_GIGA_MAC_VER_11] =
189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
190 [RTL_GIGA_MAC_VER_12] =
191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
192 [RTL_GIGA_MAC_VER_13] =
193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_14] =
195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_15] =
197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_16] =
199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
200 [RTL_GIGA_MAC_VER_17] =
201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_18] =
203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
204 [RTL_GIGA_MAC_VER_19] =
205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
206 [RTL_GIGA_MAC_VER_20] =
207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
208 [RTL_GIGA_MAC_VER_21] =
209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
210 [RTL_GIGA_MAC_VER_22] =
211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
212 [RTL_GIGA_MAC_VER_23] =
213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_24] =
215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_25] =
217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
219 [RTL_GIGA_MAC_VER_26] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
222 [RTL_GIGA_MAC_VER_27] =
223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
224 [RTL_GIGA_MAC_VER_28] =
225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
226 [RTL_GIGA_MAC_VER_29] =
227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
229 [RTL_GIGA_MAC_VER_30] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
232 [RTL_GIGA_MAC_VER_31] =
233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
234 [RTL_GIGA_MAC_VER_32] =
235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_33] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
240 [RTL_GIGA_MAC_VER_34] =
241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_35] =
244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_36] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
249 };
250 #undef _R
251
252 enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256 };
257
258 static void rtl_hw_start_8169(struct net_device *);
259 static void rtl_hw_start_8168(struct net_device *);
260 static void rtl_hw_start_8101(struct net_device *);
261
262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
276 {0,},
277 };
278
279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
281 static int rx_buf_sz = 16383;
282 static int use_dac;
283 static struct {
284 u32 msg_enable;
285 } debug = { -1 };
286
287 enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
289 MAC4 = 4,
290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
303
304 TxConfig = 0x40,
305 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
307
308 RxConfig = 0x44,
309 #define RX128_INT_EN (1 << 15) /* 8111c and later */
310 #define RX_MULTI_EN (1 << 14) /* 8111c only */
311 #define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314 #define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
317
318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340 #define TxPacketMax (8064 >> 7)
341 #define EarlySize 0x27
342
343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
347 };
348
349 enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353 };
354
355 enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358 #define CSIAR_FLAG 0x80000000
359 #define CSIAR_WRITE_CMD 0x80000000
360 #define CSIAR_BYTE_ENABLE 0x0f
361 #define CSIAR_BYTE_ENABLE_SHIFT 12
362 #define CSIAR_ADDR_MASK 0x0fff
363 PMCH = 0x6f,
364 EPHYAR = 0x80,
365 #define EPHYAR_FLAG 0x80000000
366 #define EPHYAR_WRITE_CMD 0x80000000
367 #define EPHYAR_REG_MASK 0x1f
368 #define EPHYAR_REG_SHIFT 16
369 #define EPHYAR_DATA_MASK 0xffff
370 DLLPR = 0xd0,
371 #define PFM_EN (1 << 6)
372 DBG_REG = 0xd1,
373 #define FIX_NAK_1 (1 << 4)
374 #define FIX_NAK_2 (1 << 3)
375 TWSI = 0xd2,
376 MCU = 0xd3,
377 #define NOW_IS_OOB (1 << 7)
378 #define EN_NDP (1 << 3)
379 #define EN_OOB_RESET (1 << 2)
380 EFUSEAR = 0xdc,
381 #define EFUSEAR_FLAG 0x80000000
382 #define EFUSEAR_WRITE_CMD 0x80000000
383 #define EFUSEAR_READ_CMD 0x00000000
384 #define EFUSEAR_REG_MASK 0x03ff
385 #define EFUSEAR_REG_SHIFT 8
386 #define EFUSEAR_DATA_MASK 0xff
387 };
388
389 enum rtl8168_registers {
390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
392 ERIDR = 0x70,
393 ERIAR = 0x74,
394 #define ERIAR_FLAG 0x80000000
395 #define ERIAR_WRITE_CMD 0x80000000
396 #define ERIAR_READ_CMD 0x00000000
397 #define ERIAR_ADDR_BYTE_ALIGN 4
398 #define ERIAR_TYPE_SHIFT 16
399 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_MASK_SHIFT 12
403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408 #define OCPDR_WRITE_CMD 0x80000000
409 #define OCPDR_READ_CMD 0x00000000
410 #define OCPDR_REG_MASK 0x7f
411 #define OCPDR_GPHY_REG_SHIFT 16
412 #define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414 #define OCPAR_FLAG 0x80000000
415 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
416 #define OCPAR_GPHY_READ_CMD 0x0000f060
417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
419 #define TXPLA_RST (1 << 29)
420 #define PWM_EN (1 << 22)
421 };
422
423 enum rtl_register_content {
424 /* InterruptStatusBits */
425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
436
437 /* RxStatusDesc */
438 RxBOVF = (1 << 24),
439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
444
445 /* ChipCmdBits */
446 StopReq = 0x80,
447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
451
452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
457 /* Cfg9346Bits */
458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
460
461 /* rx_mode_bits */
462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
468 #define RX_CONFIG_ACCEPT_MASK 0x3f
469
470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
474 /* Config1 register p.24 */
475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
481 PMEnable = (1 << 0), /* Power Management Enable */
482
483 /* Config2 register p. 25 */
484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
493
494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
497 /* Config5 register p.27 */
498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
501 Spi_en = (1 << 3),
502 LanWake = (1 << 1), /* LanWake enable/disable */
503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
532
533 /* rtl8169_PHYstatus */
534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
542
543 /* _TBICSRBit */
544 TBILinkOK = 0x02000000,
545
546 /* DumpCounterCommand */
547 CounterDump = 0x8,
548 };
549
550 enum rtl_desc_bit {
551 /* First doubleword. */
552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
556 };
557
558 /* Generic case. */
559 enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562 #define TD_MSS_MAX 0x07ffu /* MSS value */
563
564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566 };
567
568 /* 8169, 8168b and 810x except 8102e. */
569 enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575 };
576
577 /* 8102e, 8168c and beyond. */
578 enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584 };
585
586 static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593 } tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610 };
611
612 enum rtl_rx_desc_bit {
613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617 #define RxProtoUDP (PID1)
618 #define RxProtoTCP (PID0)
619 #define RxProtoIP (PID1 | PID0)
620 #define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626 };
627
628 #define RsvdMask 0x3fffc000
629
630 struct TxDesc {
631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
634 };
635
636 struct RxDesc {
637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
640 };
641
642 struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646 };
647
648 enum features {
649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
652 };
653
654 struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668 };
669
670 enum rtl_flag {
671 RTL_FLAG_TASK_ENABLED,
672 RTL_FLAG_TASK_SLOW_PENDING,
673 RTL_FLAG_TASK_RESET_PENDING,
674 RTL_FLAG_TASK_PHY_PENDING,
675 RTL_FLAG_MAX
676 };
677
678 struct rtl8169_stats {
679 u64 packets;
680 u64 bytes;
681 struct u64_stats_sync syncp;
682 };
683
684 struct rtl8169_private {
685 void __iomem *mmio_addr; /* memory map physical address */
686 struct pci_dev *pci_dev;
687 struct net_device *dev;
688 struct napi_struct napi;
689 u32 msg_enable;
690 u16 txd_version;
691 u16 mac_version;
692 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
693 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
694 u32 dirty_rx;
695 u32 dirty_tx;
696 struct rtl8169_stats rx_stats;
697 struct rtl8169_stats tx_stats;
698 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
699 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
700 dma_addr_t TxPhyAddr;
701 dma_addr_t RxPhyAddr;
702 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
703 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
704 struct timer_list timer;
705 u16 cp_cmd;
706
707 u16 event_slow;
708
709 struct mdio_ops {
710 void (*write)(void __iomem *, int, int);
711 int (*read)(void __iomem *, int);
712 } mdio_ops;
713
714 struct pll_power_ops {
715 void (*down)(struct rtl8169_private *);
716 void (*up)(struct rtl8169_private *);
717 } pll_power_ops;
718
719 struct jumbo_ops {
720 void (*enable)(struct rtl8169_private *);
721 void (*disable)(struct rtl8169_private *);
722 } jumbo_ops;
723
724 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
725 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
726 void (*phy_reset_enable)(struct rtl8169_private *tp);
727 void (*hw_start)(struct net_device *);
728 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
729 unsigned int (*link_ok)(void __iomem *);
730 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
731
732 struct {
733 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
734 struct mutex mutex;
735 struct work_struct work;
736 } wk;
737
738 unsigned features;
739
740 struct mii_if_info mii;
741 struct rtl8169_counters counters;
742 u32 saved_wolopts;
743 u32 opts1_mask;
744
745 struct rtl_fw {
746 const struct firmware *fw;
747
748 #define RTL_VER_SIZE 32
749
750 char version[RTL_VER_SIZE];
751
752 struct rtl_fw_phy_action {
753 __le32 *code;
754 size_t size;
755 } phy_action;
756 } *rtl_fw;
757 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
758 };
759
760 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
761 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
762 module_param(use_dac, int, 0);
763 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
764 module_param_named(debug, debug.msg_enable, int, 0);
765 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
766 MODULE_LICENSE("GPL");
767 MODULE_VERSION(RTL8169_VERSION);
768 MODULE_FIRMWARE(FIRMWARE_8168D_1);
769 MODULE_FIRMWARE(FIRMWARE_8168D_2);
770 MODULE_FIRMWARE(FIRMWARE_8168E_1);
771 MODULE_FIRMWARE(FIRMWARE_8168E_2);
772 MODULE_FIRMWARE(FIRMWARE_8168E_3);
773 MODULE_FIRMWARE(FIRMWARE_8105E_1);
774 MODULE_FIRMWARE(FIRMWARE_8168F_1);
775 MODULE_FIRMWARE(FIRMWARE_8168F_2);
776
777 static void rtl_lock_work(struct rtl8169_private *tp)
778 {
779 mutex_lock(&tp->wk.mutex);
780 }
781
782 static void rtl_unlock_work(struct rtl8169_private *tp)
783 {
784 mutex_unlock(&tp->wk.mutex);
785 }
786
787 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
788 {
789 int cap = pci_pcie_cap(pdev);
790
791 if (cap) {
792 u16 ctl;
793
794 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
795 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
796 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
797 }
798 }
799
800 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
801 {
802 void __iomem *ioaddr = tp->mmio_addr;
803 int i;
804
805 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
806 for (i = 0; i < 20; i++) {
807 udelay(100);
808 if (RTL_R32(OCPAR) & OCPAR_FLAG)
809 break;
810 }
811 return RTL_R32(OCPDR);
812 }
813
814 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
815 {
816 void __iomem *ioaddr = tp->mmio_addr;
817 int i;
818
819 RTL_W32(OCPDR, data);
820 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
821 for (i = 0; i < 20; i++) {
822 udelay(100);
823 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
824 break;
825 }
826 }
827
828 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
829 {
830 void __iomem *ioaddr = tp->mmio_addr;
831 int i;
832
833 RTL_W8(ERIDR, cmd);
834 RTL_W32(ERIAR, 0x800010e8);
835 msleep(2);
836 for (i = 0; i < 5; i++) {
837 udelay(100);
838 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
839 break;
840 }
841
842 ocp_write(tp, 0x1, 0x30, 0x00000001);
843 }
844
845 #define OOB_CMD_RESET 0x00
846 #define OOB_CMD_DRIVER_START 0x05
847 #define OOB_CMD_DRIVER_STOP 0x06
848
849 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
850 {
851 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
852 }
853
854 static void rtl8168_driver_start(struct rtl8169_private *tp)
855 {
856 u16 reg;
857 int i;
858
859 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
860
861 reg = rtl8168_get_ocp_reg(tp);
862
863 for (i = 0; i < 10; i++) {
864 msleep(10);
865 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
866 break;
867 }
868 }
869
870 static void rtl8168_driver_stop(struct rtl8169_private *tp)
871 {
872 u16 reg;
873 int i;
874
875 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
876
877 reg = rtl8168_get_ocp_reg(tp);
878
879 for (i = 0; i < 10; i++) {
880 msleep(10);
881 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
882 break;
883 }
884 }
885
886 static int r8168dp_check_dash(struct rtl8169_private *tp)
887 {
888 u16 reg = rtl8168_get_ocp_reg(tp);
889
890 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
891 }
892
893 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
894 {
895 int i;
896
897 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
898
899 for (i = 20; i > 0; i--) {
900 /*
901 * Check if the RTL8169 has completed writing to the specified
902 * MII register.
903 */
904 if (!(RTL_R32(PHYAR) & 0x80000000))
905 break;
906 udelay(25);
907 }
908 /*
909 * According to hardware specs a 20us delay is required after write
910 * complete indication, but before sending next command.
911 */
912 udelay(20);
913 }
914
915 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
916 {
917 int i, value = -1;
918
919 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
920
921 for (i = 20; i > 0; i--) {
922 /*
923 * Check if the RTL8169 has completed retrieving data from
924 * the specified MII register.
925 */
926 if (RTL_R32(PHYAR) & 0x80000000) {
927 value = RTL_R32(PHYAR) & 0xffff;
928 break;
929 }
930 udelay(25);
931 }
932 /*
933 * According to hardware specs a 20us delay is required after read
934 * complete indication, but before sending next command.
935 */
936 udelay(20);
937
938 return value;
939 }
940
941 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
942 {
943 int i;
944
945 RTL_W32(OCPDR, data |
946 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
947 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
948 RTL_W32(EPHY_RXER_NUM, 0);
949
950 for (i = 0; i < 100; i++) {
951 mdelay(1);
952 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
953 break;
954 }
955 }
956
957 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
958 {
959 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
960 (value & OCPDR_DATA_MASK));
961 }
962
963 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
964 {
965 int i;
966
967 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
968
969 mdelay(1);
970 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
971 RTL_W32(EPHY_RXER_NUM, 0);
972
973 for (i = 0; i < 100; i++) {
974 mdelay(1);
975 if (RTL_R32(OCPAR) & OCPAR_FLAG)
976 break;
977 }
978
979 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
980 }
981
982 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
983
984 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
985 {
986 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
987 }
988
989 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
990 {
991 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
992 }
993
994 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
995 {
996 r8168dp_2_mdio_start(ioaddr);
997
998 r8169_mdio_write(ioaddr, reg_addr, value);
999
1000 r8168dp_2_mdio_stop(ioaddr);
1001 }
1002
1003 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1004 {
1005 int value;
1006
1007 r8168dp_2_mdio_start(ioaddr);
1008
1009 value = r8169_mdio_read(ioaddr, reg_addr);
1010
1011 r8168dp_2_mdio_stop(ioaddr);
1012
1013 return value;
1014 }
1015
1016 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1017 {
1018 tp->mdio_ops.write(tp->mmio_addr, location, val);
1019 }
1020
1021 static int rtl_readphy(struct rtl8169_private *tp, int location)
1022 {
1023 return tp->mdio_ops.read(tp->mmio_addr, location);
1024 }
1025
1026 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027 {
1028 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1029 }
1030
1031 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1032 {
1033 int val;
1034
1035 val = rtl_readphy(tp, reg_addr);
1036 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1037 }
1038
1039 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1040 int val)
1041 {
1042 struct rtl8169_private *tp = netdev_priv(dev);
1043
1044 rtl_writephy(tp, location, val);
1045 }
1046
1047 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1048 {
1049 struct rtl8169_private *tp = netdev_priv(dev);
1050
1051 return rtl_readphy(tp, location);
1052 }
1053
1054 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1055 {
1056 unsigned int i;
1057
1058 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1059 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060
1061 for (i = 0; i < 100; i++) {
1062 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1063 break;
1064 udelay(10);
1065 }
1066 }
1067
1068 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1069 {
1070 u16 value = 0xffff;
1071 unsigned int i;
1072
1073 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1074
1075 for (i = 0; i < 100; i++) {
1076 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1077 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1078 break;
1079 }
1080 udelay(10);
1081 }
1082
1083 return value;
1084 }
1085
1086 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1087 {
1088 unsigned int i;
1089
1090 RTL_W32(CSIDR, value);
1091 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1092 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1093
1094 for (i = 0; i < 100; i++) {
1095 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1096 break;
1097 udelay(10);
1098 }
1099 }
1100
1101 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1102 {
1103 u32 value = ~0x00;
1104 unsigned int i;
1105
1106 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1107 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1108
1109 for (i = 0; i < 100; i++) {
1110 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1111 value = RTL_R32(CSIDR);
1112 break;
1113 }
1114 udelay(10);
1115 }
1116
1117 return value;
1118 }
1119
1120 static
1121 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1122 {
1123 unsigned int i;
1124
1125 BUG_ON((addr & 3) || (mask == 0));
1126 RTL_W32(ERIDR, val);
1127 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1128
1129 for (i = 0; i < 100; i++) {
1130 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1131 break;
1132 udelay(100);
1133 }
1134 }
1135
1136 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1137 {
1138 u32 value = ~0x00;
1139 unsigned int i;
1140
1141 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1142
1143 for (i = 0; i < 100; i++) {
1144 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1145 value = RTL_R32(ERIDR);
1146 break;
1147 }
1148 udelay(100);
1149 }
1150
1151 return value;
1152 }
1153
1154 static void
1155 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1156 {
1157 u32 val;
1158
1159 val = rtl_eri_read(ioaddr, addr, type);
1160 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1161 }
1162
1163 struct exgmac_reg {
1164 u16 addr;
1165 u16 mask;
1166 u32 val;
1167 };
1168
1169 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1170 const struct exgmac_reg *r, int len)
1171 {
1172 while (len-- > 0) {
1173 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1174 r++;
1175 }
1176 }
1177
1178 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1179 {
1180 u8 value = 0xff;
1181 unsigned int i;
1182
1183 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1184
1185 for (i = 0; i < 300; i++) {
1186 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1187 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1188 break;
1189 }
1190 udelay(100);
1191 }
1192
1193 return value;
1194 }
1195
1196 static u16 rtl_get_events(struct rtl8169_private *tp)
1197 {
1198 void __iomem *ioaddr = tp->mmio_addr;
1199
1200 return RTL_R16(IntrStatus);
1201 }
1202
1203 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1204 {
1205 void __iomem *ioaddr = tp->mmio_addr;
1206
1207 RTL_W16(IntrStatus, bits);
1208 mmiowb();
1209 }
1210
1211 static void rtl_irq_disable(struct rtl8169_private *tp)
1212 {
1213 void __iomem *ioaddr = tp->mmio_addr;
1214
1215 RTL_W16(IntrMask, 0);
1216 mmiowb();
1217 }
1218
1219 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1220 {
1221 void __iomem *ioaddr = tp->mmio_addr;
1222
1223 RTL_W16(IntrMask, bits);
1224 }
1225
1226 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1227 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1228 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1229
1230 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1231 {
1232 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1233 }
1234
1235 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1236 {
1237 void __iomem *ioaddr = tp->mmio_addr;
1238
1239 rtl_irq_disable(tp);
1240 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1241 RTL_R8(ChipCmd);
1242 }
1243
1244 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1245 {
1246 void __iomem *ioaddr = tp->mmio_addr;
1247
1248 return RTL_R32(TBICSR) & TBIReset;
1249 }
1250
1251 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1252 {
1253 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1254 }
1255
1256 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1257 {
1258 return RTL_R32(TBICSR) & TBILinkOk;
1259 }
1260
1261 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1262 {
1263 return RTL_R8(PHYstatus) & LinkStatus;
1264 }
1265
1266 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1267 {
1268 void __iomem *ioaddr = tp->mmio_addr;
1269
1270 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1271 }
1272
1273 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1274 {
1275 unsigned int val;
1276
1277 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1278 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1279 }
1280
1281 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1282 {
1283 void __iomem *ioaddr = tp->mmio_addr;
1284 struct net_device *dev = tp->dev;
1285
1286 if (!netif_running(dev))
1287 return;
1288
1289 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1290 if (RTL_R8(PHYstatus) & _1000bpsF) {
1291 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1292 0x00000011, ERIAR_EXGMAC);
1293 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1294 0x00000005, ERIAR_EXGMAC);
1295 } else if (RTL_R8(PHYstatus) & _100bps) {
1296 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1297 0x0000001f, ERIAR_EXGMAC);
1298 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1299 0x00000005, ERIAR_EXGMAC);
1300 } else {
1301 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1302 0x0000001f, ERIAR_EXGMAC);
1303 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1304 0x0000003f, ERIAR_EXGMAC);
1305 }
1306 /* Reset packet filter */
1307 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1308 ERIAR_EXGMAC);
1309 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1310 ERIAR_EXGMAC);
1311 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1312 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1313 if (RTL_R8(PHYstatus) & _1000bpsF) {
1314 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1315 0x00000011, ERIAR_EXGMAC);
1316 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1317 0x00000005, ERIAR_EXGMAC);
1318 } else {
1319 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1320 0x0000001f, ERIAR_EXGMAC);
1321 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1322 0x0000003f, ERIAR_EXGMAC);
1323 }
1324 }
1325 }
1326
1327 static void __rtl8169_check_link_status(struct net_device *dev,
1328 struct rtl8169_private *tp,
1329 void __iomem *ioaddr, bool pm)
1330 {
1331 if (tp->link_ok(ioaddr)) {
1332 rtl_link_chg_patch(tp);
1333 /* This is to cancel a scheduled suspend if there's one. */
1334 if (pm)
1335 pm_request_resume(&tp->pci_dev->dev);
1336 netif_carrier_on(dev);
1337 if (net_ratelimit())
1338 netif_info(tp, ifup, dev, "link up\n");
1339 } else {
1340 netif_carrier_off(dev);
1341 netif_info(tp, ifdown, dev, "link down\n");
1342 if (pm)
1343 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1344 }
1345 }
1346
1347 static void rtl8169_check_link_status(struct net_device *dev,
1348 struct rtl8169_private *tp,
1349 void __iomem *ioaddr)
1350 {
1351 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1352 }
1353
1354 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1355
1356 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1357 {
1358 void __iomem *ioaddr = tp->mmio_addr;
1359 u8 options;
1360 u32 wolopts = 0;
1361
1362 options = RTL_R8(Config1);
1363 if (!(options & PMEnable))
1364 return 0;
1365
1366 options = RTL_R8(Config3);
1367 if (options & LinkUp)
1368 wolopts |= WAKE_PHY;
1369 if (options & MagicPacket)
1370 wolopts |= WAKE_MAGIC;
1371
1372 options = RTL_R8(Config5);
1373 if (options & UWF)
1374 wolopts |= WAKE_UCAST;
1375 if (options & BWF)
1376 wolopts |= WAKE_BCAST;
1377 if (options & MWF)
1378 wolopts |= WAKE_MCAST;
1379
1380 return wolopts;
1381 }
1382
1383 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1384 {
1385 struct rtl8169_private *tp = netdev_priv(dev);
1386
1387 rtl_lock_work(tp);
1388
1389 wol->supported = WAKE_ANY;
1390 wol->wolopts = __rtl8169_get_wol(tp);
1391
1392 rtl_unlock_work(tp);
1393 }
1394
1395 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1396 {
1397 void __iomem *ioaddr = tp->mmio_addr;
1398 unsigned int i;
1399 static const struct {
1400 u32 opt;
1401 u16 reg;
1402 u8 mask;
1403 } cfg[] = {
1404 { WAKE_ANY, Config1, PMEnable },
1405 { WAKE_PHY, Config3, LinkUp },
1406 { WAKE_MAGIC, Config3, MagicPacket },
1407 { WAKE_UCAST, Config5, UWF },
1408 { WAKE_BCAST, Config5, BWF },
1409 { WAKE_MCAST, Config5, MWF },
1410 { WAKE_ANY, Config5, LanWake }
1411 };
1412
1413 RTL_W8(Cfg9346, Cfg9346_Unlock);
1414
1415 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1416 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1417 if (wolopts & cfg[i].opt)
1418 options |= cfg[i].mask;
1419 RTL_W8(cfg[i].reg, options);
1420 }
1421
1422 RTL_W8(Cfg9346, Cfg9346_Lock);
1423 }
1424
1425 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1426 {
1427 struct rtl8169_private *tp = netdev_priv(dev);
1428
1429 rtl_lock_work(tp);
1430
1431 if (wol->wolopts)
1432 tp->features |= RTL_FEATURE_WOL;
1433 else
1434 tp->features &= ~RTL_FEATURE_WOL;
1435 __rtl8169_set_wol(tp, wol->wolopts);
1436
1437 rtl_unlock_work(tp);
1438
1439 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1440
1441 return 0;
1442 }
1443
1444 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1445 {
1446 return rtl_chip_infos[tp->mac_version].fw_name;
1447 }
1448
1449 static void rtl8169_get_drvinfo(struct net_device *dev,
1450 struct ethtool_drvinfo *info)
1451 {
1452 struct rtl8169_private *tp = netdev_priv(dev);
1453 struct rtl_fw *rtl_fw = tp->rtl_fw;
1454
1455 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1456 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1457 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1458 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1459 if (!IS_ERR_OR_NULL(rtl_fw))
1460 strlcpy(info->fw_version, rtl_fw->version,
1461 sizeof(info->fw_version));
1462 }
1463
1464 static int rtl8169_get_regs_len(struct net_device *dev)
1465 {
1466 return R8169_REGS_SIZE;
1467 }
1468
1469 static int rtl8169_set_speed_tbi(struct net_device *dev,
1470 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1471 {
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473 void __iomem *ioaddr = tp->mmio_addr;
1474 int ret = 0;
1475 u32 reg;
1476
1477 reg = RTL_R32(TBICSR);
1478 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1479 (duplex == DUPLEX_FULL)) {
1480 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1481 } else if (autoneg == AUTONEG_ENABLE)
1482 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1483 else {
1484 netif_warn(tp, link, dev,
1485 "incorrect speed setting refused in TBI mode\n");
1486 ret = -EOPNOTSUPP;
1487 }
1488
1489 return ret;
1490 }
1491
1492 static int rtl8169_set_speed_xmii(struct net_device *dev,
1493 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1494 {
1495 struct rtl8169_private *tp = netdev_priv(dev);
1496 int giga_ctrl, bmcr;
1497 int rc = -EINVAL;
1498
1499 rtl_writephy(tp, 0x1f, 0x0000);
1500
1501 if (autoneg == AUTONEG_ENABLE) {
1502 int auto_nego;
1503
1504 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1505 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1506 ADVERTISE_100HALF | ADVERTISE_100FULL);
1507
1508 if (adv & ADVERTISED_10baseT_Half)
1509 auto_nego |= ADVERTISE_10HALF;
1510 if (adv & ADVERTISED_10baseT_Full)
1511 auto_nego |= ADVERTISE_10FULL;
1512 if (adv & ADVERTISED_100baseT_Half)
1513 auto_nego |= ADVERTISE_100HALF;
1514 if (adv & ADVERTISED_100baseT_Full)
1515 auto_nego |= ADVERTISE_100FULL;
1516
1517 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1518
1519 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1520 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1521
1522 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1523 if (tp->mii.supports_gmii) {
1524 if (adv & ADVERTISED_1000baseT_Half)
1525 giga_ctrl |= ADVERTISE_1000HALF;
1526 if (adv & ADVERTISED_1000baseT_Full)
1527 giga_ctrl |= ADVERTISE_1000FULL;
1528 } else if (adv & (ADVERTISED_1000baseT_Half |
1529 ADVERTISED_1000baseT_Full)) {
1530 netif_info(tp, link, dev,
1531 "PHY does not support 1000Mbps\n");
1532 goto out;
1533 }
1534
1535 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1536
1537 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1538 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1539 } else {
1540 giga_ctrl = 0;
1541
1542 if (speed == SPEED_10)
1543 bmcr = 0;
1544 else if (speed == SPEED_100)
1545 bmcr = BMCR_SPEED100;
1546 else
1547 goto out;
1548
1549 if (duplex == DUPLEX_FULL)
1550 bmcr |= BMCR_FULLDPLX;
1551 }
1552
1553 rtl_writephy(tp, MII_BMCR, bmcr);
1554
1555 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1556 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1557 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1558 rtl_writephy(tp, 0x17, 0x2138);
1559 rtl_writephy(tp, 0x0e, 0x0260);
1560 } else {
1561 rtl_writephy(tp, 0x17, 0x2108);
1562 rtl_writephy(tp, 0x0e, 0x0000);
1563 }
1564 }
1565
1566 rc = 0;
1567 out:
1568 return rc;
1569 }
1570
1571 static int rtl8169_set_speed(struct net_device *dev,
1572 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1573 {
1574 struct rtl8169_private *tp = netdev_priv(dev);
1575 int ret;
1576
1577 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1578 if (ret < 0)
1579 goto out;
1580
1581 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1582 (advertising & ADVERTISED_1000baseT_Full)) {
1583 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1584 }
1585 out:
1586 return ret;
1587 }
1588
1589 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1590 {
1591 struct rtl8169_private *tp = netdev_priv(dev);
1592 int ret;
1593
1594 del_timer_sync(&tp->timer);
1595
1596 rtl_lock_work(tp);
1597 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1598 cmd->duplex, cmd->advertising);
1599 rtl_unlock_work(tp);
1600
1601 return ret;
1602 }
1603
1604 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1605 netdev_features_t features)
1606 {
1607 struct rtl8169_private *tp = netdev_priv(dev);
1608
1609 if (dev->mtu > TD_MSS_MAX)
1610 features &= ~NETIF_F_ALL_TSO;
1611
1612 if (dev->mtu > JUMBO_1K &&
1613 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1614 features &= ~NETIF_F_IP_CSUM;
1615
1616 return features;
1617 }
1618
1619 static void __rtl8169_set_features(struct net_device *dev,
1620 netdev_features_t features)
1621 {
1622 struct rtl8169_private *tp = netdev_priv(dev);
1623 netdev_features_t changed = features ^ dev->features;
1624 void __iomem *ioaddr = tp->mmio_addr;
1625
1626 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1627 return;
1628
1629 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1630 if (features & NETIF_F_RXCSUM)
1631 tp->cp_cmd |= RxChkSum;
1632 else
1633 tp->cp_cmd &= ~RxChkSum;
1634
1635 if (dev->features & NETIF_F_HW_VLAN_RX)
1636 tp->cp_cmd |= RxVlan;
1637 else
1638 tp->cp_cmd &= ~RxVlan;
1639
1640 RTL_W16(CPlusCmd, tp->cp_cmd);
1641 RTL_R16(CPlusCmd);
1642 }
1643 if (changed & NETIF_F_RXALL) {
1644 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1645 if (features & NETIF_F_RXALL)
1646 tmp |= (AcceptErr | AcceptRunt);
1647 RTL_W32(RxConfig, tmp);
1648 }
1649 }
1650
1651 static int rtl8169_set_features(struct net_device *dev,
1652 netdev_features_t features)
1653 {
1654 struct rtl8169_private *tp = netdev_priv(dev);
1655
1656 rtl_lock_work(tp);
1657 __rtl8169_set_features(dev, features);
1658 rtl_unlock_work(tp);
1659
1660 return 0;
1661 }
1662
1663
1664 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1665 struct sk_buff *skb)
1666 {
1667 return (vlan_tx_tag_present(skb)) ?
1668 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1669 }
1670
1671 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1672 {
1673 u32 opts2 = le32_to_cpu(desc->opts2);
1674
1675 if (opts2 & RxVlanTag)
1676 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1677
1678 desc->opts2 = 0;
1679 }
1680
1681 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1682 {
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684 void __iomem *ioaddr = tp->mmio_addr;
1685 u32 status;
1686
1687 cmd->supported =
1688 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1689 cmd->port = PORT_FIBRE;
1690 cmd->transceiver = XCVR_INTERNAL;
1691
1692 status = RTL_R32(TBICSR);
1693 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1694 cmd->autoneg = !!(status & TBINwEnable);
1695
1696 ethtool_cmd_speed_set(cmd, SPEED_1000);
1697 cmd->duplex = DUPLEX_FULL; /* Always set */
1698
1699 return 0;
1700 }
1701
1702 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1703 {
1704 struct rtl8169_private *tp = netdev_priv(dev);
1705
1706 return mii_ethtool_gset(&tp->mii, cmd);
1707 }
1708
1709 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1710 {
1711 struct rtl8169_private *tp = netdev_priv(dev);
1712 int rc;
1713
1714 rtl_lock_work(tp);
1715 rc = tp->get_settings(dev, cmd);
1716 rtl_unlock_work(tp);
1717
1718 return rc;
1719 }
1720
1721 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1722 void *p)
1723 {
1724 struct rtl8169_private *tp = netdev_priv(dev);
1725
1726 if (regs->len > R8169_REGS_SIZE)
1727 regs->len = R8169_REGS_SIZE;
1728
1729 rtl_lock_work(tp);
1730 memcpy_fromio(p, tp->mmio_addr, regs->len);
1731 rtl_unlock_work(tp);
1732 }
1733
1734 static u32 rtl8169_get_msglevel(struct net_device *dev)
1735 {
1736 struct rtl8169_private *tp = netdev_priv(dev);
1737
1738 return tp->msg_enable;
1739 }
1740
1741 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1742 {
1743 struct rtl8169_private *tp = netdev_priv(dev);
1744
1745 tp->msg_enable = value;
1746 }
1747
1748 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1749 "tx_packets",
1750 "rx_packets",
1751 "tx_errors",
1752 "rx_errors",
1753 "rx_missed",
1754 "align_errors",
1755 "tx_single_collisions",
1756 "tx_multi_collisions",
1757 "unicast",
1758 "broadcast",
1759 "multicast",
1760 "tx_aborted",
1761 "tx_underrun",
1762 };
1763
1764 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1765 {
1766 switch (sset) {
1767 case ETH_SS_STATS:
1768 return ARRAY_SIZE(rtl8169_gstrings);
1769 default:
1770 return -EOPNOTSUPP;
1771 }
1772 }
1773
1774 static void rtl8169_update_counters(struct net_device *dev)
1775 {
1776 struct rtl8169_private *tp = netdev_priv(dev);
1777 void __iomem *ioaddr = tp->mmio_addr;
1778 struct device *d = &tp->pci_dev->dev;
1779 struct rtl8169_counters *counters;
1780 dma_addr_t paddr;
1781 u32 cmd;
1782 int wait = 1000;
1783
1784 /*
1785 * Some chips are unable to dump tally counters when the receiver
1786 * is disabled.
1787 */
1788 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1789 return;
1790
1791 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1792 if (!counters)
1793 return;
1794
1795 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1796 cmd = (u64)paddr & DMA_BIT_MASK(32);
1797 RTL_W32(CounterAddrLow, cmd);
1798 RTL_W32(CounterAddrLow, cmd | CounterDump);
1799
1800 while (wait--) {
1801 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1802 memcpy(&tp->counters, counters, sizeof(*counters));
1803 break;
1804 }
1805 udelay(10);
1806 }
1807
1808 RTL_W32(CounterAddrLow, 0);
1809 RTL_W32(CounterAddrHigh, 0);
1810
1811 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1812 }
1813
1814 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1815 struct ethtool_stats *stats, u64 *data)
1816 {
1817 struct rtl8169_private *tp = netdev_priv(dev);
1818
1819 ASSERT_RTNL();
1820
1821 rtl8169_update_counters(dev);
1822
1823 data[0] = le64_to_cpu(tp->counters.tx_packets);
1824 data[1] = le64_to_cpu(tp->counters.rx_packets);
1825 data[2] = le64_to_cpu(tp->counters.tx_errors);
1826 data[3] = le32_to_cpu(tp->counters.rx_errors);
1827 data[4] = le16_to_cpu(tp->counters.rx_missed);
1828 data[5] = le16_to_cpu(tp->counters.align_errors);
1829 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1830 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1831 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1832 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1833 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1834 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1835 data[12] = le16_to_cpu(tp->counters.tx_underun);
1836 }
1837
1838 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1839 {
1840 switch(stringset) {
1841 case ETH_SS_STATS:
1842 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1843 break;
1844 }
1845 }
1846
1847 static const struct ethtool_ops rtl8169_ethtool_ops = {
1848 .get_drvinfo = rtl8169_get_drvinfo,
1849 .get_regs_len = rtl8169_get_regs_len,
1850 .get_link = ethtool_op_get_link,
1851 .get_settings = rtl8169_get_settings,
1852 .set_settings = rtl8169_set_settings,
1853 .get_msglevel = rtl8169_get_msglevel,
1854 .set_msglevel = rtl8169_set_msglevel,
1855 .get_regs = rtl8169_get_regs,
1856 .get_wol = rtl8169_get_wol,
1857 .set_wol = rtl8169_set_wol,
1858 .get_strings = rtl8169_get_strings,
1859 .get_sset_count = rtl8169_get_sset_count,
1860 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1861 };
1862
1863 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1864 struct net_device *dev, u8 default_version)
1865 {
1866 void __iomem *ioaddr = tp->mmio_addr;
1867 /*
1868 * The driver currently handles the 8168Bf and the 8168Be identically
1869 * but they can be identified more specifically through the test below
1870 * if needed:
1871 *
1872 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1873 *
1874 * Same thing for the 8101Eb and the 8101Ec:
1875 *
1876 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1877 */
1878 static const struct rtl_mac_info {
1879 u32 mask;
1880 u32 val;
1881 int mac_version;
1882 } mac_info[] = {
1883 /* 8168F family. */
1884 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1885 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1886
1887 /* 8168E family. */
1888 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1889 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1890 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1891 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1892
1893 /* 8168D family. */
1894 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1895 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1896 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1897
1898 /* 8168DP family. */
1899 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1900 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1901 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1902
1903 /* 8168C family. */
1904 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1905 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1906 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1907 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1908 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1909 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1910 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1911 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1912 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1913
1914 /* 8168B family. */
1915 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1916 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1917 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1918 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1919
1920 /* 8101 family. */
1921 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1922 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1923 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1924 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1925 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1926 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1927 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1928 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1929 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1930 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1931 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1932 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1933 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1934 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1935 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1936 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1937 /* FIXME: where did these entries come from ? -- FR */
1938 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1939 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1940
1941 /* 8110 family. */
1942 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1943 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1944 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1945 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1946 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1947 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1948
1949 /* Catch-all */
1950 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1951 };
1952 const struct rtl_mac_info *p = mac_info;
1953 u32 reg;
1954
1955 reg = RTL_R32(TxConfig);
1956 while ((reg & p->mask) != p->val)
1957 p++;
1958 tp->mac_version = p->mac_version;
1959
1960 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1961 netif_notice(tp, probe, dev,
1962 "unknown MAC, using family default\n");
1963 tp->mac_version = default_version;
1964 }
1965 }
1966
1967 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1968 {
1969 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1970 }
1971
1972 struct phy_reg {
1973 u16 reg;
1974 u16 val;
1975 };
1976
1977 static void rtl_writephy_batch(struct rtl8169_private *tp,
1978 const struct phy_reg *regs, int len)
1979 {
1980 while (len-- > 0) {
1981 rtl_writephy(tp, regs->reg, regs->val);
1982 regs++;
1983 }
1984 }
1985
1986 #define PHY_READ 0x00000000
1987 #define PHY_DATA_OR 0x10000000
1988 #define PHY_DATA_AND 0x20000000
1989 #define PHY_BJMPN 0x30000000
1990 #define PHY_READ_EFUSE 0x40000000
1991 #define PHY_READ_MAC_BYTE 0x50000000
1992 #define PHY_WRITE_MAC_BYTE 0x60000000
1993 #define PHY_CLEAR_READCOUNT 0x70000000
1994 #define PHY_WRITE 0x80000000
1995 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1996 #define PHY_COMP_EQ_SKIPN 0xa0000000
1997 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1998 #define PHY_WRITE_PREVIOUS 0xc0000000
1999 #define PHY_SKIPN 0xd0000000
2000 #define PHY_DELAY_MS 0xe0000000
2001 #define PHY_WRITE_ERI_WORD 0xf0000000
2002
2003 struct fw_info {
2004 u32 magic;
2005 char version[RTL_VER_SIZE];
2006 __le32 fw_start;
2007 __le32 fw_len;
2008 u8 chksum;
2009 } __packed;
2010
2011 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2012
2013 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2014 {
2015 const struct firmware *fw = rtl_fw->fw;
2016 struct fw_info *fw_info = (struct fw_info *)fw->data;
2017 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2018 char *version = rtl_fw->version;
2019 bool rc = false;
2020
2021 if (fw->size < FW_OPCODE_SIZE)
2022 goto out;
2023
2024 if (!fw_info->magic) {
2025 size_t i, size, start;
2026 u8 checksum = 0;
2027
2028 if (fw->size < sizeof(*fw_info))
2029 goto out;
2030
2031 for (i = 0; i < fw->size; i++)
2032 checksum += fw->data[i];
2033 if (checksum != 0)
2034 goto out;
2035
2036 start = le32_to_cpu(fw_info->fw_start);
2037 if (start > fw->size)
2038 goto out;
2039
2040 size = le32_to_cpu(fw_info->fw_len);
2041 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2042 goto out;
2043
2044 memcpy(version, fw_info->version, RTL_VER_SIZE);
2045
2046 pa->code = (__le32 *)(fw->data + start);
2047 pa->size = size;
2048 } else {
2049 if (fw->size % FW_OPCODE_SIZE)
2050 goto out;
2051
2052 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2053
2054 pa->code = (__le32 *)fw->data;
2055 pa->size = fw->size / FW_OPCODE_SIZE;
2056 }
2057 version[RTL_VER_SIZE - 1] = 0;
2058
2059 rc = true;
2060 out:
2061 return rc;
2062 }
2063
2064 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2065 struct rtl_fw_phy_action *pa)
2066 {
2067 bool rc = false;
2068 size_t index;
2069
2070 for (index = 0; index < pa->size; index++) {
2071 u32 action = le32_to_cpu(pa->code[index]);
2072 u32 regno = (action & 0x0fff0000) >> 16;
2073
2074 switch(action & 0xf0000000) {
2075 case PHY_READ:
2076 case PHY_DATA_OR:
2077 case PHY_DATA_AND:
2078 case PHY_READ_EFUSE:
2079 case PHY_CLEAR_READCOUNT:
2080 case PHY_WRITE:
2081 case PHY_WRITE_PREVIOUS:
2082 case PHY_DELAY_MS:
2083 break;
2084
2085 case PHY_BJMPN:
2086 if (regno > index) {
2087 netif_err(tp, ifup, tp->dev,
2088 "Out of range of firmware\n");
2089 goto out;
2090 }
2091 break;
2092 case PHY_READCOUNT_EQ_SKIP:
2093 if (index + 2 >= pa->size) {
2094 netif_err(tp, ifup, tp->dev,
2095 "Out of range of firmware\n");
2096 goto out;
2097 }
2098 break;
2099 case PHY_COMP_EQ_SKIPN:
2100 case PHY_COMP_NEQ_SKIPN:
2101 case PHY_SKIPN:
2102 if (index + 1 + regno >= pa->size) {
2103 netif_err(tp, ifup, tp->dev,
2104 "Out of range of firmware\n");
2105 goto out;
2106 }
2107 break;
2108
2109 case PHY_READ_MAC_BYTE:
2110 case PHY_WRITE_MAC_BYTE:
2111 case PHY_WRITE_ERI_WORD:
2112 default:
2113 netif_err(tp, ifup, tp->dev,
2114 "Invalid action 0x%08x\n", action);
2115 goto out;
2116 }
2117 }
2118 rc = true;
2119 out:
2120 return rc;
2121 }
2122
2123 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2124 {
2125 struct net_device *dev = tp->dev;
2126 int rc = -EINVAL;
2127
2128 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2129 netif_err(tp, ifup, dev, "invalid firwmare\n");
2130 goto out;
2131 }
2132
2133 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2134 rc = 0;
2135 out:
2136 return rc;
2137 }
2138
2139 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2140 {
2141 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2142 u32 predata, count;
2143 size_t index;
2144
2145 predata = count = 0;
2146
2147 for (index = 0; index < pa->size; ) {
2148 u32 action = le32_to_cpu(pa->code[index]);
2149 u32 data = action & 0x0000ffff;
2150 u32 regno = (action & 0x0fff0000) >> 16;
2151
2152 if (!action)
2153 break;
2154
2155 switch(action & 0xf0000000) {
2156 case PHY_READ:
2157 predata = rtl_readphy(tp, regno);
2158 count++;
2159 index++;
2160 break;
2161 case PHY_DATA_OR:
2162 predata |= data;
2163 index++;
2164 break;
2165 case PHY_DATA_AND:
2166 predata &= data;
2167 index++;
2168 break;
2169 case PHY_BJMPN:
2170 index -= regno;
2171 break;
2172 case PHY_READ_EFUSE:
2173 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2174 index++;
2175 break;
2176 case PHY_CLEAR_READCOUNT:
2177 count = 0;
2178 index++;
2179 break;
2180 case PHY_WRITE:
2181 rtl_writephy(tp, regno, data);
2182 index++;
2183 break;
2184 case PHY_READCOUNT_EQ_SKIP:
2185 index += (count == data) ? 2 : 1;
2186 break;
2187 case PHY_COMP_EQ_SKIPN:
2188 if (predata == data)
2189 index += regno;
2190 index++;
2191 break;
2192 case PHY_COMP_NEQ_SKIPN:
2193 if (predata != data)
2194 index += regno;
2195 index++;
2196 break;
2197 case PHY_WRITE_PREVIOUS:
2198 rtl_writephy(tp, regno, predata);
2199 index++;
2200 break;
2201 case PHY_SKIPN:
2202 index += regno + 1;
2203 break;
2204 case PHY_DELAY_MS:
2205 mdelay(data);
2206 index++;
2207 break;
2208
2209 case PHY_READ_MAC_BYTE:
2210 case PHY_WRITE_MAC_BYTE:
2211 case PHY_WRITE_ERI_WORD:
2212 default:
2213 BUG();
2214 }
2215 }
2216 }
2217
2218 static void rtl_release_firmware(struct rtl8169_private *tp)
2219 {
2220 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2221 release_firmware(tp->rtl_fw->fw);
2222 kfree(tp->rtl_fw);
2223 }
2224 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2225 }
2226
2227 static void rtl_apply_firmware(struct rtl8169_private *tp)
2228 {
2229 struct rtl_fw *rtl_fw = tp->rtl_fw;
2230
2231 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2232 if (!IS_ERR_OR_NULL(rtl_fw))
2233 rtl_phy_write_fw(tp, rtl_fw);
2234 }
2235
2236 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2237 {
2238 if (rtl_readphy(tp, reg) != val)
2239 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2240 else
2241 rtl_apply_firmware(tp);
2242 }
2243
2244 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2245 {
2246 static const struct phy_reg phy_reg_init[] = {
2247 { 0x1f, 0x0001 },
2248 { 0x06, 0x006e },
2249 { 0x08, 0x0708 },
2250 { 0x15, 0x4000 },
2251 { 0x18, 0x65c7 },
2252
2253 { 0x1f, 0x0001 },
2254 { 0x03, 0x00a1 },
2255 { 0x02, 0x0008 },
2256 { 0x01, 0x0120 },
2257 { 0x00, 0x1000 },
2258 { 0x04, 0x0800 },
2259 { 0x04, 0x0000 },
2260
2261 { 0x03, 0xff41 },
2262 { 0x02, 0xdf60 },
2263 { 0x01, 0x0140 },
2264 { 0x00, 0x0077 },
2265 { 0x04, 0x7800 },
2266 { 0x04, 0x7000 },
2267
2268 { 0x03, 0x802f },
2269 { 0x02, 0x4f02 },
2270 { 0x01, 0x0409 },
2271 { 0x00, 0xf0f9 },
2272 { 0x04, 0x9800 },
2273 { 0x04, 0x9000 },
2274
2275 { 0x03, 0xdf01 },
2276 { 0x02, 0xdf20 },
2277 { 0x01, 0xff95 },
2278 { 0x00, 0xba00 },
2279 { 0x04, 0xa800 },
2280 { 0x04, 0xa000 },
2281
2282 { 0x03, 0xff41 },
2283 { 0x02, 0xdf20 },
2284 { 0x01, 0x0140 },
2285 { 0x00, 0x00bb },
2286 { 0x04, 0xb800 },
2287 { 0x04, 0xb000 },
2288
2289 { 0x03, 0xdf41 },
2290 { 0x02, 0xdc60 },
2291 { 0x01, 0x6340 },
2292 { 0x00, 0x007d },
2293 { 0x04, 0xd800 },
2294 { 0x04, 0xd000 },
2295
2296 { 0x03, 0xdf01 },
2297 { 0x02, 0xdf20 },
2298 { 0x01, 0x100a },
2299 { 0x00, 0xa0ff },
2300 { 0x04, 0xf800 },
2301 { 0x04, 0xf000 },
2302
2303 { 0x1f, 0x0000 },
2304 { 0x0b, 0x0000 },
2305 { 0x00, 0x9200 }
2306 };
2307
2308 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2309 }
2310
2311 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2312 {
2313 static const struct phy_reg phy_reg_init[] = {
2314 { 0x1f, 0x0002 },
2315 { 0x01, 0x90d0 },
2316 { 0x1f, 0x0000 }
2317 };
2318
2319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2320 }
2321
2322 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2323 {
2324 struct pci_dev *pdev = tp->pci_dev;
2325
2326 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2327 (pdev->subsystem_device != 0xe000))
2328 return;
2329
2330 rtl_writephy(tp, 0x1f, 0x0001);
2331 rtl_writephy(tp, 0x10, 0xf01b);
2332 rtl_writephy(tp, 0x1f, 0x0000);
2333 }
2334
2335 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2336 {
2337 static const struct phy_reg phy_reg_init[] = {
2338 { 0x1f, 0x0001 },
2339 { 0x04, 0x0000 },
2340 { 0x03, 0x00a1 },
2341 { 0x02, 0x0008 },
2342 { 0x01, 0x0120 },
2343 { 0x00, 0x1000 },
2344 { 0x04, 0x0800 },
2345 { 0x04, 0x9000 },
2346 { 0x03, 0x802f },
2347 { 0x02, 0x4f02 },
2348 { 0x01, 0x0409 },
2349 { 0x00, 0xf099 },
2350 { 0x04, 0x9800 },
2351 { 0x04, 0xa000 },
2352 { 0x03, 0xdf01 },
2353 { 0x02, 0xdf20 },
2354 { 0x01, 0xff95 },
2355 { 0x00, 0xba00 },
2356 { 0x04, 0xa800 },
2357 { 0x04, 0xf000 },
2358 { 0x03, 0xdf01 },
2359 { 0x02, 0xdf20 },
2360 { 0x01, 0x101a },
2361 { 0x00, 0xa0ff },
2362 { 0x04, 0xf800 },
2363 { 0x04, 0x0000 },
2364 { 0x1f, 0x0000 },
2365
2366 { 0x1f, 0x0001 },
2367 { 0x10, 0xf41b },
2368 { 0x14, 0xfb54 },
2369 { 0x18, 0xf5c7 },
2370 { 0x1f, 0x0000 },
2371
2372 { 0x1f, 0x0001 },
2373 { 0x17, 0x0cc0 },
2374 { 0x1f, 0x0000 }
2375 };
2376
2377 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378
2379 rtl8169scd_hw_phy_config_quirk(tp);
2380 }
2381
2382 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2383 {
2384 static const struct phy_reg phy_reg_init[] = {
2385 { 0x1f, 0x0001 },
2386 { 0x04, 0x0000 },
2387 { 0x03, 0x00a1 },
2388 { 0x02, 0x0008 },
2389 { 0x01, 0x0120 },
2390 { 0x00, 0x1000 },
2391 { 0x04, 0x0800 },
2392 { 0x04, 0x9000 },
2393 { 0x03, 0x802f },
2394 { 0x02, 0x4f02 },
2395 { 0x01, 0x0409 },
2396 { 0x00, 0xf099 },
2397 { 0x04, 0x9800 },
2398 { 0x04, 0xa000 },
2399 { 0x03, 0xdf01 },
2400 { 0x02, 0xdf20 },
2401 { 0x01, 0xff95 },
2402 { 0x00, 0xba00 },
2403 { 0x04, 0xa800 },
2404 { 0x04, 0xf000 },
2405 { 0x03, 0xdf01 },
2406 { 0x02, 0xdf20 },
2407 { 0x01, 0x101a },
2408 { 0x00, 0xa0ff },
2409 { 0x04, 0xf800 },
2410 { 0x04, 0x0000 },
2411 { 0x1f, 0x0000 },
2412
2413 { 0x1f, 0x0001 },
2414 { 0x0b, 0x8480 },
2415 { 0x1f, 0x0000 },
2416
2417 { 0x1f, 0x0001 },
2418 { 0x18, 0x67c7 },
2419 { 0x04, 0x2000 },
2420 { 0x03, 0x002f },
2421 { 0x02, 0x4360 },
2422 { 0x01, 0x0109 },
2423 { 0x00, 0x3022 },
2424 { 0x04, 0x2800 },
2425 { 0x1f, 0x0000 },
2426
2427 { 0x1f, 0x0001 },
2428 { 0x17, 0x0cc0 },
2429 { 0x1f, 0x0000 }
2430 };
2431
2432 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2433 }
2434
2435 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2436 {
2437 static const struct phy_reg phy_reg_init[] = {
2438 { 0x10, 0xf41b },
2439 { 0x1f, 0x0000 }
2440 };
2441
2442 rtl_writephy(tp, 0x1f, 0x0001);
2443 rtl_patchphy(tp, 0x16, 1 << 0);
2444
2445 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2446 }
2447
2448 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2449 {
2450 static const struct phy_reg phy_reg_init[] = {
2451 { 0x1f, 0x0001 },
2452 { 0x10, 0xf41b },
2453 { 0x1f, 0x0000 }
2454 };
2455
2456 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2457 }
2458
2459 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2460 {
2461 static const struct phy_reg phy_reg_init[] = {
2462 { 0x1f, 0x0000 },
2463 { 0x1d, 0x0f00 },
2464 { 0x1f, 0x0002 },
2465 { 0x0c, 0x1ec8 },
2466 { 0x1f, 0x0000 }
2467 };
2468
2469 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2470 }
2471
2472 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2473 {
2474 static const struct phy_reg phy_reg_init[] = {
2475 { 0x1f, 0x0001 },
2476 { 0x1d, 0x3d98 },
2477 { 0x1f, 0x0000 }
2478 };
2479
2480 rtl_writephy(tp, 0x1f, 0x0000);
2481 rtl_patchphy(tp, 0x14, 1 << 5);
2482 rtl_patchphy(tp, 0x0d, 1 << 5);
2483
2484 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2485 }
2486
2487 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2488 {
2489 static const struct phy_reg phy_reg_init[] = {
2490 { 0x1f, 0x0001 },
2491 { 0x12, 0x2300 },
2492 { 0x1f, 0x0002 },
2493 { 0x00, 0x88d4 },
2494 { 0x01, 0x82b1 },
2495 { 0x03, 0x7002 },
2496 { 0x08, 0x9e30 },
2497 { 0x09, 0x01f0 },
2498 { 0x0a, 0x5500 },
2499 { 0x0c, 0x00c8 },
2500 { 0x1f, 0x0003 },
2501 { 0x12, 0xc096 },
2502 { 0x16, 0x000a },
2503 { 0x1f, 0x0000 },
2504 { 0x1f, 0x0000 },
2505 { 0x09, 0x2000 },
2506 { 0x09, 0x0000 }
2507 };
2508
2509 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2510
2511 rtl_patchphy(tp, 0x14, 1 << 5);
2512 rtl_patchphy(tp, 0x0d, 1 << 5);
2513 rtl_writephy(tp, 0x1f, 0x0000);
2514 }
2515
2516 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2517 {
2518 static const struct phy_reg phy_reg_init[] = {
2519 { 0x1f, 0x0001 },
2520 { 0x12, 0x2300 },
2521 { 0x03, 0x802f },
2522 { 0x02, 0x4f02 },
2523 { 0x01, 0x0409 },
2524 { 0x00, 0xf099 },
2525 { 0x04, 0x9800 },
2526 { 0x04, 0x9000 },
2527 { 0x1d, 0x3d98 },
2528 { 0x1f, 0x0002 },
2529 { 0x0c, 0x7eb8 },
2530 { 0x06, 0x0761 },
2531 { 0x1f, 0x0003 },
2532 { 0x16, 0x0f0a },
2533 { 0x1f, 0x0000 }
2534 };
2535
2536 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537
2538 rtl_patchphy(tp, 0x16, 1 << 0);
2539 rtl_patchphy(tp, 0x14, 1 << 5);
2540 rtl_patchphy(tp, 0x0d, 1 << 5);
2541 rtl_writephy(tp, 0x1f, 0x0000);
2542 }
2543
2544 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2545 {
2546 static const struct phy_reg phy_reg_init[] = {
2547 { 0x1f, 0x0001 },
2548 { 0x12, 0x2300 },
2549 { 0x1d, 0x3d98 },
2550 { 0x1f, 0x0002 },
2551 { 0x0c, 0x7eb8 },
2552 { 0x06, 0x5461 },
2553 { 0x1f, 0x0003 },
2554 { 0x16, 0x0f0a },
2555 { 0x1f, 0x0000 }
2556 };
2557
2558 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559
2560 rtl_patchphy(tp, 0x16, 1 << 0);
2561 rtl_patchphy(tp, 0x14, 1 << 5);
2562 rtl_patchphy(tp, 0x0d, 1 << 5);
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564 }
2565
2566 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2567 {
2568 rtl8168c_3_hw_phy_config(tp);
2569 }
2570
2571 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2572 {
2573 static const struct phy_reg phy_reg_init_0[] = {
2574 /* Channel Estimation */
2575 { 0x1f, 0x0001 },
2576 { 0x06, 0x4064 },
2577 { 0x07, 0x2863 },
2578 { 0x08, 0x059c },
2579 { 0x09, 0x26b4 },
2580 { 0x0a, 0x6a19 },
2581 { 0x0b, 0xdcc8 },
2582 { 0x10, 0xf06d },
2583 { 0x14, 0x7f68 },
2584 { 0x18, 0x7fd9 },
2585 { 0x1c, 0xf0ff },
2586 { 0x1d, 0x3d9c },
2587 { 0x1f, 0x0003 },
2588 { 0x12, 0xf49f },
2589 { 0x13, 0x070b },
2590 { 0x1a, 0x05ad },
2591 { 0x14, 0x94c0 },
2592
2593 /*
2594 * Tx Error Issue
2595 * Enhance line driver power
2596 */
2597 { 0x1f, 0x0002 },
2598 { 0x06, 0x5561 },
2599 { 0x1f, 0x0005 },
2600 { 0x05, 0x8332 },
2601 { 0x06, 0x5561 },
2602
2603 /*
2604 * Can not link to 1Gbps with bad cable
2605 * Decrease SNR threshold form 21.07dB to 19.04dB
2606 */
2607 { 0x1f, 0x0001 },
2608 { 0x17, 0x0cc0 },
2609
2610 { 0x1f, 0x0000 },
2611 { 0x0d, 0xf880 }
2612 };
2613 void __iomem *ioaddr = tp->mmio_addr;
2614
2615 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2616
2617 /*
2618 * Rx Error Issue
2619 * Fine Tune Switching regulator parameter
2620 */
2621 rtl_writephy(tp, 0x1f, 0x0002);
2622 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2623 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2624
2625 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2626 static const struct phy_reg phy_reg_init[] = {
2627 { 0x1f, 0x0002 },
2628 { 0x05, 0x669a },
2629 { 0x1f, 0x0005 },
2630 { 0x05, 0x8330 },
2631 { 0x06, 0x669a },
2632 { 0x1f, 0x0002 }
2633 };
2634 int val;
2635
2636 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637
2638 val = rtl_readphy(tp, 0x0d);
2639
2640 if ((val & 0x00ff) != 0x006c) {
2641 static const u32 set[] = {
2642 0x0065, 0x0066, 0x0067, 0x0068,
2643 0x0069, 0x006a, 0x006b, 0x006c
2644 };
2645 int i;
2646
2647 rtl_writephy(tp, 0x1f, 0x0002);
2648
2649 val &= 0xff00;
2650 for (i = 0; i < ARRAY_SIZE(set); i++)
2651 rtl_writephy(tp, 0x0d, val | set[i]);
2652 }
2653 } else {
2654 static const struct phy_reg phy_reg_init[] = {
2655 { 0x1f, 0x0002 },
2656 { 0x05, 0x6662 },
2657 { 0x1f, 0x0005 },
2658 { 0x05, 0x8330 },
2659 { 0x06, 0x6662 }
2660 };
2661
2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663 }
2664
2665 /* RSET couple improve */
2666 rtl_writephy(tp, 0x1f, 0x0002);
2667 rtl_patchphy(tp, 0x0d, 0x0300);
2668 rtl_patchphy(tp, 0x0f, 0x0010);
2669
2670 /* Fine tune PLL performance */
2671 rtl_writephy(tp, 0x1f, 0x0002);
2672 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2673 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2674
2675 rtl_writephy(tp, 0x1f, 0x0005);
2676 rtl_writephy(tp, 0x05, 0x001b);
2677
2678 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2679
2680 rtl_writephy(tp, 0x1f, 0x0000);
2681 }
2682
2683 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2684 {
2685 static const struct phy_reg phy_reg_init_0[] = {
2686 /* Channel Estimation */
2687 { 0x1f, 0x0001 },
2688 { 0x06, 0x4064 },
2689 { 0x07, 0x2863 },
2690 { 0x08, 0x059c },
2691 { 0x09, 0x26b4 },
2692 { 0x0a, 0x6a19 },
2693 { 0x0b, 0xdcc8 },
2694 { 0x10, 0xf06d },
2695 { 0x14, 0x7f68 },
2696 { 0x18, 0x7fd9 },
2697 { 0x1c, 0xf0ff },
2698 { 0x1d, 0x3d9c },
2699 { 0x1f, 0x0003 },
2700 { 0x12, 0xf49f },
2701 { 0x13, 0x070b },
2702 { 0x1a, 0x05ad },
2703 { 0x14, 0x94c0 },
2704
2705 /*
2706 * Tx Error Issue
2707 * Enhance line driver power
2708 */
2709 { 0x1f, 0x0002 },
2710 { 0x06, 0x5561 },
2711 { 0x1f, 0x0005 },
2712 { 0x05, 0x8332 },
2713 { 0x06, 0x5561 },
2714
2715 /*
2716 * Can not link to 1Gbps with bad cable
2717 * Decrease SNR threshold form 21.07dB to 19.04dB
2718 */
2719 { 0x1f, 0x0001 },
2720 { 0x17, 0x0cc0 },
2721
2722 { 0x1f, 0x0000 },
2723 { 0x0d, 0xf880 }
2724 };
2725 void __iomem *ioaddr = tp->mmio_addr;
2726
2727 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2728
2729 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2730 static const struct phy_reg phy_reg_init[] = {
2731 { 0x1f, 0x0002 },
2732 { 0x05, 0x669a },
2733 { 0x1f, 0x0005 },
2734 { 0x05, 0x8330 },
2735 { 0x06, 0x669a },
2736
2737 { 0x1f, 0x0002 }
2738 };
2739 int val;
2740
2741 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742
2743 val = rtl_readphy(tp, 0x0d);
2744 if ((val & 0x00ff) != 0x006c) {
2745 static const u32 set[] = {
2746 0x0065, 0x0066, 0x0067, 0x0068,
2747 0x0069, 0x006a, 0x006b, 0x006c
2748 };
2749 int i;
2750
2751 rtl_writephy(tp, 0x1f, 0x0002);
2752
2753 val &= 0xff00;
2754 for (i = 0; i < ARRAY_SIZE(set); i++)
2755 rtl_writephy(tp, 0x0d, val | set[i]);
2756 }
2757 } else {
2758 static const struct phy_reg phy_reg_init[] = {
2759 { 0x1f, 0x0002 },
2760 { 0x05, 0x2642 },
2761 { 0x1f, 0x0005 },
2762 { 0x05, 0x8330 },
2763 { 0x06, 0x2642 }
2764 };
2765
2766 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2767 }
2768
2769 /* Fine tune PLL performance */
2770 rtl_writephy(tp, 0x1f, 0x0002);
2771 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2772 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2773
2774 /* Switching regulator Slew rate */
2775 rtl_writephy(tp, 0x1f, 0x0002);
2776 rtl_patchphy(tp, 0x0f, 0x0017);
2777
2778 rtl_writephy(tp, 0x1f, 0x0005);
2779 rtl_writephy(tp, 0x05, 0x001b);
2780
2781 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2782
2783 rtl_writephy(tp, 0x1f, 0x0000);
2784 }
2785
2786 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2787 {
2788 static const struct phy_reg phy_reg_init[] = {
2789 { 0x1f, 0x0002 },
2790 { 0x10, 0x0008 },
2791 { 0x0d, 0x006c },
2792
2793 { 0x1f, 0x0000 },
2794 { 0x0d, 0xf880 },
2795
2796 { 0x1f, 0x0001 },
2797 { 0x17, 0x0cc0 },
2798
2799 { 0x1f, 0x0001 },
2800 { 0x0b, 0xa4d8 },
2801 { 0x09, 0x281c },
2802 { 0x07, 0x2883 },
2803 { 0x0a, 0x6b35 },
2804 { 0x1d, 0x3da4 },
2805 { 0x1c, 0xeffd },
2806 { 0x14, 0x7f52 },
2807 { 0x18, 0x7fc6 },
2808 { 0x08, 0x0601 },
2809 { 0x06, 0x4063 },
2810 { 0x10, 0xf074 },
2811 { 0x1f, 0x0003 },
2812 { 0x13, 0x0789 },
2813 { 0x12, 0xf4bd },
2814 { 0x1a, 0x04fd },
2815 { 0x14, 0x84b0 },
2816 { 0x1f, 0x0000 },
2817 { 0x00, 0x9200 },
2818
2819 { 0x1f, 0x0005 },
2820 { 0x01, 0x0340 },
2821 { 0x1f, 0x0001 },
2822 { 0x04, 0x4000 },
2823 { 0x03, 0x1d21 },
2824 { 0x02, 0x0c32 },
2825 { 0x01, 0x0200 },
2826 { 0x00, 0x5554 },
2827 { 0x04, 0x4800 },
2828 { 0x04, 0x4000 },
2829 { 0x04, 0xf000 },
2830 { 0x03, 0xdf01 },
2831 { 0x02, 0xdf20 },
2832 { 0x01, 0x101a },
2833 { 0x00, 0xa0ff },
2834 { 0x04, 0xf800 },
2835 { 0x04, 0xf000 },
2836 { 0x1f, 0x0000 },
2837
2838 { 0x1f, 0x0007 },
2839 { 0x1e, 0x0023 },
2840 { 0x16, 0x0000 },
2841 { 0x1f, 0x0000 }
2842 };
2843
2844 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2845 }
2846
2847 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2848 {
2849 static const struct phy_reg phy_reg_init[] = {
2850 { 0x1f, 0x0001 },
2851 { 0x17, 0x0cc0 },
2852
2853 { 0x1f, 0x0007 },
2854 { 0x1e, 0x002d },
2855 { 0x18, 0x0040 },
2856 { 0x1f, 0x0000 }
2857 };
2858
2859 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2860 rtl_patchphy(tp, 0x0d, 1 << 5);
2861 }
2862
2863 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2864 {
2865 static const struct phy_reg phy_reg_init[] = {
2866 /* Enable Delay cap */
2867 { 0x1f, 0x0005 },
2868 { 0x05, 0x8b80 },
2869 { 0x06, 0xc896 },
2870 { 0x1f, 0x0000 },
2871
2872 /* Channel estimation fine tune */
2873 { 0x1f, 0x0001 },
2874 { 0x0b, 0x6c20 },
2875 { 0x07, 0x2872 },
2876 { 0x1c, 0xefff },
2877 { 0x1f, 0x0003 },
2878 { 0x14, 0x6420 },
2879 { 0x1f, 0x0000 },
2880
2881 /* Update PFM & 10M TX idle timer */
2882 { 0x1f, 0x0007 },
2883 { 0x1e, 0x002f },
2884 { 0x15, 0x1919 },
2885 { 0x1f, 0x0000 },
2886
2887 { 0x1f, 0x0007 },
2888 { 0x1e, 0x00ac },
2889 { 0x18, 0x0006 },
2890 { 0x1f, 0x0000 }
2891 };
2892
2893 rtl_apply_firmware(tp);
2894
2895 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2896
2897 /* DCO enable for 10M IDLE Power */
2898 rtl_writephy(tp, 0x1f, 0x0007);
2899 rtl_writephy(tp, 0x1e, 0x0023);
2900 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2901 rtl_writephy(tp, 0x1f, 0x0000);
2902
2903 /* For impedance matching */
2904 rtl_writephy(tp, 0x1f, 0x0002);
2905 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2906 rtl_writephy(tp, 0x1f, 0x0000);
2907
2908 /* PHY auto speed down */
2909 rtl_writephy(tp, 0x1f, 0x0007);
2910 rtl_writephy(tp, 0x1e, 0x002d);
2911 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2912 rtl_writephy(tp, 0x1f, 0x0000);
2913 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2914
2915 rtl_writephy(tp, 0x1f, 0x0005);
2916 rtl_writephy(tp, 0x05, 0x8b86);
2917 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919
2920 rtl_writephy(tp, 0x1f, 0x0005);
2921 rtl_writephy(tp, 0x05, 0x8b85);
2922 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2923 rtl_writephy(tp, 0x1f, 0x0007);
2924 rtl_writephy(tp, 0x1e, 0x0020);
2925 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2926 rtl_writephy(tp, 0x1f, 0x0006);
2927 rtl_writephy(tp, 0x00, 0x5a00);
2928 rtl_writephy(tp, 0x1f, 0x0000);
2929 rtl_writephy(tp, 0x0d, 0x0007);
2930 rtl_writephy(tp, 0x0e, 0x003c);
2931 rtl_writephy(tp, 0x0d, 0x4007);
2932 rtl_writephy(tp, 0x0e, 0x0000);
2933 rtl_writephy(tp, 0x0d, 0x0000);
2934 }
2935
2936 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2937 {
2938 static const struct phy_reg phy_reg_init[] = {
2939 /* Enable Delay cap */
2940 { 0x1f, 0x0004 },
2941 { 0x1f, 0x0007 },
2942 { 0x1e, 0x00ac },
2943 { 0x18, 0x0006 },
2944 { 0x1f, 0x0002 },
2945 { 0x1f, 0x0000 },
2946 { 0x1f, 0x0000 },
2947
2948 /* Channel estimation fine tune */
2949 { 0x1f, 0x0003 },
2950 { 0x09, 0xa20f },
2951 { 0x1f, 0x0000 },
2952 { 0x1f, 0x0000 },
2953
2954 /* Green Setting */
2955 { 0x1f, 0x0005 },
2956 { 0x05, 0x8b5b },
2957 { 0x06, 0x9222 },
2958 { 0x05, 0x8b6d },
2959 { 0x06, 0x8000 },
2960 { 0x05, 0x8b76 },
2961 { 0x06, 0x8000 },
2962 { 0x1f, 0x0000 }
2963 };
2964
2965 rtl_apply_firmware(tp);
2966
2967 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2968
2969 /* For 4-corner performance improve */
2970 rtl_writephy(tp, 0x1f, 0x0005);
2971 rtl_writephy(tp, 0x05, 0x8b80);
2972 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2973 rtl_writephy(tp, 0x1f, 0x0000);
2974
2975 /* PHY auto speed down */
2976 rtl_writephy(tp, 0x1f, 0x0004);
2977 rtl_writephy(tp, 0x1f, 0x0007);
2978 rtl_writephy(tp, 0x1e, 0x002d);
2979 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2980 rtl_writephy(tp, 0x1f, 0x0002);
2981 rtl_writephy(tp, 0x1f, 0x0000);
2982 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2983
2984 /* improve 10M EEE waveform */
2985 rtl_writephy(tp, 0x1f, 0x0005);
2986 rtl_writephy(tp, 0x05, 0x8b86);
2987 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2988 rtl_writephy(tp, 0x1f, 0x0000);
2989
2990 /* Improve 2-pair detection performance */
2991 rtl_writephy(tp, 0x1f, 0x0005);
2992 rtl_writephy(tp, 0x05, 0x8b85);
2993 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2994 rtl_writephy(tp, 0x1f, 0x0000);
2995
2996 /* EEE setting */
2997 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2998 ERIAR_EXGMAC);
2999 rtl_writephy(tp, 0x1f, 0x0005);
3000 rtl_writephy(tp, 0x05, 0x8b85);
3001 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3002 rtl_writephy(tp, 0x1f, 0x0004);
3003 rtl_writephy(tp, 0x1f, 0x0007);
3004 rtl_writephy(tp, 0x1e, 0x0020);
3005 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3006 rtl_writephy(tp, 0x1f, 0x0002);
3007 rtl_writephy(tp, 0x1f, 0x0000);
3008 rtl_writephy(tp, 0x0d, 0x0007);
3009 rtl_writephy(tp, 0x0e, 0x003c);
3010 rtl_writephy(tp, 0x0d, 0x4007);
3011 rtl_writephy(tp, 0x0e, 0x0000);
3012 rtl_writephy(tp, 0x0d, 0x0000);
3013
3014 /* Green feature */
3015 rtl_writephy(tp, 0x1f, 0x0003);
3016 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3017 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3018 rtl_writephy(tp, 0x1f, 0x0000);
3019 }
3020
3021 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3022 {
3023 static const struct phy_reg phy_reg_init[] = {
3024 /* Channel estimation fine tune */
3025 { 0x1f, 0x0003 },
3026 { 0x09, 0xa20f },
3027 { 0x1f, 0x0000 },
3028
3029 /* Modify green table for giga & fnet */
3030 { 0x1f, 0x0005 },
3031 { 0x05, 0x8b55 },
3032 { 0x06, 0x0000 },
3033 { 0x05, 0x8b5e },
3034 { 0x06, 0x0000 },
3035 { 0x05, 0x8b67 },
3036 { 0x06, 0x0000 },
3037 { 0x05, 0x8b70 },
3038 { 0x06, 0x0000 },
3039 { 0x1f, 0x0000 },
3040 { 0x1f, 0x0007 },
3041 { 0x1e, 0x0078 },
3042 { 0x17, 0x0000 },
3043 { 0x19, 0x00fb },
3044 { 0x1f, 0x0000 },
3045
3046 /* Modify green table for 10M */
3047 { 0x1f, 0x0005 },
3048 { 0x05, 0x8b79 },
3049 { 0x06, 0xaa00 },
3050 { 0x1f, 0x0000 },
3051
3052 /* Disable hiimpedance detection (RTCT) */
3053 { 0x1f, 0x0003 },
3054 { 0x01, 0x328a },
3055 { 0x1f, 0x0000 }
3056 };
3057
3058 rtl_apply_firmware(tp);
3059
3060 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3061
3062 /* For 4-corner performance improve */
3063 rtl_writephy(tp, 0x1f, 0x0005);
3064 rtl_writephy(tp, 0x05, 0x8b80);
3065 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3066 rtl_writephy(tp, 0x1f, 0x0000);
3067
3068 /* PHY auto speed down */
3069 rtl_writephy(tp, 0x1f, 0x0007);
3070 rtl_writephy(tp, 0x1e, 0x002d);
3071 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3072 rtl_writephy(tp, 0x1f, 0x0000);
3073 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3074
3075 /* Improve 10M EEE waveform */
3076 rtl_writephy(tp, 0x1f, 0x0005);
3077 rtl_writephy(tp, 0x05, 0x8b86);
3078 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3079 rtl_writephy(tp, 0x1f, 0x0000);
3080
3081 /* Improve 2-pair detection performance */
3082 rtl_writephy(tp, 0x1f, 0x0005);
3083 rtl_writephy(tp, 0x05, 0x8b85);
3084 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3085 rtl_writephy(tp, 0x1f, 0x0000);
3086 }
3087
3088 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3089 {
3090 rtl_apply_firmware(tp);
3091
3092 /* For 4-corner performance improve */
3093 rtl_writephy(tp, 0x1f, 0x0005);
3094 rtl_writephy(tp, 0x05, 0x8b80);
3095 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3096 rtl_writephy(tp, 0x1f, 0x0000);
3097
3098 /* PHY auto speed down */
3099 rtl_writephy(tp, 0x1f, 0x0007);
3100 rtl_writephy(tp, 0x1e, 0x002d);
3101 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3102 rtl_writephy(tp, 0x1f, 0x0000);
3103 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3104
3105 /* Improve 10M EEE waveform */
3106 rtl_writephy(tp, 0x1f, 0x0005);
3107 rtl_writephy(tp, 0x05, 0x8b86);
3108 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3109 rtl_writephy(tp, 0x1f, 0x0000);
3110 }
3111
3112 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3113 {
3114 static const struct phy_reg phy_reg_init[] = {
3115 { 0x1f, 0x0003 },
3116 { 0x08, 0x441d },
3117 { 0x01, 0x9100 },
3118 { 0x1f, 0x0000 }
3119 };
3120
3121 rtl_writephy(tp, 0x1f, 0x0000);
3122 rtl_patchphy(tp, 0x11, 1 << 12);
3123 rtl_patchphy(tp, 0x19, 1 << 13);
3124 rtl_patchphy(tp, 0x10, 1 << 15);
3125
3126 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3127 }
3128
3129 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3130 {
3131 static const struct phy_reg phy_reg_init[] = {
3132 { 0x1f, 0x0005 },
3133 { 0x1a, 0x0000 },
3134 { 0x1f, 0x0000 },
3135
3136 { 0x1f, 0x0004 },
3137 { 0x1c, 0x0000 },
3138 { 0x1f, 0x0000 },
3139
3140 { 0x1f, 0x0001 },
3141 { 0x15, 0x7701 },
3142 { 0x1f, 0x0000 }
3143 };
3144
3145 /* Disable ALDPS before ram code */
3146 rtl_writephy(tp, 0x1f, 0x0000);
3147 rtl_writephy(tp, 0x18, 0x0310);
3148 msleep(100);
3149
3150 rtl_apply_firmware(tp);
3151
3152 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153 }
3154
3155 static void rtl_hw_phy_config(struct net_device *dev)
3156 {
3157 struct rtl8169_private *tp = netdev_priv(dev);
3158
3159 rtl8169_print_mac_version(tp);
3160
3161 switch (tp->mac_version) {
3162 case RTL_GIGA_MAC_VER_01:
3163 break;
3164 case RTL_GIGA_MAC_VER_02:
3165 case RTL_GIGA_MAC_VER_03:
3166 rtl8169s_hw_phy_config(tp);
3167 break;
3168 case RTL_GIGA_MAC_VER_04:
3169 rtl8169sb_hw_phy_config(tp);
3170 break;
3171 case RTL_GIGA_MAC_VER_05:
3172 rtl8169scd_hw_phy_config(tp);
3173 break;
3174 case RTL_GIGA_MAC_VER_06:
3175 rtl8169sce_hw_phy_config(tp);
3176 break;
3177 case RTL_GIGA_MAC_VER_07:
3178 case RTL_GIGA_MAC_VER_08:
3179 case RTL_GIGA_MAC_VER_09:
3180 rtl8102e_hw_phy_config(tp);
3181 break;
3182 case RTL_GIGA_MAC_VER_11:
3183 rtl8168bb_hw_phy_config(tp);
3184 break;
3185 case RTL_GIGA_MAC_VER_12:
3186 rtl8168bef_hw_phy_config(tp);
3187 break;
3188 case RTL_GIGA_MAC_VER_17:
3189 rtl8168bef_hw_phy_config(tp);
3190 break;
3191 case RTL_GIGA_MAC_VER_18:
3192 rtl8168cp_1_hw_phy_config(tp);
3193 break;
3194 case RTL_GIGA_MAC_VER_19:
3195 rtl8168c_1_hw_phy_config(tp);
3196 break;
3197 case RTL_GIGA_MAC_VER_20:
3198 rtl8168c_2_hw_phy_config(tp);
3199 break;
3200 case RTL_GIGA_MAC_VER_21:
3201 rtl8168c_3_hw_phy_config(tp);
3202 break;
3203 case RTL_GIGA_MAC_VER_22:
3204 rtl8168c_4_hw_phy_config(tp);
3205 break;
3206 case RTL_GIGA_MAC_VER_23:
3207 case RTL_GIGA_MAC_VER_24:
3208 rtl8168cp_2_hw_phy_config(tp);
3209 break;
3210 case RTL_GIGA_MAC_VER_25:
3211 rtl8168d_1_hw_phy_config(tp);
3212 break;
3213 case RTL_GIGA_MAC_VER_26:
3214 rtl8168d_2_hw_phy_config(tp);
3215 break;
3216 case RTL_GIGA_MAC_VER_27:
3217 rtl8168d_3_hw_phy_config(tp);
3218 break;
3219 case RTL_GIGA_MAC_VER_28:
3220 rtl8168d_4_hw_phy_config(tp);
3221 break;
3222 case RTL_GIGA_MAC_VER_29:
3223 case RTL_GIGA_MAC_VER_30:
3224 rtl8105e_hw_phy_config(tp);
3225 break;
3226 case RTL_GIGA_MAC_VER_31:
3227 /* None. */
3228 break;
3229 case RTL_GIGA_MAC_VER_32:
3230 case RTL_GIGA_MAC_VER_33:
3231 rtl8168e_1_hw_phy_config(tp);
3232 break;
3233 case RTL_GIGA_MAC_VER_34:
3234 rtl8168e_2_hw_phy_config(tp);
3235 break;
3236 case RTL_GIGA_MAC_VER_35:
3237 rtl8168f_1_hw_phy_config(tp);
3238 break;
3239 case RTL_GIGA_MAC_VER_36:
3240 rtl8168f_2_hw_phy_config(tp);
3241 break;
3242
3243 default:
3244 break;
3245 }
3246 }
3247
3248 static void rtl_phy_work(struct rtl8169_private *tp)
3249 {
3250 struct timer_list *timer = &tp->timer;
3251 void __iomem *ioaddr = tp->mmio_addr;
3252 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3253
3254 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3255
3256 if (tp->phy_reset_pending(tp)) {
3257 /*
3258 * A busy loop could burn quite a few cycles on nowadays CPU.
3259 * Let's delay the execution of the timer for a few ticks.
3260 */
3261 timeout = HZ/10;
3262 goto out_mod_timer;
3263 }
3264
3265 if (tp->link_ok(ioaddr))
3266 return;
3267
3268 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3269
3270 tp->phy_reset_enable(tp);
3271
3272 out_mod_timer:
3273 mod_timer(timer, jiffies + timeout);
3274 }
3275
3276 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3277 {
3278 if (!test_and_set_bit(flag, tp->wk.flags))
3279 schedule_work(&tp->wk.work);
3280 }
3281
3282 static void rtl8169_phy_timer(unsigned long __opaque)
3283 {
3284 struct net_device *dev = (struct net_device *)__opaque;
3285 struct rtl8169_private *tp = netdev_priv(dev);
3286
3287 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3288 }
3289
3290 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3291 void __iomem *ioaddr)
3292 {
3293 iounmap(ioaddr);
3294 pci_release_regions(pdev);
3295 pci_clear_mwi(pdev);
3296 pci_disable_device(pdev);
3297 free_netdev(dev);
3298 }
3299
3300 static void rtl8169_phy_reset(struct net_device *dev,
3301 struct rtl8169_private *tp)
3302 {
3303 unsigned int i;
3304
3305 tp->phy_reset_enable(tp);
3306 for (i = 0; i < 100; i++) {
3307 if (!tp->phy_reset_pending(tp))
3308 return;
3309 msleep(1);
3310 }
3311 netif_err(tp, link, dev, "PHY reset failed\n");
3312 }
3313
3314 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3315 {
3316 void __iomem *ioaddr = tp->mmio_addr;
3317
3318 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3319 (RTL_R8(PHYstatus) & TBI_Enable);
3320 }
3321
3322 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3323 {
3324 void __iomem *ioaddr = tp->mmio_addr;
3325
3326 rtl_hw_phy_config(dev);
3327
3328 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3329 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3330 RTL_W8(0x82, 0x01);
3331 }
3332
3333 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3334
3335 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3336 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3337
3338 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3339 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3340 RTL_W8(0x82, 0x01);
3341 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3342 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3343 }
3344
3345 rtl8169_phy_reset(dev, tp);
3346
3347 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3348 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3349 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3350 (tp->mii.supports_gmii ?
3351 ADVERTISED_1000baseT_Half |
3352 ADVERTISED_1000baseT_Full : 0));
3353
3354 if (rtl_tbi_enabled(tp))
3355 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3356 }
3357
3358 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3359 {
3360 void __iomem *ioaddr = tp->mmio_addr;
3361 u32 high;
3362 u32 low;
3363
3364 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3365 high = addr[4] | (addr[5] << 8);
3366
3367 rtl_lock_work(tp);
3368
3369 RTL_W8(Cfg9346, Cfg9346_Unlock);
3370
3371 RTL_W32(MAC4, high);
3372 RTL_R32(MAC4);
3373
3374 RTL_W32(MAC0, low);
3375 RTL_R32(MAC0);
3376
3377 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3378 const struct exgmac_reg e[] = {
3379 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3380 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3381 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3382 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3383 low >> 16 },
3384 };
3385
3386 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3387 }
3388
3389 RTL_W8(Cfg9346, Cfg9346_Lock);
3390
3391 rtl_unlock_work(tp);
3392 }
3393
3394 static int rtl_set_mac_address(struct net_device *dev, void *p)
3395 {
3396 struct rtl8169_private *tp = netdev_priv(dev);
3397 struct sockaddr *addr = p;
3398
3399 if (!is_valid_ether_addr(addr->sa_data))
3400 return -EADDRNOTAVAIL;
3401
3402 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3403
3404 rtl_rar_set(tp, dev->dev_addr);
3405
3406 return 0;
3407 }
3408
3409 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3410 {
3411 struct rtl8169_private *tp = netdev_priv(dev);
3412 struct mii_ioctl_data *data = if_mii(ifr);
3413
3414 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3415 }
3416
3417 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3418 struct mii_ioctl_data *data, int cmd)
3419 {
3420 switch (cmd) {
3421 case SIOCGMIIPHY:
3422 data->phy_id = 32; /* Internal PHY */
3423 return 0;
3424
3425 case SIOCGMIIREG:
3426 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3427 return 0;
3428
3429 case SIOCSMIIREG:
3430 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3431 return 0;
3432 }
3433 return -EOPNOTSUPP;
3434 }
3435
3436 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3437 {
3438 return -EOPNOTSUPP;
3439 }
3440
3441 static const struct rtl_cfg_info {
3442 void (*hw_start)(struct net_device *);
3443 unsigned int region;
3444 unsigned int align;
3445 u16 event_slow;
3446 unsigned features;
3447 u8 default_ver;
3448 } rtl_cfg_infos [] = {
3449 [RTL_CFG_0] = {
3450 .hw_start = rtl_hw_start_8169,
3451 .region = 1,
3452 .align = 0,
3453 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3454 .features = RTL_FEATURE_GMII,
3455 .default_ver = RTL_GIGA_MAC_VER_01,
3456 },
3457 [RTL_CFG_1] = {
3458 .hw_start = rtl_hw_start_8168,
3459 .region = 2,
3460 .align = 8,
3461 .event_slow = SYSErr | LinkChg | RxOverflow,
3462 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3463 .default_ver = RTL_GIGA_MAC_VER_11,
3464 },
3465 [RTL_CFG_2] = {
3466 .hw_start = rtl_hw_start_8101,
3467 .region = 2,
3468 .align = 8,
3469 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3470 PCSTimeout,
3471 .features = RTL_FEATURE_MSI,
3472 .default_ver = RTL_GIGA_MAC_VER_13,
3473 }
3474 };
3475
3476 /* Cfg9346_Unlock assumed. */
3477 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3478 const struct rtl_cfg_info *cfg)
3479 {
3480 void __iomem *ioaddr = tp->mmio_addr;
3481 unsigned msi = 0;
3482 u8 cfg2;
3483
3484 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3485 if (cfg->features & RTL_FEATURE_MSI) {
3486 if (pci_enable_msi(tp->pci_dev)) {
3487 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3488 } else {
3489 cfg2 |= MSIEnable;
3490 msi = RTL_FEATURE_MSI;
3491 }
3492 }
3493 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3494 RTL_W8(Config2, cfg2);
3495 return msi;
3496 }
3497
3498 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3499 {
3500 if (tp->features & RTL_FEATURE_MSI) {
3501 pci_disable_msi(pdev);
3502 tp->features &= ~RTL_FEATURE_MSI;
3503 }
3504 }
3505
3506 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3507 {
3508 struct mdio_ops *ops = &tp->mdio_ops;
3509
3510 switch (tp->mac_version) {
3511 case RTL_GIGA_MAC_VER_27:
3512 ops->write = r8168dp_1_mdio_write;
3513 ops->read = r8168dp_1_mdio_read;
3514 break;
3515 case RTL_GIGA_MAC_VER_28:
3516 case RTL_GIGA_MAC_VER_31:
3517 ops->write = r8168dp_2_mdio_write;
3518 ops->read = r8168dp_2_mdio_read;
3519 break;
3520 default:
3521 ops->write = r8169_mdio_write;
3522 ops->read = r8169_mdio_read;
3523 break;
3524 }
3525 }
3526
3527 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3528 {
3529 void __iomem *ioaddr = tp->mmio_addr;
3530
3531 switch (tp->mac_version) {
3532 case RTL_GIGA_MAC_VER_29:
3533 case RTL_GIGA_MAC_VER_30:
3534 case RTL_GIGA_MAC_VER_32:
3535 case RTL_GIGA_MAC_VER_33:
3536 case RTL_GIGA_MAC_VER_34:
3537 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3538 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3539 break;
3540 default:
3541 break;
3542 }
3543 }
3544
3545 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3546 {
3547 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3548 return false;
3549
3550 rtl_writephy(tp, 0x1f, 0x0000);
3551 rtl_writephy(tp, MII_BMCR, 0x0000);
3552
3553 rtl_wol_suspend_quirk(tp);
3554
3555 return true;
3556 }
3557
3558 static void r810x_phy_power_down(struct rtl8169_private *tp)
3559 {
3560 rtl_writephy(tp, 0x1f, 0x0000);
3561 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3562 }
3563
3564 static void r810x_phy_power_up(struct rtl8169_private *tp)
3565 {
3566 rtl_writephy(tp, 0x1f, 0x0000);
3567 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3568 }
3569
3570 static void r810x_pll_power_down(struct rtl8169_private *tp)
3571 {
3572 if (rtl_wol_pll_power_down(tp))
3573 return;
3574
3575 r810x_phy_power_down(tp);
3576 }
3577
3578 static void r810x_pll_power_up(struct rtl8169_private *tp)
3579 {
3580 r810x_phy_power_up(tp);
3581 }
3582
3583 static void r8168_phy_power_up(struct rtl8169_private *tp)
3584 {
3585 rtl_writephy(tp, 0x1f, 0x0000);
3586 switch (tp->mac_version) {
3587 case RTL_GIGA_MAC_VER_11:
3588 case RTL_GIGA_MAC_VER_12:
3589 case RTL_GIGA_MAC_VER_17:
3590 case RTL_GIGA_MAC_VER_18:
3591 case RTL_GIGA_MAC_VER_19:
3592 case RTL_GIGA_MAC_VER_20:
3593 case RTL_GIGA_MAC_VER_21:
3594 case RTL_GIGA_MAC_VER_22:
3595 case RTL_GIGA_MAC_VER_23:
3596 case RTL_GIGA_MAC_VER_24:
3597 case RTL_GIGA_MAC_VER_25:
3598 case RTL_GIGA_MAC_VER_26:
3599 case RTL_GIGA_MAC_VER_27:
3600 case RTL_GIGA_MAC_VER_28:
3601 case RTL_GIGA_MAC_VER_31:
3602 rtl_writephy(tp, 0x0e, 0x0000);
3603 break;
3604 default:
3605 break;
3606 }
3607 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3608 }
3609
3610 static void r8168_phy_power_down(struct rtl8169_private *tp)
3611 {
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613 switch (tp->mac_version) {
3614 case RTL_GIGA_MAC_VER_32:
3615 case RTL_GIGA_MAC_VER_33:
3616 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3617 break;
3618
3619 case RTL_GIGA_MAC_VER_11:
3620 case RTL_GIGA_MAC_VER_12:
3621 case RTL_GIGA_MAC_VER_17:
3622 case RTL_GIGA_MAC_VER_18:
3623 case RTL_GIGA_MAC_VER_19:
3624 case RTL_GIGA_MAC_VER_20:
3625 case RTL_GIGA_MAC_VER_21:
3626 case RTL_GIGA_MAC_VER_22:
3627 case RTL_GIGA_MAC_VER_23:
3628 case RTL_GIGA_MAC_VER_24:
3629 case RTL_GIGA_MAC_VER_25:
3630 case RTL_GIGA_MAC_VER_26:
3631 case RTL_GIGA_MAC_VER_27:
3632 case RTL_GIGA_MAC_VER_28:
3633 case RTL_GIGA_MAC_VER_31:
3634 rtl_writephy(tp, 0x0e, 0x0200);
3635 default:
3636 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3637 break;
3638 }
3639 }
3640
3641 static void r8168_pll_power_down(struct rtl8169_private *tp)
3642 {
3643 void __iomem *ioaddr = tp->mmio_addr;
3644
3645 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3646 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3647 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3648 r8168dp_check_dash(tp)) {
3649 return;
3650 }
3651
3652 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3653 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3654 (RTL_R16(CPlusCmd) & ASF)) {
3655 return;
3656 }
3657
3658 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3659 tp->mac_version == RTL_GIGA_MAC_VER_33)
3660 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3661
3662 if (rtl_wol_pll_power_down(tp))
3663 return;
3664
3665 r8168_phy_power_down(tp);
3666
3667 switch (tp->mac_version) {
3668 case RTL_GIGA_MAC_VER_25:
3669 case RTL_GIGA_MAC_VER_26:
3670 case RTL_GIGA_MAC_VER_27:
3671 case RTL_GIGA_MAC_VER_28:
3672 case RTL_GIGA_MAC_VER_31:
3673 case RTL_GIGA_MAC_VER_32:
3674 case RTL_GIGA_MAC_VER_33:
3675 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3676 break;
3677 }
3678 }
3679
3680 static void r8168_pll_power_up(struct rtl8169_private *tp)
3681 {
3682 void __iomem *ioaddr = tp->mmio_addr;
3683
3684 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3685 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3686 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3687 r8168dp_check_dash(tp)) {
3688 return;
3689 }
3690
3691 switch (tp->mac_version) {
3692 case RTL_GIGA_MAC_VER_25:
3693 case RTL_GIGA_MAC_VER_26:
3694 case RTL_GIGA_MAC_VER_27:
3695 case RTL_GIGA_MAC_VER_28:
3696 case RTL_GIGA_MAC_VER_31:
3697 case RTL_GIGA_MAC_VER_32:
3698 case RTL_GIGA_MAC_VER_33:
3699 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3700 break;
3701 }
3702
3703 r8168_phy_power_up(tp);
3704 }
3705
3706 static void rtl_generic_op(struct rtl8169_private *tp,
3707 void (*op)(struct rtl8169_private *))
3708 {
3709 if (op)
3710 op(tp);
3711 }
3712
3713 static void rtl_pll_power_down(struct rtl8169_private *tp)
3714 {
3715 rtl_generic_op(tp, tp->pll_power_ops.down);
3716 }
3717
3718 static void rtl_pll_power_up(struct rtl8169_private *tp)
3719 {
3720 rtl_generic_op(tp, tp->pll_power_ops.up);
3721 }
3722
3723 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3724 {
3725 struct pll_power_ops *ops = &tp->pll_power_ops;
3726
3727 switch (tp->mac_version) {
3728 case RTL_GIGA_MAC_VER_07:
3729 case RTL_GIGA_MAC_VER_08:
3730 case RTL_GIGA_MAC_VER_09:
3731 case RTL_GIGA_MAC_VER_10:
3732 case RTL_GIGA_MAC_VER_16:
3733 case RTL_GIGA_MAC_VER_29:
3734 case RTL_GIGA_MAC_VER_30:
3735 ops->down = r810x_pll_power_down;
3736 ops->up = r810x_pll_power_up;
3737 break;
3738
3739 case RTL_GIGA_MAC_VER_11:
3740 case RTL_GIGA_MAC_VER_12:
3741 case RTL_GIGA_MAC_VER_17:
3742 case RTL_GIGA_MAC_VER_18:
3743 case RTL_GIGA_MAC_VER_19:
3744 case RTL_GIGA_MAC_VER_20:
3745 case RTL_GIGA_MAC_VER_21:
3746 case RTL_GIGA_MAC_VER_22:
3747 case RTL_GIGA_MAC_VER_23:
3748 case RTL_GIGA_MAC_VER_24:
3749 case RTL_GIGA_MAC_VER_25:
3750 case RTL_GIGA_MAC_VER_26:
3751 case RTL_GIGA_MAC_VER_27:
3752 case RTL_GIGA_MAC_VER_28:
3753 case RTL_GIGA_MAC_VER_31:
3754 case RTL_GIGA_MAC_VER_32:
3755 case RTL_GIGA_MAC_VER_33:
3756 case RTL_GIGA_MAC_VER_34:
3757 case RTL_GIGA_MAC_VER_35:
3758 case RTL_GIGA_MAC_VER_36:
3759 ops->down = r8168_pll_power_down;
3760 ops->up = r8168_pll_power_up;
3761 break;
3762
3763 default:
3764 ops->down = NULL;
3765 ops->up = NULL;
3766 break;
3767 }
3768 }
3769
3770 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3771 {
3772 void __iomem *ioaddr = tp->mmio_addr;
3773
3774 switch (tp->mac_version) {
3775 case RTL_GIGA_MAC_VER_01:
3776 case RTL_GIGA_MAC_VER_02:
3777 case RTL_GIGA_MAC_VER_03:
3778 case RTL_GIGA_MAC_VER_04:
3779 case RTL_GIGA_MAC_VER_05:
3780 case RTL_GIGA_MAC_VER_06:
3781 case RTL_GIGA_MAC_VER_10:
3782 case RTL_GIGA_MAC_VER_11:
3783 case RTL_GIGA_MAC_VER_12:
3784 case RTL_GIGA_MAC_VER_13:
3785 case RTL_GIGA_MAC_VER_14:
3786 case RTL_GIGA_MAC_VER_15:
3787 case RTL_GIGA_MAC_VER_16:
3788 case RTL_GIGA_MAC_VER_17:
3789 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3790 break;
3791 case RTL_GIGA_MAC_VER_18:
3792 case RTL_GIGA_MAC_VER_19:
3793 case RTL_GIGA_MAC_VER_20:
3794 case RTL_GIGA_MAC_VER_21:
3795 case RTL_GIGA_MAC_VER_22:
3796 case RTL_GIGA_MAC_VER_23:
3797 case RTL_GIGA_MAC_VER_24:
3798 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3799 break;
3800 default:
3801 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3802 break;
3803 }
3804 }
3805
3806 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3807 {
3808 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3809 }
3810
3811 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3812 {
3813 void __iomem *ioaddr = tp->mmio_addr;
3814
3815 RTL_W8(Cfg9346, Cfg9346_Unlock);
3816 rtl_generic_op(tp, tp->jumbo_ops.enable);
3817 RTL_W8(Cfg9346, Cfg9346_Lock);
3818 }
3819
3820 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3821 {
3822 void __iomem *ioaddr = tp->mmio_addr;
3823
3824 RTL_W8(Cfg9346, Cfg9346_Unlock);
3825 rtl_generic_op(tp, tp->jumbo_ops.disable);
3826 RTL_W8(Cfg9346, Cfg9346_Lock);
3827 }
3828
3829 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3830 {
3831 void __iomem *ioaddr = tp->mmio_addr;
3832
3833 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3834 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3835 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3836 }
3837
3838 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3839 {
3840 void __iomem *ioaddr = tp->mmio_addr;
3841
3842 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3843 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3844 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3845 }
3846
3847 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3848 {
3849 void __iomem *ioaddr = tp->mmio_addr;
3850
3851 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3852 }
3853
3854 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3855 {
3856 void __iomem *ioaddr = tp->mmio_addr;
3857
3858 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3859 }
3860
3861 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3862 {
3863 void __iomem *ioaddr = tp->mmio_addr;
3864
3865 RTL_W8(MaxTxPacketSize, 0x3f);
3866 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3867 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3868 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3869 }
3870
3871 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3872 {
3873 void __iomem *ioaddr = tp->mmio_addr;
3874
3875 RTL_W8(MaxTxPacketSize, 0x0c);
3876 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3877 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3878 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3879 }
3880
3881 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3882 {
3883 rtl_tx_performance_tweak(tp->pci_dev,
3884 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3885 }
3886
3887 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3888 {
3889 rtl_tx_performance_tweak(tp->pci_dev,
3890 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3891 }
3892
3893 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3894 {
3895 void __iomem *ioaddr = tp->mmio_addr;
3896
3897 r8168b_0_hw_jumbo_enable(tp);
3898
3899 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3900 }
3901
3902 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3903 {
3904 void __iomem *ioaddr = tp->mmio_addr;
3905
3906 r8168b_0_hw_jumbo_disable(tp);
3907
3908 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3909 }
3910
3911 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3912 {
3913 struct jumbo_ops *ops = &tp->jumbo_ops;
3914
3915 switch (tp->mac_version) {
3916 case RTL_GIGA_MAC_VER_11:
3917 ops->disable = r8168b_0_hw_jumbo_disable;
3918 ops->enable = r8168b_0_hw_jumbo_enable;
3919 break;
3920 case RTL_GIGA_MAC_VER_12:
3921 case RTL_GIGA_MAC_VER_17:
3922 ops->disable = r8168b_1_hw_jumbo_disable;
3923 ops->enable = r8168b_1_hw_jumbo_enable;
3924 break;
3925 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3926 case RTL_GIGA_MAC_VER_19:
3927 case RTL_GIGA_MAC_VER_20:
3928 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3929 case RTL_GIGA_MAC_VER_22:
3930 case RTL_GIGA_MAC_VER_23:
3931 case RTL_GIGA_MAC_VER_24:
3932 case RTL_GIGA_MAC_VER_25:
3933 case RTL_GIGA_MAC_VER_26:
3934 ops->disable = r8168c_hw_jumbo_disable;
3935 ops->enable = r8168c_hw_jumbo_enable;
3936 break;
3937 case RTL_GIGA_MAC_VER_27:
3938 case RTL_GIGA_MAC_VER_28:
3939 ops->disable = r8168dp_hw_jumbo_disable;
3940 ops->enable = r8168dp_hw_jumbo_enable;
3941 break;
3942 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3943 case RTL_GIGA_MAC_VER_32:
3944 case RTL_GIGA_MAC_VER_33:
3945 case RTL_GIGA_MAC_VER_34:
3946 ops->disable = r8168e_hw_jumbo_disable;
3947 ops->enable = r8168e_hw_jumbo_enable;
3948 break;
3949
3950 /*
3951 * No action needed for jumbo frames with 8169.
3952 * No jumbo for 810x at all.
3953 */
3954 default:
3955 ops->disable = NULL;
3956 ops->enable = NULL;
3957 break;
3958 }
3959 }
3960
3961 static void rtl_hw_reset(struct rtl8169_private *tp)
3962 {
3963 void __iomem *ioaddr = tp->mmio_addr;
3964 int i;
3965
3966 /* Soft reset the chip. */
3967 RTL_W8(ChipCmd, CmdReset);
3968
3969 /* Check that the chip has finished the reset. */
3970 for (i = 0; i < 100; i++) {
3971 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3972 break;
3973 udelay(100);
3974 }
3975 }
3976
3977 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3978 {
3979 struct rtl_fw *rtl_fw;
3980 const char *name;
3981 int rc = -ENOMEM;
3982
3983 name = rtl_lookup_firmware_name(tp);
3984 if (!name)
3985 goto out_no_firmware;
3986
3987 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3988 if (!rtl_fw)
3989 goto err_warn;
3990
3991 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3992 if (rc < 0)
3993 goto err_free;
3994
3995 rc = rtl_check_firmware(tp, rtl_fw);
3996 if (rc < 0)
3997 goto err_release_firmware;
3998
3999 tp->rtl_fw = rtl_fw;
4000 out:
4001 return;
4002
4003 err_release_firmware:
4004 release_firmware(rtl_fw->fw);
4005 err_free:
4006 kfree(rtl_fw);
4007 err_warn:
4008 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4009 name, rc);
4010 out_no_firmware:
4011 tp->rtl_fw = NULL;
4012 goto out;
4013 }
4014
4015 static void rtl_request_firmware(struct rtl8169_private *tp)
4016 {
4017 if (IS_ERR(tp->rtl_fw))
4018 rtl_request_uncached_firmware(tp);
4019 }
4020
4021 static void rtl_rx_close(struct rtl8169_private *tp)
4022 {
4023 void __iomem *ioaddr = tp->mmio_addr;
4024
4025 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4026 }
4027
4028 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4029 {
4030 void __iomem *ioaddr = tp->mmio_addr;
4031
4032 /* Disable interrupts */
4033 rtl8169_irq_mask_and_ack(tp);
4034
4035 rtl_rx_close(tp);
4036
4037 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4038 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4039 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4040 while (RTL_R8(TxPoll) & NPQ)
4041 udelay(20);
4042 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4043 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4044 tp->mac_version == RTL_GIGA_MAC_VER_36) {
4045 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4046 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4047 udelay(100);
4048 } else {
4049 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4050 udelay(100);
4051 }
4052
4053 rtl_hw_reset(tp);
4054 }
4055
4056 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4057 {
4058 void __iomem *ioaddr = tp->mmio_addr;
4059
4060 /* Set DMA burst size and Interframe Gap Time */
4061 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4062 (InterFrameGap << TxInterFrameGapShift));
4063 }
4064
4065 static void rtl_hw_start(struct net_device *dev)
4066 {
4067 struct rtl8169_private *tp = netdev_priv(dev);
4068
4069 tp->hw_start(dev);
4070
4071 rtl_irq_enable_all(tp);
4072 }
4073
4074 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4075 void __iomem *ioaddr)
4076 {
4077 /*
4078 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4079 * register to be written before TxDescAddrLow to work.
4080 * Switching from MMIO to I/O access fixes the issue as well.
4081 */
4082 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4083 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4084 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4085 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4086 }
4087
4088 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4089 {
4090 u16 cmd;
4091
4092 cmd = RTL_R16(CPlusCmd);
4093 RTL_W16(CPlusCmd, cmd);
4094 return cmd;
4095 }
4096
4097 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4098 {
4099 /* Low hurts. Let's disable the filtering. */
4100 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4101 }
4102
4103 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4104 {
4105 static const struct rtl_cfg2_info {
4106 u32 mac_version;
4107 u32 clk;
4108 u32 val;
4109 } cfg2_info [] = {
4110 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4111 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4112 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4113 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4114 };
4115 const struct rtl_cfg2_info *p = cfg2_info;
4116 unsigned int i;
4117 u32 clk;
4118
4119 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4120 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4121 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4122 RTL_W32(0x7c, p->val);
4123 break;
4124 }
4125 }
4126 }
4127
4128 static void rtl_set_rx_mode(struct net_device *dev)
4129 {
4130 struct rtl8169_private *tp = netdev_priv(dev);
4131 void __iomem *ioaddr = tp->mmio_addr;
4132 u32 mc_filter[2]; /* Multicast hash filter */
4133 int rx_mode;
4134 u32 tmp = 0;
4135
4136 if (dev->flags & IFF_PROMISC) {
4137 /* Unconditionally log net taps. */
4138 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4139 rx_mode =
4140 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4141 AcceptAllPhys;
4142 mc_filter[1] = mc_filter[0] = 0xffffffff;
4143 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4144 (dev->flags & IFF_ALLMULTI)) {
4145 /* Too many to filter perfectly -- accept all multicasts. */
4146 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4147 mc_filter[1] = mc_filter[0] = 0xffffffff;
4148 } else {
4149 struct netdev_hw_addr *ha;
4150
4151 rx_mode = AcceptBroadcast | AcceptMyPhys;
4152 mc_filter[1] = mc_filter[0] = 0;
4153 netdev_for_each_mc_addr(ha, dev) {
4154 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4155 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4156 rx_mode |= AcceptMulticast;
4157 }
4158 }
4159
4160 if (dev->features & NETIF_F_RXALL)
4161 rx_mode |= (AcceptErr | AcceptRunt);
4162
4163 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4164
4165 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4166 u32 data = mc_filter[0];
4167
4168 mc_filter[0] = swab32(mc_filter[1]);
4169 mc_filter[1] = swab32(data);
4170 }
4171
4172 RTL_W32(MAR0 + 4, mc_filter[1]);
4173 RTL_W32(MAR0 + 0, mc_filter[0]);
4174
4175 RTL_W32(RxConfig, tmp);
4176 }
4177
4178 static void rtl_hw_start_8169(struct net_device *dev)
4179 {
4180 struct rtl8169_private *tp = netdev_priv(dev);
4181 void __iomem *ioaddr = tp->mmio_addr;
4182 struct pci_dev *pdev = tp->pci_dev;
4183
4184 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4185 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4186 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4187 }
4188
4189 RTL_W8(Cfg9346, Cfg9346_Unlock);
4190 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4191 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4192 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4193 tp->mac_version == RTL_GIGA_MAC_VER_04)
4194 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4195
4196 rtl_init_rxcfg(tp);
4197
4198 RTL_W8(EarlyTxThres, NoEarlyTx);
4199
4200 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4201
4202 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4203 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4204 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4205 tp->mac_version == RTL_GIGA_MAC_VER_04)
4206 rtl_set_rx_tx_config_registers(tp);
4207
4208 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4209
4210 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4211 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4212 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4213 "Bit-3 and bit-14 MUST be 1\n");
4214 tp->cp_cmd |= (1 << 14);
4215 }
4216
4217 RTL_W16(CPlusCmd, tp->cp_cmd);
4218
4219 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4220
4221 /*
4222 * Undocumented corner. Supposedly:
4223 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4224 */
4225 RTL_W16(IntrMitigate, 0x0000);
4226
4227 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4228
4229 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4230 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4231 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4232 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4233 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4234 rtl_set_rx_tx_config_registers(tp);
4235 }
4236
4237 RTL_W8(Cfg9346, Cfg9346_Lock);
4238
4239 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4240 RTL_R8(IntrMask);
4241
4242 RTL_W32(RxMissed, 0);
4243
4244 rtl_set_rx_mode(dev);
4245
4246 /* no early-rx interrupts */
4247 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4248 }
4249
4250 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4251 {
4252 u32 csi;
4253
4254 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4255 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4256 }
4257
4258 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4259 {
4260 rtl_csi_access_enable(ioaddr, 0x17000000);
4261 }
4262
4263 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4264 {
4265 rtl_csi_access_enable(ioaddr, 0x27000000);
4266 }
4267
4268 struct ephy_info {
4269 unsigned int offset;
4270 u16 mask;
4271 u16 bits;
4272 };
4273
4274 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4275 {
4276 u16 w;
4277
4278 while (len-- > 0) {
4279 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4280 rtl_ephy_write(ioaddr, e->offset, w);
4281 e++;
4282 }
4283 }
4284
4285 static void rtl_disable_clock_request(struct pci_dev *pdev)
4286 {
4287 int cap = pci_pcie_cap(pdev);
4288
4289 if (cap) {
4290 u16 ctl;
4291
4292 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4293 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4294 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4295 }
4296 }
4297
4298 static void rtl_enable_clock_request(struct pci_dev *pdev)
4299 {
4300 int cap = pci_pcie_cap(pdev);
4301
4302 if (cap) {
4303 u16 ctl;
4304
4305 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4306 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4307 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4308 }
4309 }
4310
4311 #define R8168_CPCMD_QUIRK_MASK (\
4312 EnableBist | \
4313 Mac_dbgo_oe | \
4314 Force_half_dup | \
4315 Force_rxflow_en | \
4316 Force_txflow_en | \
4317 Cxpl_dbg_sel | \
4318 ASF | \
4319 PktCntrDisable | \
4320 Mac_dbgo_sel)
4321
4322 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4323 {
4324 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4325
4326 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4327
4328 rtl_tx_performance_tweak(pdev,
4329 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4330 }
4331
4332 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4333 {
4334 rtl_hw_start_8168bb(ioaddr, pdev);
4335
4336 RTL_W8(MaxTxPacketSize, TxPacketMax);
4337
4338 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4339 }
4340
4341 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4342 {
4343 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4344
4345 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4346
4347 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4348
4349 rtl_disable_clock_request(pdev);
4350
4351 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4352 }
4353
4354 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4355 {
4356 static const struct ephy_info e_info_8168cp[] = {
4357 { 0x01, 0, 0x0001 },
4358 { 0x02, 0x0800, 0x1000 },
4359 { 0x03, 0, 0x0042 },
4360 { 0x06, 0x0080, 0x0000 },
4361 { 0x07, 0, 0x2000 }
4362 };
4363
4364 rtl_csi_access_enable_2(ioaddr);
4365
4366 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4367
4368 __rtl_hw_start_8168cp(ioaddr, pdev);
4369 }
4370
4371 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4372 {
4373 rtl_csi_access_enable_2(ioaddr);
4374
4375 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4376
4377 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4378
4379 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4380 }
4381
4382 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4383 {
4384 rtl_csi_access_enable_2(ioaddr);
4385
4386 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4387
4388 /* Magic. */
4389 RTL_W8(DBG_REG, 0x20);
4390
4391 RTL_W8(MaxTxPacketSize, TxPacketMax);
4392
4393 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4394
4395 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4396 }
4397
4398 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4399 {
4400 static const struct ephy_info e_info_8168c_1[] = {
4401 { 0x02, 0x0800, 0x1000 },
4402 { 0x03, 0, 0x0002 },
4403 { 0x06, 0x0080, 0x0000 }
4404 };
4405
4406 rtl_csi_access_enable_2(ioaddr);
4407
4408 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4409
4410 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4411
4412 __rtl_hw_start_8168cp(ioaddr, pdev);
4413 }
4414
4415 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4416 {
4417 static const struct ephy_info e_info_8168c_2[] = {
4418 { 0x01, 0, 0x0001 },
4419 { 0x03, 0x0400, 0x0220 }
4420 };
4421
4422 rtl_csi_access_enable_2(ioaddr);
4423
4424 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4425
4426 __rtl_hw_start_8168cp(ioaddr, pdev);
4427 }
4428
4429 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4430 {
4431 rtl_hw_start_8168c_2(ioaddr, pdev);
4432 }
4433
4434 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4435 {
4436 rtl_csi_access_enable_2(ioaddr);
4437
4438 __rtl_hw_start_8168cp(ioaddr, pdev);
4439 }
4440
4441 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4442 {
4443 rtl_csi_access_enable_2(ioaddr);
4444
4445 rtl_disable_clock_request(pdev);
4446
4447 RTL_W8(MaxTxPacketSize, TxPacketMax);
4448
4449 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4450
4451 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4452 }
4453
4454 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4455 {
4456 rtl_csi_access_enable_1(ioaddr);
4457
4458 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4459
4460 RTL_W8(MaxTxPacketSize, TxPacketMax);
4461
4462 rtl_disable_clock_request(pdev);
4463 }
4464
4465 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4466 {
4467 static const struct ephy_info e_info_8168d_4[] = {
4468 { 0x0b, ~0, 0x48 },
4469 { 0x19, 0x20, 0x50 },
4470 { 0x0c, ~0, 0x20 }
4471 };
4472 int i;
4473
4474 rtl_csi_access_enable_1(ioaddr);
4475
4476 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4477
4478 RTL_W8(MaxTxPacketSize, TxPacketMax);
4479
4480 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4481 const struct ephy_info *e = e_info_8168d_4 + i;
4482 u16 w;
4483
4484 w = rtl_ephy_read(ioaddr, e->offset);
4485 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4486 }
4487
4488 rtl_enable_clock_request(pdev);
4489 }
4490
4491 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4492 {
4493 static const struct ephy_info e_info_8168e_1[] = {
4494 { 0x00, 0x0200, 0x0100 },
4495 { 0x00, 0x0000, 0x0004 },
4496 { 0x06, 0x0002, 0x0001 },
4497 { 0x06, 0x0000, 0x0030 },
4498 { 0x07, 0x0000, 0x2000 },
4499 { 0x00, 0x0000, 0x0020 },
4500 { 0x03, 0x5800, 0x2000 },
4501 { 0x03, 0x0000, 0x0001 },
4502 { 0x01, 0x0800, 0x1000 },
4503 { 0x07, 0x0000, 0x4000 },
4504 { 0x1e, 0x0000, 0x2000 },
4505 { 0x19, 0xffff, 0xfe6c },
4506 { 0x0a, 0x0000, 0x0040 }
4507 };
4508
4509 rtl_csi_access_enable_2(ioaddr);
4510
4511 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4512
4513 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4514
4515 RTL_W8(MaxTxPacketSize, TxPacketMax);
4516
4517 rtl_disable_clock_request(pdev);
4518
4519 /* Reset tx FIFO pointer */
4520 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4521 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4522
4523 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4524 }
4525
4526 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4527 {
4528 static const struct ephy_info e_info_8168e_2[] = {
4529 { 0x09, 0x0000, 0x0080 },
4530 { 0x19, 0x0000, 0x0224 }
4531 };
4532
4533 rtl_csi_access_enable_1(ioaddr);
4534
4535 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4536
4537 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4538
4539 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4540 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4541 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4542 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4543 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4544 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4545 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4546 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4547 ERIAR_EXGMAC);
4548
4549 RTL_W8(MaxTxPacketSize, EarlySize);
4550
4551 rtl_disable_clock_request(pdev);
4552
4553 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4554 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4555
4556 /* Adjust EEE LED frequency */
4557 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4558
4559 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4560 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4561 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4562 }
4563
4564 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4565 {
4566 static const struct ephy_info e_info_8168f_1[] = {
4567 { 0x06, 0x00c0, 0x0020 },
4568 { 0x08, 0x0001, 0x0002 },
4569 { 0x09, 0x0000, 0x0080 },
4570 { 0x19, 0x0000, 0x0224 }
4571 };
4572
4573 rtl_csi_access_enable_1(ioaddr);
4574
4575 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4576
4577 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4578
4579 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4580 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4581 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4582 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4583 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4584 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4585 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4586 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4587 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4588 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4589 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4590 ERIAR_EXGMAC);
4591
4592 RTL_W8(MaxTxPacketSize, EarlySize);
4593
4594 rtl_disable_clock_request(pdev);
4595
4596 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4597 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4598
4599 /* Adjust EEE LED frequency */
4600 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4601
4602 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4603 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4604 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4605 }
4606
4607 static void rtl_hw_start_8168(struct net_device *dev)
4608 {
4609 struct rtl8169_private *tp = netdev_priv(dev);
4610 void __iomem *ioaddr = tp->mmio_addr;
4611 struct pci_dev *pdev = tp->pci_dev;
4612
4613 RTL_W8(Cfg9346, Cfg9346_Unlock);
4614
4615 RTL_W8(MaxTxPacketSize, TxPacketMax);
4616
4617 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4618
4619 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4620
4621 RTL_W16(CPlusCmd, tp->cp_cmd);
4622
4623 RTL_W16(IntrMitigate, 0x5151);
4624
4625 /* Work around for RxFIFO overflow. */
4626 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4627 tp->event_slow |= RxFIFOOver | PCSTimeout;
4628 tp->event_slow &= ~RxOverflow;
4629 }
4630
4631 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4632
4633 rtl_set_rx_mode(dev);
4634
4635 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4636 (InterFrameGap << TxInterFrameGapShift));
4637
4638 RTL_R8(IntrMask);
4639
4640 switch (tp->mac_version) {
4641 case RTL_GIGA_MAC_VER_11:
4642 rtl_hw_start_8168bb(ioaddr, pdev);
4643 break;
4644
4645 case RTL_GIGA_MAC_VER_12:
4646 case RTL_GIGA_MAC_VER_17:
4647 rtl_hw_start_8168bef(ioaddr, pdev);
4648 break;
4649
4650 case RTL_GIGA_MAC_VER_18:
4651 rtl_hw_start_8168cp_1(ioaddr, pdev);
4652 break;
4653
4654 case RTL_GIGA_MAC_VER_19:
4655 rtl_hw_start_8168c_1(ioaddr, pdev);
4656 break;
4657
4658 case RTL_GIGA_MAC_VER_20:
4659 rtl_hw_start_8168c_2(ioaddr, pdev);
4660 break;
4661
4662 case RTL_GIGA_MAC_VER_21:
4663 rtl_hw_start_8168c_3(ioaddr, pdev);
4664 break;
4665
4666 case RTL_GIGA_MAC_VER_22:
4667 rtl_hw_start_8168c_4(ioaddr, pdev);
4668 break;
4669
4670 case RTL_GIGA_MAC_VER_23:
4671 rtl_hw_start_8168cp_2(ioaddr, pdev);
4672 break;
4673
4674 case RTL_GIGA_MAC_VER_24:
4675 rtl_hw_start_8168cp_3(ioaddr, pdev);
4676 break;
4677
4678 case RTL_GIGA_MAC_VER_25:
4679 case RTL_GIGA_MAC_VER_26:
4680 case RTL_GIGA_MAC_VER_27:
4681 rtl_hw_start_8168d(ioaddr, pdev);
4682 break;
4683
4684 case RTL_GIGA_MAC_VER_28:
4685 rtl_hw_start_8168d_4(ioaddr, pdev);
4686 break;
4687
4688 case RTL_GIGA_MAC_VER_31:
4689 rtl_hw_start_8168dp(ioaddr, pdev);
4690 break;
4691
4692 case RTL_GIGA_MAC_VER_32:
4693 case RTL_GIGA_MAC_VER_33:
4694 rtl_hw_start_8168e_1(ioaddr, pdev);
4695 break;
4696 case RTL_GIGA_MAC_VER_34:
4697 rtl_hw_start_8168e_2(ioaddr, pdev);
4698 break;
4699
4700 case RTL_GIGA_MAC_VER_35:
4701 case RTL_GIGA_MAC_VER_36:
4702 rtl_hw_start_8168f_1(ioaddr, pdev);
4703 break;
4704
4705 default:
4706 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4707 dev->name, tp->mac_version);
4708 break;
4709 }
4710
4711 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4712
4713 RTL_W8(Cfg9346, Cfg9346_Lock);
4714
4715 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4716 }
4717
4718 #define R810X_CPCMD_QUIRK_MASK (\
4719 EnableBist | \
4720 Mac_dbgo_oe | \
4721 Force_half_dup | \
4722 Force_rxflow_en | \
4723 Force_txflow_en | \
4724 Cxpl_dbg_sel | \
4725 ASF | \
4726 PktCntrDisable | \
4727 Mac_dbgo_sel)
4728
4729 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4730 {
4731 static const struct ephy_info e_info_8102e_1[] = {
4732 { 0x01, 0, 0x6e65 },
4733 { 0x02, 0, 0x091f },
4734 { 0x03, 0, 0xc2f9 },
4735 { 0x06, 0, 0xafb5 },
4736 { 0x07, 0, 0x0e00 },
4737 { 0x19, 0, 0xec80 },
4738 { 0x01, 0, 0x2e65 },
4739 { 0x01, 0, 0x6e65 }
4740 };
4741 u8 cfg1;
4742
4743 rtl_csi_access_enable_2(ioaddr);
4744
4745 RTL_W8(DBG_REG, FIX_NAK_1);
4746
4747 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4748
4749 RTL_W8(Config1,
4750 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4751 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4752
4753 cfg1 = RTL_R8(Config1);
4754 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4755 RTL_W8(Config1, cfg1 & ~LEDS0);
4756
4757 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4758 }
4759
4760 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4761 {
4762 rtl_csi_access_enable_2(ioaddr);
4763
4764 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4765
4766 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4767 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4768 }
4769
4770 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4771 {
4772 rtl_hw_start_8102e_2(ioaddr, pdev);
4773
4774 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4775 }
4776
4777 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4778 {
4779 static const struct ephy_info e_info_8105e_1[] = {
4780 { 0x07, 0, 0x4000 },
4781 { 0x19, 0, 0x0200 },
4782 { 0x19, 0, 0x0020 },
4783 { 0x1e, 0, 0x2000 },
4784 { 0x03, 0, 0x0001 },
4785 { 0x19, 0, 0x0100 },
4786 { 0x19, 0, 0x0004 },
4787 { 0x0a, 0, 0x0020 }
4788 };
4789
4790 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4791 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4792
4793 /* Disable Early Tally Counter */
4794 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4795
4796 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4797 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4798
4799 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4800 }
4801
4802 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4803 {
4804 rtl_hw_start_8105e_1(ioaddr, pdev);
4805 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4806 }
4807
4808 static void rtl_hw_start_8101(struct net_device *dev)
4809 {
4810 struct rtl8169_private *tp = netdev_priv(dev);
4811 void __iomem *ioaddr = tp->mmio_addr;
4812 struct pci_dev *pdev = tp->pci_dev;
4813
4814 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4815 tp->event_slow &= ~RxFIFOOver;
4816
4817 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4818 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4819 int cap = pci_pcie_cap(pdev);
4820
4821 if (cap) {
4822 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4823 PCI_EXP_DEVCTL_NOSNOOP_EN);
4824 }
4825 }
4826
4827 RTL_W8(Cfg9346, Cfg9346_Unlock);
4828
4829 switch (tp->mac_version) {
4830 case RTL_GIGA_MAC_VER_07:
4831 rtl_hw_start_8102e_1(ioaddr, pdev);
4832 break;
4833
4834 case RTL_GIGA_MAC_VER_08:
4835 rtl_hw_start_8102e_3(ioaddr, pdev);
4836 break;
4837
4838 case RTL_GIGA_MAC_VER_09:
4839 rtl_hw_start_8102e_2(ioaddr, pdev);
4840 break;
4841
4842 case RTL_GIGA_MAC_VER_29:
4843 rtl_hw_start_8105e_1(ioaddr, pdev);
4844 break;
4845 case RTL_GIGA_MAC_VER_30:
4846 rtl_hw_start_8105e_2(ioaddr, pdev);
4847 break;
4848 }
4849
4850 RTL_W8(Cfg9346, Cfg9346_Lock);
4851
4852 RTL_W8(MaxTxPacketSize, TxPacketMax);
4853
4854 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4855
4856 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4857 RTL_W16(CPlusCmd, tp->cp_cmd);
4858
4859 RTL_W16(IntrMitigate, 0x0000);
4860
4861 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4862
4863 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4864 rtl_set_rx_tx_config_registers(tp);
4865
4866 RTL_R8(IntrMask);
4867
4868 rtl_set_rx_mode(dev);
4869
4870 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4871 }
4872
4873 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4874 {
4875 struct rtl8169_private *tp = netdev_priv(dev);
4876
4877 if (new_mtu < ETH_ZLEN ||
4878 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4879 return -EINVAL;
4880
4881 if (new_mtu > ETH_DATA_LEN)
4882 rtl_hw_jumbo_enable(tp);
4883 else
4884 rtl_hw_jumbo_disable(tp);
4885
4886 dev->mtu = new_mtu;
4887 netdev_update_features(dev);
4888
4889 return 0;
4890 }
4891
4892 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4893 {
4894 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4895 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4896 }
4897
4898 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4899 void **data_buff, struct RxDesc *desc)
4900 {
4901 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4902 DMA_FROM_DEVICE);
4903
4904 kfree(*data_buff);
4905 *data_buff = NULL;
4906 rtl8169_make_unusable_by_asic(desc);
4907 }
4908
4909 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4910 {
4911 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4912
4913 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4914 }
4915
4916 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4917 u32 rx_buf_sz)
4918 {
4919 desc->addr = cpu_to_le64(mapping);
4920 wmb();
4921 rtl8169_mark_to_asic(desc, rx_buf_sz);
4922 }
4923
4924 static inline void *rtl8169_align(void *data)
4925 {
4926 return (void *)ALIGN((long)data, 16);
4927 }
4928
4929 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4930 struct RxDesc *desc)
4931 {
4932 void *data;
4933 dma_addr_t mapping;
4934 struct device *d = &tp->pci_dev->dev;
4935 struct net_device *dev = tp->dev;
4936 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4937
4938 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4939 if (!data)
4940 return NULL;
4941
4942 if (rtl8169_align(data) != data) {
4943 kfree(data);
4944 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4945 if (!data)
4946 return NULL;
4947 }
4948
4949 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4950 DMA_FROM_DEVICE);
4951 if (unlikely(dma_mapping_error(d, mapping))) {
4952 if (net_ratelimit())
4953 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4954 goto err_out;
4955 }
4956
4957 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4958 return data;
4959
4960 err_out:
4961 kfree(data);
4962 return NULL;
4963 }
4964
4965 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4966 {
4967 unsigned int i;
4968
4969 for (i = 0; i < NUM_RX_DESC; i++) {
4970 if (tp->Rx_databuff[i]) {
4971 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4972 tp->RxDescArray + i);
4973 }
4974 }
4975 }
4976
4977 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4978 {
4979 desc->opts1 |= cpu_to_le32(RingEnd);
4980 }
4981
4982 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4983 {
4984 unsigned int i;
4985
4986 for (i = 0; i < NUM_RX_DESC; i++) {
4987 void *data;
4988
4989 if (tp->Rx_databuff[i])
4990 continue;
4991
4992 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4993 if (!data) {
4994 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4995 goto err_out;
4996 }
4997 tp->Rx_databuff[i] = data;
4998 }
4999
5000 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5001 return 0;
5002
5003 err_out:
5004 rtl8169_rx_clear(tp);
5005 return -ENOMEM;
5006 }
5007
5008 static int rtl8169_init_ring(struct net_device *dev)
5009 {
5010 struct rtl8169_private *tp = netdev_priv(dev);
5011
5012 rtl8169_init_ring_indexes(tp);
5013
5014 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5015 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5016
5017 return rtl8169_rx_fill(tp);
5018 }
5019
5020 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5021 struct TxDesc *desc)
5022 {
5023 unsigned int len = tx_skb->len;
5024
5025 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5026
5027 desc->opts1 = 0x00;
5028 desc->opts2 = 0x00;
5029 desc->addr = 0x00;
5030 tx_skb->len = 0;
5031 }
5032
5033 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5034 unsigned int n)
5035 {
5036 unsigned int i;
5037
5038 for (i = 0; i < n; i++) {
5039 unsigned int entry = (start + i) % NUM_TX_DESC;
5040 struct ring_info *tx_skb = tp->tx_skb + entry;
5041 unsigned int len = tx_skb->len;
5042
5043 if (len) {
5044 struct sk_buff *skb = tx_skb->skb;
5045
5046 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5047 tp->TxDescArray + entry);
5048 if (skb) {
5049 tp->dev->stats.tx_dropped++;
5050 dev_kfree_skb(skb);
5051 tx_skb->skb = NULL;
5052 }
5053 }
5054 }
5055 }
5056
5057 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5058 {
5059 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5060 tp->cur_tx = tp->dirty_tx = 0;
5061 netdev_reset_queue(tp->dev);
5062 }
5063
5064 static void rtl_reset_work(struct rtl8169_private *tp)
5065 {
5066 struct net_device *dev = tp->dev;
5067 int i;
5068
5069 napi_disable(&tp->napi);
5070 netif_stop_queue(dev);
5071 synchronize_sched();
5072
5073 rtl8169_hw_reset(tp);
5074
5075 for (i = 0; i < NUM_RX_DESC; i++)
5076 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5077
5078 rtl8169_tx_clear(tp);
5079 rtl8169_init_ring_indexes(tp);
5080
5081 napi_enable(&tp->napi);
5082 rtl_hw_start(dev);
5083 netif_wake_queue(dev);
5084 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5085 }
5086
5087 static void rtl8169_tx_timeout(struct net_device *dev)
5088 {
5089 struct rtl8169_private *tp = netdev_priv(dev);
5090
5091 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5092 }
5093
5094 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5095 u32 *opts)
5096 {
5097 struct skb_shared_info *info = skb_shinfo(skb);
5098 unsigned int cur_frag, entry;
5099 struct TxDesc * uninitialized_var(txd);
5100 struct device *d = &tp->pci_dev->dev;
5101
5102 entry = tp->cur_tx;
5103 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5104 const skb_frag_t *frag = info->frags + cur_frag;
5105 dma_addr_t mapping;
5106 u32 status, len;
5107 void *addr;
5108
5109 entry = (entry + 1) % NUM_TX_DESC;
5110
5111 txd = tp->TxDescArray + entry;
5112 len = skb_frag_size(frag);
5113 addr = skb_frag_address(frag);
5114 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5115 if (unlikely(dma_mapping_error(d, mapping))) {
5116 if (net_ratelimit())
5117 netif_err(tp, drv, tp->dev,
5118 "Failed to map TX fragments DMA!\n");
5119 goto err_out;
5120 }
5121
5122 /* Anti gcc 2.95.3 bugware (sic) */
5123 status = opts[0] | len |
5124 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5125
5126 txd->opts1 = cpu_to_le32(status);
5127 txd->opts2 = cpu_to_le32(opts[1]);
5128 txd->addr = cpu_to_le64(mapping);
5129
5130 tp->tx_skb[entry].len = len;
5131 }
5132
5133 if (cur_frag) {
5134 tp->tx_skb[entry].skb = skb;
5135 txd->opts1 |= cpu_to_le32(LastFrag);
5136 }
5137
5138 return cur_frag;
5139
5140 err_out:
5141 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5142 return -EIO;
5143 }
5144
5145 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5146 struct sk_buff *skb, u32 *opts)
5147 {
5148 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5149 u32 mss = skb_shinfo(skb)->gso_size;
5150 int offset = info->opts_offset;
5151
5152 if (mss) {
5153 opts[0] |= TD_LSO;
5154 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5155 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5156 const struct iphdr *ip = ip_hdr(skb);
5157
5158 if (ip->protocol == IPPROTO_TCP)
5159 opts[offset] |= info->checksum.tcp;
5160 else if (ip->protocol == IPPROTO_UDP)
5161 opts[offset] |= info->checksum.udp;
5162 else
5163 WARN_ON_ONCE(1);
5164 }
5165 }
5166
5167 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5168 struct net_device *dev)
5169 {
5170 struct rtl8169_private *tp = netdev_priv(dev);
5171 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5172 struct TxDesc *txd = tp->TxDescArray + entry;
5173 void __iomem *ioaddr = tp->mmio_addr;
5174 struct device *d = &tp->pci_dev->dev;
5175 dma_addr_t mapping;
5176 u32 status, len;
5177 u32 opts[2];
5178 int frags;
5179
5180 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5181 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5182 goto err_stop_0;
5183 }
5184
5185 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5186 goto err_stop_0;
5187
5188 len = skb_headlen(skb);
5189 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5190 if (unlikely(dma_mapping_error(d, mapping))) {
5191 if (net_ratelimit())
5192 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5193 goto err_dma_0;
5194 }
5195
5196 tp->tx_skb[entry].len = len;
5197 txd->addr = cpu_to_le64(mapping);
5198
5199 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5200 opts[0] = DescOwn;
5201
5202 rtl8169_tso_csum(tp, skb, opts);
5203
5204 frags = rtl8169_xmit_frags(tp, skb, opts);
5205 if (frags < 0)
5206 goto err_dma_1;
5207 else if (frags)
5208 opts[0] |= FirstFrag;
5209 else {
5210 opts[0] |= FirstFrag | LastFrag;
5211 tp->tx_skb[entry].skb = skb;
5212 }
5213
5214 txd->opts2 = cpu_to_le32(opts[1]);
5215
5216 netdev_sent_queue(dev, skb->len);
5217
5218 wmb();
5219
5220 /* Anti gcc 2.95.3 bugware (sic) */
5221 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5222 txd->opts1 = cpu_to_le32(status);
5223
5224 tp->cur_tx += frags + 1;
5225
5226 wmb();
5227
5228 RTL_W8(TxPoll, NPQ);
5229
5230 mmiowb();
5231
5232 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5233 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5234 * not miss a ring update when it notices a stopped queue.
5235 */
5236 smp_wmb();
5237 netif_stop_queue(dev);
5238 /* Sync with rtl_tx:
5239 * - publish queue status and cur_tx ring index (write barrier)
5240 * - refresh dirty_tx ring index (read barrier).
5241 * May the current thread have a pessimistic view of the ring
5242 * status and forget to wake up queue, a racing rtl_tx thread
5243 * can't.
5244 */
5245 smp_mb();
5246 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5247 netif_wake_queue(dev);
5248 }
5249
5250 return NETDEV_TX_OK;
5251
5252 err_dma_1:
5253 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5254 err_dma_0:
5255 dev_kfree_skb(skb);
5256 dev->stats.tx_dropped++;
5257 return NETDEV_TX_OK;
5258
5259 err_stop_0:
5260 netif_stop_queue(dev);
5261 dev->stats.tx_dropped++;
5262 return NETDEV_TX_BUSY;
5263 }
5264
5265 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5266 {
5267 struct rtl8169_private *tp = netdev_priv(dev);
5268 struct pci_dev *pdev = tp->pci_dev;
5269 u16 pci_status, pci_cmd;
5270
5271 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5272 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5273
5274 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5275 pci_cmd, pci_status);
5276
5277 /*
5278 * The recovery sequence below admits a very elaborated explanation:
5279 * - it seems to work;
5280 * - I did not see what else could be done;
5281 * - it makes iop3xx happy.
5282 *
5283 * Feel free to adjust to your needs.
5284 */
5285 if (pdev->broken_parity_status)
5286 pci_cmd &= ~PCI_COMMAND_PARITY;
5287 else
5288 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5289
5290 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5291
5292 pci_write_config_word(pdev, PCI_STATUS,
5293 pci_status & (PCI_STATUS_DETECTED_PARITY |
5294 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5295 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5296
5297 /* The infamous DAC f*ckup only happens at boot time */
5298 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5299 void __iomem *ioaddr = tp->mmio_addr;
5300
5301 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5302 tp->cp_cmd &= ~PCIDAC;
5303 RTL_W16(CPlusCmd, tp->cp_cmd);
5304 dev->features &= ~NETIF_F_HIGHDMA;
5305 }
5306
5307 rtl8169_hw_reset(tp);
5308
5309 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5310 }
5311
5312 struct rtl_txc {
5313 int packets;
5314 int bytes;
5315 };
5316
5317 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5318 {
5319 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5320 unsigned int dirty_tx, tx_left;
5321 struct rtl_txc txc = { 0, 0 };
5322
5323 dirty_tx = tp->dirty_tx;
5324 smp_rmb();
5325 tx_left = tp->cur_tx - dirty_tx;
5326
5327 while (tx_left > 0) {
5328 unsigned int entry = dirty_tx % NUM_TX_DESC;
5329 struct ring_info *tx_skb = tp->tx_skb + entry;
5330 u32 status;
5331
5332 rmb();
5333 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5334 if (status & DescOwn)
5335 break;
5336
5337 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5338 tp->TxDescArray + entry);
5339 if (status & LastFrag) {
5340 struct sk_buff *skb = tx_skb->skb;
5341
5342 txc.packets++;
5343 txc.bytes += skb->len;
5344 dev_kfree_skb(skb);
5345 tx_skb->skb = NULL;
5346 }
5347 dirty_tx++;
5348 tx_left--;
5349 }
5350
5351 u64_stats_update_begin(&tx_stats->syncp);
5352 tx_stats->packets += txc.packets;
5353 tx_stats->bytes += txc.bytes;
5354 u64_stats_update_end(&tx_stats->syncp);
5355
5356 netdev_completed_queue(dev, txc.packets, txc.bytes);
5357
5358 if (tp->dirty_tx != dirty_tx) {
5359 tp->dirty_tx = dirty_tx;
5360 /* Sync with rtl8169_start_xmit:
5361 * - publish dirty_tx ring index (write barrier)
5362 * - refresh cur_tx ring index and queue status (read barrier)
5363 * May the current thread miss the stopped queue condition,
5364 * a racing xmit thread can only have a right view of the
5365 * ring status.
5366 */
5367 smp_mb();
5368 if (netif_queue_stopped(dev) &&
5369 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5370 netif_wake_queue(dev);
5371 }
5372 /*
5373 * 8168 hack: TxPoll requests are lost when the Tx packets are
5374 * too close. Let's kick an extra TxPoll request when a burst
5375 * of start_xmit activity is detected (if it is not detected,
5376 * it is slow enough). -- FR
5377 */
5378 if (tp->cur_tx != dirty_tx) {
5379 void __iomem *ioaddr = tp->mmio_addr;
5380
5381 RTL_W8(TxPoll, NPQ);
5382 }
5383 }
5384 }
5385
5386 static inline int rtl8169_fragmented_frame(u32 status)
5387 {
5388 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5389 }
5390
5391 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5392 {
5393 u32 status = opts1 & RxProtoMask;
5394
5395 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5396 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5397 skb->ip_summed = CHECKSUM_UNNECESSARY;
5398 else
5399 skb_checksum_none_assert(skb);
5400 }
5401
5402 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5403 struct rtl8169_private *tp,
5404 int pkt_size,
5405 dma_addr_t addr)
5406 {
5407 struct sk_buff *skb;
5408 struct device *d = &tp->pci_dev->dev;
5409
5410 data = rtl8169_align(data);
5411 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5412 prefetch(data);
5413 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5414 if (skb)
5415 memcpy(skb->data, data, pkt_size);
5416 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5417
5418 return skb;
5419 }
5420
5421 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5422 {
5423 unsigned int cur_rx, rx_left;
5424 unsigned int count;
5425
5426 cur_rx = tp->cur_rx;
5427 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5428 rx_left = min(rx_left, budget);
5429
5430 for (; rx_left > 0; rx_left--, cur_rx++) {
5431 unsigned int entry = cur_rx % NUM_RX_DESC;
5432 struct RxDesc *desc = tp->RxDescArray + entry;
5433 u32 status;
5434
5435 rmb();
5436 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5437
5438 if (status & DescOwn)
5439 break;
5440 if (unlikely(status & RxRES)) {
5441 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5442 status);
5443 dev->stats.rx_errors++;
5444 if (status & (RxRWT | RxRUNT))
5445 dev->stats.rx_length_errors++;
5446 if (status & RxCRC)
5447 dev->stats.rx_crc_errors++;
5448 if (status & RxFOVF) {
5449 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5450 dev->stats.rx_fifo_errors++;
5451 }
5452 if ((status & (RxRUNT | RxCRC)) &&
5453 !(status & (RxRWT | RxFOVF)) &&
5454 (dev->features & NETIF_F_RXALL))
5455 goto process_pkt;
5456
5457 rtl8169_mark_to_asic(desc, rx_buf_sz);
5458 } else {
5459 struct sk_buff *skb;
5460 dma_addr_t addr;
5461 int pkt_size;
5462
5463 process_pkt:
5464 addr = le64_to_cpu(desc->addr);
5465 if (likely(!(dev->features & NETIF_F_RXFCS)))
5466 pkt_size = (status & 0x00003fff) - 4;
5467 else
5468 pkt_size = status & 0x00003fff;
5469
5470 /*
5471 * The driver does not support incoming fragmented
5472 * frames. They are seen as a symptom of over-mtu
5473 * sized frames.
5474 */
5475 if (unlikely(rtl8169_fragmented_frame(status))) {
5476 dev->stats.rx_dropped++;
5477 dev->stats.rx_length_errors++;
5478 rtl8169_mark_to_asic(desc, rx_buf_sz);
5479 continue;
5480 }
5481
5482 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5483 tp, pkt_size, addr);
5484 rtl8169_mark_to_asic(desc, rx_buf_sz);
5485 if (!skb) {
5486 dev->stats.rx_dropped++;
5487 continue;
5488 }
5489
5490 rtl8169_rx_csum(skb, status);
5491 skb_put(skb, pkt_size);
5492 skb->protocol = eth_type_trans(skb, dev);
5493
5494 rtl8169_rx_vlan_tag(desc, skb);
5495
5496 napi_gro_receive(&tp->napi, skb);
5497
5498 u64_stats_update_begin(&tp->rx_stats.syncp);
5499 tp->rx_stats.packets++;
5500 tp->rx_stats.bytes += pkt_size;
5501 u64_stats_update_end(&tp->rx_stats.syncp);
5502 }
5503
5504 /* Work around for AMD plateform. */
5505 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5506 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5507 desc->opts2 = 0;
5508 cur_rx++;
5509 }
5510 }
5511
5512 count = cur_rx - tp->cur_rx;
5513 tp->cur_rx = cur_rx;
5514
5515 tp->dirty_rx += count;
5516
5517 return count;
5518 }
5519
5520 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5521 {
5522 struct net_device *dev = dev_instance;
5523 struct rtl8169_private *tp = netdev_priv(dev);
5524 int handled = 0;
5525 u16 status;
5526
5527 status = rtl_get_events(tp);
5528 if (status && status != 0xffff) {
5529 status &= RTL_EVENT_NAPI | tp->event_slow;
5530 if (status) {
5531 handled = 1;
5532
5533 rtl_irq_disable(tp);
5534 napi_schedule(&tp->napi);
5535 }
5536 }
5537 return IRQ_RETVAL(handled);
5538 }
5539
5540 /*
5541 * Workqueue context.
5542 */
5543 static void rtl_slow_event_work(struct rtl8169_private *tp)
5544 {
5545 struct net_device *dev = tp->dev;
5546 u16 status;
5547
5548 status = rtl_get_events(tp) & tp->event_slow;
5549 rtl_ack_events(tp, status);
5550
5551 if (unlikely(status & RxFIFOOver)) {
5552 switch (tp->mac_version) {
5553 /* Work around for rx fifo overflow */
5554 case RTL_GIGA_MAC_VER_11:
5555 netif_stop_queue(dev);
5556 /* XXX - Hack alert. See rtl_task(). */
5557 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5558 default:
5559 break;
5560 }
5561 }
5562
5563 if (unlikely(status & SYSErr))
5564 rtl8169_pcierr_interrupt(dev);
5565
5566 if (status & LinkChg)
5567 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5568
5569 napi_disable(&tp->napi);
5570 rtl_irq_disable(tp);
5571
5572 napi_enable(&tp->napi);
5573 napi_schedule(&tp->napi);
5574 }
5575
5576 static void rtl_task(struct work_struct *work)
5577 {
5578 static const struct {
5579 int bitnr;
5580 void (*action)(struct rtl8169_private *);
5581 } rtl_work[] = {
5582 /* XXX - keep rtl_slow_event_work() as first element. */
5583 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5584 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5585 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5586 };
5587 struct rtl8169_private *tp =
5588 container_of(work, struct rtl8169_private, wk.work);
5589 struct net_device *dev = tp->dev;
5590 int i;
5591
5592 rtl_lock_work(tp);
5593
5594 if (!netif_running(dev) ||
5595 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5596 goto out_unlock;
5597
5598 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5599 bool pending;
5600
5601 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5602 if (pending)
5603 rtl_work[i].action(tp);
5604 }
5605
5606 out_unlock:
5607 rtl_unlock_work(tp);
5608 }
5609
5610 static int rtl8169_poll(struct napi_struct *napi, int budget)
5611 {
5612 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5613 struct net_device *dev = tp->dev;
5614 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5615 int work_done= 0;
5616 u16 status;
5617
5618 status = rtl_get_events(tp);
5619 rtl_ack_events(tp, status & ~tp->event_slow);
5620
5621 if (status & RTL_EVENT_NAPI_RX)
5622 work_done = rtl_rx(dev, tp, (u32) budget);
5623
5624 if (status & RTL_EVENT_NAPI_TX)
5625 rtl_tx(dev, tp);
5626
5627 if (status & tp->event_slow) {
5628 enable_mask &= ~tp->event_slow;
5629
5630 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5631 }
5632
5633 if (work_done < budget) {
5634 napi_complete(napi);
5635
5636 rtl_irq_enable(tp, enable_mask);
5637 mmiowb();
5638 }
5639
5640 return work_done;
5641 }
5642
5643 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5644 {
5645 struct rtl8169_private *tp = netdev_priv(dev);
5646
5647 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5648 return;
5649
5650 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5651 RTL_W32(RxMissed, 0);
5652 }
5653
5654 static void rtl8169_down(struct net_device *dev)
5655 {
5656 struct rtl8169_private *tp = netdev_priv(dev);
5657 void __iomem *ioaddr = tp->mmio_addr;
5658
5659 del_timer_sync(&tp->timer);
5660
5661 napi_disable(&tp->napi);
5662 netif_stop_queue(dev);
5663
5664 rtl8169_hw_reset(tp);
5665 /*
5666 * At this point device interrupts can not be enabled in any function,
5667 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5668 * and napi is disabled (rtl8169_poll).
5669 */
5670 rtl8169_rx_missed(dev, ioaddr);
5671
5672 /* Give a racing hard_start_xmit a few cycles to complete. */
5673 synchronize_sched();
5674
5675 rtl8169_tx_clear(tp);
5676
5677 rtl8169_rx_clear(tp);
5678
5679 rtl_pll_power_down(tp);
5680 }
5681
5682 static int rtl8169_close(struct net_device *dev)
5683 {
5684 struct rtl8169_private *tp = netdev_priv(dev);
5685 struct pci_dev *pdev = tp->pci_dev;
5686
5687 pm_runtime_get_sync(&pdev->dev);
5688
5689 /* Update counters before going down */
5690 rtl8169_update_counters(dev);
5691
5692 rtl_lock_work(tp);
5693 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5694
5695 rtl8169_down(dev);
5696 rtl_unlock_work(tp);
5697
5698 free_irq(dev->irq, dev);
5699
5700 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5701 tp->RxPhyAddr);
5702 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5703 tp->TxPhyAddr);
5704 tp->TxDescArray = NULL;
5705 tp->RxDescArray = NULL;
5706
5707 pm_runtime_put_sync(&pdev->dev);
5708
5709 return 0;
5710 }
5711
5712 #ifdef CONFIG_NET_POLL_CONTROLLER
5713 static void rtl8169_netpoll(struct net_device *dev)
5714 {
5715 struct rtl8169_private *tp = netdev_priv(dev);
5716
5717 rtl8169_interrupt(tp->pci_dev->irq, dev);
5718 }
5719 #endif
5720
5721 static int rtl_open(struct net_device *dev)
5722 {
5723 struct rtl8169_private *tp = netdev_priv(dev);
5724 void __iomem *ioaddr = tp->mmio_addr;
5725 struct pci_dev *pdev = tp->pci_dev;
5726 int retval = -ENOMEM;
5727
5728 pm_runtime_get_sync(&pdev->dev);
5729
5730 /*
5731 * Rx and Tx desscriptors needs 256 bytes alignment.
5732 * dma_alloc_coherent provides more.
5733 */
5734 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5735 &tp->TxPhyAddr, GFP_KERNEL);
5736 if (!tp->TxDescArray)
5737 goto err_pm_runtime_put;
5738
5739 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5740 &tp->RxPhyAddr, GFP_KERNEL);
5741 if (!tp->RxDescArray)
5742 goto err_free_tx_0;
5743
5744 retval = rtl8169_init_ring(dev);
5745 if (retval < 0)
5746 goto err_free_rx_1;
5747
5748 INIT_WORK(&tp->wk.work, rtl_task);
5749
5750 smp_mb();
5751
5752 rtl_request_firmware(tp);
5753
5754 retval = request_irq(dev->irq, rtl8169_interrupt,
5755 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5756 dev->name, dev);
5757 if (retval < 0)
5758 goto err_release_fw_2;
5759
5760 rtl_lock_work(tp);
5761
5762 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5763
5764 napi_enable(&tp->napi);
5765
5766 rtl8169_init_phy(dev, tp);
5767
5768 __rtl8169_set_features(dev, dev->features);
5769
5770 rtl_pll_power_up(tp);
5771
5772 rtl_hw_start(dev);
5773
5774 netif_start_queue(dev);
5775
5776 rtl_unlock_work(tp);
5777
5778 tp->saved_wolopts = 0;
5779 pm_runtime_put_noidle(&pdev->dev);
5780
5781 rtl8169_check_link_status(dev, tp, ioaddr);
5782 out:
5783 return retval;
5784
5785 err_release_fw_2:
5786 rtl_release_firmware(tp);
5787 rtl8169_rx_clear(tp);
5788 err_free_rx_1:
5789 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5790 tp->RxPhyAddr);
5791 tp->RxDescArray = NULL;
5792 err_free_tx_0:
5793 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5794 tp->TxPhyAddr);
5795 tp->TxDescArray = NULL;
5796 err_pm_runtime_put:
5797 pm_runtime_put_noidle(&pdev->dev);
5798 goto out;
5799 }
5800
5801 static struct rtnl_link_stats64 *
5802 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5803 {
5804 struct rtl8169_private *tp = netdev_priv(dev);
5805 void __iomem *ioaddr = tp->mmio_addr;
5806 unsigned int start;
5807
5808 if (netif_running(dev))
5809 rtl8169_rx_missed(dev, ioaddr);
5810
5811 do {
5812 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5813 stats->rx_packets = tp->rx_stats.packets;
5814 stats->rx_bytes = tp->rx_stats.bytes;
5815 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5816
5817
5818 do {
5819 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5820 stats->tx_packets = tp->tx_stats.packets;
5821 stats->tx_bytes = tp->tx_stats.bytes;
5822 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5823
5824 stats->rx_dropped = dev->stats.rx_dropped;
5825 stats->tx_dropped = dev->stats.tx_dropped;
5826 stats->rx_length_errors = dev->stats.rx_length_errors;
5827 stats->rx_errors = dev->stats.rx_errors;
5828 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5829 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5830 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5831
5832 return stats;
5833 }
5834
5835 static void rtl8169_net_suspend(struct net_device *dev)
5836 {
5837 struct rtl8169_private *tp = netdev_priv(dev);
5838
5839 if (!netif_running(dev))
5840 return;
5841
5842 netif_device_detach(dev);
5843 netif_stop_queue(dev);
5844
5845 rtl_lock_work(tp);
5846 napi_disable(&tp->napi);
5847 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5848 rtl_unlock_work(tp);
5849
5850 rtl_pll_power_down(tp);
5851 }
5852
5853 #ifdef CONFIG_PM
5854
5855 static int rtl8169_suspend(struct device *device)
5856 {
5857 struct pci_dev *pdev = to_pci_dev(device);
5858 struct net_device *dev = pci_get_drvdata(pdev);
5859
5860 rtl8169_net_suspend(dev);
5861
5862 return 0;
5863 }
5864
5865 static void __rtl8169_resume(struct net_device *dev)
5866 {
5867 struct rtl8169_private *tp = netdev_priv(dev);
5868
5869 netif_device_attach(dev);
5870
5871 rtl_pll_power_up(tp);
5872
5873 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5874
5875 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5876 }
5877
5878 static int rtl8169_resume(struct device *device)
5879 {
5880 struct pci_dev *pdev = to_pci_dev(device);
5881 struct net_device *dev = pci_get_drvdata(pdev);
5882 struct rtl8169_private *tp = netdev_priv(dev);
5883
5884 rtl8169_init_phy(dev, tp);
5885
5886 if (netif_running(dev))
5887 __rtl8169_resume(dev);
5888
5889 return 0;
5890 }
5891
5892 static int rtl8169_runtime_suspend(struct device *device)
5893 {
5894 struct pci_dev *pdev = to_pci_dev(device);
5895 struct net_device *dev = pci_get_drvdata(pdev);
5896 struct rtl8169_private *tp = netdev_priv(dev);
5897
5898 if (!tp->TxDescArray)
5899 return 0;
5900
5901 rtl_lock_work(tp);
5902 tp->saved_wolopts = __rtl8169_get_wol(tp);
5903 __rtl8169_set_wol(tp, WAKE_ANY);
5904 rtl_unlock_work(tp);
5905
5906 rtl8169_net_suspend(dev);
5907
5908 return 0;
5909 }
5910
5911 static int rtl8169_runtime_resume(struct device *device)
5912 {
5913 struct pci_dev *pdev = to_pci_dev(device);
5914 struct net_device *dev = pci_get_drvdata(pdev);
5915 struct rtl8169_private *tp = netdev_priv(dev);
5916
5917 if (!tp->TxDescArray)
5918 return 0;
5919
5920 rtl_lock_work(tp);
5921 __rtl8169_set_wol(tp, tp->saved_wolopts);
5922 tp->saved_wolopts = 0;
5923 rtl_unlock_work(tp);
5924
5925 rtl8169_init_phy(dev, tp);
5926
5927 __rtl8169_resume(dev);
5928
5929 return 0;
5930 }
5931
5932 static int rtl8169_runtime_idle(struct device *device)
5933 {
5934 struct pci_dev *pdev = to_pci_dev(device);
5935 struct net_device *dev = pci_get_drvdata(pdev);
5936 struct rtl8169_private *tp = netdev_priv(dev);
5937
5938 return tp->TxDescArray ? -EBUSY : 0;
5939 }
5940
5941 static const struct dev_pm_ops rtl8169_pm_ops = {
5942 .suspend = rtl8169_suspend,
5943 .resume = rtl8169_resume,
5944 .freeze = rtl8169_suspend,
5945 .thaw = rtl8169_resume,
5946 .poweroff = rtl8169_suspend,
5947 .restore = rtl8169_resume,
5948 .runtime_suspend = rtl8169_runtime_suspend,
5949 .runtime_resume = rtl8169_runtime_resume,
5950 .runtime_idle = rtl8169_runtime_idle,
5951 };
5952
5953 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5954
5955 #else /* !CONFIG_PM */
5956
5957 #define RTL8169_PM_OPS NULL
5958
5959 #endif /* !CONFIG_PM */
5960
5961 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5962 {
5963 void __iomem *ioaddr = tp->mmio_addr;
5964
5965 /* WoL fails with 8168b when the receiver is disabled. */
5966 switch (tp->mac_version) {
5967 case RTL_GIGA_MAC_VER_11:
5968 case RTL_GIGA_MAC_VER_12:
5969 case RTL_GIGA_MAC_VER_17:
5970 pci_clear_master(tp->pci_dev);
5971
5972 RTL_W8(ChipCmd, CmdRxEnb);
5973 /* PCI commit */
5974 RTL_R8(ChipCmd);
5975 break;
5976 default:
5977 break;
5978 }
5979 }
5980
5981 static void rtl_shutdown(struct pci_dev *pdev)
5982 {
5983 struct net_device *dev = pci_get_drvdata(pdev);
5984 struct rtl8169_private *tp = netdev_priv(dev);
5985 struct device *d = &pdev->dev;
5986
5987 pm_runtime_get_sync(d);
5988
5989 rtl8169_net_suspend(dev);
5990
5991 /* Restore original MAC address */
5992 rtl_rar_set(tp, dev->perm_addr);
5993
5994 rtl8169_hw_reset(tp);
5995
5996 if (system_state == SYSTEM_POWER_OFF) {
5997 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5998 rtl_wol_suspend_quirk(tp);
5999 rtl_wol_shutdown_quirk(tp);
6000 }
6001
6002 pci_wake_from_d3(pdev, true);
6003 pci_set_power_state(pdev, PCI_D3hot);
6004 }
6005
6006 pm_runtime_put_noidle(d);
6007 }
6008
6009 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6010 {
6011 struct net_device *dev = pci_get_drvdata(pdev);
6012 struct rtl8169_private *tp = netdev_priv(dev);
6013
6014 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6015 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6016 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6017 rtl8168_driver_stop(tp);
6018 }
6019
6020 cancel_work_sync(&tp->wk.work);
6021
6022 unregister_netdev(dev);
6023
6024 rtl_release_firmware(tp);
6025
6026 if (pci_dev_run_wake(pdev))
6027 pm_runtime_get_noresume(&pdev->dev);
6028
6029 /* restore original MAC address */
6030 rtl_rar_set(tp, dev->perm_addr);
6031
6032 rtl_disable_msi(pdev, tp);
6033 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6034 pci_set_drvdata(pdev, NULL);
6035 }
6036
6037 static const struct net_device_ops rtl_netdev_ops = {
6038 .ndo_open = rtl_open,
6039 .ndo_stop = rtl8169_close,
6040 .ndo_get_stats64 = rtl8169_get_stats64,
6041 .ndo_start_xmit = rtl8169_start_xmit,
6042 .ndo_tx_timeout = rtl8169_tx_timeout,
6043 .ndo_validate_addr = eth_validate_addr,
6044 .ndo_change_mtu = rtl8169_change_mtu,
6045 .ndo_fix_features = rtl8169_fix_features,
6046 .ndo_set_features = rtl8169_set_features,
6047 .ndo_set_mac_address = rtl_set_mac_address,
6048 .ndo_do_ioctl = rtl8169_ioctl,
6049 .ndo_set_rx_mode = rtl_set_rx_mode,
6050 #ifdef CONFIG_NET_POLL_CONTROLLER
6051 .ndo_poll_controller = rtl8169_netpoll,
6052 #endif
6053
6054 };
6055
6056 static int __devinit
6057 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6058 {
6059 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6060 const unsigned int region = cfg->region;
6061 struct rtl8169_private *tp;
6062 struct mii_if_info *mii;
6063 struct net_device *dev;
6064 void __iomem *ioaddr;
6065 int chipset, i;
6066 int rc;
6067
6068 if (netif_msg_drv(&debug)) {
6069 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6070 MODULENAME, RTL8169_VERSION);
6071 }
6072
6073 dev = alloc_etherdev(sizeof (*tp));
6074 if (!dev) {
6075 rc = -ENOMEM;
6076 goto out;
6077 }
6078
6079 SET_NETDEV_DEV(dev, &pdev->dev);
6080 dev->netdev_ops = &rtl_netdev_ops;
6081 tp = netdev_priv(dev);
6082 tp->dev = dev;
6083 tp->pci_dev = pdev;
6084 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6085
6086 mii = &tp->mii;
6087 mii->dev = dev;
6088 mii->mdio_read = rtl_mdio_read;
6089 mii->mdio_write = rtl_mdio_write;
6090 mii->phy_id_mask = 0x1f;
6091 mii->reg_num_mask = 0x1f;
6092 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6093
6094 /* disable ASPM completely as that cause random device stop working
6095 * problems as well as full system hangs for some PCIe devices users */
6096 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6097 PCIE_LINK_STATE_CLKPM);
6098
6099 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6100 rc = pci_enable_device(pdev);
6101 if (rc < 0) {
6102 netif_err(tp, probe, dev, "enable failure\n");
6103 goto err_out_free_dev_1;
6104 }
6105
6106 if (pci_set_mwi(pdev) < 0)
6107 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6108
6109 /* make sure PCI base addr 1 is MMIO */
6110 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6111 netif_err(tp, probe, dev,
6112 "region #%d not an MMIO resource, aborting\n",
6113 region);
6114 rc = -ENODEV;
6115 goto err_out_mwi_2;
6116 }
6117
6118 /* check for weird/broken PCI region reporting */
6119 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6120 netif_err(tp, probe, dev,
6121 "Invalid PCI region size(s), aborting\n");
6122 rc = -ENODEV;
6123 goto err_out_mwi_2;
6124 }
6125
6126 rc = pci_request_regions(pdev, MODULENAME);
6127 if (rc < 0) {
6128 netif_err(tp, probe, dev, "could not request regions\n");
6129 goto err_out_mwi_2;
6130 }
6131
6132 tp->cp_cmd = RxChkSum;
6133
6134 if ((sizeof(dma_addr_t) > 4) &&
6135 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6136 tp->cp_cmd |= PCIDAC;
6137 dev->features |= NETIF_F_HIGHDMA;
6138 } else {
6139 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6140 if (rc < 0) {
6141 netif_err(tp, probe, dev, "DMA configuration failed\n");
6142 goto err_out_free_res_3;
6143 }
6144 }
6145
6146 /* ioremap MMIO region */
6147 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6148 if (!ioaddr) {
6149 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6150 rc = -EIO;
6151 goto err_out_free_res_3;
6152 }
6153 tp->mmio_addr = ioaddr;
6154
6155 if (!pci_is_pcie(pdev))
6156 netif_info(tp, probe, dev, "not PCI Express\n");
6157
6158 /* Identify chip attached to board */
6159 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6160
6161 rtl_init_rxcfg(tp);
6162
6163 rtl_irq_disable(tp);
6164
6165 rtl_hw_reset(tp);
6166
6167 rtl_ack_events(tp, 0xffff);
6168
6169 pci_set_master(pdev);
6170
6171 /*
6172 * Pretend we are using VLANs; This bypasses a nasty bug where
6173 * Interrupts stop flowing on high load on 8110SCd controllers.
6174 */
6175 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6176 tp->cp_cmd |= RxVlan;
6177
6178 rtl_init_mdio_ops(tp);
6179 rtl_init_pll_power_ops(tp);
6180 rtl_init_jumbo_ops(tp);
6181
6182 rtl8169_print_mac_version(tp);
6183
6184 chipset = tp->mac_version;
6185 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6186
6187 RTL_W8(Cfg9346, Cfg9346_Unlock);
6188 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6189 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6190 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6191 tp->features |= RTL_FEATURE_WOL;
6192 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6193 tp->features |= RTL_FEATURE_WOL;
6194 tp->features |= rtl_try_msi(tp, cfg);
6195 RTL_W8(Cfg9346, Cfg9346_Lock);
6196
6197 if (rtl_tbi_enabled(tp)) {
6198 tp->set_speed = rtl8169_set_speed_tbi;
6199 tp->get_settings = rtl8169_gset_tbi;
6200 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6201 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6202 tp->link_ok = rtl8169_tbi_link_ok;
6203 tp->do_ioctl = rtl_tbi_ioctl;
6204 } else {
6205 tp->set_speed = rtl8169_set_speed_xmii;
6206 tp->get_settings = rtl8169_gset_xmii;
6207 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6208 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6209 tp->link_ok = rtl8169_xmii_link_ok;
6210 tp->do_ioctl = rtl_xmii_ioctl;
6211 }
6212
6213 mutex_init(&tp->wk.mutex);
6214
6215 /* Get MAC address */
6216 for (i = 0; i < ETH_ALEN; i++)
6217 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6218 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6219
6220 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6221 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6222 dev->irq = pdev->irq;
6223 dev->base_addr = (unsigned long) ioaddr;
6224
6225 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6226
6227 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6228 * properly for all devices */
6229 dev->features |= NETIF_F_RXCSUM |
6230 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6231
6232 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6233 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6234 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6235 NETIF_F_HIGHDMA;
6236
6237 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6238 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6239 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6240
6241 dev->hw_features |= NETIF_F_RXALL;
6242 dev->hw_features |= NETIF_F_RXFCS;
6243
6244 tp->hw_start = cfg->hw_start;
6245 tp->event_slow = cfg->event_slow;
6246
6247 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6248 ~(RxBOVF | RxFOVF) : ~0;
6249
6250 init_timer(&tp->timer);
6251 tp->timer.data = (unsigned long) dev;
6252 tp->timer.function = rtl8169_phy_timer;
6253
6254 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6255
6256 rc = register_netdev(dev);
6257 if (rc < 0)
6258 goto err_out_msi_4;
6259
6260 pci_set_drvdata(pdev, dev);
6261
6262 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
6263 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
6264 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
6265 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6266 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6267 "tx checksumming: %s]\n",
6268 rtl_chip_infos[chipset].jumbo_max,
6269 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6270 }
6271
6272 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6273 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6274 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6275 rtl8168_driver_start(tp);
6276 }
6277
6278 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6279
6280 if (pci_dev_run_wake(pdev))
6281 pm_runtime_put_noidle(&pdev->dev);
6282
6283 netif_carrier_off(dev);
6284
6285 out:
6286 return rc;
6287
6288 err_out_msi_4:
6289 rtl_disable_msi(pdev, tp);
6290 iounmap(ioaddr);
6291 err_out_free_res_3:
6292 pci_release_regions(pdev);
6293 err_out_mwi_2:
6294 pci_clear_mwi(pdev);
6295 pci_disable_device(pdev);
6296 err_out_free_dev_1:
6297 free_netdev(dev);
6298 goto out;
6299 }
6300
6301 static struct pci_driver rtl8169_pci_driver = {
6302 .name = MODULENAME,
6303 .id_table = rtl8169_pci_tbl,
6304 .probe = rtl_init_one,
6305 .remove = __devexit_p(rtl_remove_one),
6306 .shutdown = rtl_shutdown,
6307 .driver.pm = RTL8169_PM_OPS,
6308 };
6309
6310 static int __init rtl8169_init_module(void)
6311 {
6312 return pci_register_driver(&rtl8169_pci_driver);
6313 }
6314
6315 static void __exit rtl8169_cleanup_module(void)
6316 {
6317 pci_unregister_driver(&rtl8169_pci_driver);
6318 }
6319
6320 module_init(rtl8169_init_module);
6321 module_exit(rtl8169_cleanup_module);
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