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wm97xx_battery: Use DEFINE_MUTEX() for work_lock
[linux-2.6.git] / drivers / spi / spi-pl022.c
blobf103e470cb6362e248a264576e457e03f0ab5409
1 /*
2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
3 *
4 * Copyright (C) 2008-2009 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 *
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/workqueue.h>
33 #include <linux/delay.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/amba/bus.h>
37 #include <linux/amba/pl022.h>
38 #include <linux/io.h>
39 #include <linux/slab.h>
40 #include <linux/dmaengine.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/scatterlist.h>
43 #include <linux/pm_runtime.h>
44
45 /*
46 * This macro is used to define some register default values.
47 * reg is masked with mask, the OR:ed with an (again masked)
48 * val shifted sb steps to the left.
49 */
50 #define SSP_WRITE_BITS(reg, val, mask, sb) \
51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
52
53 /*
54 * This macro is also used to define some default values.
55 * It will just shift val by sb steps to the left and mask
56 * the result with mask.
57 */
58 #define GEN_MASK_BITS(val, mask, sb) \
59 (((val)<<(sb)) & (mask))
60
61 #define DRIVE_TX 0
62 #define DO_NOT_DRIVE_TX 1
63
64 #define DO_NOT_QUEUE_DMA 0
65 #define QUEUE_DMA 1
66
67 #define RX_TRANSFER 1
68 #define TX_TRANSFER 2
69
70 /*
71 * Macros to access SSP Registers with their offsets
72 */
73 #define SSP_CR0(r) (r + 0x000)
74 #define SSP_CR1(r) (r + 0x004)
75 #define SSP_DR(r) (r + 0x008)
76 #define SSP_SR(r) (r + 0x00C)
77 #define SSP_CPSR(r) (r + 0x010)
78 #define SSP_IMSC(r) (r + 0x014)
79 #define SSP_RIS(r) (r + 0x018)
80 #define SSP_MIS(r) (r + 0x01C)
81 #define SSP_ICR(r) (r + 0x020)
82 #define SSP_DMACR(r) (r + 0x024)
83 #define SSP_ITCR(r) (r + 0x080)
84 #define SSP_ITIP(r) (r + 0x084)
85 #define SSP_ITOP(r) (r + 0x088)
86 #define SSP_TDR(r) (r + 0x08C)
87
88 #define SSP_PID0(r) (r + 0xFE0)
89 #define SSP_PID1(r) (r + 0xFE4)
90 #define SSP_PID2(r) (r + 0xFE8)
91 #define SSP_PID3(r) (r + 0xFEC)
92
93 #define SSP_CID0(r) (r + 0xFF0)
94 #define SSP_CID1(r) (r + 0xFF4)
95 #define SSP_CID2(r) (r + 0xFF8)
96 #define SSP_CID3(r) (r + 0xFFC)
97
98 /*
99 * SSP Control Register 0 - SSP_CR0
100 */
101 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
102 #define SSP_CR0_MASK_FRF (0x3UL << 4)
103 #define SSP_CR0_MASK_SPO (0x1UL << 6)
104 #define SSP_CR0_MASK_SPH (0x1UL << 7)
105 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
106
107 /*
108 * The ST version of this block moves som bits
109 * in SSP_CR0 and extends it to 32 bits
110 */
111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
115
116 /*
117 * SSP Control Register 0 - SSP_CR1
118 */
119 #define SSP_CR1_MASK_LBM (0x1UL << 0)
120 #define SSP_CR1_MASK_SSE (0x1UL << 1)
121 #define SSP_CR1_MASK_MS (0x1UL << 2)
122 #define SSP_CR1_MASK_SOD (0x1UL << 3)
123
124 /*
125 * The ST version of this block adds some bits
126 * in SSP_CR1
127 */
128 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
129 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
130 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
131 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
132 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
133 /* This one is only in the PL023 variant */
134 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
135
136 /*
137 * SSP Status Register - SSP_SR
138 */
139 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
140 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
141 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
142 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
143 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
144
145 /*
146 * SSP Clock Prescale Register - SSP_CPSR
147 */
148 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
149
150 /*
151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
152 */
153 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
154 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
155 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
156 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
157
158 /*
159 * SSP Raw Interrupt Status Register - SSP_RIS
160 */
161 /* Receive Overrun Raw Interrupt status */
162 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
163 /* Receive Timeout Raw Interrupt status */
164 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
165 /* Receive FIFO Raw Interrupt status */
166 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
167 /* Transmit FIFO Raw Interrupt status */
168 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
169
170 /*
171 * SSP Masked Interrupt Status Register - SSP_MIS
172 */
173 /* Receive Overrun Masked Interrupt status */
174 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
175 /* Receive Timeout Masked Interrupt status */
176 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
177 /* Receive FIFO Masked Interrupt status */
178 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
179 /* Transmit FIFO Masked Interrupt status */
180 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
181
182 /*
183 * SSP Interrupt Clear Register - SSP_ICR
184 */
185 /* Receive Overrun Raw Clear Interrupt bit */
186 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
187 /* Receive Timeout Clear Interrupt bit */
188 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
189
190 /*
191 * SSP DMA Control Register - SSP_DMACR
192 */
193 /* Receive DMA Enable bit */
194 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
195 /* Transmit DMA Enable bit */
196 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
197
198 /*
199 * SSP Integration Test control Register - SSP_ITCR
200 */
201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
203
204 /*
205 * SSP Integration Test Input Register - SSP_ITIP
206 */
207 #define ITIP_MASK_SSPRXD (0x1UL << 0)
208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
210 #define ITIP_MASK_RXDMAC (0x1UL << 3)
211 #define ITIP_MASK_TXDMAC (0x1UL << 4)
212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
213
214 /*
215 * SSP Integration Test output Register - SSP_ITOP
216 */
217 #define ITOP_MASK_SSPTXD (0x1UL << 0)
218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
220 #define ITOP_MASK_SSPOEn (0x1UL << 3)
221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
222 #define ITOP_MASK_RORINTR (0x1UL << 5)
223 #define ITOP_MASK_RTINTR (0x1UL << 6)
224 #define ITOP_MASK_RXINTR (0x1UL << 7)
225 #define ITOP_MASK_TXINTR (0x1UL << 8)
226 #define ITOP_MASK_INTR (0x1UL << 9)
227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
231
232 /*
233 * SSP Test Data Register - SSP_TDR
234 */
235 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
236
237 /*
238 * Message State
239 * we use the spi_message.state (void *) pointer to
240 * hold a single state value, that's why all this
241 * (void *) casting is done here.
242 */
243 #define STATE_START ((void *) 0)
244 #define STATE_RUNNING ((void *) 1)
245 #define STATE_DONE ((void *) 2)
246 #define STATE_ERROR ((void *) -1)
247
248 /*
249 * SSP State - Whether Enabled or Disabled
250 */
251 #define SSP_DISABLED (0)
252 #define SSP_ENABLED (1)
253
254 /*
255 * SSP DMA State - Whether DMA Enabled or Disabled
256 */
257 #define SSP_DMA_DISABLED (0)
258 #define SSP_DMA_ENABLED (1)
259
260 /*
261 * SSP Clock Defaults
262 */
263 #define SSP_DEFAULT_CLKRATE 0x2
264 #define SSP_DEFAULT_PRESCALE 0x40
265
266 /*
267 * SSP Clock Parameter ranges
268 */
269 #define CPSDVR_MIN 0x02
270 #define CPSDVR_MAX 0xFE
271 #define SCR_MIN 0x00
272 #define SCR_MAX 0xFF
273
274 /*
275 * SSP Interrupt related Macros
276 */
277 #define DEFAULT_SSP_REG_IMSC 0x0UL
278 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
279 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
280
281 #define CLEAR_ALL_INTERRUPTS 0x3
282
283 #define SPI_POLLING_TIMEOUT 1000
284
285 /*
286 * The type of reading going on on this chip
287 */
288 enum ssp_reading {
289 READING_NULL,
290 READING_U8,
291 READING_U16,
292 READING_U32
293 };
294
295 /**
296 * The type of writing going on on this chip
297 */
298 enum ssp_writing {
299 WRITING_NULL,
300 WRITING_U8,
301 WRITING_U16,
302 WRITING_U32
303 };
304
305 /**
306 * struct vendor_data - vendor-specific config parameters
307 * for PL022 derivates
308 * @fifodepth: depth of FIFOs (both)
309 * @max_bpw: maximum number of bits per word
310 * @unidir: supports unidirection transfers
311 * @extended_cr: 32 bit wide control register 0 with extra
312 * features and extra features in CR1 as found in the ST variants
313 * @pl023: supports a subset of the ST extensions called "PL023"
314 */
315 struct vendor_data {
316 int fifodepth;
317 int max_bpw;
318 bool unidir;
319 bool extended_cr;
320 bool pl023;
321 bool loopback;
322 };
323
324 /**
325 * struct pl022 - This is the private SSP driver data structure
326 * @adev: AMBA device model hookup
327 * @vendor: vendor data for the IP block
328 * @phybase: the physical memory where the SSP device resides
329 * @virtbase: the virtual memory where the SSP is mapped
330 * @clk: outgoing clock "SPICLK" for the SPI bus
331 * @master: SPI framework hookup
332 * @master_info: controller-specific data from machine setup
333 * @workqueue: a workqueue on which any spi_message request is queued
334 * @pump_messages: work struct for scheduling work to the workqueue
335 * @queue_lock: spinlock to syncronise access to message queue
336 * @queue: message queue
337 * @busy: workqueue is busy
338 * @running: workqueue is running
339 * @pump_transfers: Tasklet used in Interrupt Transfer mode
340 * @cur_msg: Pointer to current spi_message being processed
341 * @cur_transfer: Pointer to current spi_transfer
342 * @cur_chip: pointer to current clients chip(assigned from controller_state)
343 * @tx: current position in TX buffer to be read
344 * @tx_end: end position in TX buffer to be read
345 * @rx: current position in RX buffer to be written
346 * @rx_end: end position in RX buffer to be written
347 * @read: the type of read currently going on
348 * @write: the type of write currently going on
349 * @exp_fifo_level: expected FIFO level
350 * @dma_rx_channel: optional channel for RX DMA
351 * @dma_tx_channel: optional channel for TX DMA
352 * @sgt_rx: scattertable for the RX transfer
353 * @sgt_tx: scattertable for the TX transfer
354 * @dummypage: a dummy page used for driving data on the bus with DMA
355 */
356 struct pl022 {
357 struct amba_device *adev;
358 struct vendor_data *vendor;
359 resource_size_t phybase;
360 void __iomem *virtbase;
361 struct clk *clk;
362 struct spi_master *master;
363 struct pl022_ssp_controller *master_info;
364 /* Driver message queue */
365 struct workqueue_struct *workqueue;
366 struct work_struct pump_messages;
367 spinlock_t queue_lock;
368 struct list_head queue;
369 bool busy;
370 bool running;
371 /* Message transfer pump */
372 struct tasklet_struct pump_transfers;
373 struct spi_message *cur_msg;
374 struct spi_transfer *cur_transfer;
375 struct chip_data *cur_chip;
376 void *tx;
377 void *tx_end;
378 void *rx;
379 void *rx_end;
380 enum ssp_reading read;
381 enum ssp_writing write;
382 u32 exp_fifo_level;
383 enum ssp_rx_level_trig rx_lev_trig;
384 enum ssp_tx_level_trig tx_lev_trig;
385 /* DMA settings */
386 #ifdef CONFIG_DMA_ENGINE
387 struct dma_chan *dma_rx_channel;
388 struct dma_chan *dma_tx_channel;
389 struct sg_table sgt_rx;
390 struct sg_table sgt_tx;
391 char *dummypage;
392 #endif
393 };
394
395 /**
396 * struct chip_data - To maintain runtime state of SSP for each client chip
397 * @cr0: Value of control register CR0 of SSP - on later ST variants this
398 * register is 32 bits wide rather than just 16
399 * @cr1: Value of control register CR1 of SSP
400 * @dmacr: Value of DMA control Register of SSP
401 * @cpsr: Value of Clock prescale register
402 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
403 * @enable_dma: Whether to enable DMA or not
404 * @read: function ptr to be used to read when doing xfer for this chip
405 * @write: function ptr to be used to write when doing xfer for this chip
406 * @cs_control: chip select callback provided by chip
407 * @xfer_type: polling/interrupt/DMA
408 *
409 * Runtime state of the SSP controller, maintained per chip,
410 * This would be set according to the current message that would be served
411 */
412 struct chip_data {
413 u32 cr0;
414 u16 cr1;
415 u16 dmacr;
416 u16 cpsr;
417 u8 n_bytes;
418 bool enable_dma;
419 enum ssp_reading read;
420 enum ssp_writing write;
421 void (*cs_control) (u32 command);
422 int xfer_type;
423 };
424
425 /**
426 * null_cs_control - Dummy chip select function
427 * @command: select/delect the chip
428 *
429 * If no chip select function is provided by client this is used as dummy
430 * chip select
431 */
432 static void null_cs_control(u32 command)
433 {
434 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
435 }
436
437 /**
438 * giveback - current spi_message is over, schedule next message and call
439 * callback of this message. Assumes that caller already
440 * set message->status; dma and pio irqs are blocked
441 * @pl022: SSP driver private data structure
442 */
443 static void giveback(struct pl022 *pl022)
444 {
445 struct spi_transfer *last_transfer;
446 unsigned long flags;
447 struct spi_message *msg;
448 void (*curr_cs_control) (u32 command);
449
450 /*
451 * This local reference to the chip select function
452 * is needed because we set curr_chip to NULL
453 * as a step toward termininating the message.
454 */
455 curr_cs_control = pl022->cur_chip->cs_control;
456 spin_lock_irqsave(&pl022->queue_lock, flags);
457 msg = pl022->cur_msg;
458 pl022->cur_msg = NULL;
459 pl022->cur_transfer = NULL;
460 pl022->cur_chip = NULL;
461 queue_work(pl022->workqueue, &pl022->pump_messages);
462 spin_unlock_irqrestore(&pl022->queue_lock, flags);
463
464 last_transfer = list_entry(msg->transfers.prev,
465 struct spi_transfer,
466 transfer_list);
467
468 /* Delay if requested before any change in chip select */
469 if (last_transfer->delay_usecs)
470 /*
471 * FIXME: This runs in interrupt context.
472 * Is this really smart?
473 */
474 udelay(last_transfer->delay_usecs);
475
476 /*
477 * Drop chip select UNLESS cs_change is true or we are returning
478 * a message with an error, or next message is for another chip
479 */
480 if (!last_transfer->cs_change)
481 curr_cs_control(SSP_CHIP_DESELECT);
482 else {
483 struct spi_message *next_msg;
484
485 /* Holding of cs was hinted, but we need to make sure
486 * the next message is for the same chip. Don't waste
487 * time with the following tests unless this was hinted.
488 *
489 * We cannot postpone this until pump_messages, because
490 * after calling msg->complete (below) the driver that
491 * sent the current message could be unloaded, which
492 * could invalidate the cs_control() callback...
493 */
494
495 /* get a pointer to the next message, if any */
496 spin_lock_irqsave(&pl022->queue_lock, flags);
497 if (list_empty(&pl022->queue))
498 next_msg = NULL;
499 else
500 next_msg = list_entry(pl022->queue.next,
501 struct spi_message, queue);
502 spin_unlock_irqrestore(&pl022->queue_lock, flags);
503
504 /* see if the next and current messages point
505 * to the same chip
506 */
507 if (next_msg && next_msg->spi != msg->spi)
508 next_msg = NULL;
509 if (!next_msg || msg->state == STATE_ERROR)
510 curr_cs_control(SSP_CHIP_DESELECT);
511 }
512 msg->state = NULL;
513 if (msg->complete)
514 msg->complete(msg->context);
515 /* This message is completed, so let's turn off the clocks & power */
516 pm_runtime_put(&pl022->adev->dev);
517 }
518
519 /**
520 * flush - flush the FIFO to reach a clean state
521 * @pl022: SSP driver private data structure
522 */
523 static int flush(struct pl022 *pl022)
524 {
525 unsigned long limit = loops_per_jiffy << 1;
526
527 dev_dbg(&pl022->adev->dev, "flush\n");
528 do {
529 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
530 readw(SSP_DR(pl022->virtbase));
531 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
532
533 pl022->exp_fifo_level = 0;
534
535 return limit;
536 }
537
538 /**
539 * restore_state - Load configuration of current chip
540 * @pl022: SSP driver private data structure
541 */
542 static void restore_state(struct pl022 *pl022)
543 {
544 struct chip_data *chip = pl022->cur_chip;
545
546 if (pl022->vendor->extended_cr)
547 writel(chip->cr0, SSP_CR0(pl022->virtbase));
548 else
549 writew(chip->cr0, SSP_CR0(pl022->virtbase));
550 writew(chip->cr1, SSP_CR1(pl022->virtbase));
551 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
552 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
553 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
554 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
555 }
556
557 /*
558 * Default SSP Register Values
559 */
560 #define DEFAULT_SSP_REG_CR0 ( \
561 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
562 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
563 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
564 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
565 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
566 )
567
568 /* ST versions have slightly different bit layout */
569 #define DEFAULT_SSP_REG_CR0_ST ( \
570 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
571 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
572 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
573 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
574 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
575 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
576 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
577 )
578
579 /* The PL023 version is slightly different again */
580 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
581 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
582 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
583 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
584 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
585 )
586
587 #define DEFAULT_SSP_REG_CR1 ( \
588 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
589 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
590 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
591 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
592 )
593
594 /* ST versions extend this register to use all 16 bits */
595 #define DEFAULT_SSP_REG_CR1_ST ( \
596 DEFAULT_SSP_REG_CR1 | \
597 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
598 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
599 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
600 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
601 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
602 )
603
604 /*
605 * The PL023 variant has further differences: no loopback mode, no microwire
606 * support, and a new clock feedback delay setting.
607 */
608 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
609 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
610 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
611 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
612 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
613 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
614 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
615 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
616 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
617 )
618
619 #define DEFAULT_SSP_REG_CPSR ( \
620 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
621 )
622
623 #define DEFAULT_SSP_REG_DMACR (\
624 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
625 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
626 )
627
628 /**
629 * load_ssp_default_config - Load default configuration for SSP
630 * @pl022: SSP driver private data structure
631 */
632 static void load_ssp_default_config(struct pl022 *pl022)
633 {
634 if (pl022->vendor->pl023) {
635 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
636 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
637 } else if (pl022->vendor->extended_cr) {
638 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
640 } else {
641 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
643 }
644 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
645 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
646 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
647 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
648 }
649
650 /**
651 * This will write to TX and read from RX according to the parameters
652 * set in pl022.
653 */
654 static void readwriter(struct pl022 *pl022)
655 {
656
657 /*
658 * The FIFO depth is different between primecell variants.
659 * I believe filling in too much in the FIFO might cause
660 * errons in 8bit wide transfers on ARM variants (just 8 words
661 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
662 *
663 * To prevent this issue, the TX FIFO is only filled to the
664 * unused RX FIFO fill length, regardless of what the TX
665 * FIFO status flag indicates.
666 */
667 dev_dbg(&pl022->adev->dev,
668 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
669 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
670
671 /* Read as much as you can */
672 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
673 && (pl022->rx < pl022->rx_end)) {
674 switch (pl022->read) {
675 case READING_NULL:
676 readw(SSP_DR(pl022->virtbase));
677 break;
678 case READING_U8:
679 *(u8 *) (pl022->rx) =
680 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
681 break;
682 case READING_U16:
683 *(u16 *) (pl022->rx) =
684 (u16) readw(SSP_DR(pl022->virtbase));
685 break;
686 case READING_U32:
687 *(u32 *) (pl022->rx) =
688 readl(SSP_DR(pl022->virtbase));
689 break;
690 }
691 pl022->rx += (pl022->cur_chip->n_bytes);
692 pl022->exp_fifo_level--;
693 }
694 /*
695 * Write as much as possible up to the RX FIFO size
696 */
697 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
698 && (pl022->tx < pl022->tx_end)) {
699 switch (pl022->write) {
700 case WRITING_NULL:
701 writew(0x0, SSP_DR(pl022->virtbase));
702 break;
703 case WRITING_U8:
704 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
705 break;
706 case WRITING_U16:
707 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
708 break;
709 case WRITING_U32:
710 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
711 break;
712 }
713 pl022->tx += (pl022->cur_chip->n_bytes);
714 pl022->exp_fifo_level++;
715 /*
716 * This inner reader takes care of things appearing in the RX
717 * FIFO as we're transmitting. This will happen a lot since the
718 * clock starts running when you put things into the TX FIFO,
719 * and then things are continuously clocked into the RX FIFO.
720 */
721 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
722 && (pl022->rx < pl022->rx_end)) {
723 switch (pl022->read) {
724 case READING_NULL:
725 readw(SSP_DR(pl022->virtbase));
726 break;
727 case READING_U8:
728 *(u8 *) (pl022->rx) =
729 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
730 break;
731 case READING_U16:
732 *(u16 *) (pl022->rx) =
733 (u16) readw(SSP_DR(pl022->virtbase));
734 break;
735 case READING_U32:
736 *(u32 *) (pl022->rx) =
737 readl(SSP_DR(pl022->virtbase));
738 break;
739 }
740 pl022->rx += (pl022->cur_chip->n_bytes);
741 pl022->exp_fifo_level--;
742 }
743 }
744 /*
745 * When we exit here the TX FIFO should be full and the RX FIFO
746 * should be empty
747 */
748 }
749
750 /**
751 * next_transfer - Move to the Next transfer in the current spi message
752 * @pl022: SSP driver private data structure
753 *
754 * This function moves though the linked list of spi transfers in the
755 * current spi message and returns with the state of current spi
756 * message i.e whether its last transfer is done(STATE_DONE) or
757 * Next transfer is ready(STATE_RUNNING)
758 */
759 static void *next_transfer(struct pl022 *pl022)
760 {
761 struct spi_message *msg = pl022->cur_msg;
762 struct spi_transfer *trans = pl022->cur_transfer;
763
764 /* Move to next transfer */
765 if (trans->transfer_list.next != &msg->transfers) {
766 pl022->cur_transfer =
767 list_entry(trans->transfer_list.next,
768 struct spi_transfer, transfer_list);
769 return STATE_RUNNING;
770 }
771 return STATE_DONE;
772 }
773
774 /*
775 * This DMA functionality is only compiled in if we have
776 * access to the generic DMA devices/DMA engine.
777 */
778 #ifdef CONFIG_DMA_ENGINE
779 static void unmap_free_dma_scatter(struct pl022 *pl022)
780 {
781 /* Unmap and free the SG tables */
782 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
783 pl022->sgt_tx.nents, DMA_TO_DEVICE);
784 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
785 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
786 sg_free_table(&pl022->sgt_rx);
787 sg_free_table(&pl022->sgt_tx);
788 }
789
790 static void dma_callback(void *data)
791 {
792 struct pl022 *pl022 = data;
793 struct spi_message *msg = pl022->cur_msg;
794
795 BUG_ON(!pl022->sgt_rx.sgl);
796
797 #ifdef VERBOSE_DEBUG
798 /*
799 * Optionally dump out buffers to inspect contents, this is
800 * good if you want to convince yourself that the loopback
801 * read/write contents are the same, when adopting to a new
802 * DMA engine.
803 */
804 {
805 struct scatterlist *sg;
806 unsigned int i;
807
808 dma_sync_sg_for_cpu(&pl022->adev->dev,
809 pl022->sgt_rx.sgl,
810 pl022->sgt_rx.nents,
811 DMA_FROM_DEVICE);
812
813 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
814 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
815 print_hex_dump(KERN_ERR, "SPI RX: ",
816 DUMP_PREFIX_OFFSET,
817 16,
818 1,
819 sg_virt(sg),
820 sg_dma_len(sg),
821 1);
822 }
823 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
824 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
825 print_hex_dump(KERN_ERR, "SPI TX: ",
826 DUMP_PREFIX_OFFSET,
827 16,
828 1,
829 sg_virt(sg),
830 sg_dma_len(sg),
831 1);
832 }
833 }
834 #endif
835
836 unmap_free_dma_scatter(pl022);
837
838 /* Update total bytes transferred */
839 msg->actual_length += pl022->cur_transfer->len;
840 if (pl022->cur_transfer->cs_change)
841 pl022->cur_chip->
842 cs_control(SSP_CHIP_DESELECT);
843
844 /* Move to next transfer */
845 msg->state = next_transfer(pl022);
846 tasklet_schedule(&pl022->pump_transfers);
847 }
848
849 static void setup_dma_scatter(struct pl022 *pl022,
850 void *buffer,
851 unsigned int length,
852 struct sg_table *sgtab)
853 {
854 struct scatterlist *sg;
855 int bytesleft = length;
856 void *bufp = buffer;
857 int mapbytes;
858 int i;
859
860 if (buffer) {
861 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
862 /*
863 * If there are less bytes left than what fits
864 * in the current page (plus page alignment offset)
865 * we just feed in this, else we stuff in as much
866 * as we can.
867 */
868 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
869 mapbytes = bytesleft;
870 else
871 mapbytes = PAGE_SIZE - offset_in_page(bufp);
872 sg_set_page(sg, virt_to_page(bufp),
873 mapbytes, offset_in_page(bufp));
874 bufp += mapbytes;
875 bytesleft -= mapbytes;
876 dev_dbg(&pl022->adev->dev,
877 "set RX/TX target page @ %p, %d bytes, %d left\n",
878 bufp, mapbytes, bytesleft);
879 }
880 } else {
881 /* Map the dummy buffer on every page */
882 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
883 if (bytesleft < PAGE_SIZE)
884 mapbytes = bytesleft;
885 else
886 mapbytes = PAGE_SIZE;
887 sg_set_page(sg, virt_to_page(pl022->dummypage),
888 mapbytes, 0);
889 bytesleft -= mapbytes;
890 dev_dbg(&pl022->adev->dev,
891 "set RX/TX to dummy page %d bytes, %d left\n",
892 mapbytes, bytesleft);
893
894 }
895 }
896 BUG_ON(bytesleft);
897 }
898
899 /**
900 * configure_dma - configures the channels for the next transfer
901 * @pl022: SSP driver's private data structure
902 */
903 static int configure_dma(struct pl022 *pl022)
904 {
905 struct dma_slave_config rx_conf = {
906 .src_addr = SSP_DR(pl022->phybase),
907 .direction = DMA_FROM_DEVICE,
908 };
909 struct dma_slave_config tx_conf = {
910 .dst_addr = SSP_DR(pl022->phybase),
911 .direction = DMA_TO_DEVICE,
912 };
913 unsigned int pages;
914 int ret;
915 int rx_sglen, tx_sglen;
916 struct dma_chan *rxchan = pl022->dma_rx_channel;
917 struct dma_chan *txchan = pl022->dma_tx_channel;
918 struct dma_async_tx_descriptor *rxdesc;
919 struct dma_async_tx_descriptor *txdesc;
920
921 /* Check that the channels are available */
922 if (!rxchan || !txchan)
923 return -ENODEV;
924
925 /*
926 * If supplied, the DMA burstsize should equal the FIFO trigger level.
927 * Notice that the DMA engine uses one-to-one mapping. Since we can
928 * not trigger on 2 elements this needs explicit mapping rather than
929 * calculation.
930 */
931 switch (pl022->rx_lev_trig) {
932 case SSP_RX_1_OR_MORE_ELEM:
933 rx_conf.src_maxburst = 1;
934 break;
935 case SSP_RX_4_OR_MORE_ELEM:
936 rx_conf.src_maxburst = 4;
937 break;
938 case SSP_RX_8_OR_MORE_ELEM:
939 rx_conf.src_maxburst = 8;
940 break;
941 case SSP_RX_16_OR_MORE_ELEM:
942 rx_conf.src_maxburst = 16;
943 break;
944 case SSP_RX_32_OR_MORE_ELEM:
945 rx_conf.src_maxburst = 32;
946 break;
947 default:
948 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
949 break;
950 }
951
952 switch (pl022->tx_lev_trig) {
953 case SSP_TX_1_OR_MORE_EMPTY_LOC:
954 tx_conf.dst_maxburst = 1;
955 break;
956 case SSP_TX_4_OR_MORE_EMPTY_LOC:
957 tx_conf.dst_maxburst = 4;
958 break;
959 case SSP_TX_8_OR_MORE_EMPTY_LOC:
960 tx_conf.dst_maxburst = 8;
961 break;
962 case SSP_TX_16_OR_MORE_EMPTY_LOC:
963 tx_conf.dst_maxburst = 16;
964 break;
965 case SSP_TX_32_OR_MORE_EMPTY_LOC:
966 tx_conf.dst_maxburst = 32;
967 break;
968 default:
969 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
970 break;
971 }
972
973 switch (pl022->read) {
974 case READING_NULL:
975 /* Use the same as for writing */
976 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
977 break;
978 case READING_U8:
979 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
980 break;
981 case READING_U16:
982 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
983 break;
984 case READING_U32:
985 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
986 break;
987 }
988
989 switch (pl022->write) {
990 case WRITING_NULL:
991 /* Use the same as for reading */
992 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
993 break;
994 case WRITING_U8:
995 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
996 break;
997 case WRITING_U16:
998 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
999 break;
1000 case WRITING_U32:
1001 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1002 break;
1003 }
1004
1005 /* SPI pecularity: we need to read and write the same width */
1006 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1007 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1008 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1009 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1010 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1011
1012 dmaengine_slave_config(rxchan, &rx_conf);
1013 dmaengine_slave_config(txchan, &tx_conf);
1014
1015 /* Create sglists for the transfers */
1016 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1017 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1018
1019 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1020 if (ret)
1021 goto err_alloc_rx_sg;
1022
1023 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1024 if (ret)
1025 goto err_alloc_tx_sg;
1026
1027 /* Fill in the scatterlists for the RX+TX buffers */
1028 setup_dma_scatter(pl022, pl022->rx,
1029 pl022->cur_transfer->len, &pl022->sgt_rx);
1030 setup_dma_scatter(pl022, pl022->tx,
1031 pl022->cur_transfer->len, &pl022->sgt_tx);
1032
1033 /* Map DMA buffers */
1034 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1035 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1036 if (!rx_sglen)
1037 goto err_rx_sgmap;
1038
1039 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1040 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1041 if (!tx_sglen)
1042 goto err_tx_sgmap;
1043
1044 /* Send both scatterlists */
1045 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1046 pl022->sgt_rx.sgl,
1047 rx_sglen,
1048 DMA_FROM_DEVICE,
1049 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050 if (!rxdesc)
1051 goto err_rxdesc;
1052
1053 txdesc = txchan->device->device_prep_slave_sg(txchan,
1054 pl022->sgt_tx.sgl,
1055 tx_sglen,
1056 DMA_TO_DEVICE,
1057 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1058 if (!txdesc)
1059 goto err_txdesc;
1060
1061 /* Put the callback on the RX transfer only, that should finish last */
1062 rxdesc->callback = dma_callback;
1063 rxdesc->callback_param = pl022;
1064
1065 /* Submit and fire RX and TX with TX last so we're ready to read! */
1066 dmaengine_submit(rxdesc);
1067 dmaengine_submit(txdesc);
1068 dma_async_issue_pending(rxchan);
1069 dma_async_issue_pending(txchan);
1070
1071 return 0;
1072
1073 err_txdesc:
1074 dmaengine_terminate_all(txchan);
1075 err_rxdesc:
1076 dmaengine_terminate_all(rxchan);
1077 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1078 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1079 err_tx_sgmap:
1080 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1081 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1082 err_rx_sgmap:
1083 sg_free_table(&pl022->sgt_tx);
1084 err_alloc_tx_sg:
1085 sg_free_table(&pl022->sgt_rx);
1086 err_alloc_rx_sg:
1087 return -ENOMEM;
1088 }
1089
1090 static int __init pl022_dma_probe(struct pl022 *pl022)
1091 {
1092 dma_cap_mask_t mask;
1093
1094 /* Try to acquire a generic DMA engine slave channel */
1095 dma_cap_zero(mask);
1096 dma_cap_set(DMA_SLAVE, mask);
1097 /*
1098 * We need both RX and TX channels to do DMA, else do none
1099 * of them.
1100 */
1101 pl022->dma_rx_channel = dma_request_channel(mask,
1102 pl022->master_info->dma_filter,
1103 pl022->master_info->dma_rx_param);
1104 if (!pl022->dma_rx_channel) {
1105 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1106 goto err_no_rxchan;
1107 }
1108
1109 pl022->dma_tx_channel = dma_request_channel(mask,
1110 pl022->master_info->dma_filter,
1111 pl022->master_info->dma_tx_param);
1112 if (!pl022->dma_tx_channel) {
1113 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1114 goto err_no_txchan;
1115 }
1116
1117 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1118 if (!pl022->dummypage) {
1119 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1120 goto err_no_dummypage;
1121 }
1122
1123 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1124 dma_chan_name(pl022->dma_rx_channel),
1125 dma_chan_name(pl022->dma_tx_channel));
1126
1127 return 0;
1128
1129 err_no_dummypage:
1130 dma_release_channel(pl022->dma_tx_channel);
1131 err_no_txchan:
1132 dma_release_channel(pl022->dma_rx_channel);
1133 pl022->dma_rx_channel = NULL;
1134 err_no_rxchan:
1135 dev_err(&pl022->adev->dev,
1136 "Failed to work in dma mode, work without dma!\n");
1137 return -ENODEV;
1138 }
1139
1140 static void terminate_dma(struct pl022 *pl022)
1141 {
1142 struct dma_chan *rxchan = pl022->dma_rx_channel;
1143 struct dma_chan *txchan = pl022->dma_tx_channel;
1144
1145 dmaengine_terminate_all(rxchan);
1146 dmaengine_terminate_all(txchan);
1147 unmap_free_dma_scatter(pl022);
1148 }
1149
1150 static void pl022_dma_remove(struct pl022 *pl022)
1151 {
1152 if (pl022->busy)
1153 terminate_dma(pl022);
1154 if (pl022->dma_tx_channel)
1155 dma_release_channel(pl022->dma_tx_channel);
1156 if (pl022->dma_rx_channel)
1157 dma_release_channel(pl022->dma_rx_channel);
1158 kfree(pl022->dummypage);
1159 }
1160
1161 #else
1162 static inline int configure_dma(struct pl022 *pl022)
1163 {
1164 return -ENODEV;
1165 }
1166
1167 static inline int pl022_dma_probe(struct pl022 *pl022)
1168 {
1169 return 0;
1170 }
1171
1172 static inline void pl022_dma_remove(struct pl022 *pl022)
1173 {
1174 }
1175 #endif
1176
1177 /**
1178 * pl022_interrupt_handler - Interrupt handler for SSP controller
1179 *
1180 * This function handles interrupts generated for an interrupt based transfer.
1181 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1182 * current message's state as STATE_ERROR and schedule the tasklet
1183 * pump_transfers which will do the postprocessing of the current message by
1184 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1185 * more data, and writes data in TX FIFO till it is not full. If we complete
1186 * the transfer we move to the next transfer and schedule the tasklet.
1187 */
1188 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1189 {
1190 struct pl022 *pl022 = dev_id;
1191 struct spi_message *msg = pl022->cur_msg;
1192 u16 irq_status = 0;
1193 u16 flag = 0;
1194
1195 if (unlikely(!msg)) {
1196 dev_err(&pl022->adev->dev,
1197 "bad message state in interrupt handler");
1198 /* Never fail */
1199 return IRQ_HANDLED;
1200 }
1201
1202 /* Read the Interrupt Status Register */
1203 irq_status = readw(SSP_MIS(pl022->virtbase));
1204
1205 if (unlikely(!irq_status))
1206 return IRQ_NONE;
1207
1208 /*
1209 * This handles the FIFO interrupts, the timeout
1210 * interrupts are flatly ignored, they cannot be
1211 * trusted.
1212 */
1213 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1214 /*
1215 * Overrun interrupt - bail out since our Data has been
1216 * corrupted
1217 */
1218 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1219 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1220 dev_err(&pl022->adev->dev,
1221 "RXFIFO is full\n");
1222 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1223 dev_err(&pl022->adev->dev,
1224 "TXFIFO is full\n");
1225
1226 /*
1227 * Disable and clear interrupts, disable SSP,
1228 * mark message with bad status so it can be
1229 * retried.
1230 */
1231 writew(DISABLE_ALL_INTERRUPTS,
1232 SSP_IMSC(pl022->virtbase));
1233 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1234 writew((readw(SSP_CR1(pl022->virtbase)) &
1235 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1236 msg->state = STATE_ERROR;
1237
1238 /* Schedule message queue handler */
1239 tasklet_schedule(&pl022->pump_transfers);
1240 return IRQ_HANDLED;
1241 }
1242
1243 readwriter(pl022);
1244
1245 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1246 flag = 1;
1247 /* Disable Transmit interrupt */
1248 writew(readw(SSP_IMSC(pl022->virtbase)) &
1249 (~SSP_IMSC_MASK_TXIM),
1250 SSP_IMSC(pl022->virtbase));
1251 }
1252
1253 /*
1254 * Since all transactions must write as much as shall be read,
1255 * we can conclude the entire transaction once RX is complete.
1256 * At this point, all TX will always be finished.
1257 */
1258 if (pl022->rx >= pl022->rx_end) {
1259 writew(DISABLE_ALL_INTERRUPTS,
1260 SSP_IMSC(pl022->virtbase));
1261 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1262 if (unlikely(pl022->rx > pl022->rx_end)) {
1263 dev_warn(&pl022->adev->dev, "read %u surplus "
1264 "bytes (did you request an odd "
1265 "number of bytes on a 16bit bus?)\n",
1266 (u32) (pl022->rx - pl022->rx_end));
1267 }
1268 /* Update total bytes transferred */
1269 msg->actual_length += pl022->cur_transfer->len;
1270 if (pl022->cur_transfer->cs_change)
1271 pl022->cur_chip->
1272 cs_control(SSP_CHIP_DESELECT);
1273 /* Move to next transfer */
1274 msg->state = next_transfer(pl022);
1275 tasklet_schedule(&pl022->pump_transfers);
1276 return IRQ_HANDLED;
1277 }
1278
1279 return IRQ_HANDLED;
1280 }
1281
1282 /**
1283 * This sets up the pointers to memory for the next message to
1284 * send out on the SPI bus.
1285 */
1286 static int set_up_next_transfer(struct pl022 *pl022,
1287 struct spi_transfer *transfer)
1288 {
1289 int residue;
1290
1291 /* Sanity check the message for this bus width */
1292 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1293 if (unlikely(residue != 0)) {
1294 dev_err(&pl022->adev->dev,
1295 "message of %u bytes to transmit but the current "
1296 "chip bus has a data width of %u bytes!\n",
1297 pl022->cur_transfer->len,
1298 pl022->cur_chip->n_bytes);
1299 dev_err(&pl022->adev->dev, "skipping this message\n");
1300 return -EIO;
1301 }
1302 pl022->tx = (void *)transfer->tx_buf;
1303 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1304 pl022->rx = (void *)transfer->rx_buf;
1305 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1306 pl022->write =
1307 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1308 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1309 return 0;
1310 }
1311
1312 /**
1313 * pump_transfers - Tasklet function which schedules next transfer
1314 * when running in interrupt or DMA transfer mode.
1315 * @data: SSP driver private data structure
1316 *
1317 */
1318 static void pump_transfers(unsigned long data)
1319 {
1320 struct pl022 *pl022 = (struct pl022 *) data;
1321 struct spi_message *message = NULL;
1322 struct spi_transfer *transfer = NULL;
1323 struct spi_transfer *previous = NULL;
1324
1325 /* Get current state information */
1326 message = pl022->cur_msg;
1327 transfer = pl022->cur_transfer;
1328
1329 /* Handle for abort */
1330 if (message->state == STATE_ERROR) {
1331 message->status = -EIO;
1332 giveback(pl022);
1333 return;
1334 }
1335
1336 /* Handle end of message */
1337 if (message->state == STATE_DONE) {
1338 message->status = 0;
1339 giveback(pl022);
1340 return;
1341 }
1342
1343 /* Delay if requested at end of transfer before CS change */
1344 if (message->state == STATE_RUNNING) {
1345 previous = list_entry(transfer->transfer_list.prev,
1346 struct spi_transfer,
1347 transfer_list);
1348 if (previous->delay_usecs)
1349 /*
1350 * FIXME: This runs in interrupt context.
1351 * Is this really smart?
1352 */
1353 udelay(previous->delay_usecs);
1354
1355 /* Drop chip select only if cs_change is requested */
1356 if (previous->cs_change)
1357 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1358 } else {
1359 /* STATE_START */
1360 message->state = STATE_RUNNING;
1361 }
1362
1363 if (set_up_next_transfer(pl022, transfer)) {
1364 message->state = STATE_ERROR;
1365 message->status = -EIO;
1366 giveback(pl022);
1367 return;
1368 }
1369 /* Flush the FIFOs and let's go! */
1370 flush(pl022);
1371
1372 if (pl022->cur_chip->enable_dma) {
1373 if (configure_dma(pl022)) {
1374 dev_dbg(&pl022->adev->dev,
1375 "configuration of DMA failed, fall back to interrupt mode\n");
1376 goto err_config_dma;
1377 }
1378 return;
1379 }
1380
1381 err_config_dma:
1382 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1383 }
1384
1385 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1386 {
1387 u32 irqflags = ENABLE_ALL_INTERRUPTS;
1388
1389 /* Enable target chip */
1390 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1391 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1392 /* Error path */
1393 pl022->cur_msg->state = STATE_ERROR;
1394 pl022->cur_msg->status = -EIO;
1395 giveback(pl022);
1396 return;
1397 }
1398 /* If we're using DMA, set up DMA here */
1399 if (pl022->cur_chip->enable_dma) {
1400 /* Configure DMA transfer */
1401 if (configure_dma(pl022)) {
1402 dev_dbg(&pl022->adev->dev,
1403 "configuration of DMA failed, fall back to interrupt mode\n");
1404 goto err_config_dma;
1405 }
1406 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1407 irqflags = DISABLE_ALL_INTERRUPTS;
1408 }
1409 err_config_dma:
1410 /* Enable SSP, turn on interrupts */
1411 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1412 SSP_CR1(pl022->virtbase));
1413 writew(irqflags, SSP_IMSC(pl022->virtbase));
1414 }
1415
1416 static void do_polling_transfer(struct pl022 *pl022)
1417 {
1418 struct spi_message *message = NULL;
1419 struct spi_transfer *transfer = NULL;
1420 struct spi_transfer *previous = NULL;
1421 struct chip_data *chip;
1422 unsigned long time, timeout;
1423
1424 chip = pl022->cur_chip;
1425 message = pl022->cur_msg;
1426
1427 while (message->state != STATE_DONE) {
1428 /* Handle for abort */
1429 if (message->state == STATE_ERROR)
1430 break;
1431 transfer = pl022->cur_transfer;
1432
1433 /* Delay if requested at end of transfer */
1434 if (message->state == STATE_RUNNING) {
1435 previous =
1436 list_entry(transfer->transfer_list.prev,
1437 struct spi_transfer, transfer_list);
1438 if (previous->delay_usecs)
1439 udelay(previous->delay_usecs);
1440 if (previous->cs_change)
1441 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1442 } else {
1443 /* STATE_START */
1444 message->state = STATE_RUNNING;
1445 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1446 }
1447
1448 /* Configuration Changing Per Transfer */
1449 if (set_up_next_transfer(pl022, transfer)) {
1450 /* Error path */
1451 message->state = STATE_ERROR;
1452 break;
1453 }
1454 /* Flush FIFOs and enable SSP */
1455 flush(pl022);
1456 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1457 SSP_CR1(pl022->virtbase));
1458
1459 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1460
1461 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1462 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1463 time = jiffies;
1464 readwriter(pl022);
1465 if (time_after(time, timeout)) {
1466 dev_warn(&pl022->adev->dev,
1467 "%s: timeout!\n", __func__);
1468 message->state = STATE_ERROR;
1469 goto out;
1470 }
1471 cpu_relax();
1472 }
1473
1474 /* Update total byte transferred */
1475 message->actual_length += pl022->cur_transfer->len;
1476 if (pl022->cur_transfer->cs_change)
1477 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1478 /* Move to next transfer */
1479 message->state = next_transfer(pl022);
1480 }
1481 out:
1482 /* Handle end of message */
1483 if (message->state == STATE_DONE)
1484 message->status = 0;
1485 else
1486 message->status = -EIO;
1487
1488 giveback(pl022);
1489 return;
1490 }
1491
1492 /**
1493 * pump_messages - Workqueue function which processes spi message queue
1494 * @data: pointer to private data of SSP driver
1495 *
1496 * This function checks if there is any spi message in the queue that
1497 * needs processing and delegate control to appropriate function
1498 * do_polling_transfer()/do_interrupt_dma_transfer()
1499 * based on the kind of the transfer
1500 *
1501 */
1502 static void pump_messages(struct work_struct *work)
1503 {
1504 struct pl022 *pl022 =
1505 container_of(work, struct pl022, pump_messages);
1506 unsigned long flags;
1507
1508 /* Lock queue and check for queue work */
1509 spin_lock_irqsave(&pl022->queue_lock, flags);
1510 if (list_empty(&pl022->queue) || !pl022->running) {
1511 pl022->busy = false;
1512 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1513 return;
1514 }
1515 /* Make sure we are not already running a message */
1516 if (pl022->cur_msg) {
1517 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1518 return;
1519 }
1520 /* Extract head of queue */
1521 pl022->cur_msg =
1522 list_entry(pl022->queue.next, struct spi_message, queue);
1523
1524 list_del_init(&pl022->cur_msg->queue);
1525 pl022->busy = true;
1526 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1527
1528 /* Initial message state */
1529 pl022->cur_msg->state = STATE_START;
1530 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1531 struct spi_transfer, transfer_list);
1532
1533 /* Setup the SPI using the per chip configuration */
1534 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1535 /*
1536 * We enable the core voltage and clocks here, then the clocks
1537 * and core will be disabled when giveback() is called in each method
1538 * (poll/interrupt/DMA)
1539 */
1540 pm_runtime_get_sync(&pl022->adev->dev);
1541 restore_state(pl022);
1542 flush(pl022);
1543
1544 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1545 do_polling_transfer(pl022);
1546 else
1547 do_interrupt_dma_transfer(pl022);
1548 }
1549
1550 static int __init init_queue(struct pl022 *pl022)
1551 {
1552 INIT_LIST_HEAD(&pl022->queue);
1553 spin_lock_init(&pl022->queue_lock);
1554
1555 pl022->running = false;
1556 pl022->busy = false;
1557
1558 tasklet_init(&pl022->pump_transfers, pump_transfers,
1559 (unsigned long)pl022);
1560
1561 INIT_WORK(&pl022->pump_messages, pump_messages);
1562 pl022->workqueue = create_singlethread_workqueue(
1563 dev_name(pl022->master->dev.parent));
1564 if (pl022->workqueue == NULL)
1565 return -EBUSY;
1566
1567 return 0;
1568 }
1569
1570 static int start_queue(struct pl022 *pl022)
1571 {
1572 unsigned long flags;
1573
1574 spin_lock_irqsave(&pl022->queue_lock, flags);
1575
1576 if (pl022->running || pl022->busy) {
1577 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1578 return -EBUSY;
1579 }
1580
1581 pl022->running = true;
1582 pl022->cur_msg = NULL;
1583 pl022->cur_transfer = NULL;
1584 pl022->cur_chip = NULL;
1585 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1586
1587 queue_work(pl022->workqueue, &pl022->pump_messages);
1588
1589 return 0;
1590 }
1591
1592 static int stop_queue(struct pl022 *pl022)
1593 {
1594 unsigned long flags;
1595 unsigned limit = 500;
1596 int status = 0;
1597
1598 spin_lock_irqsave(&pl022->queue_lock, flags);
1599
1600 /* This is a bit lame, but is optimized for the common execution path.
1601 * A wait_queue on the pl022->busy could be used, but then the common
1602 * execution path (pump_messages) would be required to call wake_up or
1603 * friends on every SPI message. Do this instead */
1604 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
1605 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1606 msleep(10);
1607 spin_lock_irqsave(&pl022->queue_lock, flags);
1608 }
1609
1610 if (!list_empty(&pl022->queue) || pl022->busy)
1611 status = -EBUSY;
1612 else
1613 pl022->running = false;
1614
1615 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1616
1617 return status;
1618 }
1619
1620 static int destroy_queue(struct pl022 *pl022)
1621 {
1622 int status;
1623
1624 status = stop_queue(pl022);
1625 /* we are unloading the module or failing to load (only two calls
1626 * to this routine), and neither call can handle a return value.
1627 * However, destroy_workqueue calls flush_workqueue, and that will
1628 * block until all work is done. If the reason that stop_queue
1629 * timed out is that the work will never finish, then it does no
1630 * good to call destroy_workqueue, so return anyway. */
1631 if (status != 0)
1632 return status;
1633
1634 destroy_workqueue(pl022->workqueue);
1635
1636 return 0;
1637 }
1638
1639 static int verify_controller_parameters(struct pl022 *pl022,
1640 struct pl022_config_chip const *chip_info)
1641 {
1642 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1643 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1644 dev_err(&pl022->adev->dev,
1645 "interface is configured incorrectly\n");
1646 return -EINVAL;
1647 }
1648 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1649 (!pl022->vendor->unidir)) {
1650 dev_err(&pl022->adev->dev,
1651 "unidirectional mode not supported in this "
1652 "hardware version\n");
1653 return -EINVAL;
1654 }
1655 if ((chip_info->hierarchy != SSP_MASTER)
1656 && (chip_info->hierarchy != SSP_SLAVE)) {
1657 dev_err(&pl022->adev->dev,
1658 "hierarchy is configured incorrectly\n");
1659 return -EINVAL;
1660 }
1661 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1662 && (chip_info->com_mode != DMA_TRANSFER)
1663 && (chip_info->com_mode != POLLING_TRANSFER)) {
1664 dev_err(&pl022->adev->dev,
1665 "Communication mode is configured incorrectly\n");
1666 return -EINVAL;
1667 }
1668 switch (chip_info->rx_lev_trig) {
1669 case SSP_RX_1_OR_MORE_ELEM:
1670 case SSP_RX_4_OR_MORE_ELEM:
1671 case SSP_RX_8_OR_MORE_ELEM:
1672 /* These are always OK, all variants can handle this */
1673 break;
1674 case SSP_RX_16_OR_MORE_ELEM:
1675 if (pl022->vendor->fifodepth < 16) {
1676 dev_err(&pl022->adev->dev,
1677 "RX FIFO Trigger Level is configured incorrectly\n");
1678 return -EINVAL;
1679 }
1680 break;
1681 case SSP_RX_32_OR_MORE_ELEM:
1682 if (pl022->vendor->fifodepth < 32) {
1683 dev_err(&pl022->adev->dev,
1684 "RX FIFO Trigger Level is configured incorrectly\n");
1685 return -EINVAL;
1686 }
1687 break;
1688 default:
1689 dev_err(&pl022->adev->dev,
1690 "RX FIFO Trigger Level is configured incorrectly\n");
1691 return -EINVAL;
1692 break;
1693 }
1694 switch (chip_info->tx_lev_trig) {
1695 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1696 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1697 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1698 /* These are always OK, all variants can handle this */
1699 break;
1700 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1701 if (pl022->vendor->fifodepth < 16) {
1702 dev_err(&pl022->adev->dev,
1703 "TX FIFO Trigger Level is configured incorrectly\n");
1704 return -EINVAL;
1705 }
1706 break;
1707 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1708 if (pl022->vendor->fifodepth < 32) {
1709 dev_err(&pl022->adev->dev,
1710 "TX FIFO Trigger Level is configured incorrectly\n");
1711 return -EINVAL;
1712 }
1713 break;
1714 default:
1715 dev_err(&pl022->adev->dev,
1716 "TX FIFO Trigger Level is configured incorrectly\n");
1717 return -EINVAL;
1718 break;
1719 }
1720 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1721 if ((chip_info->ctrl_len < SSP_BITS_4)
1722 || (chip_info->ctrl_len > SSP_BITS_32)) {
1723 dev_err(&pl022->adev->dev,
1724 "CTRL LEN is configured incorrectly\n");
1725 return -EINVAL;
1726 }
1727 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1728 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1729 dev_err(&pl022->adev->dev,
1730 "Wait State is configured incorrectly\n");
1731 return -EINVAL;
1732 }
1733 /* Half duplex is only available in the ST Micro version */
1734 if (pl022->vendor->extended_cr) {
1735 if ((chip_info->duplex !=
1736 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1737 && (chip_info->duplex !=
1738 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1739 dev_err(&pl022->adev->dev,
1740 "Microwire duplex mode is configured incorrectly\n");
1741 return -EINVAL;
1742 }
1743 } else {
1744 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1745 dev_err(&pl022->adev->dev,
1746 "Microwire half duplex mode requested,"
1747 " but this is only available in the"
1748 " ST version of PL022\n");
1749 return -EINVAL;
1750 }
1751 }
1752 return 0;
1753 }
1754
1755 /**
1756 * pl022_transfer - transfer function registered to SPI master framework
1757 * @spi: spi device which is requesting transfer
1758 * @msg: spi message which is to handled is queued to driver queue
1759 *
1760 * This function is registered to the SPI framework for this SPI master
1761 * controller. It will queue the spi_message in the queue of driver if
1762 * the queue is not stopped and return.
1763 */
1764 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1765 {
1766 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1767 unsigned long flags;
1768
1769 spin_lock_irqsave(&pl022->queue_lock, flags);
1770
1771 if (!pl022->running) {
1772 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1773 return -ESHUTDOWN;
1774 }
1775 msg->actual_length = 0;
1776 msg->status = -EINPROGRESS;
1777 msg->state = STATE_START;
1778
1779 list_add_tail(&msg->queue, &pl022->queue);
1780 if (pl022->running && !pl022->busy)
1781 queue_work(pl022->workqueue, &pl022->pump_messages);
1782
1783 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1784 return 0;
1785 }
1786
1787 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1788 {
1789 return rate / (cpsdvsr * (1 + scr));
1790 }
1791
1792 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1793 ssp_clock_params * clk_freq)
1794 {
1795 /* Lets calculate the frequency parameters */
1796 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1797 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1798 best_scr = 0, tmp, found = 0;
1799
1800 rate = clk_get_rate(pl022->clk);
1801 /* cpsdvscr = 2 & scr 0 */
1802 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1803 /* cpsdvsr = 254 & scr = 255 */
1804 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1805
1806 if (!((freq <= max_tclk) && (freq >= min_tclk))) {
1807 dev_err(&pl022->adev->dev,
1808 "controller data is incorrect: out of range frequency");
1809 return -EINVAL;
1810 }
1811
1812 /*
1813 * best_freq will give closest possible available rate (<= requested
1814 * freq) for all values of scr & cpsdvsr.
1815 */
1816 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1817 while (scr <= SCR_MAX) {
1818 tmp = spi_rate(rate, cpsdvsr, scr);
1819
1820 if (tmp > freq)
1821 scr++;
1822 /*
1823 * If found exact value, update and break.
1824 * If found more closer value, update and continue.
1825 */
1826 else if ((tmp == freq) || (tmp > best_freq)) {
1827 best_freq = tmp;
1828 best_cpsdvsr = cpsdvsr;
1829 best_scr = scr;
1830
1831 if (tmp == freq)
1832 break;
1833 }
1834 scr++;
1835 }
1836 cpsdvsr += 2;
1837 scr = SCR_MIN;
1838 }
1839
1840 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1841 clk_freq->scr = (u8) (best_scr & 0xFF);
1842 dev_dbg(&pl022->adev->dev,
1843 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1844 freq, best_freq);
1845 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1846 clk_freq->cpsdvsr, clk_freq->scr);
1847
1848 return 0;
1849 }
1850
1851 /*
1852 * A piece of default chip info unless the platform
1853 * supplies it.
1854 */
1855 static const struct pl022_config_chip pl022_default_chip_info = {
1856 .com_mode = POLLING_TRANSFER,
1857 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1858 .hierarchy = SSP_SLAVE,
1859 .slave_tx_disable = DO_NOT_DRIVE_TX,
1860 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1861 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1862 .ctrl_len = SSP_BITS_8,
1863 .wait_state = SSP_MWIRE_WAIT_ZERO,
1864 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1865 .cs_control = null_cs_control,
1866 };
1867
1868 /**
1869 * pl022_setup - setup function registered to SPI master framework
1870 * @spi: spi device which is requesting setup
1871 *
1872 * This function is registered to the SPI framework for this SPI master
1873 * controller. If it is the first time when setup is called by this device,
1874 * this function will initialize the runtime state for this chip and save
1875 * the same in the device structure. Else it will update the runtime info
1876 * with the updated chip info. Nothing is really being written to the
1877 * controller hardware here, that is not done until the actual transfer
1878 * commence.
1879 */
1880 static int pl022_setup(struct spi_device *spi)
1881 {
1882 struct pl022_config_chip const *chip_info;
1883 struct chip_data *chip;
1884 struct ssp_clock_params clk_freq = {0, };
1885 int status = 0;
1886 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1887 unsigned int bits = spi->bits_per_word;
1888 u32 tmp;
1889
1890 if (!spi->max_speed_hz)
1891 return -EINVAL;
1892
1893 /* Get controller_state if one is supplied */
1894 chip = spi_get_ctldata(spi);
1895
1896 if (chip == NULL) {
1897 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1898 if (!chip) {
1899 dev_err(&spi->dev,
1900 "cannot allocate controller state\n");
1901 return -ENOMEM;
1902 }
1903 dev_dbg(&spi->dev,
1904 "allocated memory for controller's runtime state\n");
1905 }
1906
1907 /* Get controller data if one is supplied */
1908 chip_info = spi->controller_data;
1909
1910 if (chip_info == NULL) {
1911 chip_info = &pl022_default_chip_info;
1912 /* spi_board_info.controller_data not is supplied */
1913 dev_dbg(&spi->dev,
1914 "using default controller_data settings\n");
1915 } else
1916 dev_dbg(&spi->dev,
1917 "using user supplied controller_data settings\n");
1918
1919 /*
1920 * We can override with custom divisors, else we use the board
1921 * frequency setting
1922 */
1923 if ((0 == chip_info->clk_freq.cpsdvsr)
1924 && (0 == chip_info->clk_freq.scr)) {
1925 status = calculate_effective_freq(pl022,
1926 spi->max_speed_hz,
1927 &clk_freq);
1928 if (status < 0)
1929 goto err_config_params;
1930 } else {
1931 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1932 if ((clk_freq.cpsdvsr % 2) != 0)
1933 clk_freq.cpsdvsr =
1934 clk_freq.cpsdvsr - 1;
1935 }
1936 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1937 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1938 status = -EINVAL;
1939 dev_err(&spi->dev,
1940 "cpsdvsr is configured incorrectly\n");
1941 goto err_config_params;
1942 }
1943
1944 status = verify_controller_parameters(pl022, chip_info);
1945 if (status) {
1946 dev_err(&spi->dev, "controller data is incorrect");
1947 goto err_config_params;
1948 }
1949
1950 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1951 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1952
1953 /* Now set controller state based on controller data */
1954 chip->xfer_type = chip_info->com_mode;
1955 if (!chip_info->cs_control) {
1956 chip->cs_control = null_cs_control;
1957 dev_warn(&spi->dev,
1958 "chip select function is NULL for this chip\n");
1959 } else
1960 chip->cs_control = chip_info->cs_control;
1961
1962 if (bits <= 3) {
1963 /* PL022 doesn't support less than 4-bits */
1964 status = -ENOTSUPP;
1965 goto err_config_params;
1966 } else if (bits <= 8) {
1967 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1968 chip->n_bytes = 1;
1969 chip->read = READING_U8;
1970 chip->write = WRITING_U8;
1971 } else if (bits <= 16) {
1972 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1973 chip->n_bytes = 2;
1974 chip->read = READING_U16;
1975 chip->write = WRITING_U16;
1976 } else {
1977 if (pl022->vendor->max_bpw >= 32) {
1978 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1979 chip->n_bytes = 4;
1980 chip->read = READING_U32;
1981 chip->write = WRITING_U32;
1982 } else {
1983 dev_err(&spi->dev,
1984 "illegal data size for this controller!\n");
1985 dev_err(&spi->dev,
1986 "a standard pl022 can only handle "
1987 "1 <= n <= 16 bit words\n");
1988 status = -ENOTSUPP;
1989 goto err_config_params;
1990 }
1991 }
1992
1993 /* Now Initialize all register settings required for this chip */
1994 chip->cr0 = 0;
1995 chip->cr1 = 0;
1996 chip->dmacr = 0;
1997 chip->cpsr = 0;
1998 if ((chip_info->com_mode == DMA_TRANSFER)
1999 && ((pl022->master_info)->enable_dma)) {
2000 chip->enable_dma = true;
2001 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
2002 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2003 SSP_DMACR_MASK_RXDMAE, 0);
2004 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2005 SSP_DMACR_MASK_TXDMAE, 1);
2006 } else {
2007 chip->enable_dma = false;
2008 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
2009 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2010 SSP_DMACR_MASK_RXDMAE, 0);
2011 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2012 SSP_DMACR_MASK_TXDMAE, 1);
2013 }
2014
2015 chip->cpsr = clk_freq.cpsdvsr;
2016
2017 /* Special setup for the ST micro extended control registers */
2018 if (pl022->vendor->extended_cr) {
2019 u32 etx;
2020
2021 if (pl022->vendor->pl023) {
2022 /* These bits are only in the PL023 */
2023 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2024 SSP_CR1_MASK_FBCLKDEL_ST, 13);
2025 } else {
2026 /* These bits are in the PL022 but not PL023 */
2027 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2028 SSP_CR0_MASK_HALFDUP_ST, 5);
2029 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2030 SSP_CR0_MASK_CSS_ST, 16);
2031 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2032 SSP_CR0_MASK_FRF_ST, 21);
2033 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2034 SSP_CR1_MASK_MWAIT_ST, 6);
2035 }
2036 SSP_WRITE_BITS(chip->cr0, bits - 1,
2037 SSP_CR0_MASK_DSS_ST, 0);
2038
2039 if (spi->mode & SPI_LSB_FIRST) {
2040 tmp = SSP_RX_LSB;
2041 etx = SSP_TX_LSB;
2042 } else {
2043 tmp = SSP_RX_MSB;
2044 etx = SSP_TX_MSB;
2045 }
2046 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2047 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2048 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2049 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2050 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2051 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2052 } else {
2053 SSP_WRITE_BITS(chip->cr0, bits - 1,
2054 SSP_CR0_MASK_DSS, 0);
2055 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2056 SSP_CR0_MASK_FRF, 4);
2057 }
2058
2059 /* Stuff that is common for all versions */
2060 if (spi->mode & SPI_CPOL)
2061 tmp = SSP_CLK_POL_IDLE_HIGH;
2062 else
2063 tmp = SSP_CLK_POL_IDLE_LOW;
2064 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2065
2066 if (spi->mode & SPI_CPHA)
2067 tmp = SSP_CLK_SECOND_EDGE;
2068 else
2069 tmp = SSP_CLK_FIRST_EDGE;
2070 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2071
2072 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2073 /* Loopback is available on all versions except PL023 */
2074 if (pl022->vendor->loopback) {
2075 if (spi->mode & SPI_LOOP)
2076 tmp = LOOPBACK_ENABLED;
2077 else
2078 tmp = LOOPBACK_DISABLED;
2079 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2080 }
2081 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2082 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2083 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2084 3);
2085
2086 /* Save controller_state */
2087 spi_set_ctldata(spi, chip);
2088 return status;
2089 err_config_params:
2090 spi_set_ctldata(spi, NULL);
2091 kfree(chip);
2092 return status;
2093 }
2094
2095 /**
2096 * pl022_cleanup - cleanup function registered to SPI master framework
2097 * @spi: spi device which is requesting cleanup
2098 *
2099 * This function is registered to the SPI framework for this SPI master
2100 * controller. It will free the runtime state of chip.
2101 */
2102 static void pl022_cleanup(struct spi_device *spi)
2103 {
2104 struct chip_data *chip = spi_get_ctldata(spi);
2105
2106 spi_set_ctldata(spi, NULL);
2107 kfree(chip);
2108 }
2109
2110 static int __devinit
2111 pl022_probe(struct amba_device *adev, const struct amba_id *id)
2112 {
2113 struct device *dev = &adev->dev;
2114 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2115 struct spi_master *master;
2116 struct pl022 *pl022 = NULL; /*Data for this driver */
2117 int status = 0;
2118
2119 dev_info(&adev->dev,
2120 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2121 if (platform_info == NULL) {
2122 dev_err(&adev->dev, "probe - no platform data supplied\n");
2123 status = -ENODEV;
2124 goto err_no_pdata;
2125 }
2126
2127 /* Allocate master with space for data */
2128 master = spi_alloc_master(dev, sizeof(struct pl022));
2129 if (master == NULL) {
2130 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2131 status = -ENOMEM;
2132 goto err_no_master;
2133 }
2134
2135 pl022 = spi_master_get_devdata(master);
2136 pl022->master = master;
2137 pl022->master_info = platform_info;
2138 pl022->adev = adev;
2139 pl022->vendor = id->data;
2140
2141 /*
2142 * Bus Number Which has been Assigned to this SSP controller
2143 * on this board
2144 */
2145 master->bus_num = platform_info->bus_id;
2146 master->num_chipselect = platform_info->num_chipselect;
2147 master->cleanup = pl022_cleanup;
2148 master->setup = pl022_setup;
2149 master->transfer = pl022_transfer;
2150
2151 /*
2152 * Supports mode 0-3, loopback, and active low CS. Transfers are
2153 * always MS bit first on the original pl022.
2154 */
2155 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2156 if (pl022->vendor->extended_cr)
2157 master->mode_bits |= SPI_LSB_FIRST;
2158
2159 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2160
2161 status = amba_request_regions(adev, NULL);
2162 if (status)
2163 goto err_no_ioregion;
2164
2165 pl022->phybase = adev->res.start;
2166 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2167 if (pl022->virtbase == NULL) {
2168 status = -ENOMEM;
2169 goto err_no_ioremap;
2170 }
2171 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2172 adev->res.start, pl022->virtbase);
2173
2174 pl022->clk = clk_get(&adev->dev, NULL);
2175 if (IS_ERR(pl022->clk)) {
2176 status = PTR_ERR(pl022->clk);
2177 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2178 goto err_no_clk;
2179 }
2180
2181 status = clk_prepare(pl022->clk);
2182 if (status) {
2183 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2184 goto err_clk_prep;
2185 }
2186
2187 /* Disable SSP */
2188 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2189 SSP_CR1(pl022->virtbase));
2190 load_ssp_default_config(pl022);
2191
2192 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2193 pl022);
2194 if (status < 0) {
2195 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2196 goto err_no_irq;
2197 }
2198
2199 /* Get DMA channels */
2200 if (platform_info->enable_dma) {
2201 status = pl022_dma_probe(pl022);
2202 if (status != 0)
2203 platform_info->enable_dma = 0;
2204 }
2205
2206 /* Initialize and start queue */
2207 status = init_queue(pl022);
2208 if (status != 0) {
2209 dev_err(&adev->dev, "probe - problem initializing queue\n");
2210 goto err_init_queue;
2211 }
2212 status = start_queue(pl022);
2213 if (status != 0) {
2214 dev_err(&adev->dev, "probe - problem starting queue\n");
2215 goto err_start_queue;
2216 }
2217 /* Register with the SPI framework */
2218 amba_set_drvdata(adev, pl022);
2219 status = spi_register_master(master);
2220 if (status != 0) {
2221 dev_err(&adev->dev,
2222 "probe - problem registering spi master\n");
2223 goto err_spi_register;
2224 }
2225 dev_dbg(dev, "probe succeeded\n");
2226
2227 /* let runtime pm put suspend */
2228 pm_runtime_put(dev);
2229 return 0;
2230
2231 err_spi_register:
2232 err_start_queue:
2233 err_init_queue:
2234 destroy_queue(pl022);
2235 if (platform_info->enable_dma)
2236 pl022_dma_remove(pl022);
2237
2238 free_irq(adev->irq[0], pl022);
2239 err_no_irq:
2240 clk_unprepare(pl022->clk);
2241 err_clk_prep:
2242 clk_put(pl022->clk);
2243 err_no_clk:
2244 iounmap(pl022->virtbase);
2245 err_no_ioremap:
2246 amba_release_regions(adev);
2247 err_no_ioregion:
2248 spi_master_put(master);
2249 err_no_master:
2250 err_no_pdata:
2251 return status;
2252 }
2253
2254 static int __devexit
2255 pl022_remove(struct amba_device *adev)
2256 {
2257 struct pl022 *pl022 = amba_get_drvdata(adev);
2258
2259 if (!pl022)
2260 return 0;
2261
2262 /*
2263 * undo pm_runtime_put() in probe. I assume that we're not
2264 * accessing the primecell here.
2265 */
2266 pm_runtime_get_noresume(&adev->dev);
2267
2268 /* Remove the queue */
2269 if (destroy_queue(pl022) != 0)
2270 dev_err(&adev->dev, "queue remove failed\n");
2271 load_ssp_default_config(pl022);
2272 if (pl022->master_info->enable_dma)
2273 pl022_dma_remove(pl022);
2274
2275 free_irq(adev->irq[0], pl022);
2276 clk_disable(pl022->clk);
2277 clk_unprepare(pl022->clk);
2278 clk_put(pl022->clk);
2279 iounmap(pl022->virtbase);
2280 amba_release_regions(adev);
2281 tasklet_disable(&pl022->pump_transfers);
2282 spi_unregister_master(pl022->master);
2283 spi_master_put(pl022->master);
2284 amba_set_drvdata(adev, NULL);
2285 return 0;
2286 }
2287
2288 #ifdef CONFIG_SUSPEND
2289 static int pl022_suspend(struct device *dev)
2290 {
2291 struct pl022 *pl022 = dev_get_drvdata(dev);
2292 int status = 0;
2293
2294 status = stop_queue(pl022);
2295 if (status) {
2296 dev_warn(dev, "suspend cannot stop queue\n");
2297 return status;
2298 }
2299
2300 amba_vcore_enable(pl022->adev);
2301 amba_pclk_enable(pl022->adev);
2302 load_ssp_default_config(pl022);
2303 amba_pclk_disable(pl022->adev);
2304 amba_vcore_disable(pl022->adev);
2305 dev_dbg(dev, "suspended\n");
2306 return 0;
2307 }
2308
2309 static int pl022_resume(struct device *dev)
2310 {
2311 struct pl022 *pl022 = dev_get_drvdata(dev);
2312 int status = 0;
2313
2314 /* Start the queue running */
2315 status = start_queue(pl022);
2316 if (status)
2317 dev_err(dev, "problem starting queue (%d)\n", status);
2318 else
2319 dev_dbg(dev, "resumed\n");
2320
2321 return status;
2322 }
2323 #endif /* CONFIG_PM */
2324
2325 #ifdef CONFIG_PM_RUNTIME
2326 static int pl022_runtime_suspend(struct device *dev)
2327 {
2328 struct pl022 *pl022 = dev_get_drvdata(dev);
2329
2330 clk_disable(pl022->clk);
2331 amba_vcore_disable(pl022->adev);
2332
2333 return 0;
2334 }
2335
2336 static int pl022_runtime_resume(struct device *dev)
2337 {
2338 struct pl022 *pl022 = dev_get_drvdata(dev);
2339
2340 amba_vcore_enable(pl022->adev);
2341 clk_enable(pl022->clk);
2342
2343 return 0;
2344 }
2345 #endif
2346
2347 static const struct dev_pm_ops pl022_dev_pm_ops = {
2348 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2349 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2350 };
2351
2352 static struct vendor_data vendor_arm = {
2353 .fifodepth = 8,
2354 .max_bpw = 16,
2355 .unidir = false,
2356 .extended_cr = false,
2357 .pl023 = false,
2358 .loopback = true,
2359 };
2360
2361 static struct vendor_data vendor_st = {
2362 .fifodepth = 32,
2363 .max_bpw = 32,
2364 .unidir = false,
2365 .extended_cr = true,
2366 .pl023 = false,
2367 .loopback = true,
2368 };
2369
2370 static struct vendor_data vendor_st_pl023 = {
2371 .fifodepth = 32,
2372 .max_bpw = 32,
2373 .unidir = false,
2374 .extended_cr = true,
2375 .pl023 = true,
2376 .loopback = false,
2377 };
2378
2379 static struct vendor_data vendor_db5500_pl023 = {
2380 .fifodepth = 32,
2381 .max_bpw = 32,
2382 .unidir = false,
2383 .extended_cr = true,
2384 .pl023 = true,
2385 .loopback = true,
2386 };
2387
2388 static struct amba_id pl022_ids[] = {
2389 {
2390 /*
2391 * ARM PL022 variant, this has a 16bit wide
2392 * and 8 locations deep TX/RX FIFO
2393 */
2394 .id = 0x00041022,
2395 .mask = 0x000fffff,
2396 .data = &vendor_arm,
2397 },
2398 {
2399 /*
2400 * ST Micro derivative, this has 32bit wide
2401 * and 32 locations deep TX/RX FIFO
2402 */
2403 .id = 0x01080022,
2404 .mask = 0xffffffff,
2405 .data = &vendor_st,
2406 },
2407 {
2408 /*
2409 * ST-Ericsson derivative "PL023" (this is not
2410 * an official ARM number), this is a PL022 SSP block
2411 * stripped to SPI mode only, it has 32bit wide
2412 * and 32 locations deep TX/RX FIFO but no extended
2413 * CR0/CR1 register
2414 */
2415 .id = 0x00080023,
2416 .mask = 0xffffffff,
2417 .data = &vendor_st_pl023,
2418 },
2419 {
2420 .id = 0x10080023,
2421 .mask = 0xffffffff,
2422 .data = &vendor_db5500_pl023,
2423 },
2424 { 0, 0 },
2425 };
2426
2427 static struct amba_driver pl022_driver = {
2428 .drv = {
2429 .name = "ssp-pl022",
2430 .pm = &pl022_dev_pm_ops,
2431 },
2432 .id_table = pl022_ids,
2433 .probe = pl022_probe,
2434 .remove = __devexit_p(pl022_remove),
2435 };
2436
2437 static int __init pl022_init(void)
2438 {
2439 return amba_driver_register(&pl022_driver);
2440 }
2441 subsys_initcall(pl022_init);
2442
2443 static void __exit pl022_exit(void)
2444 {
2445 amba_driver_unregister(&pl022_driver);
2446 }
2447 module_exit(pl022_exit);
2448
2449 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2450 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2451 MODULE_LICENSE("GPL");
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