2 * SPI bus via the Blackfin SPORT peripheral
4 * Enter bugs at http://blackfin.uclinux.org/
6 * Copyright 2009-2011 Analog Devices Inc.
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
25 #include <asm/portmux.h>
26 #include <asm/bfin5xx_spi.h>
27 #include <asm/blackfin.h>
28 #include <asm/bfin_sport.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-sport-spi"
32 #define DRV_DESC "SPI bus via the Blackfin SPORT"
34 MODULE_AUTHOR("Cliff Cai");
35 MODULE_DESCRIPTION(DRV_DESC
);
36 MODULE_LICENSE("GPL");
37 MODULE_ALIAS("platform:bfin-sport-spi");
39 enum bfin_sport_spi_state
{
46 struct bfin_sport_spi_master_data
;
48 struct bfin_sport_transfer_ops
{
49 void (*write
) (struct bfin_sport_spi_master_data
*);
50 void (*read
) (struct bfin_sport_spi_master_data
*);
51 void (*duplex
) (struct bfin_sport_spi_master_data
*);
54 struct bfin_sport_spi_master_data
{
55 /* Driver model hookup */
58 /* SPI framework hookup */
59 struct spi_master
*master
;
61 /* Regs base of SPI controller */
62 struct sport_register __iomem
*regs
;
65 /* Pin request list */
68 /* Driver message queue */
69 struct workqueue_struct
*workqueue
;
70 struct work_struct pump_messages
;
72 struct list_head queue
;
76 /* Message Transfer pump */
77 struct tasklet_struct pump_transfers
;
79 /* Current message transfer state info */
80 enum bfin_sport_spi_state state
;
81 struct spi_message
*cur_msg
;
82 struct spi_transfer
*cur_transfer
;
83 struct bfin_sport_spi_slave_data
*cur_chip
;
98 struct bfin_sport_transfer_ops
*ops
;
101 struct bfin_sport_spi_slave_data
{
104 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
107 struct bfin_sport_transfer_ops
*ops
;
111 bfin_sport_spi_enable(struct bfin_sport_spi_master_data
*drv_data
)
113 bfin_write_or(&drv_data
->regs
->tcr1
, TSPEN
);
114 bfin_write_or(&drv_data
->regs
->rcr1
, TSPEN
);
119 bfin_sport_spi_disable(struct bfin_sport_spi_master_data
*drv_data
)
121 bfin_write_and(&drv_data
->regs
->tcr1
, ~TSPEN
);
122 bfin_write_and(&drv_data
->regs
->rcr1
, ~TSPEN
);
126 /* Caculate the SPI_BAUD register value based on input HZ */
128 bfin_sport_hz_to_spi_baud(u32 speed_hz
)
130 u_long clk
, sclk
= get_sclk();
131 int div
= (sclk
/ (2 * speed_hz
)) - 1;
136 clk
= sclk
/ (2 * (div
+ 1));
144 /* Chip select operation functions for cs_change flag */
146 bfin_sport_spi_cs_active(struct bfin_sport_spi_slave_data
*chip
)
148 gpio_direction_output(chip
->cs_gpio
, 0);
152 bfin_sport_spi_cs_deactive(struct bfin_sport_spi_slave_data
*chip
)
154 gpio_direction_output(chip
->cs_gpio
, 1);
155 /* Move delay here for consistency */
156 if (chip
->cs_chg_udelay
)
157 udelay(chip
->cs_chg_udelay
);
161 bfin_sport_spi_stat_poll_complete(struct bfin_sport_spi_master_data
*drv_data
)
163 unsigned long timeout
= jiffies
+ HZ
;
164 while (!(bfin_read(&drv_data
->regs
->stat
) & RXNE
)) {
165 if (!time_before(jiffies
, timeout
))
171 bfin_sport_spi_u8_writer(struct bfin_sport_spi_master_data
*drv_data
)
175 while (drv_data
->tx
< drv_data
->tx_end
) {
176 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx8
++);
177 bfin_sport_spi_stat_poll_complete(drv_data
);
178 dummy
= bfin_read(&drv_data
->regs
->rx16
);
183 bfin_sport_spi_u8_reader(struct bfin_sport_spi_master_data
*drv_data
)
185 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
187 while (drv_data
->rx
< drv_data
->rx_end
) {
188 bfin_write(&drv_data
->regs
->tx16
, tx_val
);
189 bfin_sport_spi_stat_poll_complete(drv_data
);
190 *drv_data
->rx8
++ = bfin_read(&drv_data
->regs
->rx16
);
195 bfin_sport_spi_u8_duplex(struct bfin_sport_spi_master_data
*drv_data
)
197 while (drv_data
->rx
< drv_data
->rx_end
) {
198 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx8
++);
199 bfin_sport_spi_stat_poll_complete(drv_data
);
200 *drv_data
->rx8
++ = bfin_read(&drv_data
->regs
->rx16
);
204 static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u8
= {
205 .write
= bfin_sport_spi_u8_writer
,
206 .read
= bfin_sport_spi_u8_reader
,
207 .duplex
= bfin_sport_spi_u8_duplex
,
211 bfin_sport_spi_u16_writer(struct bfin_sport_spi_master_data
*drv_data
)
215 while (drv_data
->tx
< drv_data
->tx_end
) {
216 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx16
++);
217 bfin_sport_spi_stat_poll_complete(drv_data
);
218 dummy
= bfin_read(&drv_data
->regs
->rx16
);
223 bfin_sport_spi_u16_reader(struct bfin_sport_spi_master_data
*drv_data
)
225 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
227 while (drv_data
->rx
< drv_data
->rx_end
) {
228 bfin_write(&drv_data
->regs
->tx16
, tx_val
);
229 bfin_sport_spi_stat_poll_complete(drv_data
);
230 *drv_data
->rx16
++ = bfin_read(&drv_data
->regs
->rx16
);
235 bfin_sport_spi_u16_duplex(struct bfin_sport_spi_master_data
*drv_data
)
237 while (drv_data
->rx
< drv_data
->rx_end
) {
238 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx16
++);
239 bfin_sport_spi_stat_poll_complete(drv_data
);
240 *drv_data
->rx16
++ = bfin_read(&drv_data
->regs
->rx16
);
244 static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u16
= {
245 .write
= bfin_sport_spi_u16_writer
,
246 .read
= bfin_sport_spi_u16_reader
,
247 .duplex
= bfin_sport_spi_u16_duplex
,
250 /* stop controller and re-config current chip */
252 bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data
*drv_data
)
254 struct bfin_sport_spi_slave_data
*chip
= drv_data
->cur_chip
;
255 unsigned int bits
= (drv_data
->ops
== &bfin_sport_transfer_ops_u8
? 7 : 15);
257 bfin_sport_spi_disable(drv_data
);
258 dev_dbg(drv_data
->dev
, "restoring spi ctl state\n");
260 bfin_write(&drv_data
->regs
->tcr1
, chip
->ctl_reg
);
261 bfin_write(&drv_data
->regs
->tcr2
, bits
);
262 bfin_write(&drv_data
->regs
->tclkdiv
, chip
->baud
);
263 bfin_write(&drv_data
->regs
->tfsdiv
, bits
);
266 bfin_write(&drv_data
->regs
->rcr1
, chip
->ctl_reg
& ~(ITCLK
| ITFS
));
267 bfin_write(&drv_data
->regs
->rcr2
, bits
);
270 bfin_sport_spi_cs_active(chip
);
273 /* test if there is more transfer to be done */
274 static enum bfin_sport_spi_state
275 bfin_sport_spi_next_transfer(struct bfin_sport_spi_master_data
*drv_data
)
277 struct spi_message
*msg
= drv_data
->cur_msg
;
278 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
280 /* Move to next transfer */
281 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
282 drv_data
->cur_transfer
=
283 list_entry(trans
->transfer_list
.next
,
284 struct spi_transfer
, transfer_list
);
285 return RUNNING_STATE
;
292 * caller already set message->status;
293 * dma and pio irqs are blocked give finished message back
296 bfin_sport_spi_giveback(struct bfin_sport_spi_master_data
*drv_data
)
298 struct bfin_sport_spi_slave_data
*chip
= drv_data
->cur_chip
;
300 struct spi_message
*msg
;
302 spin_lock_irqsave(&drv_data
->lock
, flags
);
303 msg
= drv_data
->cur_msg
;
304 drv_data
->state
= START_STATE
;
305 drv_data
->cur_msg
= NULL
;
306 drv_data
->cur_transfer
= NULL
;
307 drv_data
->cur_chip
= NULL
;
308 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
309 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
311 if (!drv_data
->cs_change
)
312 bfin_sport_spi_cs_deactive(chip
);
315 msg
->complete(msg
->context
);
319 sport_err_handler(int irq
, void *dev_id
)
321 struct bfin_sport_spi_master_data
*drv_data
= dev_id
;
324 dev_dbg(drv_data
->dev
, "%s enter\n", __func__
);
325 status
= bfin_read(&drv_data
->regs
->stat
) & (TOVF
| TUVF
| ROVF
| RUVF
);
328 bfin_write(&drv_data
->regs
->stat
, status
);
331 bfin_sport_spi_disable(drv_data
);
332 dev_err(drv_data
->dev
, "status error:%s%s%s%s\n",
333 status
& TOVF
? " TOVF" : "",
334 status
& TUVF
? " TUVF" : "",
335 status
& ROVF
? " ROVF" : "",
336 status
& RUVF
? " RUVF" : "");
343 bfin_sport_spi_pump_transfers(unsigned long data
)
345 struct bfin_sport_spi_master_data
*drv_data
= (void *)data
;
346 struct spi_message
*message
= NULL
;
347 struct spi_transfer
*transfer
= NULL
;
348 struct spi_transfer
*previous
= NULL
;
349 struct bfin_sport_spi_slave_data
*chip
= NULL
;
350 unsigned int bits_per_word
;
351 u32 tranf_success
= 1;
355 /* Get current state information */
356 message
= drv_data
->cur_msg
;
357 transfer
= drv_data
->cur_transfer
;
358 chip
= drv_data
->cur_chip
;
360 if (transfer
->speed_hz
)
361 transfer_speed
= bfin_sport_hz_to_spi_baud(transfer
->speed_hz
);
363 transfer_speed
= chip
->baud
;
364 bfin_write(&drv_data
->regs
->tclkdiv
, transfer_speed
);
368 * if msg is error or done, report it back using complete() callback
371 /* Handle for abort */
372 if (drv_data
->state
== ERROR_STATE
) {
373 dev_dbg(drv_data
->dev
, "transfer: we've hit an error\n");
374 message
->status
= -EIO
;
375 bfin_sport_spi_giveback(drv_data
);
379 /* Handle end of message */
380 if (drv_data
->state
== DONE_STATE
) {
381 dev_dbg(drv_data
->dev
, "transfer: all done!\n");
383 bfin_sport_spi_giveback(drv_data
);
387 /* Delay if requested at end of transfer */
388 if (drv_data
->state
== RUNNING_STATE
) {
389 dev_dbg(drv_data
->dev
, "transfer: still running ...\n");
390 previous
= list_entry(transfer
->transfer_list
.prev
,
391 struct spi_transfer
, transfer_list
);
392 if (previous
->delay_usecs
)
393 udelay(previous
->delay_usecs
);
396 if (transfer
->len
== 0) {
397 /* Move to next transfer of this msg */
398 drv_data
->state
= bfin_sport_spi_next_transfer(drv_data
);
399 /* Schedule next transfer tasklet */
400 tasklet_schedule(&drv_data
->pump_transfers
);
403 if (transfer
->tx_buf
!= NULL
) {
404 drv_data
->tx
= (void *)transfer
->tx_buf
;
405 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
406 dev_dbg(drv_data
->dev
, "tx_buf is %p, tx_end is %p\n",
407 transfer
->tx_buf
, drv_data
->tx_end
);
411 if (transfer
->rx_buf
!= NULL
) {
412 full_duplex
= transfer
->tx_buf
!= NULL
;
413 drv_data
->rx
= transfer
->rx_buf
;
414 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
415 dev_dbg(drv_data
->dev
, "rx_buf is %p, rx_end is %p\n",
416 transfer
->rx_buf
, drv_data
->rx_end
);
420 drv_data
->cs_change
= transfer
->cs_change
;
422 /* Bits per word setup */
423 bits_per_word
= transfer
->bits_per_word
? : message
->spi
->bits_per_word
;
424 if (bits_per_word
== 8)
425 drv_data
->ops
= &bfin_sport_transfer_ops_u8
;
427 drv_data
->ops
= &bfin_sport_transfer_ops_u16
;
429 drv_data
->state
= RUNNING_STATE
;
431 if (drv_data
->cs_change
)
432 bfin_sport_spi_cs_active(chip
);
434 dev_dbg(drv_data
->dev
,
435 "now pumping a transfer: width is %d, len is %d\n",
436 bits_per_word
, transfer
->len
);
438 /* PIO mode write then read */
439 dev_dbg(drv_data
->dev
, "doing IO transfer\n");
441 bfin_sport_spi_enable(drv_data
);
443 /* full duplex mode */
444 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
445 (drv_data
->rx_end
- drv_data
->rx
));
446 drv_data
->ops
->duplex(drv_data
);
448 if (drv_data
->tx
!= drv_data
->tx_end
)
450 } else if (drv_data
->tx
!= NULL
) {
451 /* write only half duplex */
453 drv_data
->ops
->write(drv_data
);
455 if (drv_data
->tx
!= drv_data
->tx_end
)
457 } else if (drv_data
->rx
!= NULL
) {
458 /* read only half duplex */
460 drv_data
->ops
->read(drv_data
);
461 if (drv_data
->rx
!= drv_data
->rx_end
)
464 bfin_sport_spi_disable(drv_data
);
466 if (!tranf_success
) {
467 dev_dbg(drv_data
->dev
, "IO write error!\n");
468 drv_data
->state
= ERROR_STATE
;
470 /* Update total byte transfered */
471 message
->actual_length
+= transfer
->len
;
472 /* Move to next transfer of this msg */
473 drv_data
->state
= bfin_sport_spi_next_transfer(drv_data
);
474 if (drv_data
->cs_change
)
475 bfin_sport_spi_cs_deactive(chip
);
478 /* Schedule next transfer tasklet */
479 tasklet_schedule(&drv_data
->pump_transfers
);
482 /* pop a msg from queue and kick off real transfer */
484 bfin_sport_spi_pump_messages(struct work_struct
*work
)
486 struct bfin_sport_spi_master_data
*drv_data
;
488 struct spi_message
*next_msg
;
490 drv_data
= container_of(work
, struct bfin_sport_spi_master_data
, pump_messages
);
492 /* Lock queue and check for queue work */
493 spin_lock_irqsave(&drv_data
->lock
, flags
);
494 if (list_empty(&drv_data
->queue
) || !drv_data
->run
) {
495 /* pumper kicked off but no work to do */
497 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
501 /* Make sure we are not already running a message */
502 if (drv_data
->cur_msg
) {
503 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
507 /* Extract head of queue */
508 next_msg
= list_entry(drv_data
->queue
.next
,
509 struct spi_message
, queue
);
511 drv_data
->cur_msg
= next_msg
;
513 /* Setup the SSP using the per chip configuration */
514 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
516 list_del_init(&drv_data
->cur_msg
->queue
);
518 /* Initialize message state */
519 drv_data
->cur_msg
->state
= START_STATE
;
520 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
521 struct spi_transfer
, transfer_list
);
522 bfin_sport_spi_restore_state(drv_data
);
523 dev_dbg(drv_data
->dev
, "got a message to pump, "
524 "state is set to: baud %d, cs_gpio %i, ctl 0x%x\n",
525 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->cs_gpio
,
526 drv_data
->cur_chip
->ctl_reg
);
528 dev_dbg(drv_data
->dev
,
529 "the first transfer len is %d\n",
530 drv_data
->cur_transfer
->len
);
532 /* Mark as busy and launch transfers */
533 tasklet_schedule(&drv_data
->pump_transfers
);
536 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
540 * got a msg to transfer, queue it in drv_data->queue.
541 * And kick off message pumper
544 bfin_sport_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
546 struct bfin_sport_spi_master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
549 spin_lock_irqsave(&drv_data
->lock
, flags
);
551 if (!drv_data
->run
) {
552 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
556 msg
->actual_length
= 0;
557 msg
->status
= -EINPROGRESS
;
558 msg
->state
= START_STATE
;
560 dev_dbg(&spi
->dev
, "adding an msg in transfer()\n");
561 list_add_tail(&msg
->queue
, &drv_data
->queue
);
563 if (drv_data
->run
&& !drv_data
->busy
)
564 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
566 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
571 /* Called every time common spi devices change state */
573 bfin_sport_spi_setup(struct spi_device
*spi
)
575 struct bfin_sport_spi_slave_data
*chip
, *first
= NULL
;
578 /* Only alloc (or use chip_info) on first setup */
579 chip
= spi_get_ctldata(spi
);
581 struct bfin5xx_spi_chip
*chip_info
;
583 chip
= first
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
587 /* platform chip_info isn't required */
588 chip_info
= spi
->controller_data
;
591 * DITFS and TDTYPE are only thing we don't set, but
592 * they probably shouldn't be changed by people.
594 if (chip_info
->ctl_reg
|| chip_info
->enable_dma
) {
596 dev_err(&spi
->dev
, "don't set ctl_reg/enable_dma fields");
599 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
600 chip
->idle_tx_val
= chip_info
->idle_tx_val
;
601 spi
->bits_per_word
= chip_info
->bits_per_word
;
605 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16) {
610 /* translate common spi framework into our register
611 * following configure contents are same for tx and rx.
614 if (spi
->mode
& SPI_CPHA
)
615 chip
->ctl_reg
&= ~TCKFE
;
617 chip
->ctl_reg
|= TCKFE
;
619 if (spi
->mode
& SPI_LSB_FIRST
)
620 chip
->ctl_reg
|= TLSBIT
;
622 chip
->ctl_reg
&= ~TLSBIT
;
624 /* Sport in master mode */
625 chip
->ctl_reg
|= ITCLK
| ITFS
| TFSR
| LATFS
| LTFS
;
627 chip
->baud
= bfin_sport_hz_to_spi_baud(spi
->max_speed_hz
);
629 chip
->cs_gpio
= spi
->chip_select
;
630 ret
= gpio_request(chip
->cs_gpio
, spi
->modalias
);
634 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d\n",
635 spi
->modalias
, spi
->bits_per_word
);
636 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, GPIO is %i\n",
637 chip
->ctl_reg
, spi
->chip_select
);
639 spi_set_ctldata(spi
, chip
);
641 bfin_sport_spi_cs_deactive(chip
);
651 * callback for spi framework.
652 * clean driver specific data
655 bfin_sport_spi_cleanup(struct spi_device
*spi
)
657 struct bfin_sport_spi_slave_data
*chip
= spi_get_ctldata(spi
);
662 gpio_free(chip
->cs_gpio
);
668 bfin_sport_spi_init_queue(struct bfin_sport_spi_master_data
*drv_data
)
670 INIT_LIST_HEAD(&drv_data
->queue
);
671 spin_lock_init(&drv_data
->lock
);
673 drv_data
->run
= false;
676 /* init transfer tasklet */
677 tasklet_init(&drv_data
->pump_transfers
,
678 bfin_sport_spi_pump_transfers
, (unsigned long)drv_data
);
680 /* init messages workqueue */
681 INIT_WORK(&drv_data
->pump_messages
, bfin_sport_spi_pump_messages
);
682 drv_data
->workqueue
=
683 create_singlethread_workqueue(dev_name(drv_data
->master
->dev
.parent
));
684 if (drv_data
->workqueue
== NULL
)
691 bfin_sport_spi_start_queue(struct bfin_sport_spi_master_data
*drv_data
)
695 spin_lock_irqsave(&drv_data
->lock
, flags
);
697 if (drv_data
->run
|| drv_data
->busy
) {
698 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
702 drv_data
->run
= true;
703 drv_data
->cur_msg
= NULL
;
704 drv_data
->cur_transfer
= NULL
;
705 drv_data
->cur_chip
= NULL
;
706 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
708 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
714 bfin_sport_spi_stop_queue(struct bfin_sport_spi_master_data
*drv_data
)
717 unsigned limit
= 500;
720 spin_lock_irqsave(&drv_data
->lock
, flags
);
723 * This is a bit lame, but is optimized for the common execution path.
724 * A wait_queue on the drv_data->busy could be used, but then the common
725 * execution path (pump_messages) would be required to call wake_up or
726 * friends on every SPI message. Do this instead
728 drv_data
->run
= false;
729 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
730 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
732 spin_lock_irqsave(&drv_data
->lock
, flags
);
735 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
738 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
744 bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data
*drv_data
)
748 status
= bfin_sport_spi_stop_queue(drv_data
);
752 destroy_workqueue(drv_data
->workqueue
);
758 bfin_sport_spi_probe(struct platform_device
*pdev
)
760 struct device
*dev
= &pdev
->dev
;
761 struct bfin5xx_spi_master
*platform_info
;
762 struct spi_master
*master
;
763 struct resource
*res
, *ires
;
764 struct bfin_sport_spi_master_data
*drv_data
;
767 platform_info
= dev
->platform_data
;
769 /* Allocate master with space for drv_data */
770 master
= spi_alloc_master(dev
, sizeof(*master
) + 16);
772 dev_err(dev
, "cannot alloc spi_master\n");
776 drv_data
= spi_master_get_devdata(master
);
777 drv_data
->master
= master
;
779 drv_data
->pin_req
= platform_info
->pin_req
;
781 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
782 master
->bus_num
= pdev
->id
;
783 master
->num_chipselect
= platform_info
->num_chipselect
;
784 master
->cleanup
= bfin_sport_spi_cleanup
;
785 master
->setup
= bfin_sport_spi_setup
;
786 master
->transfer
= bfin_sport_spi_transfer
;
788 /* Find and map our resources */
789 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
791 dev_err(dev
, "cannot get IORESOURCE_MEM\n");
793 goto out_error_get_res
;
796 drv_data
->regs
= ioremap(res
->start
, resource_size(res
));
797 if (drv_data
->regs
== NULL
) {
798 dev_err(dev
, "cannot map registers\n");
800 goto out_error_ioremap
;
803 ires
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
805 dev_err(dev
, "cannot get IORESOURCE_IRQ\n");
807 goto out_error_get_ires
;
809 drv_data
->err_irq
= ires
->start
;
811 /* Initial and start queue */
812 status
= bfin_sport_spi_init_queue(drv_data
);
814 dev_err(dev
, "problem initializing queue\n");
815 goto out_error_queue_alloc
;
818 status
= bfin_sport_spi_start_queue(drv_data
);
820 dev_err(dev
, "problem starting queue\n");
821 goto out_error_queue_alloc
;
824 status
= request_irq(drv_data
->err_irq
, sport_err_handler
,
825 0, "sport_spi_err", drv_data
);
827 dev_err(dev
, "unable to request sport err irq\n");
831 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
833 dev_err(dev
, "requesting peripherals failed\n");
834 goto out_error_peripheral
;
837 /* Register with the SPI framework */
838 platform_set_drvdata(pdev
, drv_data
);
839 status
= spi_register_master(master
);
841 dev_err(dev
, "problem registering spi master\n");
842 goto out_error_master
;
845 dev_info(dev
, "%s, regs_base@%p\n", DRV_DESC
, drv_data
->regs
);
849 peripheral_free_list(drv_data
->pin_req
);
850 out_error_peripheral
:
851 free_irq(drv_data
->err_irq
, drv_data
);
853 out_error_queue_alloc
:
854 bfin_sport_spi_destroy_queue(drv_data
);
856 iounmap(drv_data
->regs
);
859 spi_master_put(master
);
864 /* stop hardware and remove the driver */
866 bfin_sport_spi_remove(struct platform_device
*pdev
)
868 struct bfin_sport_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
874 /* Remove the queue */
875 status
= bfin_sport_spi_destroy_queue(drv_data
);
879 /* Disable the SSP at the peripheral and SOC level */
880 bfin_sport_spi_disable(drv_data
);
882 /* Disconnect from the SPI framework */
883 spi_unregister_master(drv_data
->master
);
885 peripheral_free_list(drv_data
->pin_req
);
887 /* Prevent double remove */
888 platform_set_drvdata(pdev
, NULL
);
895 bfin_sport_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
897 struct bfin_sport_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
900 status
= bfin_sport_spi_stop_queue(drv_data
);
905 bfin_sport_spi_disable(drv_data
);
911 bfin_sport_spi_resume(struct platform_device
*pdev
)
913 struct bfin_sport_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
916 /* Enable the SPI interface */
917 bfin_sport_spi_enable(drv_data
);
919 /* Start the queue running */
920 status
= bfin_sport_spi_start_queue(drv_data
);
922 dev_err(drv_data
->dev
, "problem resuming queue\n");
927 # define bfin_sport_spi_suspend NULL
928 # define bfin_sport_spi_resume NULL
931 static struct platform_driver bfin_sport_spi_driver
= {
934 .owner
= THIS_MODULE
,
936 .probe
= bfin_sport_spi_probe
,
937 .remove
= __devexit_p(bfin_sport_spi_remove
),
938 .suspend
= bfin_sport_spi_suspend
,
939 .resume
= bfin_sport_spi_resume
,
941 module_platform_driver(bfin_sport_spi_driver
);