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ahci: jmb361 has only one port
[linux-2.6.git] / drivers / ata / ahci.c
blob29f34d03bd75bd207c169d58e6d846954f3b7947
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6,
93
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
100
101 /* HOST_CTL bits */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
105
106 /* HOST_CAP bits */
107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
115
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
132
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152
153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
154 PORT_IRQ_IF_ERR |
155 PORT_IRQ_CONNECT |
156 PORT_IRQ_PHYRDY |
157 PORT_IRQ_UNK_FIS |
158 PORT_IRQ_BAD_PMP,
159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_TF_ERR |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
165
166 /* PORT_CMD bits */
167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
174 PORT_CMD_CLO = (1 << 3), /* Command list override */
175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178
179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
183
184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
194 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
195
196 /* ap->flags bits */
197
198 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
199 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
200 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
201 ATA_FLAG_IPM,
202
203 ICH_MAP = 0x90, /* ICH MAP register */
204 };
205
206 struct ahci_cmd_hdr {
207 __le32 opts;
208 __le32 status;
209 __le32 tbl_addr;
210 __le32 tbl_addr_hi;
211 __le32 reserved[4];
212 };
213
214 struct ahci_sg {
215 __le32 addr;
216 __le32 addr_hi;
217 __le32 reserved;
218 __le32 flags_size;
219 };
220
221 struct ahci_host_priv {
222 unsigned int flags; /* AHCI_HFLAG_* */
223 u32 cap; /* cap to use */
224 u32 port_map; /* port map to use */
225 u32 saved_cap; /* saved initial cap */
226 u32 saved_port_map; /* saved initial port_map */
227 };
228
229 struct ahci_port_priv {
230 struct ata_link *active_link;
231 struct ahci_cmd_hdr *cmd_slot;
232 dma_addr_t cmd_slot_dma;
233 void *cmd_tbl;
234 dma_addr_t cmd_tbl_dma;
235 void *rx_fis;
236 dma_addr_t rx_fis_dma;
237 /* for NCQ spurious interrupt analysis */
238 unsigned int ncq_saw_d2h:1;
239 unsigned int ncq_saw_dmas:1;
240 unsigned int ncq_saw_sdb:1;
241 u32 intr_mask; /* interrupts to enable */
242 };
243
244 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
245 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
246 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
247 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
248 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
249 static int ahci_port_start(struct ata_port *ap);
250 static void ahci_port_stop(struct ata_port *ap);
251 static void ahci_qc_prep(struct ata_queued_cmd *qc);
252 static void ahci_freeze(struct ata_port *ap);
253 static void ahci_thaw(struct ata_port *ap);
254 static void ahci_pmp_attach(struct ata_port *ap);
255 static void ahci_pmp_detach(struct ata_port *ap);
256 static int ahci_softreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline);
258 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline);
260 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
261 unsigned long deadline);
262 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
263 unsigned long deadline);
264 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
265 unsigned long deadline);
266 static void ahci_postreset(struct ata_link *link, unsigned int *class);
267 static void ahci_error_handler(struct ata_port *ap);
268 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
269 static int ahci_port_resume(struct ata_port *ap);
270 static void ahci_dev_config(struct ata_device *dev);
271 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
272 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
273 u32 opts);
274 #ifdef CONFIG_PM
275 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
276 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
277 static int ahci_pci_device_resume(struct pci_dev *pdev);
278 #endif
279
280 static struct device_attribute *ahci_shost_attrs[] = {
281 &dev_attr_link_power_management_policy,
282 NULL
283 };
284
285 static struct scsi_host_template ahci_sht = {
286 ATA_NCQ_SHT(DRV_NAME),
287 .can_queue = AHCI_MAX_CMDS - 1,
288 .sg_tablesize = AHCI_MAX_SG,
289 .dma_boundary = AHCI_DMA_BOUNDARY,
290 .shost_attrs = ahci_shost_attrs,
291 };
292
293 static struct ata_port_operations ahci_ops = {
294 .inherits = &sata_pmp_port_ops,
295
296 .qc_defer = sata_pmp_qc_defer_cmd_switch,
297 .qc_prep = ahci_qc_prep,
298 .qc_issue = ahci_qc_issue,
299 .qc_fill_rtf = ahci_qc_fill_rtf,
300
301 .freeze = ahci_freeze,
302 .thaw = ahci_thaw,
303 .softreset = ahci_softreset,
304 .hardreset = ahci_hardreset,
305 .postreset = ahci_postreset,
306 .pmp_softreset = ahci_softreset,
307 .error_handler = ahci_error_handler,
308 .post_internal_cmd = ahci_post_internal_cmd,
309 .dev_config = ahci_dev_config,
310
311 .scr_read = ahci_scr_read,
312 .scr_write = ahci_scr_write,
313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
315
316 .enable_pm = ahci_enable_alpm,
317 .disable_pm = ahci_disable_alpm,
318 #ifdef CONFIG_PM
319 .port_suspend = ahci_port_suspend,
320 .port_resume = ahci_port_resume,
321 #endif
322 .port_start = ahci_port_start,
323 .port_stop = ahci_port_stop,
324 };
325
326 static struct ata_port_operations ahci_vt8251_ops = {
327 .inherits = &ahci_ops,
328 .hardreset = ahci_vt8251_hardreset,
329 };
330
331 static struct ata_port_operations ahci_p5wdh_ops = {
332 .inherits = &ahci_ops,
333 .hardreset = ahci_p5wdh_hardreset,
334 };
335
336 static struct ata_port_operations ahci_sb600_ops = {
337 .inherits = &ahci_ops,
338 .softreset = ahci_sb600_softreset,
339 .pmp_softreset = ahci_sb600_softreset,
340 };
341
342 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
343
344 static const struct ata_port_info ahci_port_info[] = {
345 /* board_ahci */
346 {
347 .flags = AHCI_FLAG_COMMON,
348 .pio_mask = 0x1f, /* pio0-4 */
349 .udma_mask = ATA_UDMA6,
350 .port_ops = &ahci_ops,
351 },
352 /* board_ahci_vt8251 */
353 {
354 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
355 .flags = AHCI_FLAG_COMMON,
356 .pio_mask = 0x1f, /* pio0-4 */
357 .udma_mask = ATA_UDMA6,
358 .port_ops = &ahci_vt8251_ops,
359 },
360 /* board_ahci_ign_iferr */
361 {
362 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
363 .flags = AHCI_FLAG_COMMON,
364 .pio_mask = 0x1f, /* pio0-4 */
365 .udma_mask = ATA_UDMA6,
366 .port_ops = &ahci_ops,
367 },
368 /* board_ahci_sb600 */
369 {
370 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
371 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
372 AHCI_HFLAG_SECT255),
373 .flags = AHCI_FLAG_COMMON,
374 .pio_mask = 0x1f, /* pio0-4 */
375 .udma_mask = ATA_UDMA6,
376 .port_ops = &ahci_sb600_ops,
377 },
378 /* board_ahci_mv */
379 {
380 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
381 AHCI_HFLAG_MV_PATA),
382 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
383 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
384 .pio_mask = 0x1f, /* pio0-4 */
385 .udma_mask = ATA_UDMA6,
386 .port_ops = &ahci_ops,
387 },
388 /* board_ahci_sb700 */
389 {
390 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
391 .flags = AHCI_FLAG_COMMON,
392 .pio_mask = 0x1f, /* pio0-4 */
393 .udma_mask = ATA_UDMA6,
394 .port_ops = &ahci_sb600_ops,
395 },
396 /* board_ahci_mcp65 */
397 {
398 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
399 .flags = AHCI_FLAG_COMMON,
400 .pio_mask = 0x1f, /* pio0-4 */
401 .udma_mask = ATA_UDMA6,
402 .port_ops = &ahci_ops,
403 },
404 };
405
406 static const struct pci_device_id ahci_pci_tbl[] = {
407 /* Intel */
408 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
409 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
410 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
411 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
412 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
413 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
414 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
415 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
416 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
417 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
418 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
419 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
420 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
421 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
422 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
423 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
424 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
425 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
426 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
427 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
428 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
429 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
430 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
431 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
432 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
433 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
434 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
435 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
436 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
437 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
438 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
439
440 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
441 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
442 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
443
444 /* ATI */
445 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
446 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
451 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
452
453 /* VIA */
454 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
455 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
456
457 /* NVIDIA */
458 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
484 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
505 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
506 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
508 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
515 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
516 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
517 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
518 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
519 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
520 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
521 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
522 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
523 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
524 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
525 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
526
527 /* SiS */
528 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
529 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
530 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
531
532 /* Marvell */
533 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
534 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
535
536 /* Generic, PCI class code for AHCI */
537 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
538 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
539
540 { } /* terminate list */
541 };
542
543
544 static struct pci_driver ahci_pci_driver = {
545 .name = DRV_NAME,
546 .id_table = ahci_pci_tbl,
547 .probe = ahci_init_one,
548 .remove = ata_pci_remove_one,
549 #ifdef CONFIG_PM
550 .suspend = ahci_pci_device_suspend,
551 .resume = ahci_pci_device_resume,
552 #endif
553 };
554
555
556 static inline int ahci_nr_ports(u32 cap)
557 {
558 return (cap & 0x1f) + 1;
559 }
560
561 static inline void __iomem *__ahci_port_base(struct ata_host *host,
562 unsigned int port_no)
563 {
564 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
565
566 return mmio + 0x100 + (port_no * 0x80);
567 }
568
569 static inline void __iomem *ahci_port_base(struct ata_port *ap)
570 {
571 return __ahci_port_base(ap->host, ap->port_no);
572 }
573
574 static void ahci_enable_ahci(void __iomem *mmio)
575 {
576 int i;
577 u32 tmp;
578
579 /* turn on AHCI_EN */
580 tmp = readl(mmio + HOST_CTL);
581 if (tmp & HOST_AHCI_EN)
582 return;
583
584 /* Some controllers need AHCI_EN to be written multiple times.
585 * Try a few times before giving up.
586 */
587 for (i = 0; i < 5; i++) {
588 tmp |= HOST_AHCI_EN;
589 writel(tmp, mmio + HOST_CTL);
590 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
591 if (tmp & HOST_AHCI_EN)
592 return;
593 msleep(10);
594 }
595
596 WARN_ON(1);
597 }
598
599 /**
600 * ahci_save_initial_config - Save and fixup initial config values
601 * @pdev: target PCI device
602 * @hpriv: host private area to store config values
603 *
604 * Some registers containing configuration info might be setup by
605 * BIOS and might be cleared on reset. This function saves the
606 * initial values of those registers into @hpriv such that they
607 * can be restored after controller reset.
608 *
609 * If inconsistent, config values are fixed up by this function.
610 *
611 * LOCKING:
612 * None.
613 */
614 static void ahci_save_initial_config(struct pci_dev *pdev,
615 struct ahci_host_priv *hpriv)
616 {
617 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
618 u32 cap, port_map;
619 int i;
620 int mv;
621
622 /* make sure AHCI mode is enabled before accessing CAP */
623 ahci_enable_ahci(mmio);
624
625 /* Values prefixed with saved_ are written back to host after
626 * reset. Values without are used for driver operation.
627 */
628 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
629 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
630
631 /* some chips have errata preventing 64bit use */
632 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
633 dev_printk(KERN_INFO, &pdev->dev,
634 "controller can't do 64bit DMA, forcing 32bit\n");
635 cap &= ~HOST_CAP_64;
636 }
637
638 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
639 dev_printk(KERN_INFO, &pdev->dev,
640 "controller can't do NCQ, turning off CAP_NCQ\n");
641 cap &= ~HOST_CAP_NCQ;
642 }
643
644 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
645 dev_printk(KERN_INFO, &pdev->dev,
646 "controller can do NCQ, turning on CAP_NCQ\n");
647 cap |= HOST_CAP_NCQ;
648 }
649
650 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
651 dev_printk(KERN_INFO, &pdev->dev,
652 "controller can't do PMP, turning off CAP_PMP\n");
653 cap &= ~HOST_CAP_PMP;
654 }
655
656 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
657 port_map != 1) {
658 dev_printk(KERN_INFO, &pdev->dev,
659 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
660 port_map, 1);
661 port_map = 1;
662 }
663
664 /*
665 * Temporary Marvell 6145 hack: PATA port presence
666 * is asserted through the standard AHCI port
667 * presence register, as bit 4 (counting from 0)
668 */
669 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
670 if (pdev->device == 0x6121)
671 mv = 0x3;
672 else
673 mv = 0xf;
674 dev_printk(KERN_ERR, &pdev->dev,
675 "MV_AHCI HACK: port_map %x -> %x\n",
676 port_map,
677 port_map & mv);
678
679 port_map &= mv;
680 }
681
682 /* cross check port_map and cap.n_ports */
683 if (port_map) {
684 int map_ports = 0;
685
686 for (i = 0; i < AHCI_MAX_PORTS; i++)
687 if (port_map & (1 << i))
688 map_ports++;
689
690 /* If PI has more ports than n_ports, whine, clear
691 * port_map and let it be generated from n_ports.
692 */
693 if (map_ports > ahci_nr_ports(cap)) {
694 dev_printk(KERN_WARNING, &pdev->dev,
695 "implemented port map (0x%x) contains more "
696 "ports than nr_ports (%u), using nr_ports\n",
697 port_map, ahci_nr_ports(cap));
698 port_map = 0;
699 }
700 }
701
702 /* fabricate port_map from cap.nr_ports */
703 if (!port_map) {
704 port_map = (1 << ahci_nr_ports(cap)) - 1;
705 dev_printk(KERN_WARNING, &pdev->dev,
706 "forcing PORTS_IMPL to 0x%x\n", port_map);
707
708 /* write the fixed up value to the PI register */
709 hpriv->saved_port_map = port_map;
710 }
711
712 /* record values to use during operation */
713 hpriv->cap = cap;
714 hpriv->port_map = port_map;
715 }
716
717 /**
718 * ahci_restore_initial_config - Restore initial config
719 * @host: target ATA host
720 *
721 * Restore initial config stored by ahci_save_initial_config().
722 *
723 * LOCKING:
724 * None.
725 */
726 static void ahci_restore_initial_config(struct ata_host *host)
727 {
728 struct ahci_host_priv *hpriv = host->private_data;
729 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
730
731 writel(hpriv->saved_cap, mmio + HOST_CAP);
732 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
733 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
734 }
735
736 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
737 {
738 static const int offset[] = {
739 [SCR_STATUS] = PORT_SCR_STAT,
740 [SCR_CONTROL] = PORT_SCR_CTL,
741 [SCR_ERROR] = PORT_SCR_ERR,
742 [SCR_ACTIVE] = PORT_SCR_ACT,
743 [SCR_NOTIFICATION] = PORT_SCR_NTF,
744 };
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746
747 if (sc_reg < ARRAY_SIZE(offset) &&
748 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
749 return offset[sc_reg];
750 return 0;
751 }
752
753 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
754 {
755 void __iomem *port_mmio = ahci_port_base(ap);
756 int offset = ahci_scr_offset(ap, sc_reg);
757
758 if (offset) {
759 *val = readl(port_mmio + offset);
760 return 0;
761 }
762 return -EINVAL;
763 }
764
765 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
766 {
767 void __iomem *port_mmio = ahci_port_base(ap);
768 int offset = ahci_scr_offset(ap, sc_reg);
769
770 if (offset) {
771 writel(val, port_mmio + offset);
772 return 0;
773 }
774 return -EINVAL;
775 }
776
777 static void ahci_start_engine(struct ata_port *ap)
778 {
779 void __iomem *port_mmio = ahci_port_base(ap);
780 u32 tmp;
781
782 /* start DMA */
783 tmp = readl(port_mmio + PORT_CMD);
784 tmp |= PORT_CMD_START;
785 writel(tmp, port_mmio + PORT_CMD);
786 readl(port_mmio + PORT_CMD); /* flush */
787 }
788
789 static int ahci_stop_engine(struct ata_port *ap)
790 {
791 void __iomem *port_mmio = ahci_port_base(ap);
792 u32 tmp;
793
794 tmp = readl(port_mmio + PORT_CMD);
795
796 /* check if the HBA is idle */
797 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
798 return 0;
799
800 /* setting HBA to idle */
801 tmp &= ~PORT_CMD_START;
802 writel(tmp, port_mmio + PORT_CMD);
803
804 /* wait for engine to stop. This could be as long as 500 msec */
805 tmp = ata_wait_register(port_mmio + PORT_CMD,
806 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
807 if (tmp & PORT_CMD_LIST_ON)
808 return -EIO;
809
810 return 0;
811 }
812
813 static void ahci_start_fis_rx(struct ata_port *ap)
814 {
815 void __iomem *port_mmio = ahci_port_base(ap);
816 struct ahci_host_priv *hpriv = ap->host->private_data;
817 struct ahci_port_priv *pp = ap->private_data;
818 u32 tmp;
819
820 /* set FIS registers */
821 if (hpriv->cap & HOST_CAP_64)
822 writel((pp->cmd_slot_dma >> 16) >> 16,
823 port_mmio + PORT_LST_ADDR_HI);
824 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
825
826 if (hpriv->cap & HOST_CAP_64)
827 writel((pp->rx_fis_dma >> 16) >> 16,
828 port_mmio + PORT_FIS_ADDR_HI);
829 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
830
831 /* enable FIS reception */
832 tmp = readl(port_mmio + PORT_CMD);
833 tmp |= PORT_CMD_FIS_RX;
834 writel(tmp, port_mmio + PORT_CMD);
835
836 /* flush */
837 readl(port_mmio + PORT_CMD);
838 }
839
840 static int ahci_stop_fis_rx(struct ata_port *ap)
841 {
842 void __iomem *port_mmio = ahci_port_base(ap);
843 u32 tmp;
844
845 /* disable FIS reception */
846 tmp = readl(port_mmio + PORT_CMD);
847 tmp &= ~PORT_CMD_FIS_RX;
848 writel(tmp, port_mmio + PORT_CMD);
849
850 /* wait for completion, spec says 500ms, give it 1000 */
851 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
852 PORT_CMD_FIS_ON, 10, 1000);
853 if (tmp & PORT_CMD_FIS_ON)
854 return -EBUSY;
855
856 return 0;
857 }
858
859 static void ahci_power_up(struct ata_port *ap)
860 {
861 struct ahci_host_priv *hpriv = ap->host->private_data;
862 void __iomem *port_mmio = ahci_port_base(ap);
863 u32 cmd;
864
865 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
866
867 /* spin up device */
868 if (hpriv->cap & HOST_CAP_SSS) {
869 cmd |= PORT_CMD_SPIN_UP;
870 writel(cmd, port_mmio + PORT_CMD);
871 }
872
873 /* wake up link */
874 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
875 }
876
877 static void ahci_disable_alpm(struct ata_port *ap)
878 {
879 struct ahci_host_priv *hpriv = ap->host->private_data;
880 void __iomem *port_mmio = ahci_port_base(ap);
881 u32 cmd;
882 struct ahci_port_priv *pp = ap->private_data;
883
884 /* IPM bits should be disabled by libata-core */
885 /* get the existing command bits */
886 cmd = readl(port_mmio + PORT_CMD);
887
888 /* disable ALPM and ASP */
889 cmd &= ~PORT_CMD_ASP;
890 cmd &= ~PORT_CMD_ALPE;
891
892 /* force the interface back to active */
893 cmd |= PORT_CMD_ICC_ACTIVE;
894
895 /* write out new cmd value */
896 writel(cmd, port_mmio + PORT_CMD);
897 cmd = readl(port_mmio + PORT_CMD);
898
899 /* wait 10ms to be sure we've come out of any low power state */
900 msleep(10);
901
902 /* clear out any PhyRdy stuff from interrupt status */
903 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
904
905 /* go ahead and clean out PhyRdy Change from Serror too */
906 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
907
908 /*
909 * Clear flag to indicate that we should ignore all PhyRdy
910 * state changes
911 */
912 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
913
914 /*
915 * Enable interrupts on Phy Ready.
916 */
917 pp->intr_mask |= PORT_IRQ_PHYRDY;
918 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
919
920 /*
921 * don't change the link pm policy - we can be called
922 * just to turn of link pm temporarily
923 */
924 }
925
926 static int ahci_enable_alpm(struct ata_port *ap,
927 enum link_pm policy)
928 {
929 struct ahci_host_priv *hpriv = ap->host->private_data;
930 void __iomem *port_mmio = ahci_port_base(ap);
931 u32 cmd;
932 struct ahci_port_priv *pp = ap->private_data;
933 u32 asp;
934
935 /* Make sure the host is capable of link power management */
936 if (!(hpriv->cap & HOST_CAP_ALPM))
937 return -EINVAL;
938
939 switch (policy) {
940 case MAX_PERFORMANCE:
941 case NOT_AVAILABLE:
942 /*
943 * if we came here with NOT_AVAILABLE,
944 * it just means this is the first time we
945 * have tried to enable - default to max performance,
946 * and let the user go to lower power modes on request.
947 */
948 ahci_disable_alpm(ap);
949 return 0;
950 case MIN_POWER:
951 /* configure HBA to enter SLUMBER */
952 asp = PORT_CMD_ASP;
953 break;
954 case MEDIUM_POWER:
955 /* configure HBA to enter PARTIAL */
956 asp = 0;
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 /*
963 * Disable interrupts on Phy Ready. This keeps us from
964 * getting woken up due to spurious phy ready interrupts
965 * TBD - Hot plug should be done via polling now, is
966 * that even supported?
967 */
968 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
969 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
970
971 /*
972 * Set a flag to indicate that we should ignore all PhyRdy
973 * state changes since these can happen now whenever we
974 * change link state
975 */
976 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
977
978 /* get the existing command bits */
979 cmd = readl(port_mmio + PORT_CMD);
980
981 /*
982 * Set ASP based on Policy
983 */
984 cmd |= asp;
985
986 /*
987 * Setting this bit will instruct the HBA to aggressively
988 * enter a lower power link state when it's appropriate and
989 * based on the value set above for ASP
990 */
991 cmd |= PORT_CMD_ALPE;
992
993 /* write out new cmd value */
994 writel(cmd, port_mmio + PORT_CMD);
995 cmd = readl(port_mmio + PORT_CMD);
996
997 /* IPM bits should be set by libata-core */
998 return 0;
999 }
1000
1001 #ifdef CONFIG_PM
1002 static void ahci_power_down(struct ata_port *ap)
1003 {
1004 struct ahci_host_priv *hpriv = ap->host->private_data;
1005 void __iomem *port_mmio = ahci_port_base(ap);
1006 u32 cmd, scontrol;
1007
1008 if (!(hpriv->cap & HOST_CAP_SSS))
1009 return;
1010
1011 /* put device into listen mode, first set PxSCTL.DET to 0 */
1012 scontrol = readl(port_mmio + PORT_SCR_CTL);
1013 scontrol &= ~0xf;
1014 writel(scontrol, port_mmio + PORT_SCR_CTL);
1015
1016 /* then set PxCMD.SUD to 0 */
1017 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1018 cmd &= ~PORT_CMD_SPIN_UP;
1019 writel(cmd, port_mmio + PORT_CMD);
1020 }
1021 #endif
1022
1023 static void ahci_start_port(struct ata_port *ap)
1024 {
1025 /* enable FIS reception */
1026 ahci_start_fis_rx(ap);
1027
1028 /* enable DMA */
1029 ahci_start_engine(ap);
1030 }
1031
1032 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1033 {
1034 int rc;
1035
1036 /* disable DMA */
1037 rc = ahci_stop_engine(ap);
1038 if (rc) {
1039 *emsg = "failed to stop engine";
1040 return rc;
1041 }
1042
1043 /* disable FIS reception */
1044 rc = ahci_stop_fis_rx(ap);
1045 if (rc) {
1046 *emsg = "failed stop FIS RX";
1047 return rc;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int ahci_reset_controller(struct ata_host *host)
1054 {
1055 struct pci_dev *pdev = to_pci_dev(host->dev);
1056 struct ahci_host_priv *hpriv = host->private_data;
1057 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1058 u32 tmp;
1059
1060 /* we must be in AHCI mode, before using anything
1061 * AHCI-specific, such as HOST_RESET.
1062 */
1063 ahci_enable_ahci(mmio);
1064
1065 /* global controller reset */
1066 if (!ahci_skip_host_reset) {
1067 tmp = readl(mmio + HOST_CTL);
1068 if ((tmp & HOST_RESET) == 0) {
1069 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1070 readl(mmio + HOST_CTL); /* flush */
1071 }
1072
1073 /* reset must complete within 1 second, or
1074 * the hardware should be considered fried.
1075 */
1076 ssleep(1);
1077
1078 tmp = readl(mmio + HOST_CTL);
1079 if (tmp & HOST_RESET) {
1080 dev_printk(KERN_ERR, host->dev,
1081 "controller reset failed (0x%x)\n", tmp);
1082 return -EIO;
1083 }
1084
1085 /* turn on AHCI mode */
1086 ahci_enable_ahci(mmio);
1087
1088 /* Some registers might be cleared on reset. Restore
1089 * initial values.
1090 */
1091 ahci_restore_initial_config(host);
1092 } else
1093 dev_printk(KERN_INFO, host->dev,
1094 "skipping global host reset\n");
1095
1096 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1097 u16 tmp16;
1098
1099 /* configure PCS */
1100 pci_read_config_word(pdev, 0x92, &tmp16);
1101 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1102 tmp16 |= hpriv->port_map;
1103 pci_write_config_word(pdev, 0x92, tmp16);
1104 }
1105 }
1106
1107 return 0;
1108 }
1109
1110 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1111 int port_no, void __iomem *mmio,
1112 void __iomem *port_mmio)
1113 {
1114 const char *emsg = NULL;
1115 int rc;
1116 u32 tmp;
1117
1118 /* make sure port is not active */
1119 rc = ahci_deinit_port(ap, &emsg);
1120 if (rc)
1121 dev_printk(KERN_WARNING, &pdev->dev,
1122 "%s (%d)\n", emsg, rc);
1123
1124 /* clear SError */
1125 tmp = readl(port_mmio + PORT_SCR_ERR);
1126 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1127 writel(tmp, port_mmio + PORT_SCR_ERR);
1128
1129 /* clear port IRQ */
1130 tmp = readl(port_mmio + PORT_IRQ_STAT);
1131 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1132 if (tmp)
1133 writel(tmp, port_mmio + PORT_IRQ_STAT);
1134
1135 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1136 }
1137
1138 static void ahci_init_controller(struct ata_host *host)
1139 {
1140 struct ahci_host_priv *hpriv = host->private_data;
1141 struct pci_dev *pdev = to_pci_dev(host->dev);
1142 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1143 int i;
1144 void __iomem *port_mmio;
1145 u32 tmp;
1146 int mv;
1147
1148 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1149 if (pdev->device == 0x6121)
1150 mv = 2;
1151 else
1152 mv = 4;
1153 port_mmio = __ahci_port_base(host, mv);
1154
1155 writel(0, port_mmio + PORT_IRQ_MASK);
1156
1157 /* clear port IRQ */
1158 tmp = readl(port_mmio + PORT_IRQ_STAT);
1159 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1160 if (tmp)
1161 writel(tmp, port_mmio + PORT_IRQ_STAT);
1162 }
1163
1164 for (i = 0; i < host->n_ports; i++) {
1165 struct ata_port *ap = host->ports[i];
1166
1167 port_mmio = ahci_port_base(ap);
1168 if (ata_port_is_dummy(ap))
1169 continue;
1170
1171 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1172 }
1173
1174 tmp = readl(mmio + HOST_CTL);
1175 VPRINTK("HOST_CTL 0x%x\n", tmp);
1176 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1177 tmp = readl(mmio + HOST_CTL);
1178 VPRINTK("HOST_CTL 0x%x\n", tmp);
1179 }
1180
1181 static void ahci_dev_config(struct ata_device *dev)
1182 {
1183 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1184
1185 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1186 dev->max_sectors = 255;
1187 ata_dev_printk(dev, KERN_INFO,
1188 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1189 }
1190 }
1191
1192 static unsigned int ahci_dev_classify(struct ata_port *ap)
1193 {
1194 void __iomem *port_mmio = ahci_port_base(ap);
1195 struct ata_taskfile tf;
1196 u32 tmp;
1197
1198 tmp = readl(port_mmio + PORT_SIG);
1199 tf.lbah = (tmp >> 24) & 0xff;
1200 tf.lbam = (tmp >> 16) & 0xff;
1201 tf.lbal = (tmp >> 8) & 0xff;
1202 tf.nsect = (tmp) & 0xff;
1203
1204 return ata_dev_classify(&tf);
1205 }
1206
1207 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1208 u32 opts)
1209 {
1210 dma_addr_t cmd_tbl_dma;
1211
1212 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1213
1214 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1215 pp->cmd_slot[tag].status = 0;
1216 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1217 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1218 }
1219
1220 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1221 {
1222 void __iomem *port_mmio = ahci_port_base(ap);
1223 struct ahci_host_priv *hpriv = ap->host->private_data;
1224 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1225 u32 tmp;
1226 int busy, rc;
1227
1228 /* do we need to kick the port? */
1229 busy = status & (ATA_BUSY | ATA_DRQ);
1230 if (!busy && !force_restart)
1231 return 0;
1232
1233 /* stop engine */
1234 rc = ahci_stop_engine(ap);
1235 if (rc)
1236 goto out_restart;
1237
1238 /* need to do CLO? */
1239 if (!busy) {
1240 rc = 0;
1241 goto out_restart;
1242 }
1243
1244 if (!(hpriv->cap & HOST_CAP_CLO)) {
1245 rc = -EOPNOTSUPP;
1246 goto out_restart;
1247 }
1248
1249 /* perform CLO */
1250 tmp = readl(port_mmio + PORT_CMD);
1251 tmp |= PORT_CMD_CLO;
1252 writel(tmp, port_mmio + PORT_CMD);
1253
1254 rc = 0;
1255 tmp = ata_wait_register(port_mmio + PORT_CMD,
1256 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1257 if (tmp & PORT_CMD_CLO)
1258 rc = -EIO;
1259
1260 /* restart engine */
1261 out_restart:
1262 ahci_start_engine(ap);
1263 return rc;
1264 }
1265
1266 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1267 struct ata_taskfile *tf, int is_cmd, u16 flags,
1268 unsigned long timeout_msec)
1269 {
1270 const u32 cmd_fis_len = 5; /* five dwords */
1271 struct ahci_port_priv *pp = ap->private_data;
1272 void __iomem *port_mmio = ahci_port_base(ap);
1273 u8 *fis = pp->cmd_tbl;
1274 u32 tmp;
1275
1276 /* prep the command */
1277 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1278 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1279
1280 /* issue & wait */
1281 writel(1, port_mmio + PORT_CMD_ISSUE);
1282
1283 if (timeout_msec) {
1284 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1285 1, timeout_msec);
1286 if (tmp & 0x1) {
1287 ahci_kick_engine(ap, 1);
1288 return -EBUSY;
1289 }
1290 } else
1291 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1292
1293 return 0;
1294 }
1295
1296 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1297 int pmp, unsigned long deadline,
1298 int (*check_ready)(struct ata_link *link))
1299 {
1300 struct ata_port *ap = link->ap;
1301 const char *reason = NULL;
1302 unsigned long now, msecs;
1303 struct ata_taskfile tf;
1304 int rc;
1305
1306 DPRINTK("ENTER\n");
1307
1308 /* prepare for SRST (AHCI-1.1 10.4.1) */
1309 rc = ahci_kick_engine(ap, 1);
1310 if (rc && rc != -EOPNOTSUPP)
1311 ata_link_printk(link, KERN_WARNING,
1312 "failed to reset engine (errno=%d)\n", rc);
1313
1314 ata_tf_init(link->device, &tf);
1315
1316 /* issue the first D2H Register FIS */
1317 msecs = 0;
1318 now = jiffies;
1319 if (time_after(now, deadline))
1320 msecs = jiffies_to_msecs(deadline - now);
1321
1322 tf.ctl |= ATA_SRST;
1323 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1324 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1325 rc = -EIO;
1326 reason = "1st FIS failed";
1327 goto fail;
1328 }
1329
1330 /* spec says at least 5us, but be generous and sleep for 1ms */
1331 msleep(1);
1332
1333 /* issue the second D2H Register FIS */
1334 tf.ctl &= ~ATA_SRST;
1335 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1336
1337 /* wait for link to become ready */
1338 rc = ata_wait_after_reset(link, deadline, check_ready);
1339 /* link occupied, -ENODEV too is an error */
1340 if (rc) {
1341 reason = "device not ready";
1342 goto fail;
1343 }
1344 *class = ahci_dev_classify(ap);
1345
1346 DPRINTK("EXIT, class=%u\n", *class);
1347 return 0;
1348
1349 fail:
1350 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1351 return rc;
1352 }
1353
1354 static int ahci_check_ready(struct ata_link *link)
1355 {
1356 void __iomem *port_mmio = ahci_port_base(link->ap);
1357 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1358
1359 return ata_check_ready(status);
1360 }
1361
1362 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1363 unsigned long deadline)
1364 {
1365 int pmp = sata_srst_pmp(link);
1366
1367 DPRINTK("ENTER\n");
1368
1369 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1370 }
1371
1372 static int ahci_sb600_check_ready(struct ata_link *link)
1373 {
1374 void __iomem *port_mmio = ahci_port_base(link->ap);
1375 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1376 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1377
1378 /*
1379 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1380 * which can save timeout delay.
1381 */
1382 if (irq_status & PORT_IRQ_BAD_PMP)
1383 return -EIO;
1384
1385 return ata_check_ready(status);
1386 }
1387
1388 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1389 unsigned long deadline)
1390 {
1391 struct ata_port *ap = link->ap;
1392 void __iomem *port_mmio = ahci_port_base(ap);
1393 int pmp = sata_srst_pmp(link);
1394 int rc;
1395 u32 irq_sts;
1396
1397 DPRINTK("ENTER\n");
1398
1399 rc = ahci_do_softreset(link, class, pmp, deadline,
1400 ahci_sb600_check_ready);
1401
1402 /*
1403 * Soft reset fails on some ATI chips with IPMS set when PMP
1404 * is enabled but SATA HDD/ODD is connected to SATA port,
1405 * do soft reset again to port 0.
1406 */
1407 if (rc == -EIO) {
1408 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1409 if (irq_sts & PORT_IRQ_BAD_PMP) {
1410 ata_link_printk(link, KERN_WARNING,
1411 "failed due to HW bug, retry pmp=0\n");
1412 rc = ahci_do_softreset(link, class, 0, deadline,
1413 ahci_check_ready);
1414 }
1415 }
1416
1417 return rc;
1418 }
1419
1420 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1421 unsigned long deadline)
1422 {
1423 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1424 struct ata_port *ap = link->ap;
1425 struct ahci_port_priv *pp = ap->private_data;
1426 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1427 struct ata_taskfile tf;
1428 bool online;
1429 int rc;
1430
1431 DPRINTK("ENTER\n");
1432
1433 ahci_stop_engine(ap);
1434
1435 /* clear D2H reception area to properly wait for D2H FIS */
1436 ata_tf_init(link->device, &tf);
1437 tf.command = 0x80;
1438 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1439
1440 rc = sata_link_hardreset(link, timing, deadline, &online,
1441 ahci_check_ready);
1442
1443 ahci_start_engine(ap);
1444
1445 if (online)
1446 *class = ahci_dev_classify(ap);
1447
1448 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1449 return rc;
1450 }
1451
1452 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1453 unsigned long deadline)
1454 {
1455 struct ata_port *ap = link->ap;
1456 bool online;
1457 int rc;
1458
1459 DPRINTK("ENTER\n");
1460
1461 ahci_stop_engine(ap);
1462
1463 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1464 deadline, &online, NULL);
1465
1466 ahci_start_engine(ap);
1467
1468 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1469
1470 /* vt8251 doesn't clear BSY on signature FIS reception,
1471 * request follow-up softreset.
1472 */
1473 return online ? -EAGAIN : rc;
1474 }
1475
1476 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1477 unsigned long deadline)
1478 {
1479 struct ata_port *ap = link->ap;
1480 struct ahci_port_priv *pp = ap->private_data;
1481 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1482 struct ata_taskfile tf;
1483 bool online;
1484 int rc;
1485
1486 ahci_stop_engine(ap);
1487
1488 /* clear D2H reception area to properly wait for D2H FIS */
1489 ata_tf_init(link->device, &tf);
1490 tf.command = 0x80;
1491 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1492
1493 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1494 deadline, &online, NULL);
1495
1496 ahci_start_engine(ap);
1497
1498 /* The pseudo configuration device on SIMG4726 attached to
1499 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1500 * hardreset if no device is attached to the first downstream
1501 * port && the pseudo device locks up on SRST w/ PMP==0. To
1502 * work around this, wait for !BSY only briefly. If BSY isn't
1503 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1504 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1505 *
1506 * Wait for two seconds. Devices attached to downstream port
1507 * which can't process the following IDENTIFY after this will
1508 * have to be reset again. For most cases, this should
1509 * suffice while making probing snappish enough.
1510 */
1511 if (online) {
1512 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1513 ahci_check_ready);
1514 if (rc)
1515 ahci_kick_engine(ap, 0);
1516 }
1517 return rc;
1518 }
1519
1520 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1521 {
1522 struct ata_port *ap = link->ap;
1523 void __iomem *port_mmio = ahci_port_base(ap);
1524 u32 new_tmp, tmp;
1525
1526 ata_std_postreset(link, class);
1527
1528 /* Make sure port's ATAPI bit is set appropriately */
1529 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1530 if (*class == ATA_DEV_ATAPI)
1531 new_tmp |= PORT_CMD_ATAPI;
1532 else
1533 new_tmp &= ~PORT_CMD_ATAPI;
1534 if (new_tmp != tmp) {
1535 writel(new_tmp, port_mmio + PORT_CMD);
1536 readl(port_mmio + PORT_CMD); /* flush */
1537 }
1538 }
1539
1540 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1541 {
1542 struct scatterlist *sg;
1543 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1544 unsigned int si;
1545
1546 VPRINTK("ENTER\n");
1547
1548 /*
1549 * Next, the S/G list.
1550 */
1551 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1552 dma_addr_t addr = sg_dma_address(sg);
1553 u32 sg_len = sg_dma_len(sg);
1554
1555 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1556 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1557 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1558 }
1559
1560 return si;
1561 }
1562
1563 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1564 {
1565 struct ata_port *ap = qc->ap;
1566 struct ahci_port_priv *pp = ap->private_data;
1567 int is_atapi = ata_is_atapi(qc->tf.protocol);
1568 void *cmd_tbl;
1569 u32 opts;
1570 const u32 cmd_fis_len = 5; /* five dwords */
1571 unsigned int n_elem;
1572
1573 /*
1574 * Fill in command table information. First, the header,
1575 * a SATA Register - Host to Device command FIS.
1576 */
1577 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1578
1579 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1580 if (is_atapi) {
1581 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1582 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1583 }
1584
1585 n_elem = 0;
1586 if (qc->flags & ATA_QCFLAG_DMAMAP)
1587 n_elem = ahci_fill_sg(qc, cmd_tbl);
1588
1589 /*
1590 * Fill in command slot information.
1591 */
1592 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1593 if (qc->tf.flags & ATA_TFLAG_WRITE)
1594 opts |= AHCI_CMD_WRITE;
1595 if (is_atapi)
1596 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1597
1598 ahci_fill_cmd_slot(pp, qc->tag, opts);
1599 }
1600
1601 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1602 {
1603 struct ahci_host_priv *hpriv = ap->host->private_data;
1604 struct ahci_port_priv *pp = ap->private_data;
1605 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1606 struct ata_link *link = NULL;
1607 struct ata_queued_cmd *active_qc;
1608 struct ata_eh_info *active_ehi;
1609 u32 serror;
1610
1611 /* determine active link */
1612 ata_port_for_each_link(link, ap)
1613 if (ata_link_active(link))
1614 break;
1615 if (!link)
1616 link = &ap->link;
1617
1618 active_qc = ata_qc_from_tag(ap, link->active_tag);
1619 active_ehi = &link->eh_info;
1620
1621 /* record irq stat */
1622 ata_ehi_clear_desc(host_ehi);
1623 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1624
1625 /* AHCI needs SError cleared; otherwise, it might lock up */
1626 ahci_scr_read(ap, SCR_ERROR, &serror);
1627 ahci_scr_write(ap, SCR_ERROR, serror);
1628 host_ehi->serror |= serror;
1629
1630 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1631 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1632 irq_stat &= ~PORT_IRQ_IF_ERR;
1633
1634 if (irq_stat & PORT_IRQ_TF_ERR) {
1635 /* If qc is active, charge it; otherwise, the active
1636 * link. There's no active qc on NCQ errors. It will
1637 * be determined by EH by reading log page 10h.
1638 */
1639 if (active_qc)
1640 active_qc->err_mask |= AC_ERR_DEV;
1641 else
1642 active_ehi->err_mask |= AC_ERR_DEV;
1643
1644 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1645 host_ehi->serror &= ~SERR_INTERNAL;
1646 }
1647
1648 if (irq_stat & PORT_IRQ_UNK_FIS) {
1649 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1650
1651 active_ehi->err_mask |= AC_ERR_HSM;
1652 active_ehi->action |= ATA_EH_RESET;
1653 ata_ehi_push_desc(active_ehi,
1654 "unknown FIS %08x %08x %08x %08x" ,
1655 unk[0], unk[1], unk[2], unk[3]);
1656 }
1657
1658 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1659 active_ehi->err_mask |= AC_ERR_HSM;
1660 active_ehi->action |= ATA_EH_RESET;
1661 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1662 }
1663
1664 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1665 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1666 host_ehi->action |= ATA_EH_RESET;
1667 ata_ehi_push_desc(host_ehi, "host bus error");
1668 }
1669
1670 if (irq_stat & PORT_IRQ_IF_ERR) {
1671 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1672 host_ehi->action |= ATA_EH_RESET;
1673 ata_ehi_push_desc(host_ehi, "interface fatal error");
1674 }
1675
1676 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1677 ata_ehi_hotplugged(host_ehi);
1678 ata_ehi_push_desc(host_ehi, "%s",
1679 irq_stat & PORT_IRQ_CONNECT ?
1680 "connection status changed" : "PHY RDY changed");
1681 }
1682
1683 /* okay, let's hand over to EH */
1684
1685 if (irq_stat & PORT_IRQ_FREEZE)
1686 ata_port_freeze(ap);
1687 else
1688 ata_port_abort(ap);
1689 }
1690
1691 static void ahci_port_intr(struct ata_port *ap)
1692 {
1693 void __iomem *port_mmio = ahci_port_base(ap);
1694 struct ata_eh_info *ehi = &ap->link.eh_info;
1695 struct ahci_port_priv *pp = ap->private_data;
1696 struct ahci_host_priv *hpriv = ap->host->private_data;
1697 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1698 u32 status, qc_active;
1699 int rc;
1700
1701 status = readl(port_mmio + PORT_IRQ_STAT);
1702 writel(status, port_mmio + PORT_IRQ_STAT);
1703
1704 /* ignore BAD_PMP while resetting */
1705 if (unlikely(resetting))
1706 status &= ~PORT_IRQ_BAD_PMP;
1707
1708 /* If we are getting PhyRdy, this is
1709 * just a power state change, we should
1710 * clear out this, plus the PhyRdy/Comm
1711 * Wake bits from Serror
1712 */
1713 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1714 (status & PORT_IRQ_PHYRDY)) {
1715 status &= ~PORT_IRQ_PHYRDY;
1716 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1717 }
1718
1719 if (unlikely(status & PORT_IRQ_ERROR)) {
1720 ahci_error_intr(ap, status);
1721 return;
1722 }
1723
1724 if (status & PORT_IRQ_SDB_FIS) {
1725 /* If SNotification is available, leave notification
1726 * handling to sata_async_notification(). If not,
1727 * emulate it by snooping SDB FIS RX area.
1728 *
1729 * Snooping FIS RX area is probably cheaper than
1730 * poking SNotification but some constrollers which
1731 * implement SNotification, ICH9 for example, don't
1732 * store AN SDB FIS into receive area.
1733 */
1734 if (hpriv->cap & HOST_CAP_SNTF)
1735 sata_async_notification(ap);
1736 else {
1737 /* If the 'N' bit in word 0 of the FIS is set,
1738 * we just received asynchronous notification.
1739 * Tell libata about it.
1740 */
1741 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1742 u32 f0 = le32_to_cpu(f[0]);
1743
1744 if (f0 & (1 << 15))
1745 sata_async_notification(ap);
1746 }
1747 }
1748
1749 /* pp->active_link is valid iff any command is in flight */
1750 if (ap->qc_active && pp->active_link->sactive)
1751 qc_active = readl(port_mmio + PORT_SCR_ACT);
1752 else
1753 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1754
1755 rc = ata_qc_complete_multiple(ap, qc_active);
1756
1757 /* while resetting, invalid completions are expected */
1758 if (unlikely(rc < 0 && !resetting)) {
1759 ehi->err_mask |= AC_ERR_HSM;
1760 ehi->action |= ATA_EH_RESET;
1761 ata_port_freeze(ap);
1762 }
1763 }
1764
1765 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1766 {
1767 struct ata_host *host = dev_instance;
1768 struct ahci_host_priv *hpriv;
1769 unsigned int i, handled = 0;
1770 void __iomem *mmio;
1771 u32 irq_stat, irq_ack = 0;
1772
1773 VPRINTK("ENTER\n");
1774
1775 hpriv = host->private_data;
1776 mmio = host->iomap[AHCI_PCI_BAR];
1777
1778 /* sigh. 0xffffffff is a valid return from h/w */
1779 irq_stat = readl(mmio + HOST_IRQ_STAT);
1780 irq_stat &= hpriv->port_map;
1781 if (!irq_stat)
1782 return IRQ_NONE;
1783
1784 spin_lock(&host->lock);
1785
1786 for (i = 0; i < host->n_ports; i++) {
1787 struct ata_port *ap;
1788
1789 if (!(irq_stat & (1 << i)))
1790 continue;
1791
1792 ap = host->ports[i];
1793 if (ap) {
1794 ahci_port_intr(ap);
1795 VPRINTK("port %u\n", i);
1796 } else {
1797 VPRINTK("port %u (no irq)\n", i);
1798 if (ata_ratelimit())
1799 dev_printk(KERN_WARNING, host->dev,
1800 "interrupt on disabled port %u\n", i);
1801 }
1802
1803 irq_ack |= (1 << i);
1804 }
1805
1806 if (irq_ack) {
1807 writel(irq_ack, mmio + HOST_IRQ_STAT);
1808 handled = 1;
1809 }
1810
1811 spin_unlock(&host->lock);
1812
1813 VPRINTK("EXIT\n");
1814
1815 return IRQ_RETVAL(handled);
1816 }
1817
1818 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1819 {
1820 struct ata_port *ap = qc->ap;
1821 void __iomem *port_mmio = ahci_port_base(ap);
1822 struct ahci_port_priv *pp = ap->private_data;
1823
1824 /* Keep track of the currently active link. It will be used
1825 * in completion path to determine whether NCQ phase is in
1826 * progress.
1827 */
1828 pp->active_link = qc->dev->link;
1829
1830 if (qc->tf.protocol == ATA_PROT_NCQ)
1831 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1832 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1833 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1834
1835 return 0;
1836 }
1837
1838 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1839 {
1840 struct ahci_port_priv *pp = qc->ap->private_data;
1841 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1842
1843 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1844 return true;
1845 }
1846
1847 static void ahci_freeze(struct ata_port *ap)
1848 {
1849 void __iomem *port_mmio = ahci_port_base(ap);
1850
1851 /* turn IRQ off */
1852 writel(0, port_mmio + PORT_IRQ_MASK);
1853 }
1854
1855 static void ahci_thaw(struct ata_port *ap)
1856 {
1857 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1858 void __iomem *port_mmio = ahci_port_base(ap);
1859 u32 tmp;
1860 struct ahci_port_priv *pp = ap->private_data;
1861
1862 /* clear IRQ */
1863 tmp = readl(port_mmio + PORT_IRQ_STAT);
1864 writel(tmp, port_mmio + PORT_IRQ_STAT);
1865 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1866
1867 /* turn IRQ back on */
1868 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1869 }
1870
1871 static void ahci_error_handler(struct ata_port *ap)
1872 {
1873 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1874 /* restart engine */
1875 ahci_stop_engine(ap);
1876 ahci_start_engine(ap);
1877 }
1878
1879 sata_pmp_error_handler(ap);
1880 }
1881
1882 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1883 {
1884 struct ata_port *ap = qc->ap;
1885
1886 /* make DMA engine forget about the failed command */
1887 if (qc->flags & ATA_QCFLAG_FAILED)
1888 ahci_kick_engine(ap, 1);
1889 }
1890
1891 static void ahci_pmp_attach(struct ata_port *ap)
1892 {
1893 void __iomem *port_mmio = ahci_port_base(ap);
1894 struct ahci_port_priv *pp = ap->private_data;
1895 u32 cmd;
1896
1897 cmd = readl(port_mmio + PORT_CMD);
1898 cmd |= PORT_CMD_PMP;
1899 writel(cmd, port_mmio + PORT_CMD);
1900
1901 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1902 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1903 }
1904
1905 static void ahci_pmp_detach(struct ata_port *ap)
1906 {
1907 void __iomem *port_mmio = ahci_port_base(ap);
1908 struct ahci_port_priv *pp = ap->private_data;
1909 u32 cmd;
1910
1911 cmd = readl(port_mmio + PORT_CMD);
1912 cmd &= ~PORT_CMD_PMP;
1913 writel(cmd, port_mmio + PORT_CMD);
1914
1915 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1916 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1917 }
1918
1919 static int ahci_port_resume(struct ata_port *ap)
1920 {
1921 ahci_power_up(ap);
1922 ahci_start_port(ap);
1923
1924 if (sata_pmp_attached(ap))
1925 ahci_pmp_attach(ap);
1926 else
1927 ahci_pmp_detach(ap);
1928
1929 return 0;
1930 }
1931
1932 #ifdef CONFIG_PM
1933 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1934 {
1935 const char *emsg = NULL;
1936 int rc;
1937
1938 rc = ahci_deinit_port(ap, &emsg);
1939 if (rc == 0)
1940 ahci_power_down(ap);
1941 else {
1942 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1943 ahci_start_port(ap);
1944 }
1945
1946 return rc;
1947 }
1948
1949 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1950 {
1951 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1952 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1953 u32 ctl;
1954
1955 if (mesg.event & PM_EVENT_SLEEP) {
1956 /* AHCI spec rev1.1 section 8.3.3:
1957 * Software must disable interrupts prior to requesting a
1958 * transition of the HBA to D3 state.
1959 */
1960 ctl = readl(mmio + HOST_CTL);
1961 ctl &= ~HOST_IRQ_EN;
1962 writel(ctl, mmio + HOST_CTL);
1963 readl(mmio + HOST_CTL); /* flush */
1964 }
1965
1966 return ata_pci_device_suspend(pdev, mesg);
1967 }
1968
1969 static int ahci_pci_device_resume(struct pci_dev *pdev)
1970 {
1971 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1972 int rc;
1973
1974 rc = ata_pci_device_do_resume(pdev);
1975 if (rc)
1976 return rc;
1977
1978 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1979 rc = ahci_reset_controller(host);
1980 if (rc)
1981 return rc;
1982
1983 ahci_init_controller(host);
1984 }
1985
1986 ata_host_resume(host);
1987
1988 return 0;
1989 }
1990 #endif
1991
1992 static int ahci_port_start(struct ata_port *ap)
1993 {
1994 struct device *dev = ap->host->dev;
1995 struct ahci_port_priv *pp;
1996 void *mem;
1997 dma_addr_t mem_dma;
1998
1999 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2000 if (!pp)
2001 return -ENOMEM;
2002
2003 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2004 GFP_KERNEL);
2005 if (!mem)
2006 return -ENOMEM;
2007 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2008
2009 /*
2010 * First item in chunk of DMA memory: 32-slot command table,
2011 * 32 bytes each in size
2012 */
2013 pp->cmd_slot = mem;
2014 pp->cmd_slot_dma = mem_dma;
2015
2016 mem += AHCI_CMD_SLOT_SZ;
2017 mem_dma += AHCI_CMD_SLOT_SZ;
2018
2019 /*
2020 * Second item: Received-FIS area
2021 */
2022 pp->rx_fis = mem;
2023 pp->rx_fis_dma = mem_dma;
2024
2025 mem += AHCI_RX_FIS_SZ;
2026 mem_dma += AHCI_RX_FIS_SZ;
2027
2028 /*
2029 * Third item: data area for storing a single command
2030 * and its scatter-gather table
2031 */
2032 pp->cmd_tbl = mem;
2033 pp->cmd_tbl_dma = mem_dma;
2034
2035 /*
2036 * Save off initial list of interrupts to be enabled.
2037 * This could be changed later
2038 */
2039 pp->intr_mask = DEF_PORT_IRQ;
2040
2041 ap->private_data = pp;
2042
2043 /* engage engines, captain */
2044 return ahci_port_resume(ap);
2045 }
2046
2047 static void ahci_port_stop(struct ata_port *ap)
2048 {
2049 const char *emsg = NULL;
2050 int rc;
2051
2052 /* de-initialize port */
2053 rc = ahci_deinit_port(ap, &emsg);
2054 if (rc)
2055 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2056 }
2057
2058 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2059 {
2060 int rc;
2061
2062 if (using_dac &&
2063 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2064 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2065 if (rc) {
2066 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2067 if (rc) {
2068 dev_printk(KERN_ERR, &pdev->dev,
2069 "64-bit DMA enable failed\n");
2070 return rc;
2071 }
2072 }
2073 } else {
2074 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2075 if (rc) {
2076 dev_printk(KERN_ERR, &pdev->dev,
2077 "32-bit DMA enable failed\n");
2078 return rc;
2079 }
2080 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2081 if (rc) {
2082 dev_printk(KERN_ERR, &pdev->dev,
2083 "32-bit consistent DMA enable failed\n");
2084 return rc;
2085 }
2086 }
2087 return 0;
2088 }
2089
2090 static void ahci_print_info(struct ata_host *host)
2091 {
2092 struct ahci_host_priv *hpriv = host->private_data;
2093 struct pci_dev *pdev = to_pci_dev(host->dev);
2094 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2095 u32 vers, cap, impl, speed;
2096 const char *speed_s;
2097 u16 cc;
2098 const char *scc_s;
2099
2100 vers = readl(mmio + HOST_VERSION);
2101 cap = hpriv->cap;
2102 impl = hpriv->port_map;
2103
2104 speed = (cap >> 20) & 0xf;
2105 if (speed == 1)
2106 speed_s = "1.5";
2107 else if (speed == 2)
2108 speed_s = "3";
2109 else
2110 speed_s = "?";
2111
2112 pci_read_config_word(pdev, 0x0a, &cc);
2113 if (cc == PCI_CLASS_STORAGE_IDE)
2114 scc_s = "IDE";
2115 else if (cc == PCI_CLASS_STORAGE_SATA)
2116 scc_s = "SATA";
2117 else if (cc == PCI_CLASS_STORAGE_RAID)
2118 scc_s = "RAID";
2119 else
2120 scc_s = "unknown";
2121
2122 dev_printk(KERN_INFO, &pdev->dev,
2123 "AHCI %02x%02x.%02x%02x "
2124 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2125 ,
2126
2127 (vers >> 24) & 0xff,
2128 (vers >> 16) & 0xff,
2129 (vers >> 8) & 0xff,
2130 vers & 0xff,
2131
2132 ((cap >> 8) & 0x1f) + 1,
2133 (cap & 0x1f) + 1,
2134 speed_s,
2135 impl,
2136 scc_s);
2137
2138 dev_printk(KERN_INFO, &pdev->dev,
2139 "flags: "
2140 "%s%s%s%s%s%s%s"
2141 "%s%s%s%s%s%s%s\n"
2142 ,
2143
2144 cap & (1 << 31) ? "64bit " : "",
2145 cap & (1 << 30) ? "ncq " : "",
2146 cap & (1 << 29) ? "sntf " : "",
2147 cap & (1 << 28) ? "ilck " : "",
2148 cap & (1 << 27) ? "stag " : "",
2149 cap & (1 << 26) ? "pm " : "",
2150 cap & (1 << 25) ? "led " : "",
2151
2152 cap & (1 << 24) ? "clo " : "",
2153 cap & (1 << 19) ? "nz " : "",
2154 cap & (1 << 18) ? "only " : "",
2155 cap & (1 << 17) ? "pmp " : "",
2156 cap & (1 << 15) ? "pio " : "",
2157 cap & (1 << 14) ? "slum " : "",
2158 cap & (1 << 13) ? "part " : ""
2159 );
2160 }
2161
2162 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2163 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2164 * support PMP and the 4726 either directly exports the device
2165 * attached to the first downstream port or acts as a hardware storage
2166 * controller and emulate a single ATA device (can be RAID 0/1 or some
2167 * other configuration).
2168 *
2169 * When there's no device attached to the first downstream port of the
2170 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2171 * configure the 4726. However, ATA emulation of the device is very
2172 * lame. It doesn't send signature D2H Reg FIS after the initial
2173 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2174 *
2175 * The following function works around the problem by always using
2176 * hardreset on the port and not depending on receiving signature FIS
2177 * afterward. If signature FIS isn't received soon, ATA class is
2178 * assumed without follow-up softreset.
2179 */
2180 static void ahci_p5wdh_workaround(struct ata_host *host)
2181 {
2182 static struct dmi_system_id sysids[] = {
2183 {
2184 .ident = "P5W DH Deluxe",
2185 .matches = {
2186 DMI_MATCH(DMI_SYS_VENDOR,
2187 "ASUSTEK COMPUTER INC"),
2188 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2189 },
2190 },
2191 { }
2192 };
2193 struct pci_dev *pdev = to_pci_dev(host->dev);
2194
2195 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2196 dmi_check_system(sysids)) {
2197 struct ata_port *ap = host->ports[1];
2198
2199 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2200 "Deluxe on-board SIMG4726 workaround\n");
2201
2202 ap->ops = &ahci_p5wdh_ops;
2203 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2204 }
2205 }
2206
2207 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2208 {
2209 static int printed_version;
2210 unsigned int board_id = ent->driver_data;
2211 struct ata_port_info pi = ahci_port_info[board_id];
2212 const struct ata_port_info *ppi[] = { &pi, NULL };
2213 struct device *dev = &pdev->dev;
2214 struct ahci_host_priv *hpriv;
2215 struct ata_host *host;
2216 int n_ports, i, rc;
2217
2218 VPRINTK("ENTER\n");
2219
2220 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2221
2222 if (!printed_version++)
2223 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2224
2225 /* acquire resources */
2226 rc = pcim_enable_device(pdev);
2227 if (rc)
2228 return rc;
2229
2230 /* AHCI controllers often implement SFF compatible interface.
2231 * Grab all PCI BARs just in case.
2232 */
2233 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2234 if (rc == -EBUSY)
2235 pcim_pin_device(pdev);
2236 if (rc)
2237 return rc;
2238
2239 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2240 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2241 u8 map;
2242
2243 /* ICH6s share the same PCI ID for both piix and ahci
2244 * modes. Enabling ahci mode while MAP indicates
2245 * combined mode is a bad idea. Yield to ata_piix.
2246 */
2247 pci_read_config_byte(pdev, ICH_MAP, &map);
2248 if (map & 0x3) {
2249 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2250 "combined mode, can't enable AHCI mode\n");
2251 return -ENODEV;
2252 }
2253 }
2254
2255 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2256 if (!hpriv)
2257 return -ENOMEM;
2258 hpriv->flags |= (unsigned long)pi.private_data;
2259
2260 /* MCP65 revision A1 and A2 can't do MSI */
2261 if (board_id == board_ahci_mcp65 &&
2262 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2263 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2264
2265 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2266 pci_intx(pdev, 1);
2267
2268 /* save initial config */
2269 ahci_save_initial_config(pdev, hpriv);
2270
2271 /* prepare host */
2272 if (hpriv->cap & HOST_CAP_NCQ)
2273 pi.flags |= ATA_FLAG_NCQ;
2274
2275 if (hpriv->cap & HOST_CAP_PMP)
2276 pi.flags |= ATA_FLAG_PMP;
2277
2278 /* CAP.NP sometimes indicate the index of the last enabled
2279 * port, at other times, that of the last possible port, so
2280 * determining the maximum port number requires looking at
2281 * both CAP.NP and port_map.
2282 */
2283 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2284
2285 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2286 if (!host)
2287 return -ENOMEM;
2288 host->iomap = pcim_iomap_table(pdev);
2289 host->private_data = hpriv;
2290
2291 for (i = 0; i < host->n_ports; i++) {
2292 struct ata_port *ap = host->ports[i];
2293
2294 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2295 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2296 0x100 + ap->port_no * 0x80, "port");
2297
2298 /* set initial link pm policy */
2299 ap->pm_policy = NOT_AVAILABLE;
2300
2301 /* disabled/not-implemented port */
2302 if (!(hpriv->port_map & (1 << i)))
2303 ap->ops = &ata_dummy_port_ops;
2304 }
2305
2306 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2307 ahci_p5wdh_workaround(host);
2308
2309 /* initialize adapter */
2310 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2311 if (rc)
2312 return rc;
2313
2314 rc = ahci_reset_controller(host);
2315 if (rc)
2316 return rc;
2317
2318 ahci_init_controller(host);
2319 ahci_print_info(host);
2320
2321 pci_set_master(pdev);
2322 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2323 &ahci_sht);
2324 }
2325
2326 static int __init ahci_init(void)
2327 {
2328 return pci_register_driver(&ahci_pci_driver);
2329 }
2330
2331 static void __exit ahci_exit(void)
2332 {
2333 pci_unregister_driver(&ahci_pci_driver);
2334 }
2335
2336
2337 MODULE_AUTHOR("Jeff Garzik");
2338 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2339 MODULE_LICENSE("GPL");
2340 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2341 MODULE_VERSION(DRV_VERSION);
2342
2343 module_init(ahci_init);
2344 module_exit(ahci_exit);
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