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iwlagn: remove warning in iwl_rx_handle
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-rx.c
blobb4eff556cd0a84de0662a8e22b91816a5302e270
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 /*TODO: Remove include to iwl-core.h*/
34 #include "iwl-core.h"
35 #include "iwl-io.h"
36 #include "iwl-helpers.h"
37 #include "iwl-trans-pcie-int.h"
38
39 /******************************************************************************
40 *
41 * RX path functions
42 *
43 ******************************************************************************/
44
45 /*
46 * Rx theory of operation
47 *
48 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
49 * each of which point to Receive Buffers to be filled by the NIC. These get
50 * used not only for Rx frames, but for any command response or notification
51 * from the NIC. The driver and NIC manage the Rx buffers by means
52 * of indexes into the circular buffer.
53 *
54 * Rx Queue Indexes
55 * The host/firmware share two index registers for managing the Rx buffers.
56 *
57 * The READ index maps to the first position that the firmware may be writing
58 * to -- the driver can read up to (but not including) this position and get
59 * good data.
60 * The READ index is managed by the firmware once the card is enabled.
61 *
62 * The WRITE index maps to the last position the driver has read from -- the
63 * position preceding WRITE is the last slot the firmware can place a packet.
64 *
65 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
66 * WRITE = READ.
67 *
68 * During initialization, the host sets up the READ queue position to the first
69 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 *
71 * When the firmware places a packet in a buffer, it will advance the READ index
72 * and fire the RX interrupt. The driver can then query the READ index and
73 * process as many packets as possible, moving the WRITE index forward as it
74 * resets the Rx queue buffers with new memory.
75 *
76 * The management in the driver is as follows:
77 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
78 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
79 * to replenish the iwl->rxq->rx_free.
80 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
81 * iwl->rxq is replenished and the READ INDEX is updated (updating the
82 * 'processed' and 'read' driver indexes as well)
83 * + A received packet is processed and handed to the kernel network stack,
84 * detached from the iwl->rxq. The driver 'processed' index is updated.
85 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
86 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
87 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
88 * were enough free buffers and RX_STALLED is set it is cleared.
89 *
90 *
91 * Driver sequence:
92 *
93 * iwl_rx_queue_alloc() Allocates rx_free
94 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
95 * iwl_rx_queue_restock
96 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
97 * queue, updates firmware pointers, and updates
98 * the WRITE index. If insufficient rx_free buffers
99 * are available, schedules iwl_rx_replenish
100 *
101 * -- enable interrupts --
102 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
103 * READ INDEX, detaching the SKB from the pool.
104 * Moves the packet buffer from queue to rx_used.
105 * Calls iwl_rx_queue_restock to refill any empty
106 * slots.
107 * ...
108 *
109 */
110
111 /**
112 * iwl_rx_queue_space - Return number of free slots available in queue.
113 */
114 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
115 {
116 int s = q->read - q->write;
117 if (s <= 0)
118 s += RX_QUEUE_SIZE;
119 /* keep some buffer to not confuse full and empty queue */
120 s -= 2;
121 if (s < 0)
122 s = 0;
123 return s;
124 }
125
126 /**
127 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
128 */
129 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
130 struct iwl_rx_queue *q)
131 {
132 unsigned long flags;
133 u32 reg;
134
135 spin_lock_irqsave(&q->lock, flags);
136
137 if (q->need_update == 0)
138 goto exit_unlock;
139
140 if (hw_params(trans).shadow_reg_enable) {
141 /* shadow register enabled */
142 /* Device expects a multiple of 8 */
143 q->write_actual = (q->write & ~0x7);
144 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
145 } else {
146 /* If power-saving is in use, make sure device is awake */
147 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
148 reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
149
150 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
151 IWL_DEBUG_INFO(trans,
152 "Rx queue requesting wakeup,"
153 " GP1 = 0x%x\n", reg);
154 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
155 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
156 goto exit_unlock;
157 }
158
159 q->write_actual = (q->write & ~0x7);
160 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
161 q->write_actual);
162
163 /* Else device is assumed to be awake */
164 } else {
165 /* Device expects a multiple of 8 */
166 q->write_actual = (q->write & ~0x7);
167 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
168 q->write_actual);
169 }
170 }
171 q->need_update = 0;
172
173 exit_unlock:
174 spin_unlock_irqrestore(&q->lock, flags);
175 }
176
177 /**
178 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
179 */
180 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
181 {
182 return cpu_to_le32((u32)(dma_addr >> 8));
183 }
184
185 /**
186 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
187 *
188 * If there are slots in the RX queue that need to be restocked,
189 * and we have free pre-allocated buffers, fill the ranks as much
190 * as we can, pulling from rx_free.
191 *
192 * This moves the 'write' index forward to catch up with 'processed', and
193 * also updates the memory address in the firmware to reference the new
194 * target buffer.
195 */
196 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
197 {
198 struct iwl_trans_pcie *trans_pcie =
199 IWL_TRANS_GET_PCIE_TRANS(trans);
200
201 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
202 struct list_head *element;
203 struct iwl_rx_mem_buffer *rxb;
204 unsigned long flags;
205
206 spin_lock_irqsave(&rxq->lock, flags);
207 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
208 /* The overwritten rxb must be a used one */
209 rxb = rxq->queue[rxq->write];
210 BUG_ON(rxb && rxb->page);
211
212 /* Get next free Rx buffer, remove from free list */
213 element = rxq->rx_free.next;
214 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
215 list_del(element);
216
217 /* Point to Rx buffer via next RBD in circular buffer */
218 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
219 rxq->queue[rxq->write] = rxb;
220 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
221 rxq->free_count--;
222 }
223 spin_unlock_irqrestore(&rxq->lock, flags);
224 /* If the pre-allocated buffer pool is dropping low, schedule to
225 * refill it */
226 if (rxq->free_count <= RX_LOW_WATERMARK)
227 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
228
229
230 /* If we've added more space for the firmware to place data, tell it.
231 * Increment device's write pointer in multiples of 8. */
232 if (rxq->write_actual != (rxq->write & ~0x7)) {
233 spin_lock_irqsave(&rxq->lock, flags);
234 rxq->need_update = 1;
235 spin_unlock_irqrestore(&rxq->lock, flags);
236 iwl_rx_queue_update_write_ptr(trans, rxq);
237 }
238 }
239
240 /**
241 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
242 *
243 * When moving to rx_free an SKB is allocated for the slot.
244 *
245 * Also restock the Rx queue via iwl_rx_queue_restock.
246 * This is called as a scheduled work item (except for during initialization)
247 */
248 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
249 {
250 struct iwl_trans_pcie *trans_pcie =
251 IWL_TRANS_GET_PCIE_TRANS(trans);
252
253 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
254 struct list_head *element;
255 struct iwl_rx_mem_buffer *rxb;
256 struct page *page;
257 unsigned long flags;
258 gfp_t gfp_mask = priority;
259
260 while (1) {
261 spin_lock_irqsave(&rxq->lock, flags);
262 if (list_empty(&rxq->rx_used)) {
263 spin_unlock_irqrestore(&rxq->lock, flags);
264 return;
265 }
266 spin_unlock_irqrestore(&rxq->lock, flags);
267
268 if (rxq->free_count > RX_LOW_WATERMARK)
269 gfp_mask |= __GFP_NOWARN;
270
271 if (hw_params(trans).rx_page_order > 0)
272 gfp_mask |= __GFP_COMP;
273
274 /* Alloc a new receive buffer */
275 page = alloc_pages(gfp_mask,
276 hw_params(trans).rx_page_order);
277 if (!page) {
278 if (net_ratelimit())
279 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
280 "order: %d\n",
281 hw_params(trans).rx_page_order);
282
283 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
284 net_ratelimit())
285 IWL_CRIT(trans, "Failed to alloc_pages with %s."
286 "Only %u free buffers remaining.\n",
287 priority == GFP_ATOMIC ?
288 "GFP_ATOMIC" : "GFP_KERNEL",
289 rxq->free_count);
290 /* We don't reschedule replenish work here -- we will
291 * call the restock method and if it still needs
292 * more buffers it will schedule replenish */
293 return;
294 }
295
296 spin_lock_irqsave(&rxq->lock, flags);
297
298 if (list_empty(&rxq->rx_used)) {
299 spin_unlock_irqrestore(&rxq->lock, flags);
300 __free_pages(page, hw_params(trans).rx_page_order);
301 return;
302 }
303 element = rxq->rx_used.next;
304 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
305 list_del(element);
306
307 spin_unlock_irqrestore(&rxq->lock, flags);
308
309 BUG_ON(rxb->page);
310 rxb->page = page;
311 /* Get physical address of the RB */
312 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
313 PAGE_SIZE << hw_params(trans).rx_page_order,
314 DMA_FROM_DEVICE);
315 /* dma address must be no more than 36 bits */
316 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
317 /* and also 256 byte aligned! */
318 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
319
320 spin_lock_irqsave(&rxq->lock, flags);
321
322 list_add_tail(&rxb->list, &rxq->rx_free);
323 rxq->free_count++;
324
325 spin_unlock_irqrestore(&rxq->lock, flags);
326 }
327 }
328
329 void iwlagn_rx_replenish(struct iwl_trans *trans)
330 {
331 unsigned long flags;
332
333 iwlagn_rx_allocate(trans, GFP_KERNEL);
334
335 spin_lock_irqsave(&trans->shrd->lock, flags);
336 iwlagn_rx_queue_restock(trans);
337 spin_unlock_irqrestore(&trans->shrd->lock, flags);
338 }
339
340 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
341 {
342 iwlagn_rx_allocate(trans, GFP_ATOMIC);
343
344 iwlagn_rx_queue_restock(trans);
345 }
346
347 void iwl_bg_rx_replenish(struct work_struct *data)
348 {
349 struct iwl_trans_pcie *trans_pcie =
350 container_of(data, struct iwl_trans_pcie, rx_replenish);
351 struct iwl_trans *trans = trans_pcie->trans;
352
353 if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
354 return;
355
356 mutex_lock(&trans->shrd->mutex);
357 iwlagn_rx_replenish(trans);
358 mutex_unlock(&trans->shrd->mutex);
359 }
360
361 /**
362 * iwl_rx_handle - Main entry function for receiving responses from uCode
363 *
364 * Uses the priv->rx_handlers callback function array to invoke
365 * the appropriate handlers, including command responses,
366 * frame-received notifications, and other notifications.
367 */
368 static void iwl_rx_handle(struct iwl_trans *trans)
369 {
370 struct iwl_rx_mem_buffer *rxb;
371 struct iwl_rx_packet *pkt;
372 struct iwl_trans_pcie *trans_pcie =
373 IWL_TRANS_GET_PCIE_TRANS(trans);
374 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
375 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
376 struct iwl_device_cmd *cmd;
377 u32 r, i;
378 int reclaim;
379 unsigned long flags;
380 u8 fill_rx = 0;
381 u32 count = 8;
382 int total_empty;
383 int index, cmd_index;
384
385 /* uCode's read index (stored in shared DRAM) indicates the last Rx
386 * buffer that the driver may process (last buffer filled by ucode). */
387 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
388 i = rxq->read;
389
390 /* Rx interrupt, but nothing sent from uCode */
391 if (i == r)
392 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
393
394 /* calculate total frames need to be restock after handling RX */
395 total_empty = r - rxq->write_actual;
396 if (total_empty < 0)
397 total_empty += RX_QUEUE_SIZE;
398
399 if (total_empty > (RX_QUEUE_SIZE / 2))
400 fill_rx = 1;
401
402 while (i != r) {
403 int len, err;
404 u16 sequence;
405
406 rxb = rxq->queue[i];
407
408 /* If an RXB doesn't have a Rx queue slot associated with it,
409 * then a bug has been introduced in the queue refilling
410 * routines -- catch it here */
411 if (WARN_ON(rxb == NULL)) {
412 i = (i + 1) & RX_QUEUE_MASK;
413 continue;
414 }
415
416 rxq->queue[i] = NULL;
417
418 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
419 PAGE_SIZE << hw_params(trans).rx_page_order,
420 DMA_FROM_DEVICE);
421 pkt = rxb_addr(rxb);
422
423 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
424 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
425
426 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
427 len += sizeof(u32); /* account for status word */
428 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
429
430 /* Reclaim a command buffer only if this packet is a response
431 * to a (driver-originated) command.
432 * If the packet (e.g. Rx frame) originated from uCode,
433 * there is no command buffer to reclaim.
434 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
435 * but apparently a few don't get set; catch them here. */
436 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
437 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
438 (pkt->hdr.cmd != REPLY_RX) &&
439 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
440 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
441 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
442 (pkt->hdr.cmd != REPLY_TX);
443
444 sequence = le16_to_cpu(pkt->hdr.sequence);
445 index = SEQ_TO_INDEX(sequence);
446 cmd_index = get_cmd_index(&txq->q, index);
447
448 if (reclaim)
449 cmd = txq->cmd[cmd_index];
450 else
451 cmd = NULL;
452
453 /* warn if this is cmd response / notification and the uCode
454 * didn't set the SEQ_RX_FRAME for a frame that is
455 * uCode-originated
456 * If you saw this code after the second half of 2012, then
457 * please remove it
458 */
459 WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
460 (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
461 "reclaim is false, SEQ_RX_FRAME unset: %s\n",
462 get_cmd_string(pkt->hdr.cmd));
463
464 err = iwl_rx_dispatch(priv(trans), rxb, cmd);
465
466 /*
467 * XXX: After here, we should always check rxb->page
468 * against NULL before touching it or its virtual
469 * memory (pkt). Because some rx_handler might have
470 * already taken or freed the pages.
471 */
472
473 if (reclaim) {
474 /* Invoke any callbacks, transfer the buffer to caller,
475 * and fire off the (possibly) blocking
476 * iwl_trans_send_cmd()
477 * as we reclaim the driver command queue */
478 if (rxb->page)
479 iwl_tx_cmd_complete(trans, rxb, err);
480 else
481 IWL_WARN(trans, "Claim null rxb?\n");
482 }
483
484 /* Reuse the page if possible. For notification packets and
485 * SKBs that fail to Rx correctly, add them back into the
486 * rx_free list for reuse later. */
487 spin_lock_irqsave(&rxq->lock, flags);
488 if (rxb->page != NULL) {
489 rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
490 0, PAGE_SIZE <<
491 hw_params(trans).rx_page_order,
492 DMA_FROM_DEVICE);
493 list_add_tail(&rxb->list, &rxq->rx_free);
494 rxq->free_count++;
495 } else
496 list_add_tail(&rxb->list, &rxq->rx_used);
497
498 spin_unlock_irqrestore(&rxq->lock, flags);
499
500 i = (i + 1) & RX_QUEUE_MASK;
501 /* If there are a lot of unused frames,
502 * restock the Rx queue so ucode wont assert. */
503 if (fill_rx) {
504 count++;
505 if (count >= 8) {
506 rxq->read = i;
507 iwlagn_rx_replenish_now(trans);
508 count = 0;
509 }
510 }
511 }
512
513 /* Backtrack one entry */
514 rxq->read = i;
515 if (fill_rx)
516 iwlagn_rx_replenish_now(trans);
517 else
518 iwlagn_rx_queue_restock(trans);
519 }
520
521 static const char * const desc_lookup_text[] = {
522 "OK",
523 "FAIL",
524 "BAD_PARAM",
525 "BAD_CHECKSUM",
526 "NMI_INTERRUPT_WDG",
527 "SYSASSERT",
528 "FATAL_ERROR",
529 "BAD_COMMAND",
530 "HW_ERROR_TUNE_LOCK",
531 "HW_ERROR_TEMPERATURE",
532 "ILLEGAL_CHAN_FREQ",
533 "VCC_NOT_STABLE",
534 "FH_ERROR",
535 "NMI_INTERRUPT_HOST",
536 "NMI_INTERRUPT_ACTION_PT",
537 "NMI_INTERRUPT_UNKNOWN",
538 "UCODE_VERSION_MISMATCH",
539 "HW_ERROR_ABS_LOCK",
540 "HW_ERROR_CAL_LOCK_FAIL",
541 "NMI_INTERRUPT_INST_ACTION_PT",
542 "NMI_INTERRUPT_DATA_ACTION_PT",
543 "NMI_TRM_HW_ER",
544 "NMI_INTERRUPT_TRM",
545 "NMI_INTERRUPT_BREAK_POINT",
546 "DEBUG_0",
547 "DEBUG_1",
548 "DEBUG_2",
549 "DEBUG_3",
550 };
551
552 static struct { char *name; u8 num; } advanced_lookup[] = {
553 { "NMI_INTERRUPT_WDG", 0x34 },
554 { "SYSASSERT", 0x35 },
555 { "UCODE_VERSION_MISMATCH", 0x37 },
556 { "BAD_COMMAND", 0x38 },
557 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
558 { "FATAL_ERROR", 0x3D },
559 { "NMI_TRM_HW_ERR", 0x46 },
560 { "NMI_INTERRUPT_TRM", 0x4C },
561 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
562 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
563 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
564 { "NMI_INTERRUPT_HOST", 0x66 },
565 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
566 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
567 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
568 { "ADVANCED_SYSASSERT", 0 },
569 };
570
571 static const char *desc_lookup(u32 num)
572 {
573 int i;
574 int max = ARRAY_SIZE(desc_lookup_text);
575
576 if (num < max)
577 return desc_lookup_text[num];
578
579 max = ARRAY_SIZE(advanced_lookup) - 1;
580 for (i = 0; i < max; i++) {
581 if (advanced_lookup[i].num == num)
582 break;
583 }
584 return advanced_lookup[i].name;
585 }
586
587 #define ERROR_START_OFFSET (1 * sizeof(u32))
588 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
589
590 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
591 {
592 u32 base;
593 struct iwl_error_event_table table;
594 struct iwl_priv *priv = priv(trans);
595 struct iwl_trans_pcie *trans_pcie =
596 IWL_TRANS_GET_PCIE_TRANS(trans);
597
598 base = priv->device_pointers.error_event_table;
599 if (priv->ucode_type == IWL_UCODE_INIT) {
600 if (!base)
601 base = priv->init_errlog_ptr;
602 } else {
603 if (!base)
604 base = priv->inst_errlog_ptr;
605 }
606
607 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
608 IWL_ERR(trans,
609 "Not valid error log pointer 0x%08X for %s uCode\n",
610 base,
611 (priv->ucode_type == IWL_UCODE_INIT)
612 ? "Init" : "RT");
613 return;
614 }
615
616 iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
617
618 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
619 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
620 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
621 trans->shrd->status, table.valid);
622 }
623
624 trans_pcie->isr_stats.err_code = table.error_id;
625
626 trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
627 table.data1, table.data2, table.line,
628 table.blink1, table.blink2, table.ilink1,
629 table.ilink2, table.bcon_time, table.gp1,
630 table.gp2, table.gp3, table.ucode_ver,
631 table.hw_ver, table.brd_ver);
632 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
633 desc_lookup(table.error_id));
634 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
635 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
636 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
637 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
638 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
639 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
640 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
641 IWL_ERR(trans, "0x%08X | line\n", table.line);
642 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
643 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
644 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
645 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
646 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
647 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
648 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
649 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
650 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
651 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
652 }
653
654 /**
655 * iwl_irq_handle_error - called for HW or SW error interrupt from card
656 */
657 static void iwl_irq_handle_error(struct iwl_trans *trans)
658 {
659 struct iwl_priv *priv = priv(trans);
660 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
661 if (priv->cfg->internal_wimax_coex &&
662 (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
663 APMS_CLK_VAL_MRB_FUNC_MODE) ||
664 (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
665 APMG_PS_CTRL_VAL_RESET_REQ))) {
666 /*
667 * Keep the restart process from trying to send host
668 * commands by clearing the ready bit.
669 */
670 clear_bit(STATUS_READY, &trans->shrd->status);
671 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
672 wake_up(&priv->shrd->wait_command_queue);
673 IWL_ERR(trans, "RF is used by WiMAX\n");
674 return;
675 }
676
677 IWL_ERR(trans, "Loaded firmware version: %s\n",
678 priv->hw->wiphy->fw_version);
679
680 iwl_dump_nic_error_log(trans);
681 iwl_dump_csr(trans);
682 iwl_dump_fh(trans, NULL, false);
683 iwl_dump_nic_event_log(trans, false, NULL, false);
684 #ifdef CONFIG_IWLWIFI_DEBUG
685 if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
686 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
687 #endif
688
689 iwlagn_fw_error(priv, false);
690 }
691
692 #define EVENT_START_OFFSET (4 * sizeof(u32))
693
694 /**
695 * iwl_print_event_log - Dump error event log to syslog
696 *
697 */
698 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
699 u32 num_events, u32 mode,
700 int pos, char **buf, size_t bufsz)
701 {
702 u32 i;
703 u32 base; /* SRAM byte address of event log header */
704 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
705 u32 ptr; /* SRAM byte address of log data */
706 u32 ev, time, data; /* event log data */
707 unsigned long reg_flags;
708 struct iwl_priv *priv = priv(trans);
709
710 if (num_events == 0)
711 return pos;
712
713 base = priv->device_pointers.log_event_table;
714 if (priv->ucode_type == IWL_UCODE_INIT) {
715 if (!base)
716 base = priv->init_evtlog_ptr;
717 } else {
718 if (!base)
719 base = priv->inst_evtlog_ptr;
720 }
721
722 if (mode == 0)
723 event_size = 2 * sizeof(u32);
724 else
725 event_size = 3 * sizeof(u32);
726
727 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
728
729 /* Make sure device is powered up for SRAM reads */
730 spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
731 iwl_grab_nic_access(bus(trans));
732
733 /* Set starting address; reads will auto-increment */
734 iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
735 rmb();
736
737 /* "time" is actually "data" for mode 0 (no timestamp).
738 * place event id # at far right for easier visual parsing. */
739 for (i = 0; i < num_events; i++) {
740 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
741 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
742 if (mode == 0) {
743 /* data, ev */
744 if (bufsz) {
745 pos += scnprintf(*buf + pos, bufsz - pos,
746 "EVT_LOG:0x%08x:%04u\n",
747 time, ev);
748 } else {
749 trace_iwlwifi_dev_ucode_event(priv, 0,
750 time, ev);
751 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
752 time, ev);
753 }
754 } else {
755 data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
756 if (bufsz) {
757 pos += scnprintf(*buf + pos, bufsz - pos,
758 "EVT_LOGT:%010u:0x%08x:%04u\n",
759 time, data, ev);
760 } else {
761 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
762 time, data, ev);
763 trace_iwlwifi_dev_ucode_event(priv, time,
764 data, ev);
765 }
766 }
767 }
768
769 /* Allow device to power down */
770 iwl_release_nic_access(bus(trans));
771 spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
772 return pos;
773 }
774
775 /**
776 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
777 */
778 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
779 u32 num_wraps, u32 next_entry,
780 u32 size, u32 mode,
781 int pos, char **buf, size_t bufsz)
782 {
783 /*
784 * display the newest DEFAULT_LOG_ENTRIES entries
785 * i.e the entries just before the next ont that uCode would fill.
786 */
787 if (num_wraps) {
788 if (next_entry < size) {
789 pos = iwl_print_event_log(trans,
790 capacity - (size - next_entry),
791 size - next_entry, mode,
792 pos, buf, bufsz);
793 pos = iwl_print_event_log(trans, 0,
794 next_entry, mode,
795 pos, buf, bufsz);
796 } else
797 pos = iwl_print_event_log(trans, next_entry - size,
798 size, mode, pos, buf, bufsz);
799 } else {
800 if (next_entry < size) {
801 pos = iwl_print_event_log(trans, 0, next_entry,
802 mode, pos, buf, bufsz);
803 } else {
804 pos = iwl_print_event_log(trans, next_entry - size,
805 size, mode, pos, buf, bufsz);
806 }
807 }
808 return pos;
809 }
810
811 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
812
813 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
814 char **buf, bool display)
815 {
816 u32 base; /* SRAM byte address of event log header */
817 u32 capacity; /* event log capacity in # entries */
818 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
819 u32 num_wraps; /* # times uCode wrapped to top of log */
820 u32 next_entry; /* index of next entry to be written by uCode */
821 u32 size; /* # entries that we'll print */
822 u32 logsize;
823 int pos = 0;
824 size_t bufsz = 0;
825 struct iwl_priv *priv = priv(trans);
826
827 base = priv->device_pointers.log_event_table;
828 if (priv->ucode_type == IWL_UCODE_INIT) {
829 logsize = priv->init_evtlog_size;
830 if (!base)
831 base = priv->init_evtlog_ptr;
832 } else {
833 logsize = priv->inst_evtlog_size;
834 if (!base)
835 base = priv->inst_evtlog_ptr;
836 }
837
838 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
839 IWL_ERR(trans,
840 "Invalid event log pointer 0x%08X for %s uCode\n",
841 base,
842 (priv->ucode_type == IWL_UCODE_INIT)
843 ? "Init" : "RT");
844 return -EINVAL;
845 }
846
847 /* event log header */
848 capacity = iwl_read_targ_mem(bus(trans), base);
849 mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
850 num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
851 next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
852
853 if (capacity > logsize) {
854 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
855 "entries\n", capacity, logsize);
856 capacity = logsize;
857 }
858
859 if (next_entry > logsize) {
860 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
861 next_entry, logsize);
862 next_entry = logsize;
863 }
864
865 size = num_wraps ? capacity : next_entry;
866
867 /* bail out if nothing in log */
868 if (size == 0) {
869 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
870 return pos;
871 }
872
873 #ifdef CONFIG_IWLWIFI_DEBUG
874 if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
875 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
876 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
877 #else
878 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
879 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
880 #endif
881 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
882 size);
883
884 #ifdef CONFIG_IWLWIFI_DEBUG
885 if (display) {
886 if (full_log)
887 bufsz = capacity * 48;
888 else
889 bufsz = size * 48;
890 *buf = kmalloc(bufsz, GFP_KERNEL);
891 if (!*buf)
892 return -ENOMEM;
893 }
894 if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
895 /*
896 * if uCode has wrapped back to top of log,
897 * start at the oldest entry,
898 * i.e the next one that uCode would fill.
899 */
900 if (num_wraps)
901 pos = iwl_print_event_log(trans, next_entry,
902 capacity - next_entry, mode,
903 pos, buf, bufsz);
904 /* (then/else) start at top of log */
905 pos = iwl_print_event_log(trans, 0,
906 next_entry, mode, pos, buf, bufsz);
907 } else
908 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
909 next_entry, size, mode,
910 pos, buf, bufsz);
911 #else
912 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
913 next_entry, size, mode,
914 pos, buf, bufsz);
915 #endif
916 return pos;
917 }
918
919 /* tasklet for iwlagn interrupt */
920 void iwl_irq_tasklet(struct iwl_trans *trans)
921 {
922 u32 inta = 0;
923 u32 handled = 0;
924 unsigned long flags;
925 u32 i;
926 #ifdef CONFIG_IWLWIFI_DEBUG
927 u32 inta_mask;
928 #endif
929
930 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
931 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
932
933
934 spin_lock_irqsave(&trans->shrd->lock, flags);
935
936 /* Ack/clear/reset pending uCode interrupts.
937 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
938 */
939 /* There is a hardware bug in the interrupt mask function that some
940 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
941 * they are disabled in the CSR_INT_MASK register. Furthermore the
942 * ICT interrupt handling mechanism has another bug that might cause
943 * these unmasked interrupts fail to be detected. We workaround the
944 * hardware bugs here by ACKing all the possible interrupts so that
945 * interrupt coalescing can still be achieved.
946 */
947 iwl_write32(bus(trans), CSR_INT,
948 trans_pcie->inta | ~trans_pcie->inta_mask);
949
950 inta = trans_pcie->inta;
951
952 #ifdef CONFIG_IWLWIFI_DEBUG
953 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
954 /* just for debug */
955 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
956 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
957 inta, inta_mask);
958 }
959 #endif
960
961 spin_unlock_irqrestore(&trans->shrd->lock, flags);
962
963 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
964 trans_pcie->inta = 0;
965
966 /* Now service all interrupt bits discovered above. */
967 if (inta & CSR_INT_BIT_HW_ERR) {
968 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
969
970 /* Tell the device to stop sending interrupts */
971 iwl_disable_interrupts(trans);
972
973 isr_stats->hw++;
974 iwl_irq_handle_error(trans);
975
976 handled |= CSR_INT_BIT_HW_ERR;
977
978 return;
979 }
980
981 #ifdef CONFIG_IWLWIFI_DEBUG
982 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
983 /* NIC fires this, but we don't use it, redundant with WAKEUP */
984 if (inta & CSR_INT_BIT_SCD) {
985 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
986 "the frame/frames.\n");
987 isr_stats->sch++;
988 }
989
990 /* Alive notification via Rx interrupt will do the real work */
991 if (inta & CSR_INT_BIT_ALIVE) {
992 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
993 isr_stats->alive++;
994 }
995 }
996 #endif
997 /* Safely ignore these bits for debug checks below */
998 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
999
1000 /* HW RF KILL switch toggled */
1001 if (inta & CSR_INT_BIT_RF_KILL) {
1002 int hw_rf_kill = 0;
1003 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1004 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1005 hw_rf_kill = 1;
1006
1007 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1008 hw_rf_kill ? "disable radio" : "enable radio");
1009
1010 isr_stats->rfkill++;
1011
1012 /* driver only loads ucode once setting the interface up.
1013 * the driver allows loading the ucode even if the radio
1014 * is killed. Hence update the killswitch state here. The
1015 * rfkill handler will care about restarting if needed.
1016 */
1017 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1018 if (hw_rf_kill)
1019 set_bit(STATUS_RF_KILL_HW,
1020 &trans->shrd->status);
1021 else
1022 clear_bit(STATUS_RF_KILL_HW,
1023 &trans->shrd->status);
1024 iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1025 }
1026
1027 handled |= CSR_INT_BIT_RF_KILL;
1028 }
1029
1030 /* Chip got too hot and stopped itself */
1031 if (inta & CSR_INT_BIT_CT_KILL) {
1032 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1033 isr_stats->ctkill++;
1034 handled |= CSR_INT_BIT_CT_KILL;
1035 }
1036
1037 /* Error detected by uCode */
1038 if (inta & CSR_INT_BIT_SW_ERR) {
1039 IWL_ERR(trans, "Microcode SW error detected. "
1040 " Restarting 0x%X.\n", inta);
1041 isr_stats->sw++;
1042 iwl_irq_handle_error(trans);
1043 handled |= CSR_INT_BIT_SW_ERR;
1044 }
1045
1046 /* uCode wakes up after power-down sleep */
1047 if (inta & CSR_INT_BIT_WAKEUP) {
1048 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1049 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1050 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1051 iwl_txq_update_write_ptr(trans,
1052 &trans_pcie->txq[i]);
1053
1054 isr_stats->wakeup++;
1055
1056 handled |= CSR_INT_BIT_WAKEUP;
1057 }
1058
1059 /* All uCode command responses, including Tx command responses,
1060 * Rx "responses" (frame-received notification), and other
1061 * notifications from uCode come through here*/
1062 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1063 CSR_INT_BIT_RX_PERIODIC)) {
1064 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1065 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1066 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1067 iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1068 CSR_FH_INT_RX_MASK);
1069 }
1070 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1071 handled |= CSR_INT_BIT_RX_PERIODIC;
1072 iwl_write32(bus(trans),
1073 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1074 }
1075 /* Sending RX interrupt require many steps to be done in the
1076 * the device:
1077 * 1- write interrupt to current index in ICT table.
1078 * 2- dma RX frame.
1079 * 3- update RX shared data to indicate last write index.
1080 * 4- send interrupt.
1081 * This could lead to RX race, driver could receive RX interrupt
1082 * but the shared data changes does not reflect this;
1083 * periodic interrupt will detect any dangling Rx activity.
1084 */
1085
1086 /* Disable periodic interrupt; we use it as just a one-shot. */
1087 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1088 CSR_INT_PERIODIC_DIS);
1089 iwl_rx_handle(trans);
1090
1091 /*
1092 * Enable periodic interrupt in 8 msec only if we received
1093 * real RX interrupt (instead of just periodic int), to catch
1094 * any dangling Rx interrupt. If it was just the periodic
1095 * interrupt, there was no dangling Rx activity, and no need
1096 * to extend the periodic interrupt; one-shot is enough.
1097 */
1098 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1099 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1100 CSR_INT_PERIODIC_ENA);
1101
1102 isr_stats->rx++;
1103 }
1104
1105 /* This "Tx" DMA channel is used only for loading uCode */
1106 if (inta & CSR_INT_BIT_FH_TX) {
1107 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1108 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1109 isr_stats->tx++;
1110 handled |= CSR_INT_BIT_FH_TX;
1111 /* Wake up uCode load routine, now that load is complete */
1112 priv(trans)->ucode_write_complete = 1;
1113 wake_up(&trans->shrd->wait_command_queue);
1114 }
1115
1116 if (inta & ~handled) {
1117 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1118 isr_stats->unhandled++;
1119 }
1120
1121 if (inta & ~(trans_pcie->inta_mask)) {
1122 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1123 inta & ~trans_pcie->inta_mask);
1124 }
1125
1126 /* Re-enable all interrupts */
1127 /* only Re-enable if disabled by irq */
1128 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1129 iwl_enable_interrupts(trans);
1130 /* Re-enable RF_KILL if it occurred */
1131 else if (handled & CSR_INT_BIT_RF_KILL)
1132 iwl_enable_rfkill_int(priv(trans));
1133 }
1134
1135 /******************************************************************************
1136 *
1137 * ICT functions
1138 *
1139 ******************************************************************************/
1140 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1141
1142 /* Free dram table */
1143 void iwl_free_isr_ict(struct iwl_trans *trans)
1144 {
1145 struct iwl_trans_pcie *trans_pcie =
1146 IWL_TRANS_GET_PCIE_TRANS(trans);
1147
1148 if (trans_pcie->ict_tbl_vir) {
1149 dma_free_coherent(bus(trans)->dev,
1150 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1151 trans_pcie->ict_tbl_vir,
1152 trans_pcie->ict_tbl_dma);
1153 trans_pcie->ict_tbl_vir = NULL;
1154 memset(&trans_pcie->ict_tbl_dma, 0,
1155 sizeof(trans_pcie->ict_tbl_dma));
1156 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1157 sizeof(trans_pcie->aligned_ict_tbl_dma));
1158 }
1159 }
1160
1161
1162 /* allocate dram shared table it is a PAGE_SIZE aligned
1163 * also reset all data related to ICT table interrupt.
1164 */
1165 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1166 {
1167 struct iwl_trans_pcie *trans_pcie =
1168 IWL_TRANS_GET_PCIE_TRANS(trans);
1169
1170 /* allocate shrared data table */
1171 trans_pcie->ict_tbl_vir =
1172 dma_alloc_coherent(bus(trans)->dev,
1173 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1174 &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1175 if (!trans_pcie->ict_tbl_vir)
1176 return -ENOMEM;
1177
1178 /* align table to PAGE_SIZE boundary */
1179 trans_pcie->aligned_ict_tbl_dma =
1180 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1181
1182 IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1183 (unsigned long long)trans_pcie->ict_tbl_dma,
1184 (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1185 (int)(trans_pcie->aligned_ict_tbl_dma -
1186 trans_pcie->ict_tbl_dma));
1187
1188 trans_pcie->ict_tbl = trans_pcie->ict_tbl_vir +
1189 (trans_pcie->aligned_ict_tbl_dma -
1190 trans_pcie->ict_tbl_dma);
1191
1192 IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1193 trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1194 (int)(trans_pcie->aligned_ict_tbl_dma -
1195 trans_pcie->ict_tbl_dma));
1196
1197 /* reset table and index to all 0 */
1198 memset(trans_pcie->ict_tbl_vir, 0,
1199 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1200 trans_pcie->ict_index = 0;
1201
1202 /* add periodic RX interrupt */
1203 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1204 return 0;
1205 }
1206
1207 /* Device is going up inform it about using ICT interrupt table,
1208 * also we need to tell the driver to start using ICT interrupt.
1209 */
1210 int iwl_reset_ict(struct iwl_trans *trans)
1211 {
1212 u32 val;
1213 unsigned long flags;
1214 struct iwl_trans_pcie *trans_pcie =
1215 IWL_TRANS_GET_PCIE_TRANS(trans);
1216
1217 if (!trans_pcie->ict_tbl_vir)
1218 return 0;
1219
1220 spin_lock_irqsave(&trans->shrd->lock, flags);
1221 iwl_disable_interrupts(trans);
1222
1223 memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1224
1225 val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1226
1227 val |= CSR_DRAM_INT_TBL_ENABLE;
1228 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1229
1230 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1231 "aligned dma address %Lx\n",
1232 val,
1233 (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1234
1235 iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1236 trans_pcie->use_ict = true;
1237 trans_pcie->ict_index = 0;
1238 iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1239 iwl_enable_interrupts(trans);
1240 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1241
1242 return 0;
1243 }
1244
1245 /* Device is going down disable ict interrupt usage */
1246 void iwl_disable_ict(struct iwl_trans *trans)
1247 {
1248 struct iwl_trans_pcie *trans_pcie =
1249 IWL_TRANS_GET_PCIE_TRANS(trans);
1250
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&trans->shrd->lock, flags);
1254 trans_pcie->use_ict = false;
1255 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1256 }
1257
1258 static irqreturn_t iwl_isr(int irq, void *data)
1259 {
1260 struct iwl_trans *trans = data;
1261 struct iwl_trans_pcie *trans_pcie;
1262 u32 inta, inta_mask;
1263 unsigned long flags;
1264 #ifdef CONFIG_IWLWIFI_DEBUG
1265 u32 inta_fh;
1266 #endif
1267 if (!trans)
1268 return IRQ_NONE;
1269
1270 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1271
1272 spin_lock_irqsave(&trans->shrd->lock, flags);
1273
1274 /* Disable (but don't clear!) interrupts here to avoid
1275 * back-to-back ISRs and sporadic interrupts from our NIC.
1276 * If we have something to service, the tasklet will re-enable ints.
1277 * If we *don't* have something, we'll re-enable before leaving here. */
1278 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1279 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1280
1281 /* Discover which interrupts are active/pending */
1282 inta = iwl_read32(bus(trans), CSR_INT);
1283
1284 /* Ignore interrupt if there's nothing in NIC to service.
1285 * This may be due to IRQ shared with another device,
1286 * or due to sporadic interrupts thrown from our NIC. */
1287 if (!inta) {
1288 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1289 goto none;
1290 }
1291
1292 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1293 /* Hardware disappeared. It might have already raised
1294 * an interrupt */
1295 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1296 goto unplugged;
1297 }
1298
1299 #ifdef CONFIG_IWLWIFI_DEBUG
1300 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1301 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1302 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1303 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1304 }
1305 #endif
1306
1307 trans_pcie->inta |= inta;
1308 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1309 if (likely(inta))
1310 tasklet_schedule(&trans_pcie->irq_tasklet);
1311 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1312 !trans_pcie->inta)
1313 iwl_enable_interrupts(trans);
1314
1315 unplugged:
1316 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1317 return IRQ_HANDLED;
1318
1319 none:
1320 /* re-enable interrupts here since we don't have anything to service. */
1321 /* only Re-enable if disabled by irq and no schedules tasklet. */
1322 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1323 !trans_pcie->inta)
1324 iwl_enable_interrupts(trans);
1325
1326 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1327 return IRQ_NONE;
1328 }
1329
1330 /* interrupt handler using ict table, with this interrupt driver will
1331 * stop using INTA register to get device's interrupt, reading this register
1332 * is expensive, device will write interrupts in ICT dram table, increment
1333 * index then will fire interrupt to driver, driver will OR all ICT table
1334 * entries from current index up to table entry with 0 value. the result is
1335 * the interrupt we need to service, driver will set the entries back to 0 and
1336 * set index.
1337 */
1338 irqreturn_t iwl_isr_ict(int irq, void *data)
1339 {
1340 struct iwl_trans *trans = data;
1341 struct iwl_trans_pcie *trans_pcie;
1342 u32 inta, inta_mask;
1343 u32 val = 0;
1344 unsigned long flags;
1345
1346 if (!trans)
1347 return IRQ_NONE;
1348
1349 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1350
1351 /* dram interrupt table not set yet,
1352 * use legacy interrupt.
1353 */
1354 if (!trans_pcie->use_ict)
1355 return iwl_isr(irq, data);
1356
1357 spin_lock_irqsave(&trans->shrd->lock, flags);
1358
1359 /* Disable (but don't clear!) interrupts here to avoid
1360 * back-to-back ISRs and sporadic interrupts from our NIC.
1361 * If we have something to service, the tasklet will re-enable ints.
1362 * If we *don't* have something, we'll re-enable before leaving here.
1363 */
1364 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1365 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1366
1367
1368 /* Ignore interrupt if there's nothing in NIC to service.
1369 * This may be due to IRQ shared with another device,
1370 * or due to sporadic interrupts thrown from our NIC. */
1371 if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1372 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1373 goto none;
1374 }
1375
1376 /* read all entries that not 0 start with ict_index */
1377 while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1378
1379 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1380 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1381 trans_pcie->ict_index,
1382 le32_to_cpu(
1383 trans_pcie->ict_tbl[trans_pcie->ict_index]));
1384 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1385 trans_pcie->ict_index =
1386 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1387
1388 }
1389
1390 /* We should not get this value, just ignore it. */
1391 if (val == 0xffffffff)
1392 val = 0;
1393
1394 /*
1395 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1396 * (bit 15 before shifting it to 31) to clear when using interrupt
1397 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1398 * so we use them to decide on the real state of the Rx bit.
1399 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1400 */
1401 if (val & 0xC0000)
1402 val |= 0x8000;
1403
1404 inta = (0xff & val) | ((0xff00 & val) << 16);
1405 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1406 inta, inta_mask, val);
1407
1408 inta &= trans_pcie->inta_mask;
1409 trans_pcie->inta |= inta;
1410
1411 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1412 if (likely(inta))
1413 tasklet_schedule(&trans_pcie->irq_tasklet);
1414 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1415 !trans_pcie->inta) {
1416 /* Allow interrupt if was disabled by this handler and
1417 * no tasklet was schedules, We should not enable interrupt,
1418 * tasklet will enable it.
1419 */
1420 iwl_enable_interrupts(trans);
1421 }
1422
1423 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1424 return IRQ_HANDLED;
1425
1426 none:
1427 /* re-enable interrupts here since we don't have anything to service.
1428 * only Re-enable if disabled by irq.
1429 */
1430 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1431 !trans_pcie->inta)
1432 iwl_enable_interrupts(trans);
1433
1434 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1435 return IRQ_NONE;
1436 }
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