drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_DEFAULT_TX_WORK               256
  57 #define IXGBE_MAX_TXD                      4096
  58 #define IXGBE_MIN_TXD                        64
  59
  60 #define IXGBE_DEFAULT_RXD                   512
  61 #define IXGBE_MAX_RXD                      4096
  62 #define IXGBE_MIN_RXD                        64
  63
  64 /* flow control */
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  75 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  76
  77 /*
  78  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  79  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  80  * this adds up to 512 bytes of extra data meaning the smallest allocation
  81  * we could have is 1K.
  82  * i.e. RXBUFFER_512 --> size-1024 slab
  83  */
  84 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  85
  86 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  87
  88 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  89 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  90
  91 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  92 #define IXGBE_TX_FLAGS_HW_VLAN          (u32)(1 << 1)
  93 #define IXGBE_TX_FLAGS_SW_VLAN          (u32)(1 << 2)
  94 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 3)
  95 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 4)
  96 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 5)
  97 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 6)
  98 #define IXGBE_TX_FLAGS_TXSW             (u32)(1 << 7)
  99 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 101 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 102 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 103
 104 #define IXGBE_MAX_RSC_INT_RATE          162760
 105
 106 #define IXGBE_MAX_VF_MC_ENTRIES         30
 107 #define IXGBE_MAX_VF_FUNCTIONS          64
 108 #define IXGBE_MAX_VFTA_ENTRIES          128
 109 #define MAX_EMULATION_MAC_ADDRS         16
 110 #define IXGBE_MAX_PF_MACVLANS           15
 111 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 112 #define IXGBE_82599_VF_DEVICE_ID        0x10ED
 113 #define IXGBE_X540_VF_DEVICE_ID         0x1515
 114
 115 struct vf_data_storage {
 116         unsigned char vf_mac_addresses[ETH_ALEN];
 117         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 118         u16 num_vf_mc_hashes;
 119         u16 default_vf_vlan_id;
 120         u16 vlans_enabled;
 121         bool clear_to_send;
 122         bool pf_set_mac;
 123         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 124         u16 pf_qos;
 125         u16 tx_rate;
 126         u16 vlan_count;
 127         u8 spoofchk_enabled;
 128         struct pci_dev *vfdev;
 129 };
 130
 131 struct vf_macvlans {
 132         struct list_head l;
 133         int vf;
 134         int rar_entry;
 135         bool free;
 136         bool is_macvlan;
 137         u8 vf_macvlan[ETH_ALEN];
 138 };
 139
 140 #define IXGBE_MAX_TXD_PWR       14
 141 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 142
 143 /* Tx Descriptors needed, worst case */
 144 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 145 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 146
 147 /* wrapper around a pointer to a socket buffer,
 148  * so a DMA handle can be stored along with the buffer */
 149 struct ixgbe_tx_buffer {
 150         union ixgbe_adv_tx_desc *next_to_watch;
 151         unsigned long time_stamp;
 152         struct sk_buff *skb;
 153         unsigned int bytecount;
 154         unsigned short gso_segs;
 155         __be16 protocol;
 156         DEFINE_DMA_UNMAP_ADDR(dma);
 157         DEFINE_DMA_UNMAP_LEN(len);
 158         u32 tx_flags;
 159 };
 160
 161 struct ixgbe_rx_buffer {
 162         struct sk_buff *skb;
 163         dma_addr_t dma;
 164         struct page *page;
 165         unsigned int page_offset;
 166 };
 167
 168 struct ixgbe_queue_stats {
 169         u64 packets;
 170         u64 bytes;
 171 };
 172
 173 struct ixgbe_tx_queue_stats {
 174         u64 restart_queue;
 175         u64 tx_busy;
 176         u64 tx_done_old;
 177 };
 178
 179 struct ixgbe_rx_queue_stats {
 180         u64 rsc_count;
 181         u64 rsc_flush;
 182         u64 non_eop_descs;
 183         u64 alloc_rx_page_failed;
 184         u64 alloc_rx_buff_failed;
 185         u64 csum_err;
 186 };
 187
 188 enum ixgbe_ring_state_t {
 189         __IXGBE_TX_FDIR_INIT_DONE,
 190         __IXGBE_TX_DETECT_HANG,
 191         __IXGBE_HANG_CHECK_ARMED,
 192         __IXGBE_RX_RSC_ENABLED,
 193         __IXGBE_RX_CSUM_UDP_ZERO_ERR,
 194         __IXGBE_RX_FCOE_BUFSZ,
 195 };
 196
 197 #define check_for_tx_hang(ring) \
 198         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 199 #define set_check_for_tx_hang(ring) \
 200         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 201 #define clear_check_for_tx_hang(ring) \
 202         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 203 #define ring_is_rsc_enabled(ring) \
 204         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 205 #define set_ring_rsc_enabled(ring) \
 206         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 207 #define clear_ring_rsc_enabled(ring) \
 208         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 209 struct ixgbe_ring {
 210         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 211         struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
 212         struct net_device *netdev;      /* netdev ring belongs to */
 213         struct device *dev;             /* device for DMA mapping */
 214         void *desc;                     /* descriptor ring memory */
 215         union {
 216                 struct ixgbe_tx_buffer *tx_buffer_info;
 217                 struct ixgbe_rx_buffer *rx_buffer_info;
 218         };
 219         unsigned long state;
 220         u8 __iomem *tail;
 221         dma_addr_t dma;                 /* phys. address of descriptor ring */
 222         unsigned int size;              /* length in bytes */
 223
 224         u16 count;                      /* amount of descriptors */
 225
 226         u8 queue_index; /* needed for multiqueue queue management */
 227         u8 reg_idx;                     /* holds the special value that gets
 228                                          * the hardware register offset
 229                                          * associated with this ring, which is
 230                                          * different for DCB and RSS modes
 231                                          */
 232         u16 next_to_use;
 233         u16 next_to_clean;
 234
 235         union {
 236                 u16 next_to_alloc;
 237                 struct {
 238                         u8 atr_sample_rate;
 239                         u8 atr_count;
 240                 };
 241         };
 242
 243         u8 dcb_tc;
 244         struct ixgbe_queue_stats stats;
 245         struct u64_stats_sync syncp;
 246         union {
 247                 struct ixgbe_tx_queue_stats tx_stats;
 248                 struct ixgbe_rx_queue_stats rx_stats;
 249         };
 250 } ____cacheline_internodealigned_in_smp;
 251
 252 enum ixgbe_ring_f_enum {
 253         RING_F_NONE = 0,
 254         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 255         RING_F_RSS,
 256         RING_F_FDIR,
 257 #ifdef IXGBE_FCOE
 258         RING_F_FCOE,
 259 #endif /* IXGBE_FCOE */
 260
 261         RING_F_ARRAY_SIZE      /* must be last in enum set */
 262 };
 263
 264 #define IXGBE_MAX_RSS_INDICES  16
 265 #define IXGBE_MAX_VMDQ_INDICES 64
 266 #define IXGBE_MAX_FDIR_INDICES 64
 267 #ifdef IXGBE_FCOE
 268 #define IXGBE_MAX_FCOE_INDICES  8
 269 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 270 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 271 #else
 272 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 273 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 274 #endif /* IXGBE_FCOE */
 275 struct ixgbe_ring_feature {
 276         int indices;
 277         int mask;
 278 } ____cacheline_internodealigned_in_smp;
 279
 280 /*
 281  * FCoE requires that all Rx buffers be over 2200 bytes in length.  Since
 282  * this is twice the size of a half page we need to double the page order
 283  * for FCoE enabled Rx queues.
 284  */
 285 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
 286 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
 287 {
 288         return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
 289 }
 290 #else
 291 #define ixgbe_rx_pg_order(_ring) 0
 292 #endif
 293 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
 294 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
 295
 296 struct ixgbe_ring_container {
 297         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 298         unsigned int total_bytes;       /* total bytes processed this int */
 299         unsigned int total_packets;     /* total packets processed this int */
 300         u16 work_limit;                 /* total work allowed per interrupt */
 301         u8 count;                       /* total number of rings in vector */
 302         u8 itr;                         /* current ITR setting for ring */
 303 };
 304
 305 /* iterator for handling rings in ring container */
 306 #define ixgbe_for_each_ring(pos, head) \
 307         for (pos = (head).ring; pos != NULL; pos = pos->next)
 308
 309 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 310                               ? 8 : 1)
 311 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 312
 313 /* MAX_MSIX_Q_VECTORS of these are allocated,
 314  * but we only use one per queue-specific vector.
 315  */
 316 struct ixgbe_q_vector {
 317         struct ixgbe_adapter *adapter;
 318 #ifdef CONFIG_IXGBE_DCA
 319         int cpu;            /* CPU for DCA */
 320 #endif
 321         u16 v_idx;              /* index of q_vector within array, also used for
 322                                  * finding the bit in EICR and friends that
 323                                  * represents the vector for this ring */
 324         u16 itr;                /* Interrupt throttle rate written to EITR */
 325         struct ixgbe_ring_container rx, tx;
 326
 327         struct napi_struct napi;
 328         cpumask_t affinity_mask;
 329         int numa_node;
 330         struct rcu_head rcu;    /* to avoid race with update stats on free */
 331         char name[IFNAMSIZ + 9];
 332
 333         /* for dynamic allocation of rings associated with this q_vector */
 334         struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
 335 };
 336
 337 /*
 338  * microsecond values for various ITR rates shifted by 2 to fit itr register
 339  * with the first 3 bits reserved 0
 340  */
 341 #define IXGBE_MIN_RSC_ITR       24
 342 #define IXGBE_100K_ITR          40
 343 #define IXGBE_20K_ITR           200
 344 #define IXGBE_10K_ITR           400
 345 #define IXGBE_8K_ITR            500
 346
 347 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
 348 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
 349                                         const u32 stat_err_bits)
 350 {
 351         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 352 }
 353
 354 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 355 {
 356         u16 ntc = ring->next_to_clean;
 357         u16 ntu = ring->next_to_use;
 358
 359         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 360 }
 361
 362 #define IXGBE_RX_DESC(R, i)         \
 363         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 364 #define IXGBE_TX_DESC(R, i)         \
 365         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 366 #define IXGBE_TX_CTXTDESC(R, i)     \
 367         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 368
 369 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 370 #ifdef IXGBE_FCOE
 371 /* Use 3K as the baby jumbo frame size for FCoE */
 372 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 373 #endif /* IXGBE_FCOE */
 374
 375 #define OTHER_VECTOR 1
 376 #define NON_Q_VECTORS (OTHER_VECTOR)
 377
 378 #define MAX_MSIX_VECTORS_82599 64
 379 #define MAX_MSIX_Q_VECTORS_82599 64
 380 #define MAX_MSIX_VECTORS_82598 18
 381 #define MAX_MSIX_Q_VECTORS_82598 16
 382
 383 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 384 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 385
 386 #define MIN_MSIX_Q_VECTORS 1
 387 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 388
 389 /* default to trying for four seconds */
 390 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 391
 392 /* board specific private data structure */
 393 struct ixgbe_adapter {
 394         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 395         /* OS defined structs */
 396         struct net_device *netdev;
 397         struct pci_dev *pdev;
 398
 399         unsigned long state;
 400
 401         /* Some features need tri-state capability,
 402          * thus the additional *_CAPABLE flags.
 403          */
 404         u32 flags;
 405 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 406 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 407 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 408 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 409 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 410 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 411 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 412 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 413 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 414 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 415 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 416 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 417 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 418 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 419 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 420 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 421 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 422 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 423 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 424 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 425 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 426 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 427 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 428 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 429 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 430 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 431
 432         u32 flags2;
 433 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 434 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 435 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 436 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 437 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 438 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 439 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 440 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 441
 442
 443         /* Tx fast path data */
 444         int num_tx_queues;
 445         u16 tx_itr_setting;
 446         u16 tx_work_limit;
 447
 448         /* Rx fast path data */
 449         int num_rx_queues;
 450         u16 rx_itr_setting;
 451
 452         /* TX */
 453         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 454
 455         u64 restart_queue;
 456         u64 lsc_int;
 457         u32 tx_timeout_count;
 458
 459         /* RX */
 460         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
 461         int num_rx_pools;               /* == num_rx_queues in 82598 */
 462         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 463         u64 hw_csum_rx_error;
 464         u64 hw_rx_no_dma_resources;
 465         u64 rsc_total_count;
 466         u64 rsc_total_flush;
 467         u64 non_eop_descs;
 468         u32 alloc_rx_page_failed;
 469         u32 alloc_rx_buff_failed;
 470
 471         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 472
 473         /* DCB parameters */
 474         struct ieee_pfc *ixgbe_ieee_pfc;
 475         struct ieee_ets *ixgbe_ieee_ets;
 476         struct ixgbe_dcb_config dcb_cfg;
 477         struct ixgbe_dcb_config temp_dcb_cfg;
 478         u8 dcb_set_bitmap;
 479         u8 dcbx_cap;
 480         enum ixgbe_fc_mode last_lfc_mode;
 481
 482         int num_msix_vectors;
 483         int max_msix_q_vectors;         /* true count of q_vectors for device */
 484         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 485         struct msix_entry *msix_entries;
 486
 487         u32 test_icr;
 488         struct ixgbe_ring test_tx_ring;
 489         struct ixgbe_ring test_rx_ring;
 490
 491         /* structs defined in ixgbe_hw.h */
 492         struct ixgbe_hw hw;
 493         u16 msg_enable;
 494         struct ixgbe_hw_stats stats;
 495
 496         u64 tx_busy;
 497         unsigned int tx_ring_count;
 498         unsigned int rx_ring_count;
 499
 500         u32 link_speed;
 501         bool link_up;
 502         unsigned long link_check_timeout;
 503
 504         struct timer_list service_timer;
 505         struct work_struct service_task;
 506
 507         struct hlist_head fdir_filter_list;
 508         unsigned long fdir_overflow; /* number of times ATR was backed off */
 509         union ixgbe_atr_input fdir_mask;
 510         int fdir_filter_count;
 511         u32 fdir_pballoc;
 512         u32 atr_sample_rate;
 513         spinlock_t fdir_perfect_lock;
 514
 515 #ifdef IXGBE_FCOE
 516         struct ixgbe_fcoe fcoe;
 517 #endif /* IXGBE_FCOE */
 518         u32 wol;
 519
 520         u16 bd_number;
 521
 522         u16 eeprom_verh;
 523         u16 eeprom_verl;
 524         u16 eeprom_cap;
 525
 526         u32 interrupt_event;
 527         u32 led_reg;
 528
 529         /* SR-IOV */
 530         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 531         unsigned int num_vfs;
 532         struct vf_data_storage *vfinfo;
 533         int vf_rate_link_speed;
 534         struct vf_macvlans vf_mvs;
 535         struct vf_macvlans *mv_list;
 536
 537         u32 timer_event_accumulator;
 538         u32 vferr_refcount;
 539 };
 540
 541 struct ixgbe_fdir_filter {
 542         struct hlist_node fdir_node;
 543         union ixgbe_atr_input filter;
 544         u16 sw_idx;
 545         u16 action;
 546 };
 547
 548 enum ixbge_state_t {
 549         __IXGBE_TESTING,
 550         __IXGBE_RESETTING,
 551         __IXGBE_DOWN,
 552         __IXGBE_SERVICE_SCHED,
 553         __IXGBE_IN_SFP_INIT,
 554 };
 555
 556 struct ixgbe_cb {
 557         union {                         /* Union defining head/tail partner */
 558                 struct sk_buff *head;
 559                 struct sk_buff *tail;
 560         };
 561         dma_addr_t dma;
 562         u16 append_cnt;
 563         bool page_released;
 564 };
 565 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
 566
 567 enum ixgbe_boards {
 568         board_82598,
 569         board_82599,
 570         board_X540,
 571 };
 572
 573 extern struct ixgbe_info ixgbe_82598_info;
 574 extern struct ixgbe_info ixgbe_82599_info;
 575 extern struct ixgbe_info ixgbe_X540_info;
 576 #ifdef CONFIG_IXGBE_DCB
 577 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 578 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 579                               struct ixgbe_dcb_config *dst_dcb_cfg,
 580                               int tc_max);
 581 #endif
 582
 583 extern char ixgbe_driver_name[];
 584 extern const char ixgbe_driver_version[];
 585 extern char ixgbe_default_device_descr[];
 586
 587 extern void ixgbe_up(struct ixgbe_adapter *adapter);
 588 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 589 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 590 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 591 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 592 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 593 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 594 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 595 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 596 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 597 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 598 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 599                                    struct ixgbe_ring *);
 600 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 601 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 602 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 603 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 604                                          struct ixgbe_adapter *,
 605                                          struct ixgbe_ring *);
 606 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 607                                              struct ixgbe_tx_buffer *);
 608 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 609 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 610 extern int ethtool_ioctl(struct ifreq *ifr);
 611 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 612 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 613 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 614 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 615                                                  union ixgbe_atr_hash_dword input,
 616                                                  union ixgbe_atr_hash_dword common,
 617                                                  u8 queue);
 618 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 619                                            union ixgbe_atr_input *input_mask);
 620 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 621                                                  union ixgbe_atr_input *input,
 622                                                  u16 soft_id, u8 queue);
 623 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 624                                                  union ixgbe_atr_input *input,
 625                                                  u16 soft_id);
 626 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 627                                                  union ixgbe_atr_input *mask);
 628 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 629 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 630 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 631 extern void ixgbe_do_reset(struct net_device *netdev);
 632 #ifdef IXGBE_FCOE
 633 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 634 extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
 635                      struct ixgbe_tx_buffer *first,
 636                      u8 *hdr_len);
 637 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 638 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 639                           union ixgbe_adv_rx_desc *rx_desc,
 640                           struct sk_buff *skb);
 641 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 642                               struct scatterlist *sgl, unsigned int sgc);
 643 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 644                                  struct scatterlist *sgl, unsigned int sgc);
 645 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 646 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 647 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 648 #ifdef CONFIG_IXGBE_DCB
 649 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 650 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 651 #endif /* CONFIG_IXGBE_DCB */
 652 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 653 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
 654                                   struct netdev_fcoe_hbainfo *info);
 655 #endif /* IXGBE_FCOE */
 656
 657 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
 658 {
 659         return netdev_get_tx_queue(ring->netdev, ring->queue_index);
 660 }
 661
 662 #endif /* _IXGBE_H_ */