?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
perf, x86: Reorder intel_pmu_enable_all()
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event_intel.c
blobd3e2424069a795cae331b74658b23838f5277645
1 #ifdef CONFIG_CPU_SUP_INTEL
2
3 /*
4 * Intel PerfMon, used on Core and later.
5 */
6 static const u64 intel_perfmon_event_map[] =
7 {
8 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
9 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
10 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
11 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
12 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
13 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
14 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
15 };
16
17 static struct event_constraint intel_core_event_constraints[] =
18 {
19 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
20 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
21 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
22 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
23 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
24 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
25 EVENT_CONSTRAINT_END
26 };
27
28 static struct event_constraint intel_core2_event_constraints[] =
29 {
30 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
31 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
32 /*
33 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
34 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
35 * ratio between these counters.
36 */
37 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
38 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
46 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
47 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
48 EVENT_CONSTRAINT_END
49 };
50
51 static struct event_constraint intel_nehalem_event_constraints[] =
52 {
53 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
54 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
55 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
56 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
57 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
58 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
59 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
60 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
61 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
62 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
63 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
64 EVENT_CONSTRAINT_END
65 };
66
67 static struct event_constraint intel_westmere_event_constraints[] =
68 {
69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
71 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
72 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
73 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
74 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
75 EVENT_CONSTRAINT_END
76 };
77
78 static struct event_constraint intel_gen_event_constraints[] =
79 {
80 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
81 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
82 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
83 EVENT_CONSTRAINT_END
84 };
85
86 static u64 intel_pmu_event_map(int hw_event)
87 {
88 return intel_perfmon_event_map[hw_event];
89 }
90
91 static __initconst u64 westmere_hw_cache_event_ids
92 [PERF_COUNT_HW_CACHE_MAX]
93 [PERF_COUNT_HW_CACHE_OP_MAX]
94 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
95 {
96 [ C(L1D) ] = {
97 [ C(OP_READ) ] = {
98 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
99 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
100 },
101 [ C(OP_WRITE) ] = {
102 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
103 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
104 },
105 [ C(OP_PREFETCH) ] = {
106 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
107 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
108 },
109 },
110 [ C(L1I ) ] = {
111 [ C(OP_READ) ] = {
112 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
113 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
114 },
115 [ C(OP_WRITE) ] = {
116 [ C(RESULT_ACCESS) ] = -1,
117 [ C(RESULT_MISS) ] = -1,
118 },
119 [ C(OP_PREFETCH) ] = {
120 [ C(RESULT_ACCESS) ] = 0x0,
121 [ C(RESULT_MISS) ] = 0x0,
122 },
123 },
124 [ C(LL ) ] = {
125 [ C(OP_READ) ] = {
126 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
127 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
128 },
129 [ C(OP_WRITE) ] = {
130 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
131 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
132 },
133 [ C(OP_PREFETCH) ] = {
134 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
135 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
136 },
137 },
138 [ C(DTLB) ] = {
139 [ C(OP_READ) ] = {
140 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
141 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
142 },
143 [ C(OP_WRITE) ] = {
144 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
145 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
146 },
147 [ C(OP_PREFETCH) ] = {
148 [ C(RESULT_ACCESS) ] = 0x0,
149 [ C(RESULT_MISS) ] = 0x0,
150 },
151 },
152 [ C(ITLB) ] = {
153 [ C(OP_READ) ] = {
154 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
155 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
156 },
157 [ C(OP_WRITE) ] = {
158 [ C(RESULT_ACCESS) ] = -1,
159 [ C(RESULT_MISS) ] = -1,
160 },
161 [ C(OP_PREFETCH) ] = {
162 [ C(RESULT_ACCESS) ] = -1,
163 [ C(RESULT_MISS) ] = -1,
164 },
165 },
166 [ C(BPU ) ] = {
167 [ C(OP_READ) ] = {
168 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
169 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
170 },
171 [ C(OP_WRITE) ] = {
172 [ C(RESULT_ACCESS) ] = -1,
173 [ C(RESULT_MISS) ] = -1,
174 },
175 [ C(OP_PREFETCH) ] = {
176 [ C(RESULT_ACCESS) ] = -1,
177 [ C(RESULT_MISS) ] = -1,
178 },
179 },
180 };
181
182 static __initconst u64 nehalem_hw_cache_event_ids
183 [PERF_COUNT_HW_CACHE_MAX]
184 [PERF_COUNT_HW_CACHE_OP_MAX]
185 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
186 {
187 [ C(L1D) ] = {
188 [ C(OP_READ) ] = {
189 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
190 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
191 },
192 [ C(OP_WRITE) ] = {
193 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
194 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
195 },
196 [ C(OP_PREFETCH) ] = {
197 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
198 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
199 },
200 },
201 [ C(L1I ) ] = {
202 [ C(OP_READ) ] = {
203 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
204 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
205 },
206 [ C(OP_WRITE) ] = {
207 [ C(RESULT_ACCESS) ] = -1,
208 [ C(RESULT_MISS) ] = -1,
209 },
210 [ C(OP_PREFETCH) ] = {
211 [ C(RESULT_ACCESS) ] = 0x0,
212 [ C(RESULT_MISS) ] = 0x0,
213 },
214 },
215 [ C(LL ) ] = {
216 [ C(OP_READ) ] = {
217 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
218 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
219 },
220 [ C(OP_WRITE) ] = {
221 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
222 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
223 },
224 [ C(OP_PREFETCH) ] = {
225 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
226 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
227 },
228 },
229 [ C(DTLB) ] = {
230 [ C(OP_READ) ] = {
231 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
232 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
233 },
234 [ C(OP_WRITE) ] = {
235 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
236 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
237 },
238 [ C(OP_PREFETCH) ] = {
239 [ C(RESULT_ACCESS) ] = 0x0,
240 [ C(RESULT_MISS) ] = 0x0,
241 },
242 },
243 [ C(ITLB) ] = {
244 [ C(OP_READ) ] = {
245 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
246 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
247 },
248 [ C(OP_WRITE) ] = {
249 [ C(RESULT_ACCESS) ] = -1,
250 [ C(RESULT_MISS) ] = -1,
251 },
252 [ C(OP_PREFETCH) ] = {
253 [ C(RESULT_ACCESS) ] = -1,
254 [ C(RESULT_MISS) ] = -1,
255 },
256 },
257 [ C(BPU ) ] = {
258 [ C(OP_READ) ] = {
259 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
260 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
261 },
262 [ C(OP_WRITE) ] = {
263 [ C(RESULT_ACCESS) ] = -1,
264 [ C(RESULT_MISS) ] = -1,
265 },
266 [ C(OP_PREFETCH) ] = {
267 [ C(RESULT_ACCESS) ] = -1,
268 [ C(RESULT_MISS) ] = -1,
269 },
270 },
271 };
272
273 static __initconst u64 core2_hw_cache_event_ids
274 [PERF_COUNT_HW_CACHE_MAX]
275 [PERF_COUNT_HW_CACHE_OP_MAX]
276 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
277 {
278 [ C(L1D) ] = {
279 [ C(OP_READ) ] = {
280 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
281 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
282 },
283 [ C(OP_WRITE) ] = {
284 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
285 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
286 },
287 [ C(OP_PREFETCH) ] = {
288 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
289 [ C(RESULT_MISS) ] = 0,
290 },
291 },
292 [ C(L1I ) ] = {
293 [ C(OP_READ) ] = {
294 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
295 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
296 },
297 [ C(OP_WRITE) ] = {
298 [ C(RESULT_ACCESS) ] = -1,
299 [ C(RESULT_MISS) ] = -1,
300 },
301 [ C(OP_PREFETCH) ] = {
302 [ C(RESULT_ACCESS) ] = 0,
303 [ C(RESULT_MISS) ] = 0,
304 },
305 },
306 [ C(LL ) ] = {
307 [ C(OP_READ) ] = {
308 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
309 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
310 },
311 [ C(OP_WRITE) ] = {
312 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
313 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
314 },
315 [ C(OP_PREFETCH) ] = {
316 [ C(RESULT_ACCESS) ] = 0,
317 [ C(RESULT_MISS) ] = 0,
318 },
319 },
320 [ C(DTLB) ] = {
321 [ C(OP_READ) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
323 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
324 },
325 [ C(OP_WRITE) ] = {
326 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
327 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
328 },
329 [ C(OP_PREFETCH) ] = {
330 [ C(RESULT_ACCESS) ] = 0,
331 [ C(RESULT_MISS) ] = 0,
332 },
333 },
334 [ C(ITLB) ] = {
335 [ C(OP_READ) ] = {
336 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
337 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
338 },
339 [ C(OP_WRITE) ] = {
340 [ C(RESULT_ACCESS) ] = -1,
341 [ C(RESULT_MISS) ] = -1,
342 },
343 [ C(OP_PREFETCH) ] = {
344 [ C(RESULT_ACCESS) ] = -1,
345 [ C(RESULT_MISS) ] = -1,
346 },
347 },
348 [ C(BPU ) ] = {
349 [ C(OP_READ) ] = {
350 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
351 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
352 },
353 [ C(OP_WRITE) ] = {
354 [ C(RESULT_ACCESS) ] = -1,
355 [ C(RESULT_MISS) ] = -1,
356 },
357 [ C(OP_PREFETCH) ] = {
358 [ C(RESULT_ACCESS) ] = -1,
359 [ C(RESULT_MISS) ] = -1,
360 },
361 },
362 };
363
364 static __initconst u64 atom_hw_cache_event_ids
365 [PERF_COUNT_HW_CACHE_MAX]
366 [PERF_COUNT_HW_CACHE_OP_MAX]
367 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
368 {
369 [ C(L1D) ] = {
370 [ C(OP_READ) ] = {
371 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
372 [ C(RESULT_MISS) ] = 0,
373 },
374 [ C(OP_WRITE) ] = {
375 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
376 [ C(RESULT_MISS) ] = 0,
377 },
378 [ C(OP_PREFETCH) ] = {
379 [ C(RESULT_ACCESS) ] = 0x0,
380 [ C(RESULT_MISS) ] = 0,
381 },
382 },
383 [ C(L1I ) ] = {
384 [ C(OP_READ) ] = {
385 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
386 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
387 },
388 [ C(OP_WRITE) ] = {
389 [ C(RESULT_ACCESS) ] = -1,
390 [ C(RESULT_MISS) ] = -1,
391 },
392 [ C(OP_PREFETCH) ] = {
393 [ C(RESULT_ACCESS) ] = 0,
394 [ C(RESULT_MISS) ] = 0,
395 },
396 },
397 [ C(LL ) ] = {
398 [ C(OP_READ) ] = {
399 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
400 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
401 },
402 [ C(OP_WRITE) ] = {
403 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
404 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
405 },
406 [ C(OP_PREFETCH) ] = {
407 [ C(RESULT_ACCESS) ] = 0,
408 [ C(RESULT_MISS) ] = 0,
409 },
410 },
411 [ C(DTLB) ] = {
412 [ C(OP_READ) ] = {
413 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
414 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
415 },
416 [ C(OP_WRITE) ] = {
417 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
418 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
419 },
420 [ C(OP_PREFETCH) ] = {
421 [ C(RESULT_ACCESS) ] = 0,
422 [ C(RESULT_MISS) ] = 0,
423 },
424 },
425 [ C(ITLB) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
428 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
429 },
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = -1,
432 [ C(RESULT_MISS) ] = -1,
433 },
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = -1,
436 [ C(RESULT_MISS) ] = -1,
437 },
438 },
439 [ C(BPU ) ] = {
440 [ C(OP_READ) ] = {
441 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
442 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = -1,
446 [ C(RESULT_MISS) ] = -1,
447 },
448 [ C(OP_PREFETCH) ] = {
449 [ C(RESULT_ACCESS) ] = -1,
450 [ C(RESULT_MISS) ] = -1,
451 },
452 },
453 };
454
455 static u64 intel_pmu_raw_event(u64 hw_event)
456 {
457 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
458 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
459 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
460 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
461 #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
462
463 #define CORE_EVNTSEL_MASK \
464 (INTEL_ARCH_EVTSEL_MASK | \
465 INTEL_ARCH_UNIT_MASK | \
466 INTEL_ARCH_EDGE_MASK | \
467 INTEL_ARCH_INV_MASK | \
468 INTEL_ARCH_CNT_MASK)
469
470 return hw_event & CORE_EVNTSEL_MASK;
471 }
472
473 static void intel_pmu_disable_all(void)
474 {
475 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
476
477 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
478
479 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
480 intel_pmu_disable_bts();
481
482 intel_pmu_pebs_disable_all();
483 intel_pmu_lbr_disable_all();
484 }
485
486 static void intel_pmu_enable_all(void)
487 {
488 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
489
490 intel_pmu_pebs_enable_all();
491 intel_pmu_lbr_enable_all();
492 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
493
494 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
495 struct perf_event *event =
496 cpuc->events[X86_PMC_IDX_FIXED_BTS];
497
498 if (WARN_ON_ONCE(!event))
499 return;
500
501 intel_pmu_enable_bts(event->hw.config);
502 }
503 }
504
505 static inline u64 intel_pmu_get_status(void)
506 {
507 u64 status;
508
509 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
510
511 return status;
512 }
513
514 static inline void intel_pmu_ack_status(u64 ack)
515 {
516 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
517 }
518
519 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
520 {
521 int idx = hwc->idx - X86_PMC_IDX_FIXED;
522 u64 ctrl_val, mask;
523
524 mask = 0xfULL << (idx * 4);
525
526 rdmsrl(hwc->config_base, ctrl_val);
527 ctrl_val &= ~mask;
528 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
529 }
530
531 static void intel_pmu_disable_event(struct perf_event *event)
532 {
533 struct hw_perf_event *hwc = &event->hw;
534
535 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
536 intel_pmu_disable_bts();
537 intel_pmu_drain_bts_buffer();
538 return;
539 }
540
541 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
542 intel_pmu_disable_fixed(hwc);
543 return;
544 }
545
546 x86_pmu_disable_event(event);
547
548 if (unlikely(event->attr.precise))
549 intel_pmu_pebs_disable(event);
550 }
551
552 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
553 {
554 int idx = hwc->idx - X86_PMC_IDX_FIXED;
555 u64 ctrl_val, bits, mask;
556 int err;
557
558 /*
559 * Enable IRQ generation (0x8),
560 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
561 * if requested:
562 */
563 bits = 0x8ULL;
564 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
565 bits |= 0x2;
566 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
567 bits |= 0x1;
568
569 /*
570 * ANY bit is supported in v3 and up
571 */
572 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
573 bits |= 0x4;
574
575 bits <<= (idx * 4);
576 mask = 0xfULL << (idx * 4);
577
578 rdmsrl(hwc->config_base, ctrl_val);
579 ctrl_val &= ~mask;
580 ctrl_val |= bits;
581 err = checking_wrmsrl(hwc->config_base, ctrl_val);
582 }
583
584 static void intel_pmu_enable_event(struct perf_event *event)
585 {
586 struct hw_perf_event *hwc = &event->hw;
587
588 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
589 if (!__get_cpu_var(cpu_hw_events).enabled)
590 return;
591
592 intel_pmu_enable_bts(hwc->config);
593 return;
594 }
595
596 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
597 intel_pmu_enable_fixed(hwc);
598 return;
599 }
600
601 if (unlikely(event->attr.precise))
602 intel_pmu_pebs_enable(event);
603
604 __x86_pmu_enable_event(hwc);
605 }
606
607 /*
608 * Save and restart an expired event. Called by NMI contexts,
609 * so it has to be careful about preempting normal event ops:
610 */
611 static int intel_pmu_save_and_restart(struct perf_event *event)
612 {
613 x86_perf_event_update(event);
614 return x86_perf_event_set_period(event);
615 }
616
617 static void intel_pmu_reset(void)
618 {
619 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
620 unsigned long flags;
621 int idx;
622
623 if (!x86_pmu.num_events)
624 return;
625
626 local_irq_save(flags);
627
628 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
629
630 for (idx = 0; idx < x86_pmu.num_events; idx++) {
631 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
632 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
633 }
634 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
635 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
636 }
637 if (ds)
638 ds->bts_index = ds->bts_buffer_base;
639
640 local_irq_restore(flags);
641 }
642
643 /*
644 * This handler is triggered by the local APIC, so the APIC IRQ handling
645 * rules apply:
646 */
647 static int intel_pmu_handle_irq(struct pt_regs *regs)
648 {
649 struct perf_sample_data data;
650 struct cpu_hw_events *cpuc;
651 int bit, loops;
652 u64 ack, status;
653
654 perf_sample_data_init(&data, 0);
655
656 cpuc = &__get_cpu_var(cpu_hw_events);
657
658 intel_pmu_disable_all();
659 intel_pmu_drain_bts_buffer();
660 status = intel_pmu_get_status();
661 if (!status) {
662 intel_pmu_enable_all();
663 return 0;
664 }
665
666 loops = 0;
667 again:
668 if (++loops > 100) {
669 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
670 perf_event_print_debug();
671 intel_pmu_reset();
672 goto done;
673 }
674
675 inc_irq_stat(apic_perf_irqs);
676 ack = status;
677
678 intel_pmu_lbr_read();
679
680 /*
681 * PEBS overflow sets bit 62 in the global status register
682 */
683 if (__test_and_clear_bit(62, (unsigned long *)&status))
684 x86_pmu.drain_pebs(regs);
685
686 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
687 struct perf_event *event = cpuc->events[bit];
688
689 if (!test_bit(bit, cpuc->active_mask))
690 continue;
691
692 if (!intel_pmu_save_and_restart(event))
693 continue;
694
695 data.period = event->hw.last_period;
696
697 if (perf_event_overflow(event, 1, &data, regs))
698 x86_pmu_stop(event);
699 }
700
701 intel_pmu_ack_status(ack);
702
703 /*
704 * Repeat if there is more work to be done:
705 */
706 status = intel_pmu_get_status();
707 if (status)
708 goto again;
709
710 done:
711 intel_pmu_enable_all();
712 return 1;
713 }
714
715 static struct event_constraint *
716 intel_bts_constraints(struct perf_event *event)
717 {
718 struct hw_perf_event *hwc = &event->hw;
719 unsigned int hw_event, bts_event;
720
721 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
722 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
723
724 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
725 return &bts_constraint;
726
727 return NULL;
728 }
729
730 static struct event_constraint *
731 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
732 {
733 struct event_constraint *c;
734
735 c = intel_bts_constraints(event);
736 if (c)
737 return c;
738
739 c = intel_pebs_constraints(event);
740 if (c)
741 return c;
742
743 return x86_get_event_constraints(cpuc, event);
744 }
745
746 static __initconst struct x86_pmu core_pmu = {
747 .name = "core",
748 .handle_irq = x86_pmu_handle_irq,
749 .disable_all = x86_pmu_disable_all,
750 .enable_all = x86_pmu_enable_all,
751 .enable = x86_pmu_enable_event,
752 .disable = x86_pmu_disable_event,
753 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
754 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
755 .event_map = intel_pmu_event_map,
756 .raw_event = intel_pmu_raw_event,
757 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
758 .apic = 1,
759 /*
760 * Intel PMCs cannot be accessed sanely above 32 bit width,
761 * so we install an artificial 1<<31 period regardless of
762 * the generic event period:
763 */
764 .max_period = (1ULL << 31) - 1,
765 .get_event_constraints = intel_get_event_constraints,
766 .event_constraints = intel_core_event_constraints,
767 };
768
769 static void intel_pmu_cpu_starting(int cpu)
770 {
771 init_debug_store_on_cpu(cpu);
772 /*
773 * Deal with CPUs that don't clear their LBRs on power-up.
774 */
775 intel_pmu_lbr_reset();
776 }
777
778 static void intel_pmu_cpu_dying(int cpu)
779 {
780 fini_debug_store_on_cpu(cpu);
781 }
782
783 static __initconst struct x86_pmu intel_pmu = {
784 .name = "Intel",
785 .handle_irq = intel_pmu_handle_irq,
786 .disable_all = intel_pmu_disable_all,
787 .enable_all = intel_pmu_enable_all,
788 .enable = intel_pmu_enable_event,
789 .disable = intel_pmu_disable_event,
790 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
791 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
792 .event_map = intel_pmu_event_map,
793 .raw_event = intel_pmu_raw_event,
794 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
795 .apic = 1,
796 /*
797 * Intel PMCs cannot be accessed sanely above 32 bit width,
798 * so we install an artificial 1<<31 period regardless of
799 * the generic event period:
800 */
801 .max_period = (1ULL << 31) - 1,
802 .get_event_constraints = intel_get_event_constraints,
803
804 .cpu_starting = intel_pmu_cpu_starting,
805 .cpu_dying = intel_pmu_cpu_dying,
806 };
807
808 static void intel_clovertown_quirks(void)
809 {
810 /*
811 * PEBS is unreliable due to:
812 *
813 * AJ67 - PEBS may experience CPL leaks
814 * AJ68 - PEBS PMI may be delayed by one event
815 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
816 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
817 *
818 * AJ67 could be worked around by restricting the OS/USR flags.
819 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
820 *
821 * AJ106 could possibly be worked around by not allowing LBR
822 * usage from PEBS, including the fixup.
823 * AJ68 could possibly be worked around by always programming
824 * a pebs_event_reset[0] value and coping with the lost events.
825 *
826 * But taken together it might just make sense to not enable PEBS on
827 * these chips.
828 */
829 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
830 x86_pmu.pebs = 0;
831 x86_pmu.pebs_constraints = NULL;
832 }
833
834 static __init int intel_pmu_init(void)
835 {
836 union cpuid10_edx edx;
837 union cpuid10_eax eax;
838 unsigned int unused;
839 unsigned int ebx;
840 int version;
841
842 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
843 /* check for P6 processor family */
844 if (boot_cpu_data.x86 == 6) {
845 return p6_pmu_init();
846 } else {
847 return -ENODEV;
848 }
849 }
850
851 /*
852 * Check whether the Architectural PerfMon supports
853 * Branch Misses Retired hw_event or not.
854 */
855 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
856 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
857 return -ENODEV;
858
859 version = eax.split.version_id;
860 if (version < 2)
861 x86_pmu = core_pmu;
862 else
863 x86_pmu = intel_pmu;
864
865 x86_pmu.version = version;
866 x86_pmu.num_events = eax.split.num_events;
867 x86_pmu.event_bits = eax.split.bit_width;
868 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
869
870 /*
871 * Quirk: v2 perfmon does not report fixed-purpose events, so
872 * assume at least 3 events:
873 */
874 if (version > 1)
875 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
876
877 /*
878 * v2 and above have a perf capabilities MSR
879 */
880 if (version > 1) {
881 u64 capabilities;
882
883 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
884 x86_pmu.intel_cap.capabilities = capabilities;
885 }
886
887 intel_ds_init();
888
889 /*
890 * Install the hw-cache-events table:
891 */
892 switch (boot_cpu_data.x86_model) {
893 case 14: /* 65 nm core solo/duo, "Yonah" */
894 pr_cont("Core events, ");
895 break;
896
897 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
898 x86_pmu.quirks = intel_clovertown_quirks;
899 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
900 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
901 case 29: /* six-core 45 nm xeon "Dunnington" */
902 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
903 sizeof(hw_cache_event_ids));
904
905 intel_pmu_lbr_init_core();
906
907 x86_pmu.event_constraints = intel_core2_event_constraints;
908 pr_cont("Core2 events, ");
909 break;
910
911 case 26: /* 45 nm nehalem, "Bloomfield" */
912 case 30: /* 45 nm nehalem, "Lynnfield" */
913 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
914 sizeof(hw_cache_event_ids));
915
916 intel_pmu_lbr_init_nhm();
917
918 x86_pmu.event_constraints = intel_nehalem_event_constraints;
919 pr_cont("Nehalem/Corei7 events, ");
920 break;
921
922 case 28: /* Atom */
923 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
924 sizeof(hw_cache_event_ids));
925
926 intel_pmu_lbr_init_atom();
927
928 x86_pmu.event_constraints = intel_gen_event_constraints;
929 pr_cont("Atom events, ");
930 break;
931
932 case 37: /* 32 nm nehalem, "Clarkdale" */
933 case 44: /* 32 nm nehalem, "Gulftown" */
934 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
935 sizeof(hw_cache_event_ids));
936
937 intel_pmu_lbr_init_nhm();
938
939 x86_pmu.event_constraints = intel_westmere_event_constraints;
940 pr_cont("Westmere events, ");
941 break;
942
943 default:
944 /*
945 * default constraints for v2 and up
946 */
947 x86_pmu.event_constraints = intel_gen_event_constraints;
948 pr_cont("generic architected perfmon, ");
949 }
950 return 0;
951 }
952
953 #else /* CONFIG_CPU_SUP_INTEL */
954
955 static int intel_pmu_init(void)
956 {
957 return 0;
958 }
959
960 #endif /* CONFIG_CPU_SUP_INTEL */
Linus' kernel tree