drivers/net/sfc/qt202x_phy.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
  11  */
  12
  13 #include <linux/timer.h>
  14 #include <linux/delay.h>
  15 #include "efx.h"
  16 #include "mdio_10g.h"
  17 #include "phy.h"
  18 #include "falcon.h"
  19
  20 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |           \
  21                               MDIO_DEVS_PMAPMD |        \
  22                               MDIO_DEVS_PHYXS)
  23
  24 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |         \
  25                           (1 << LOOPBACK_PMAPMD) |      \
  26                           (1 << LOOPBACK_NETWORK))
  27
  28 /****************************************************************************/
  29 /* Quake-specific MDIO registers */
  30 #define MDIO_QUAKE_LED0_REG     (0xD006)
  31
  32 /* QT2025C only */
  33 #define PCS_FW_HEARTBEAT_REG    0xd7ee
  34 #define PCS_FW_HEARTB_LBN       0
  35 #define PCS_FW_HEARTB_WIDTH     8
  36 #define PCS_UC8051_STATUS_REG   0xd7fd
  37 #define PCS_UC_STATUS_LBN       0
  38 #define PCS_UC_STATUS_WIDTH     8
  39 #define PCS_UC_STATUS_FW_SAVE   0x20
  40 #define PMA_PMD_FTX_CTRL2_REG   0xc309
  41 #define PMA_PMD_FTX_STATIC_LBN  13
  42 #define PMA_PMD_VEND1_REG       0xc001
  43 #define PMA_PMD_VEND1_LBTXD_LBN 15
  44 #define PCS_VEND1_REG           0xc000
  45 #define PCS_VEND1_LBTXD_LBN     5
  46
  47 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
  48 {
  49         int addr = MDIO_QUAKE_LED0_REG + led;
  50         efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
  51 }
  52
  53 struct qt202x_phy_data {
  54         enum efx_phy_mode phy_mode;
  55 };
  56
  57 #define QT2022C2_MAX_RESET_TIME 500
  58 #define QT2022C2_RESET_WAIT 10
  59
  60 static int qt2025c_wait_reset(struct efx_nic *efx)
  61 {
  62         unsigned long timeout = jiffies + 10 * HZ;
  63         int reg, old_counter = 0;
  64
  65         /* Wait for firmware heartbeat to start */
  66         for (;;) {
  67                 int counter;
  68                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
  69                 if (reg < 0)
  70                         return reg;
  71                 counter = ((reg >> PCS_FW_HEARTB_LBN) &
  72                             ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  73                 if (old_counter == 0)
  74                         old_counter = counter;
  75                 else if (counter != old_counter)
  76                         break;
  77                 if (time_after(jiffies, timeout))
  78                         return -ETIMEDOUT;
  79                 msleep(10);
  80         }
  81
  82         /* Wait for firmware status to look good */
  83         for (;;) {
  84                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
  85                 if (reg < 0)
  86                         return reg;
  87                 if ((reg &
  88                      ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
  89                     PCS_UC_STATUS_FW_SAVE)
  90                         break;
  91                 if (time_after(jiffies, timeout))
  92                         return -ETIMEDOUT;
  93                 msleep(100);
  94         }
  95
  96         return 0;
  97 }
  98
  99 static int qt202x_reset_phy(struct efx_nic *efx)
 100 {
 101         int rc;
 102
 103         if (efx->phy_type == PHY_TYPE_QT2025C) {
 104                 /* Wait for the reset triggered by falcon_reset_hw()
 105                  * to complete */
 106                 rc = qt2025c_wait_reset(efx);
 107                 if (rc < 0)
 108                         goto fail;
 109         } else {
 110                 /* Reset the PHYXS MMD. This is documented as doing
 111                  * a complete soft reset. */
 112                 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
 113                                         QT2022C2_MAX_RESET_TIME /
 114                                         QT2022C2_RESET_WAIT,
 115                                         QT2022C2_RESET_WAIT);
 116                 if (rc < 0)
 117                         goto fail;
 118         }
 119
 120         /* Wait 250ms for the PHY to complete bootup */
 121         msleep(250);
 122
 123         /* Check that all the MMDs we expect are present and responding. We
 124          * expect faults on some if the link is down, but not on the PHY XS */
 125         rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
 126         if (rc < 0)
 127                 goto fail;
 128
 129         falcon_board(efx)->type->init_phy(efx);
 130
 131         return rc;
 132
 133  fail:
 134         EFX_ERR(efx, "PHY reset timed out\n");
 135         return rc;
 136 }
 137
 138 static int qt202x_phy_init(struct efx_nic *efx)
 139 {
 140         struct qt202x_phy_data *phy_data;
 141         u32 devid;
 142         int rc;
 143
 144         rc = qt202x_reset_phy(efx);
 145         if (rc) {
 146                 EFX_ERR(efx, "PHY init failed\n");
 147                 return rc;
 148         }
 149
 150         phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
 151         if (!phy_data)
 152                 return -ENOMEM;
 153         efx->phy_data = phy_data;
 154
 155         devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
 156         EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
 157                  devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
 158                  efx_mdio_id_rev(devid));
 159
 160         phy_data->phy_mode = efx->phy_mode;
 161         return 0;
 162 }
 163
 164 static int qt202x_link_ok(struct efx_nic *efx)
 165 {
 166         return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
 167 }
 168
 169 static bool qt202x_phy_poll(struct efx_nic *efx)
 170 {
 171         bool was_up = efx->link_state.up;
 172
 173         efx->link_state.up = qt202x_link_ok(efx);
 174         efx->link_state.speed = 10000;
 175         efx->link_state.fd = true;
 176         efx->link_state.fc = efx->wanted_fc;
 177
 178         return efx->link_state.up != was_up;
 179 }
 180
 181 static int qt202x_phy_reconfigure(struct efx_nic *efx)
 182 {
 183         struct qt202x_phy_data *phy_data = efx->phy_data;
 184
 185         if (efx->phy_type == PHY_TYPE_QT2025C) {
 186                 /* There are several different register bits which can
 187                  * disable TX (and save power) on direct-attach cables
 188                  * or optical transceivers, varying somewhat between
 189                  * firmware versions.  Only 'static mode' appears to
 190                  * cover everything. */
 191                 mdio_set_flag(
 192                         &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
 193                         PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
 194                         efx->phy_mode & PHY_MODE_TX_DISABLED ||
 195                         efx->phy_mode & PHY_MODE_LOW_POWER ||
 196                         efx->loopback_mode == LOOPBACK_PCS ||
 197                         efx->loopback_mode == LOOPBACK_PMAPMD);
 198         } else {
 199                 /* Reset the PHY when moving from tx off to tx on */
 200                 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
 201                     (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
 202                         qt202x_reset_phy(efx);
 203
 204                 efx_mdio_transmit_disable(efx);
 205         }
 206
 207         efx_mdio_phy_reconfigure(efx);
 208
 209         phy_data->phy_mode = efx->phy_mode;
 210
 211         return 0;
 212 }
 213
 214 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 215 {
 216         mdio45_ethtool_gset(&efx->mdio, ecmd);
 217 }
 218
 219 static void qt202x_phy_fini(struct efx_nic *efx)
 220 {
 221         /* Free the context block */
 222         kfree(efx->phy_data);
 223         efx->phy_data = NULL;
 224 }
 225
 226 struct efx_phy_operations falcon_qt202x_phy_ops = {
 227         .macs            = EFX_XMAC,
 228         .init            = qt202x_phy_init,
 229         .reconfigure     = qt202x_phy_reconfigure,
 230         .poll            = qt202x_phy_poll,
 231         .fini            = qt202x_phy_fini,
 232         .get_settings    = qt202x_phy_get_settings,
 233         .set_settings    = efx_mdio_set_settings,
 234         .mmds            = QT202X_REQUIRED_DEVS,
 235         .loopbacks       = QT202X_LOOPBACKS,
 236 };