2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
17 #include "r8192E_dm.h"
18 #include "r8192E_hw.h"
19 #include "r819xE_phy.h"
20 #include "r819xE_phyreg.h"
21 #include "r8190_rtl8256.h"
23 #define DRV_NAME "rtl819xE"
26 // Indicate different AP vendor for IOT issue.
29 static const u32 edca_setting_DL
[HT_IOT_PEER_MAX
] =
30 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
31 static const u32 edca_setting_UL
[HT_IOT_PEER_MAX
] =
32 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
35 static const u32 edca_setting_DL
[HT_IOT_PEER_MAX
] =
36 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
37 static const u32 edca_setting_UL
[HT_IOT_PEER_MAX
] =
38 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
40 static const u32 edca_setting_DL
[HT_IOT_PEER_MAX
] =
41 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322};
42 static const u32 edca_setting_UL
[HT_IOT_PEER_MAX
] =
43 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322};
47 #define RTK_UL_EDCA 0xa44f
48 #define RTK_DL_EDCA 0x5e4322
52 // For Dynamic Rx Path Selection by Signal Strength
53 DRxPathSel DM_RxPathSelTable
;
56 /*--------------------Define export function prototype-----------------------*/
57 extern void init_hal_dm(struct net_device
*dev
);
58 extern void deinit_hal_dm(struct net_device
*dev
);
60 extern void hal_dm_watchdog(struct net_device
*dev
);
63 extern void init_rate_adaptive(struct net_device
*dev
);
64 extern void dm_txpower_trackingcallback(struct work_struct
*work
);
66 extern void dm_cck_txpower_adjust(struct net_device
*dev
,bool binch14
);
67 extern void dm_restore_dynamic_mechanism_state(struct net_device
*dev
);
68 extern void dm_backup_dynamic_mechanism_state(struct net_device
*dev
);
69 extern void dm_change_dynamic_initgain_thresh(struct net_device
*dev
,
72 extern void DM_ChangeFsyncSetting(struct net_device
*dev
,
75 extern void dm_force_tx_fw_info(struct net_device
*dev
,
78 extern void dm_init_edca_turbo(struct net_device
*dev
);
79 extern void dm_rf_operation_test_callback(unsigned long data
);
80 extern void dm_rf_pathcheck_workitemcallback(struct work_struct
*work
);
81 extern void dm_fsync_timer_callback(unsigned long data
);
82 extern void dm_check_fsync(struct net_device
*dev
);
83 extern void dm_initialize_txpower_tracking(struct net_device
*dev
);
86 extern void dm_gpio_change_rf_callback(struct work_struct
*work
);
90 // DM --> Rate Adaptive
91 static void dm_check_rate_adaptive(struct net_device
*dev
);
93 // DM --> Bandwidth switch
94 static void dm_init_bandwidth_autoswitch(struct net_device
*dev
);
95 static void dm_bandwidth_autoswitch( struct net_device
*dev
);
97 // DM --> TX power control
98 static void dm_check_txpower_tracking(struct net_device
*dev
);
100 // DM --> BB init gain restore
102 static void dm_bb_initialgain_restore(struct net_device
*dev
);
104 // DM --> BB init gain backup
105 static void dm_bb_initialgain_backup(struct net_device
*dev
);
108 // DM --> Dynamic Init Gain by RSSI
109 static void dm_dig_init(struct net_device
*dev
);
110 static void dm_ctrl_initgain_byrssi(struct net_device
*dev
);
111 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device
*dev
);
112 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device
*dev
);
113 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device
*dev
);
114 static void dm_initial_gain(struct net_device
*dev
);
115 static void dm_pd_th(struct net_device
*dev
);
116 static void dm_cs_ratio(struct net_device
*dev
);
118 static void dm_init_ctstoself(struct net_device
*dev
);
119 // DM --> EDCA turboe mode control
120 static void dm_check_edca_turbo(struct net_device
*dev
);
122 // DM --> HW RF control
123 static void dm_check_rfctrl_gpio(struct net_device
*dev
);
126 static void dm_check_pbc_gpio(struct net_device
*dev
);
128 // DM --> Check current RX RF path state
129 static void dm_check_rx_path_selection(struct net_device
*dev
);
130 static void dm_init_rxpath_selection(struct net_device
*dev
);
131 static void dm_rxpath_sel_byrssi(struct net_device
*dev
);
133 // DM --> Fsync for broadcom ap
134 static void dm_init_fsync(struct net_device
*dev
);
135 static void dm_deInit_fsync(struct net_device
*dev
);
137 static void dm_check_txrateandretrycount(struct net_device
*dev
);
140 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
141 static void dm_init_dynamic_txpower(struct net_device
*dev
);
142 static void dm_dynamic_txpower(struct net_device
*dev
);
144 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
145 static void dm_send_rssi_tofw(struct net_device
*dev
);
146 static void dm_ctstoself(struct net_device
*dev
);
149 * Prepare SW resource for HW dynamic mechanism.
150 * This function is only invoked at driver intialization once.
152 void init_hal_dm(struct net_device
*dev
)
154 struct r8192_priv
*priv
= ieee80211_priv(dev
);
156 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
157 priv
->undecorated_smoothed_pwdb
= -1;
159 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
160 dm_init_dynamic_txpower(dev
);
161 init_rate_adaptive(dev
);
162 //dm_initialize_txpower_tracking(dev);
164 dm_init_edca_turbo(dev
);
165 dm_init_bandwidth_autoswitch(dev
);
167 dm_init_rxpath_selection(dev
);
168 dm_init_ctstoself(dev
);
170 INIT_DELAYED_WORK(&priv
->gpio_change_rf_wq
, dm_gpio_change_rf_callback
);
175 void deinit_hal_dm(struct net_device
*dev
)
178 dm_deInit_fsync(dev
);
183 #ifdef USB_RX_AGGREGATION_SUPPORT
184 void dm_CheckRxAggregation(struct net_device
*dev
) {
185 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
186 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
187 static unsigned long lastTxOkCnt
= 0;
188 static unsigned long lastRxOkCnt
= 0;
189 unsigned long curTxOkCnt
= 0;
190 unsigned long curRxOkCnt
= 0;
192 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
193 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
195 if((curTxOkCnt
+ curRxOkCnt
) < 15000000) {
199 if(curTxOkCnt
> 4*curRxOkCnt
) {
200 if (priv
->bCurrentRxAggrEnable
) {
201 write_nic_dword(dev
, 0x1a8, 0);
202 priv
->bCurrentRxAggrEnable
= false;
205 if (!priv
->bCurrentRxAggrEnable
&& !pHTInfo
->bCurrentRT2RTAggregation
) {
207 ulValue
= (pHTInfo
->UsbRxFwAggrEn
<<24) | (pHTInfo
->UsbRxFwAggrPageNum
<<16) |
208 (pHTInfo
->UsbRxFwAggrPacketNum
<<8) | (pHTInfo
->UsbRxFwAggrTimeout
);
210 * If usb rx firmware aggregation is enabled,
211 * when anyone of three threshold conditions above is reached,
212 * firmware will send aggregated packet to driver.
214 write_nic_dword(dev
, 0x1a8, ulValue
);
215 priv
->bCurrentRxAggrEnable
= true;
219 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
220 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
225 // call the script file to enable
226 void dm_check_ac_dc_power(struct net_device
*dev
)
228 struct r8192_priv
*priv
= ieee80211_priv(dev
);
229 static char *ac_dc_check_script_path
= "/etc/acpi/wireless-rtl-ac-dc-power.sh";
230 char *argv
[] = {ac_dc_check_script_path
,DRV_NAME
,NULL
};
231 static char *envp
[] = {"HOME=/",
233 "PATH=/usr/bin:/bin",
236 if(priv
->ResetProgress
== RESET_TYPE_SILENT
)
238 RT_TRACE((COMP_INIT
| COMP_POWER
| COMP_RF
), "GPIOChangeRFWorkItemCallBack(): Silent Reseting!!!!!!!\n");
242 if(priv
->ieee80211
->state
!= IEEE80211_LINKED
) {
245 call_usermodehelper(ac_dc_check_script_path
,argv
,envp
,1);
248 void hal_dm_watchdog(struct net_device
*dev
)
250 dm_check_ac_dc_power(dev
);
252 /*Add by amy 2008/05/15 ,porting from windows code.*/
253 dm_check_rate_adaptive(dev
);
254 dm_dynamic_txpower(dev
);
255 dm_check_txrateandretrycount(dev
);
257 dm_check_txpower_tracking(dev
);
259 dm_ctrl_initgain_byrssi(dev
);
260 dm_check_edca_turbo(dev
);
261 dm_bandwidth_autoswitch(dev
);
263 dm_check_rfctrl_gpio(dev
);
264 dm_check_rx_path_selection(dev
);
267 // Add by amy 2008-05-15 porting from windows code.
268 dm_check_pbc_gpio(dev
);
269 dm_send_rssi_tofw(dev
);
272 #ifdef USB_RX_AGGREGATION_SUPPORT
273 dm_CheckRxAggregation(dev
);
279 * Decide Rate Adaptive Set according to distance (signal strength)
280 * 01/11/2008 MHC Modify input arguments and RATR table level.
281 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
282 * the function after making sure RF_Type.
284 void init_rate_adaptive(struct net_device
* dev
)
287 struct r8192_priv
*priv
= ieee80211_priv(dev
);
288 prate_adaptive pra
= (prate_adaptive
)&priv
->rate_adaptive
;
290 pra
->ratr_state
= DM_RATR_STA_MAX
;
291 pra
->high2low_rssi_thresh_for_ra
= RateAdaptiveTH_High
;
292 pra
->low2high_rssi_thresh_for_ra20M
= RateAdaptiveTH_Low_20M
+5;
293 pra
->low2high_rssi_thresh_for_ra40M
= RateAdaptiveTH_Low_40M
+5;
295 pra
->high_rssi_thresh_for_ra
= RateAdaptiveTH_High
+5;
296 pra
->low_rssi_thresh_for_ra20M
= RateAdaptiveTH_Low_20M
;
297 pra
->low_rssi_thresh_for_ra40M
= RateAdaptiveTH_Low_40M
;
299 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
300 pra
->ping_rssi_enable
= 1;
302 pra
->ping_rssi_enable
= 0;
303 pra
->ping_rssi_thresh_for_ra
= 15;
306 if (priv
->rf_type
== RF_2T4R
)
308 // 07/10/08 MH Modify for RA smooth scheme.
309 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
310 pra
->upper_rssi_threshold_ratr
= 0x8f0f0000;
311 pra
->middle_rssi_threshold_ratr
= 0x8f0ff000;
312 pra
->low_rssi_threshold_ratr
= 0x8f0ff001;
313 pra
->low_rssi_threshold_ratr_40M
= 0x8f0ff005;
314 pra
->low_rssi_threshold_ratr_20M
= 0x8f0ff001;
315 pra
->ping_rssi_ratr
= 0x0000000d;//cosa add for test
317 else if (priv
->rf_type
== RF_1T2R
)
319 pra
->upper_rssi_threshold_ratr
= 0x000f0000;
320 pra
->middle_rssi_threshold_ratr
= 0x000ff000;
321 pra
->low_rssi_threshold_ratr
= 0x000ff001;
322 pra
->low_rssi_threshold_ratr_40M
= 0x000ff005;
323 pra
->low_rssi_threshold_ratr_20M
= 0x000ff001;
324 pra
->ping_rssi_ratr
= 0x0000000d;//cosa add for test
330 static void dm_check_rate_adaptive(struct net_device
* dev
)
332 struct r8192_priv
*priv
= ieee80211_priv(dev
);
333 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
334 prate_adaptive pra
= (prate_adaptive
)&priv
->rate_adaptive
;
335 u32 currentRATR
, targetRATR
= 0;
336 u32 LowRSSIThreshForRA
= 0, HighRSSIThreshForRA
= 0;
337 bool bshort_gi_enabled
= false;
338 static u8 ping_rssi_state
=0;
343 RT_TRACE(COMP_RATE
, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
347 if(pra
->rate_adaptive_disabled
)//this variable is set by ioctl.
350 // TODO: Only 11n mode is implemented currently,
351 if( !(priv
->ieee80211
->mode
== WIRELESS_MODE_N_24G
||
352 priv
->ieee80211
->mode
== WIRELESS_MODE_N_5G
))
355 if( priv
->ieee80211
->state
== IEEE80211_LINKED
)
357 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
360 // Check whether Short GI is enabled
362 bshort_gi_enabled
= (pHTInfo
->bCurTxBW40MHz
&& pHTInfo
->bCurShortGI40MHz
) ||
363 (!pHTInfo
->bCurTxBW40MHz
&& pHTInfo
->bCurShortGI20MHz
);
366 pra
->upper_rssi_threshold_ratr
=
367 (pra
->upper_rssi_threshold_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
369 pra
->middle_rssi_threshold_ratr
=
370 (pra
->middle_rssi_threshold_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
372 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
374 pra
->low_rssi_threshold_ratr
=
375 (pra
->low_rssi_threshold_ratr_40M
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
379 pra
->low_rssi_threshold_ratr
=
380 (pra
->low_rssi_threshold_ratr_20M
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
383 pra
->ping_rssi_ratr
=
384 (pra
->ping_rssi_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
386 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
387 time to link with AP. We will not change upper/lower threshold. If
388 STA stay in high or low level, we must change two different threshold
389 to prevent jumping frequently. */
390 if (pra
->ratr_state
== DM_RATR_STA_HIGH
)
392 HighRSSIThreshForRA
= pra
->high2low_rssi_thresh_for_ra
;
393 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
394 (pra
->low_rssi_thresh_for_ra40M
):(pra
->low_rssi_thresh_for_ra20M
);
396 else if (pra
->ratr_state
== DM_RATR_STA_LOW
)
398 HighRSSIThreshForRA
= pra
->high_rssi_thresh_for_ra
;
399 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
400 (pra
->low2high_rssi_thresh_for_ra40M
):(pra
->low2high_rssi_thresh_for_ra20M
);
404 HighRSSIThreshForRA
= pra
->high_rssi_thresh_for_ra
;
405 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
406 (pra
->low_rssi_thresh_for_ra40M
):(pra
->low_rssi_thresh_for_ra20M
);
409 if(priv
->undecorated_smoothed_pwdb
>= (long)HighRSSIThreshForRA
)
411 pra
->ratr_state
= DM_RATR_STA_HIGH
;
412 targetRATR
= pra
->upper_rssi_threshold_ratr
;
413 }else if(priv
->undecorated_smoothed_pwdb
>= (long)LowRSSIThreshForRA
)
415 pra
->ratr_state
= DM_RATR_STA_MIDDLE
;
416 targetRATR
= pra
->middle_rssi_threshold_ratr
;
419 pra
->ratr_state
= DM_RATR_STA_LOW
;
420 targetRATR
= pra
->low_rssi_threshold_ratr
;
424 if(pra
->ping_rssi_enable
)
426 //pHalData->UndecoratedSmoothedPWDB = 19;
427 if(priv
->undecorated_smoothed_pwdb
< (long)(pra
->ping_rssi_thresh_for_ra
+5))
429 if( (priv
->undecorated_smoothed_pwdb
< (long)pra
->ping_rssi_thresh_for_ra
) ||
432 pra
->ratr_state
= DM_RATR_STA_LOW
;
433 targetRATR
= pra
->ping_rssi_ratr
;
445 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
446 if(priv
->ieee80211
->GetHalfNmodeSupportByAPsHandler(dev
))
447 targetRATR
&= 0xf00fffff;
451 // Check whether updating of RATR0 is required
453 currentRATR
= read_nic_dword(dev
, RATR0
);
454 if( targetRATR
!= currentRATR
)
457 ratr_value
= targetRATR
;
458 RT_TRACE(COMP_RATE
,"currentRATR = %x, targetRATR = %x\n", currentRATR
, targetRATR
);
459 if(priv
->rf_type
== RF_1T2R
)
461 ratr_value
&= ~(RATE_ALL_OFDM_2SS
);
463 write_nic_dword(dev
, RATR0
, ratr_value
);
464 write_nic_byte(dev
, UFWP
, 1);
466 pra
->last_ratr
= targetRATR
;
472 pra
->ratr_state
= DM_RATR_STA_MAX
;
478 static void dm_init_bandwidth_autoswitch(struct net_device
* dev
)
480 struct r8192_priv
*priv
= ieee80211_priv(dev
);
482 priv
->ieee80211
->bandwidth_auto_switch
.threshold_20Mhzto40Mhz
= BW_AUTO_SWITCH_LOW_HIGH
;
483 priv
->ieee80211
->bandwidth_auto_switch
.threshold_40Mhzto20Mhz
= BW_AUTO_SWITCH_HIGH_LOW
;
484 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= false;
485 priv
->ieee80211
->bandwidth_auto_switch
.bautoswitch_enable
= false;
490 static void dm_bandwidth_autoswitch(struct net_device
* dev
)
492 struct r8192_priv
*priv
= ieee80211_priv(dev
);
494 if(priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
||!priv
->ieee80211
->bandwidth_auto_switch
.bautoswitch_enable
){
497 if(priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
== false){//If send packets in 40 Mhz in 20/40
498 if(priv
->undecorated_smoothed_pwdb
<= priv
->ieee80211
->bandwidth_auto_switch
.threshold_40Mhzto20Mhz
)
499 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= true;
500 }else{//in force send packets in 20 Mhz in 20/40
501 if(priv
->undecorated_smoothed_pwdb
>= priv
->ieee80211
->bandwidth_auto_switch
.threshold_20Mhzto40Mhz
)
502 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= false;
508 //OFDM default at 0db, index=6.
510 static const u32 OFDMSwingTable
[OFDM_Table_Length
] = {
511 0x7f8001fe, // 0, +6db
512 0x71c001c7, // 1, +5db
513 0x65400195, // 2, +4db
514 0x5a400169, // 3, +3db
515 0x50800142, // 4, +2db
516 0x47c0011f, // 5, +1db
517 0x40000100, // 6, +0db ===> default, upper for higher temperature, lower for low temperature
518 0x390000e4, // 7, -1db
519 0x32c000cb, // 8, -2db
520 0x2d4000b5, // 9, -3db
521 0x288000a2, // 10, -4db
522 0x24000090, // 11, -5db
523 0x20000080, // 12, -6db
524 0x1c800072, // 13, -7db
525 0x19800066, // 14, -8db
526 0x26c0005b, // 15, -9db
527 0x24400051, // 16, -10db
528 0x12000048, // 17, -11db
529 0x10000040 // 18, -12db
531 static const u8 CCKSwingTable_Ch1_Ch13
[CCK_Table_length
][8] = {
532 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
533 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
534 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
535 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
536 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
537 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
538 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
539 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
540 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
541 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
542 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
543 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
546 static const u8 CCKSwingTable_Ch14
[CCK_Table_length
][8] = {
547 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
548 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
549 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
550 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
551 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
552 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
553 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
554 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
555 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
556 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
557 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
558 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
561 #define Pw_Track_Flag 0x11d
562 #define Tssi_Mea_Value 0x13c
563 #define Tssi_Report_Value1 0x134
564 #define Tssi_Report_Value2 0x13e
565 #define FW_Busy_Flag 0x13f
566 static void dm_TXPowerTrackingCallback_TSSI(struct net_device
* dev
)
568 struct r8192_priv
*priv
= ieee80211_priv(dev
);
569 bool bHighpowerstate
, viviflag
= FALSE
;
571 u8 powerlevelOFDM24G
;
572 int i
=0, j
= 0, k
= 0;
573 u8 RF_Type
, tmp_report
[5]={0, 0, 0, 0, 0};
576 u16 Avg_TSSI_Meas
, TSSI_13dBm
, Avg_TSSI_Meas_from_driver
=0;
578 RT_STATUS rtStatus
= RT_STATUS_SUCCESS
;
580 // bool rtStatus = true;
582 RT_TRACE(COMP_POWER_TRACKING
,"%s()\n",__FUNCTION__
);
583 // write_nic_byte(dev, 0x1ba, 0);
584 write_nic_byte(dev
, Pw_Track_Flag
, 0);
585 write_nic_byte(dev
, FW_Busy_Flag
, 0);
586 priv
->ieee80211
->bdynamic_txpower_enable
= false;
587 bHighpowerstate
= priv
->bDynamicTxHighPower
;
589 powerlevelOFDM24G
= (u8
)(priv
->Pwr_Track
>>24);
590 RF_Type
= priv
->rf_type
;
591 Value
= (RF_Type
<<8) | powerlevelOFDM24G
;
593 RT_TRACE(COMP_POWER_TRACKING
, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G
);
595 for(j
= 0; j
<=30; j
++)
598 tx_cmd
.Op
= TXCMD_SET_TX_PWR_TRACKING
;
600 tx_cmd
.Value
= Value
;
602 rtStatus
= SendTxCommandPacket(dev
, &tx_cmd
, 12);
603 if (rtStatus
== RT_STATUS_FAILURE
)
605 RT_TRACE(COMP_POWER_TRACKING
, "Set configuration with tx cmd queue fail!\n");
608 cmpk_message_handle_tx(dev
, (u8
*)&tx_cmd
, DESC_PACKET_TYPE_INIT
, sizeof(DCMD_TXCMD_T
));
612 for(i
= 0;i
<= 30; i
++)
614 Pwr_Flag
= read_nic_byte(dev
, Pw_Track_Flag
);
622 Avg_TSSI_Meas
= read_nic_word(dev
, Tssi_Mea_Value
);
624 if(Avg_TSSI_Meas
== 0)
626 write_nic_byte(dev
, Pw_Track_Flag
, 0);
627 write_nic_byte(dev
, FW_Busy_Flag
, 0);
631 for(k
= 0;k
< 5; k
++)
634 tmp_report
[k
] = read_nic_byte(dev
, Tssi_Report_Value1
+k
);
636 tmp_report
[k
] = read_nic_byte(dev
, Tssi_Report_Value2
);
638 RT_TRACE(COMP_POWER_TRACKING
, "TSSI_report_value = %d\n", tmp_report
[k
]);
641 //check if the report value is right
642 for(k
= 0;k
< 5; k
++)
644 if(tmp_report
[k
] <= 20)
652 write_nic_byte(dev
, Pw_Track_Flag
, 0);
654 RT_TRACE(COMP_POWER_TRACKING
, "we filted this data\n");
655 for(k
= 0;k
< 5; k
++)
660 for(k
= 0;k
< 5; k
++)
662 Avg_TSSI_Meas_from_driver
+= tmp_report
[k
];
665 Avg_TSSI_Meas_from_driver
= Avg_TSSI_Meas_from_driver
*100/5;
666 RT_TRACE(COMP_POWER_TRACKING
, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver
);
667 TSSI_13dBm
= priv
->TSSI_13dBm
;
668 RT_TRACE(COMP_POWER_TRACKING
, "TSSI_13dBm = %d\n", TSSI_13dBm
);
670 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
671 // For MacOS-compatible
672 if(Avg_TSSI_Meas_from_driver
> TSSI_13dBm
)
673 delta
= Avg_TSSI_Meas_from_driver
- TSSI_13dBm
;
675 delta
= TSSI_13dBm
- Avg_TSSI_Meas_from_driver
;
677 if(delta
<= E_FOR_TX_POWER_TRACK
)
679 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
680 write_nic_byte(dev
, Pw_Track_Flag
, 0);
681 write_nic_byte(dev
, FW_Busy_Flag
, 0);
682 RT_TRACE(COMP_POWER_TRACKING
, "tx power track is done\n");
683 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex = %d\n", priv
->rfa_txpowertrackingindex
);
684 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex_real = %d\n", priv
->rfa_txpowertrackingindex_real
);
686 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex = %d\n", priv
->rfc_txpowertrackingindex
);
687 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex_real = %d\n", priv
->rfc_txpowertrackingindex_real
);
689 RT_TRACE(COMP_POWER_TRACKING
, "priv->CCKPresentAttentuation_difference = %d\n", priv
->CCKPresentAttentuation_difference
);
690 RT_TRACE(COMP_POWER_TRACKING
, "priv->CCKPresentAttentuation = %d\n", priv
->CCKPresentAttentuation
);
695 if(Avg_TSSI_Meas_from_driver
< TSSI_13dBm
- E_FOR_TX_POWER_TRACK
)
697 if (RF_Type
== RF_2T4R
)
700 if((priv
->rfa_txpowertrackingindex
> 0) &&(priv
->rfc_txpowertrackingindex
> 0))
702 priv
->rfa_txpowertrackingindex
--;
703 if(priv
->rfa_txpowertrackingindex_real
> 4)
705 priv
->rfa_txpowertrackingindex_real
--;
706 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex_real
].txbbgain_value
);
709 priv
->rfc_txpowertrackingindex
--;
710 if(priv
->rfc_txpowertrackingindex_real
> 4)
712 priv
->rfc_txpowertrackingindex_real
--;
713 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
718 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[4].txbbgain_value
);
719 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[4].txbbgain_value
);
724 if(priv
->rfc_txpowertrackingindex
> 0)
726 priv
->rfc_txpowertrackingindex
--;
727 if(priv
->rfc_txpowertrackingindex_real
> 4)
729 priv
->rfc_txpowertrackingindex_real
--;
730 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
734 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[4].txbbgain_value
);
739 if (RF_Type
== RF_2T4R
)
741 if((priv
->rfa_txpowertrackingindex
< TxBBGainTableLength
- 1) &&(priv
->rfc_txpowertrackingindex
< TxBBGainTableLength
- 1))
743 priv
->rfa_txpowertrackingindex
++;
744 priv
->rfa_txpowertrackingindex_real
++;
745 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex_real
].txbbgain_value
);
746 priv
->rfc_txpowertrackingindex
++;
747 priv
->rfc_txpowertrackingindex_real
++;
748 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
752 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[TxBBGainTableLength
- 1].txbbgain_value
);
753 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[TxBBGainTableLength
- 1].txbbgain_value
);
758 if(priv
->rfc_txpowertrackingindex
< (TxBBGainTableLength
- 1))
760 priv
->rfc_txpowertrackingindex
++;
761 priv
->rfc_txpowertrackingindex_real
++;
762 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
765 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[TxBBGainTableLength
- 1].txbbgain_value
);
768 if (RF_Type
== RF_2T4R
)
769 priv
->CCKPresentAttentuation_difference
770 = priv
->rfa_txpowertrackingindex
- priv
->rfa_txpowertracking_default
;
772 priv
->CCKPresentAttentuation_difference
773 = priv
->rfc_txpowertrackingindex
- priv
->rfc_txpowertracking_default
;
775 if(priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
)
776 priv
->CCKPresentAttentuation
777 = priv
->CCKPresentAttentuation_20Mdefault
+ priv
->CCKPresentAttentuation_difference
;
779 priv
->CCKPresentAttentuation
780 = priv
->CCKPresentAttentuation_40Mdefault
+ priv
->CCKPresentAttentuation_difference
;
782 if(priv
->CCKPresentAttentuation
> (CCKTxBBGainTableLength
-1))
783 priv
->CCKPresentAttentuation
= CCKTxBBGainTableLength
-1;
784 if(priv
->CCKPresentAttentuation
< 0)
785 priv
->CCKPresentAttentuation
= 0;
789 if(priv
->ieee80211
->current_network
.channel
== 14 && !priv
->bcck_in_ch14
)
791 priv
->bcck_in_ch14
= TRUE
;
792 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
794 else if(priv
->ieee80211
->current_network
.channel
!= 14 && priv
->bcck_in_ch14
)
796 priv
->bcck_in_ch14
= FALSE
;
797 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
800 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
802 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex = %d\n", priv
->rfa_txpowertrackingindex
);
803 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex_real = %d\n", priv
->rfa_txpowertrackingindex_real
);
805 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex = %d\n", priv
->rfc_txpowertrackingindex
);
806 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex_real = %d\n", priv
->rfc_txpowertrackingindex_real
);
808 RT_TRACE(COMP_POWER_TRACKING
, "priv->CCKPresentAttentuation_difference = %d\n", priv
->CCKPresentAttentuation_difference
);
809 RT_TRACE(COMP_POWER_TRACKING
, "priv->CCKPresentAttentuation = %d\n", priv
->CCKPresentAttentuation
);
811 if (priv
->CCKPresentAttentuation_difference
<= -12||priv
->CCKPresentAttentuation_difference
>= 24)
813 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
814 write_nic_byte(dev
, Pw_Track_Flag
, 0);
815 write_nic_byte(dev
, FW_Busy_Flag
, 0);
816 RT_TRACE(COMP_POWER_TRACKING
, "tx power track--->limited\n");
822 write_nic_byte(dev
, Pw_Track_Flag
, 0);
823 Avg_TSSI_Meas_from_driver
= 0;
824 for(k
= 0;k
< 5; k
++)
828 write_nic_byte(dev
, FW_Busy_Flag
, 0);
830 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
831 write_nic_byte(dev
, Pw_Track_Flag
, 0);
834 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device
* dev
)
836 #define ThermalMeterVal 9
837 struct r8192_priv
*priv
= ieee80211_priv(dev
);
838 u32 tmpRegA
, TempCCk
;
839 u8 tmpOFDMindex
, tmpCCKindex
, tmpCCK20Mindex
, tmpCCK40Mindex
, tmpval
;
840 int i
=0, CCKSwingNeedUpdate
=0;
842 if(!priv
->btxpower_trackingInit
)
844 //Query OFDM default setting
845 tmpRegA
= rtl8192_QueryBBReg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
);
846 for(i
=0; i
<OFDM_Table_Length
; i
++) //find the index
848 if(tmpRegA
== OFDMSwingTable
[i
])
850 priv
->OFDM_index
= (u8
)i
;
851 RT_TRACE(COMP_POWER_TRACKING
, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
852 rOFDM0_XATxIQImbalance
, tmpRegA
, priv
->OFDM_index
);
856 //Query CCK default setting From 0xa22
857 TempCCk
= rtl8192_QueryBBReg(dev
, rCCK0_TxFilter1
, bMaskByte2
);
858 for(i
=0 ; i
<CCK_Table_length
; i
++)
860 if(TempCCk
== (u32
)CCKSwingTable_Ch1_Ch13
[i
][0])
862 priv
->CCK_index
=(u8
) i
;
863 RT_TRACE(COMP_POWER_TRACKING
, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
864 rCCK0_TxFilter1
, TempCCk
, priv
->CCK_index
);
868 priv
->btxpower_trackingInit
= TRUE
;
869 //pHalData->TXPowercount = 0;
873 // read and filter out unreasonable value
874 tmpRegA
= rtl8192_phy_QueryRFReg(dev
, RF90_PATH_A
, 0x12, 0x078); // 0x12: RF Reg[10:7]
875 RT_TRACE(COMP_POWER_TRACKING
, "Readback ThermalMeterA = %d \n", tmpRegA
);
876 if(tmpRegA
< 3 || tmpRegA
> 13)
878 if(tmpRegA
>= 12) // if over 12, TP will be bad when high temperature
880 RT_TRACE(COMP_POWER_TRACKING
, "Valid ThermalMeterA = %d \n", tmpRegA
);
881 priv
->ThermalMeter
[0] = ThermalMeterVal
; //We use fixed value by Bryant's suggestion
882 priv
->ThermalMeter
[1] = ThermalMeterVal
; //We use fixed value by Bryant's suggestion
884 //Get current RF-A temperature index
885 if(priv
->ThermalMeter
[0] >= (u8
)tmpRegA
) //lower temperature
887 tmpOFDMindex
= tmpCCK20Mindex
= 6+(priv
->ThermalMeter
[0]-(u8
)tmpRegA
);
888 tmpCCK40Mindex
= tmpCCK20Mindex
- 6;
889 if(tmpOFDMindex
>= OFDM_Table_Length
)
890 tmpOFDMindex
= OFDM_Table_Length
-1;
891 if(tmpCCK20Mindex
>= CCK_Table_length
)
892 tmpCCK20Mindex
= CCK_Table_length
-1;
893 if(tmpCCK40Mindex
>= CCK_Table_length
)
894 tmpCCK40Mindex
= CCK_Table_length
-1;
898 tmpval
= ((u8
)tmpRegA
- priv
->ThermalMeter
[0]);
899 if(tmpval
>= 6) // higher temperature
900 tmpOFDMindex
= tmpCCK20Mindex
= 0; // max to +6dB
902 tmpOFDMindex
= tmpCCK20Mindex
= 6 - tmpval
;
906 if(priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
) //40M
907 tmpCCKindex
= tmpCCK40Mindex
;
909 tmpCCKindex
= tmpCCK20Mindex
;
911 //record for bandwidth swith
912 priv
->Record_CCK_20Mindex
= tmpCCK20Mindex
;
913 priv
->Record_CCK_40Mindex
= tmpCCK40Mindex
;
914 RT_TRACE(COMP_POWER_TRACKING
, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
915 priv
->Record_CCK_20Mindex
, priv
->Record_CCK_40Mindex
);
917 if(priv
->ieee80211
->current_network
.channel
== 14 && !priv
->bcck_in_ch14
)
919 priv
->bcck_in_ch14
= TRUE
;
920 CCKSwingNeedUpdate
= 1;
922 else if(priv
->ieee80211
->current_network
.channel
!= 14 && priv
->bcck_in_ch14
)
924 priv
->bcck_in_ch14
= FALSE
;
925 CCKSwingNeedUpdate
= 1;
928 if(priv
->CCK_index
!= tmpCCKindex
)
930 priv
->CCK_index
= tmpCCKindex
;
931 CCKSwingNeedUpdate
= 1;
934 if(CCKSwingNeedUpdate
)
936 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
938 if(priv
->OFDM_index
!= tmpOFDMindex
)
940 priv
->OFDM_index
= tmpOFDMindex
;
941 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, OFDMSwingTable
[priv
->OFDM_index
]);
942 RT_TRACE(COMP_POWER_TRACKING
, "Update OFDMSwing[%d] = 0x%x\n",
943 priv
->OFDM_index
, OFDMSwingTable
[priv
->OFDM_index
]);
945 priv
->txpower_count
= 0;
948 void dm_txpower_trackingcallback(struct work_struct
*work
)
950 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
951 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,txpower_tracking_wq
);
952 struct net_device
*dev
= priv
->ieee80211
->dev
;
955 dm_TXPowerTrackingCallback_TSSI(dev
);
957 //if(priv->bDcut == TRUE)
958 if(priv
->IC_Cut
>= IC_VersionCut_D
)
959 dm_TXPowerTrackingCallback_TSSI(dev
);
961 dm_TXPowerTrackingCallback_ThermalMeter(dev
);
966 static const txbbgain_struct rtl8192_txbbgain_table
[] = {
1000 { -21, 0x1300004c },
1001 { -22, 0x12000048 },
1002 { -23, 0x11000044 },
1003 { -24, 0x10000040 },
1007 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1008 * This Table is for CH1~CH13
1010 static const ccktxbbgain_struct rtl8192_cck_txbbgain_table
[] = {
1011 {{ 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 }},
1012 {{ 0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04 }},
1013 {{ 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03 }},
1014 {{ 0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03 }},
1015 {{ 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 }},
1016 {{ 0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03 }},
1017 {{ 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 }},
1018 {{ 0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03 }},
1019 {{ 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02 }},
1020 {{ 0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02 }},
1021 {{ 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02 }},
1022 {{ 0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02 }},
1023 {{ 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02 }},
1024 {{ 0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02 }},
1025 {{ 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02 }},
1026 {{ 0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02 }},
1027 {{ 0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01 }},
1028 {{ 0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02 }},
1029 {{ 0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01 }},
1030 {{ 0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1031 {{ 0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1032 {{ 0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1033 {{ 0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1037 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1038 * This Table is for CH14
1040 static const ccktxbbgain_struct rtl8192_cck_txbbgain_ch14_table
[] = {
1041 {{ 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 }},
1042 {{ 0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00 }},
1043 {{ 0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00 }},
1044 {{ 0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00 }},
1045 {{ 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 }},
1046 {{ 0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00 }},
1047 {{ 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00 }},
1048 {{ 0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00 }},
1049 {{ 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00 }},
1050 {{ 0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00 }},
1051 {{ 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00 }},
1052 {{ 0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1053 {{ 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1054 {{ 0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00 }},
1055 {{ 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00 }},
1056 {{ 0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1057 {{ 0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1058 {{ 0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1059 {{ 0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1060 {{ 0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1061 {{ 0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1062 {{ 0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1063 {{ 0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1066 static void dm_InitializeTXPowerTracking_TSSI(struct net_device
*dev
)
1068 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1070 priv
->txbbgain_table
= rtl8192_txbbgain_table
;
1071 priv
->cck_txbbgain_table
= rtl8192_cck_txbbgain_table
;
1072 priv
->cck_txbbgain_ch14_table
= rtl8192_cck_txbbgain_ch14_table
;
1074 priv
->btxpower_tracking
= TRUE
;
1075 priv
->txpower_count
= 0;
1076 priv
->btxpower_trackingInit
= FALSE
;
1080 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device
*dev
)
1082 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1084 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1085 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1086 // 3-wire by driver cause RF goes into wrong state.
1087 if(priv
->ieee80211
->FwRWRF
)
1088 priv
->btxpower_tracking
= TRUE
;
1090 priv
->btxpower_tracking
= FALSE
;
1091 priv
->txpower_count
= 0;
1092 priv
->btxpower_trackingInit
= FALSE
;
1096 void dm_initialize_txpower_tracking(struct net_device
*dev
)
1099 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1102 dm_InitializeTXPowerTracking_TSSI(dev
);
1104 if(priv
->IC_Cut
>= IC_VersionCut_D
)
1105 dm_InitializeTXPowerTracking_TSSI(dev
);
1107 dm_InitializeTXPowerTracking_ThermalMeter(dev
);
1112 static void dm_CheckTXPowerTracking_TSSI(struct net_device
*dev
)
1114 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1115 static u32 tx_power_track_counter
= 0;
1116 RT_TRACE(COMP_POWER_TRACKING
,"%s()\n",__FUNCTION__
);
1117 if(read_nic_byte(dev
, 0x11e) ==1)
1119 if(!priv
->btxpower_tracking
)
1121 tx_power_track_counter
++;
1123 if (tx_power_track_counter
> 90) {
1124 queue_delayed_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
,0);
1125 tx_power_track_counter
=0;
1130 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device
*dev
)
1132 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1133 static u8 TM_Trigger
=0;
1135 if(!priv
->btxpower_tracking
)
1139 if(priv
->txpower_count
<= 2)
1141 priv
->txpower_count
++;
1148 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1149 //actually write reg0x02 bit1=0, then bit1=1.
1150 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
1151 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
1152 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
1153 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
1158 queue_delayed_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
,0);
1164 static void dm_check_txpower_tracking(struct net_device
*dev
)
1167 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1168 //static u32 tx_power_track_counter = 0;
1171 dm_CheckTXPowerTracking_TSSI(dev
);
1173 //if(priv->bDcut == TRUE)
1174 if(priv
->IC_Cut
>= IC_VersionCut_D
)
1175 dm_CheckTXPowerTracking_TSSI(dev
);
1177 dm_CheckTXPowerTracking_ThermalMeter(dev
);
1183 static void dm_CCKTxPowerAdjust_TSSI(struct net_device
*dev
, bool bInCH14
)
1186 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1191 TempVal
= (u32
)(priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[0] +
1192 (priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[1]<<8)) ;
1194 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
,bMaskHWord
, TempVal
);
1195 //Write 0xa24 ~ 0xa27
1197 TempVal
= (u32
)(priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[2] +
1198 (priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[3]<<8) +
1199 (priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[4]<<16 )+
1200 (priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[5]<<24));
1201 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
,bMaskDWord
, TempVal
);
1204 TempVal
= (u32
)(priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[6] +
1205 (priv
->cck_txbbgain_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[7]<<8)) ;
1207 rtl8192_setBBreg(dev
, rCCK0_DebugPort
,bMaskLWord
, TempVal
);
1211 TempVal
= (u32
)(priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[0] +
1212 (priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[1]<<8)) ;
1214 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
,bMaskHWord
, TempVal
);
1215 //Write 0xa24 ~ 0xa27
1217 TempVal
= (u32
)(priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[2] +
1218 (priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[3]<<8) +
1219 (priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[4]<<16 )+
1220 (priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[5]<<24));
1221 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
,bMaskDWord
, TempVal
);
1224 TempVal
= (u32
)(priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[6] +
1225 (priv
->cck_txbbgain_ch14_table
[(u8
)(priv
->CCKPresentAttentuation
)].ccktxbb_valuearray
[7]<<8)) ;
1227 rtl8192_setBBreg(dev
, rCCK0_DebugPort
,bMaskLWord
, TempVal
);
1233 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device
*dev
, bool bInCH14
)
1236 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1242 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][0] +
1243 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][1]<<8) ;
1244 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
, bMaskHWord
, TempVal
);
1245 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1246 rCCK0_TxFilter1
, TempVal
);
1247 //Write 0xa24 ~ 0xa27
1249 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][2] +
1250 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][3]<<8) +
1251 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][4]<<16 )+
1252 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][5]<<24);
1253 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
, bMaskDWord
, TempVal
);
1254 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1255 rCCK0_TxFilter2
, TempVal
);
1258 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][6] +
1259 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][7]<<8) ;
1261 rtl8192_setBBreg(dev
, rCCK0_DebugPort
, bMaskLWord
, TempVal
);
1262 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1263 rCCK0_DebugPort
, TempVal
);
1267 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1269 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][0] +
1270 (CCKSwingTable_Ch14
[priv
->CCK_index
][1]<<8) ;
1272 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
, bMaskHWord
, TempVal
);
1273 RT_TRACE(COMP_POWER_TRACKING
, "CCK chnl 14, reg 0x%x = 0x%x\n",
1274 rCCK0_TxFilter1
, TempVal
);
1275 //Write 0xa24 ~ 0xa27
1277 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][2] +
1278 (CCKSwingTable_Ch14
[priv
->CCK_index
][3]<<8) +
1279 (CCKSwingTable_Ch14
[priv
->CCK_index
][4]<<16 )+
1280 (CCKSwingTable_Ch14
[priv
->CCK_index
][5]<<24);
1281 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
, bMaskDWord
, TempVal
);
1282 RT_TRACE(COMP_POWER_TRACKING
, "CCK chnl 14, reg 0x%x = 0x%x\n",
1283 rCCK0_TxFilter2
, TempVal
);
1286 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][6] +
1287 (CCKSwingTable_Ch14
[priv
->CCK_index
][7]<<8) ;
1289 rtl8192_setBBreg(dev
, rCCK0_DebugPort
, bMaskLWord
, TempVal
);
1290 RT_TRACE(COMP_POWER_TRACKING
,"CCK chnl 14, reg 0x%x = 0x%x\n",
1291 rCCK0_DebugPort
, TempVal
);
1297 void dm_cck_txpower_adjust(struct net_device
*dev
, bool binch14
)
1300 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1303 dm_CCKTxPowerAdjust_TSSI(dev
, binch14
);
1305 if(priv
->IC_Cut
>= IC_VersionCut_D
)
1306 dm_CCKTxPowerAdjust_TSSI(dev
, binch14
);
1308 dm_CCKTxPowerAdjust_ThermalMeter(dev
, binch14
);
1314 static void dm_txpower_reset_recovery(
1315 struct net_device
*dev
1318 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1320 RT_TRACE(COMP_POWER_TRACKING
, "Start Reset Recovery ==>\n");
1321 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbbgain_value
);
1322 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in 0xc80 is %08x\n",priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbbgain_value
);
1323 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv
->rfa_txpowertrackingindex
);
1324 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbb_iq_amplifygain
);
1325 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: CCK Attenuation is %d dB\n",priv
->CCKPresentAttentuation
);
1326 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
1328 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbbgain_value
);
1329 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in 0xc90 is %08x\n",priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbbgain_value
);
1330 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv
->rfc_txpowertrackingindex
);
1331 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbb_iq_amplifygain
);
1335 void dm_restore_dynamic_mechanism_state(struct net_device
*dev
)
1337 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1338 u32 reg_ratr
= priv
->rate_adaptive
.last_ratr
;
1342 RT_TRACE(COMP_RATE
, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1347 // Restore previous state for rate adaptive
1349 if(priv
->rate_adaptive
.rate_adaptive_disabled
)
1351 // TODO: Only 11n mode is implemented currently,
1352 if( !(priv
->ieee80211
->mode
==WIRELESS_MODE_N_24G
||
1353 priv
->ieee80211
->mode
==WIRELESS_MODE_N_5G
))
1356 /* 2007/11/15 MH Copy from 8190PCI. */
1358 ratr_value
= reg_ratr
;
1359 if(priv
->rf_type
== RF_1T2R
) // 1T2R, Spatial Stream 2 should be disabled
1361 ratr_value
&=~ (RATE_ALL_OFDM_2SS
);
1363 write_nic_dword(dev
, RATR0
, ratr_value
);
1364 write_nic_byte(dev
, UFWP
, 1);
1366 //Resore TX Power Tracking Index
1367 if(priv
->btxpower_trackingInit
&& priv
->btxpower_tracking
){
1368 dm_txpower_reset_recovery(dev
);
1372 //Restore BB Initial Gain
1374 dm_bb_initialgain_restore(dev
);
1378 static void dm_bb_initialgain_restore(struct net_device
*dev
)
1380 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1381 u32 bit_mask
= 0x7f; //Bit0~ Bit6
1383 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
1386 //Disable Initial Gain
1387 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1388 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
1389 rtl8192_setBBreg(dev
, rOFDM0_XAAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xaagccore1
);
1390 rtl8192_setBBreg(dev
, rOFDM0_XBAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xbagccore1
);
1391 rtl8192_setBBreg(dev
, rOFDM0_XCAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xcagccore1
);
1392 rtl8192_setBBreg(dev
, rOFDM0_XDAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xdagccore1
);
1393 bit_mask
= bMaskByte2
;
1394 rtl8192_setBBreg(dev
, rCCK0_CCA
, bit_mask
, (u32
)priv
->initgain_backup
.cca
);
1396 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc50 is %x\n",priv
->initgain_backup
.xaagccore1
);
1397 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc58 is %x\n",priv
->initgain_backup
.xbagccore1
);
1398 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc60 is %x\n",priv
->initgain_backup
.xcagccore1
);
1399 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc68 is %x\n",priv
->initgain_backup
.xdagccore1
);
1400 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xa0a is %x\n",priv
->initgain_backup
.cca
);
1401 //Enable Initial Gain
1402 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1403 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
1408 void dm_backup_dynamic_mechanism_state(struct net_device
*dev
)
1410 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1412 // Fsync to avoid reset
1413 priv
->bswitch_fsync
= false;
1414 //Backup BB InitialGain
1415 dm_bb_initialgain_backup(dev
);
1420 static void dm_bb_initialgain_backup(struct net_device
*dev
)
1422 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1423 u32 bit_mask
= bMaskByte0
; //Bit0~ Bit6
1425 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
1428 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1429 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
1430 priv
->initgain_backup
.xaagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XAAGCCore1
, bit_mask
);
1431 priv
->initgain_backup
.xbagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XBAGCCore1
, bit_mask
);
1432 priv
->initgain_backup
.xcagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XCAGCCore1
, bit_mask
);
1433 priv
->initgain_backup
.xdagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XDAGCCore1
, bit_mask
);
1434 bit_mask
= bMaskByte2
;
1435 priv
->initgain_backup
.cca
= (u8
)rtl8192_QueryBBReg(dev
, rCCK0_CCA
, bit_mask
);
1437 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc50 is %x\n",priv
->initgain_backup
.xaagccore1
);
1438 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc58 is %x\n",priv
->initgain_backup
.xbagccore1
);
1439 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc60 is %x\n",priv
->initgain_backup
.xcagccore1
);
1440 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc68 is %x\n",priv
->initgain_backup
.xdagccore1
);
1441 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xa0a is %x\n",priv
->initgain_backup
.cca
);
1447 void dm_change_dynamic_initgain_thresh(struct net_device
*dev
, u32 dm_type
, u32 dm_value
)
1449 if (dm_type
== DIG_TYPE_THRESH_HIGH
)
1451 dm_digtable
.rssi_high_thresh
= dm_value
;
1453 else if (dm_type
== DIG_TYPE_THRESH_LOW
)
1455 dm_digtable
.rssi_low_thresh
= dm_value
;
1457 else if (dm_type
== DIG_TYPE_THRESH_HIGHPWR_HIGH
)
1459 dm_digtable
.rssi_high_power_highthresh
= dm_value
;
1461 else if (dm_type
== DIG_TYPE_THRESH_HIGHPWR_HIGH
)
1463 dm_digtable
.rssi_high_power_highthresh
= dm_value
;
1465 else if (dm_type
== DIG_TYPE_ENABLE
)
1467 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
1468 dm_digtable
.dig_enable_flag
= true;
1470 else if (dm_type
== DIG_TYPE_DISABLE
)
1472 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
1473 dm_digtable
.dig_enable_flag
= false;
1475 else if (dm_type
== DIG_TYPE_DBG_MODE
)
1477 if(dm_value
>= DM_DBG_MAX
)
1478 dm_value
= DM_DBG_OFF
;
1479 dm_digtable
.dbg_mode
= (u8
)dm_value
;
1481 else if (dm_type
== DIG_TYPE_RSSI
)
1485 dm_digtable
.rssi_val
= (long)dm_value
;
1487 else if (dm_type
== DIG_TYPE_ALGORITHM
)
1489 if (dm_value
>= DIG_ALGO_MAX
)
1490 dm_value
= DIG_ALGO_BY_FALSE_ALARM
;
1491 if(dm_digtable
.dig_algorithm
!= (u8
)dm_value
)
1492 dm_digtable
.dig_algorithm_switch
= 1;
1493 dm_digtable
.dig_algorithm
= (u8
)dm_value
;
1495 else if (dm_type
== DIG_TYPE_BACKOFF
)
1499 dm_digtable
.backoff_val
= (u8
)dm_value
;
1501 else if(dm_type
== DIG_TYPE_RX_GAIN_MIN
)
1505 dm_digtable
.rx_gain_range_min
= (u8
)dm_value
;
1507 else if(dm_type
== DIG_TYPE_RX_GAIN_MAX
)
1511 dm_digtable
.rx_gain_range_max
= (u8
)dm_value
;
1516 /* Set DIG scheme init value. */
1517 static void dm_dig_init(struct net_device
*dev
)
1519 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1520 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1521 dm_digtable
.dig_enable_flag
= true;
1522 dm_digtable
.dig_algorithm
= DIG_ALGO_BY_RSSI
;
1523 dm_digtable
.dbg_mode
= DM_DBG_OFF
; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
1524 dm_digtable
.dig_algorithm_switch
= 0;
1526 /* 2007/10/04 MH Define init gain threshold. */
1527 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
1528 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_MAX
;
1529 dm_digtable
.initialgain_lowerbound_state
= false;
1531 dm_digtable
.rssi_low_thresh
= DM_DIG_THRESH_LOW
;
1532 dm_digtable
.rssi_high_thresh
= DM_DIG_THRESH_HIGH
;
1534 dm_digtable
.rssi_high_power_lowthresh
= DM_DIG_HIGH_PWR_THRESH_LOW
;
1535 dm_digtable
.rssi_high_power_highthresh
= DM_DIG_HIGH_PWR_THRESH_HIGH
;
1537 dm_digtable
.rssi_val
= 50; //for new dig debug rssi value
1538 dm_digtable
.backoff_val
= DM_DIG_BACKOFF
;
1539 dm_digtable
.rx_gain_range_max
= DM_DIG_MAX
;
1540 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
1541 dm_digtable
.rx_gain_range_min
= DM_DIG_MIN_Netcore
;
1543 dm_digtable
.rx_gain_range_min
= DM_DIG_MIN
;
1549 * Driver must monitor RSSI and notify firmware to change initial
1550 * gain according to different threshold. BB team provide the
1551 * suggested solution.
1553 static void dm_ctrl_initgain_byrssi(struct net_device
*dev
)
1556 if (dm_digtable
.dig_enable_flag
== false)
1559 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_FALSE_ALARM
)
1560 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev
);
1561 else if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
1562 dm_ctrl_initgain_byrssi_by_driverrssi(dev
);
1566 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1567 struct net_device
*dev
)
1569 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1573 if (dm_digtable
.dig_enable_flag
== false)
1576 if(dm_digtable
.dig_algorithm_switch
) // if swithed algorithm, we have to disable FW Dig.
1578 if(fw_dig
<= 3) // execute several times to make sure the FW Dig is disabled
1581 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
1583 dm_digtable
.dig_state
= DM_STA_DIG_OFF
; //fw dig off.
1586 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
1587 dm_digtable
.cur_connect_state
= DIG_CONNECT
;
1589 dm_digtable
.cur_connect_state
= DIG_DISCONNECT
;
1591 if(dm_digtable
.dbg_mode
== DM_DBG_OFF
)
1592 dm_digtable
.rssi_val
= priv
->undecorated_smoothed_pwdb
;
1594 dm_initial_gain(dev
);
1597 if(dm_digtable
.dig_algorithm_switch
)
1598 dm_digtable
.dig_algorithm_switch
= 0;
1599 dm_digtable
.pre_connect_state
= dm_digtable
.cur_connect_state
;
1603 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1604 struct net_device
*dev
)
1606 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1607 static u32 reset_cnt
= 0;
1610 if (dm_digtable
.dig_enable_flag
== false)
1613 if(dm_digtable
.dig_algorithm_switch
)
1615 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
1618 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
1619 dm_digtable
.dig_algorithm_switch
= 0;
1622 if (priv
->ieee80211
->state
!= IEEE80211_LINKED
)
1625 // For smooth, we can not change DIG state.
1626 if ((priv
->undecorated_smoothed_pwdb
> dm_digtable
.rssi_low_thresh
) &&
1627 (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_thresh
))
1632 /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1633 and then execute below step. */
1634 if ((priv
->undecorated_smoothed_pwdb
<= dm_digtable
.rssi_low_thresh
))
1636 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1637 will be reset to init value. We must prevent the condition. */
1638 if (dm_digtable
.dig_state
== DM_STA_DIG_OFF
&&
1639 (priv
->reset_count
== reset_cnt
))
1645 reset_cnt
= priv
->reset_count
;
1648 // If DIG is off, DIG high power state must reset.
1649 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_MAX
;
1650 dm_digtable
.dig_state
= DM_STA_DIG_OFF
;
1653 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
1655 // 1.2 Set initial gain.
1656 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x17);
1657 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x17);
1658 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x17);
1659 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x17);
1661 // 1.3 Lower PD_TH for OFDM.
1662 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1664 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1665 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1667 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x40);
1669 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x00);
1671 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1672 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1674 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1678 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1681 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
1683 // 1.4 Lower CS ratio for CCK.
1684 write_nic_byte(dev
, 0xa0a, 0x08);
1686 // 1.5 Higher EDCCA.
1687 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
1692 /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1693 and then execute below step. */
1694 if ((priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_thresh
) )
1698 if (dm_digtable
.dig_state
== DM_STA_DIG_ON
&&
1699 (priv
->reset_count
== reset_cnt
))
1701 dm_ctrl_initgain_byrssi_highpwr(dev
);
1706 if (priv
->reset_count
!= reset_cnt
)
1709 reset_cnt
= priv
->reset_count
;
1712 dm_digtable
.dig_state
= DM_STA_DIG_ON
;
1714 // 2.1 Set initial gain.
1715 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1716 if (reset_flag
== 1)
1718 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x2c);
1719 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x2c);
1720 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x2c);
1721 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x2c);
1725 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x20);
1726 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x20);
1727 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x20);
1728 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x20);
1731 // 2.2 Higher PD_TH for OFDM.
1732 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1734 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1735 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1737 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
1739 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
1742 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1743 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1745 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1748 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1751 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
1753 // 2.3 Higher CS ratio for CCK.
1754 write_nic_byte(dev
, 0xa0a, 0xcd);
1757 /* 2008/01/11 MH 90/92 series are the same. */
1758 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
1761 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
1765 dm_ctrl_initgain_byrssi_highpwr(dev
);
1769 static void dm_ctrl_initgain_byrssi_highpwr(
1770 struct net_device
* dev
)
1772 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1773 static u32 reset_cnt_highpwr
= 0;
1775 // For smooth, we can not change high power DIG state in the range.
1776 if ((priv
->undecorated_smoothed_pwdb
> dm_digtable
.rssi_high_power_lowthresh
) &&
1777 (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_power_highthresh
))
1782 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1783 it is larger than a threshold and then execute below step. */
1784 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1785 if (priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_power_highthresh
)
1787 if (dm_digtable
.dig_highpwr_state
== DM_STA_DIG_ON
&&
1788 (priv
->reset_count
== reset_cnt_highpwr
))
1791 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_ON
;
1793 // 3.1 Higher PD_TH for OFDM for high power state.
1794 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1797 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x41);
1799 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x10);
1802 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1803 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1808 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x43);
1812 if (dm_digtable
.dig_highpwr_state
== DM_STA_DIG_OFF
&&
1813 (priv
->reset_count
== reset_cnt_highpwr
))
1816 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_OFF
;
1818 if (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_power_lowthresh
&&
1819 priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_thresh
)
1821 // 3.2 Recover PD_TH for OFDM for normal power region.
1822 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1825 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
1827 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
1829 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1830 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1835 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
1839 reset_cnt_highpwr
= priv
->reset_count
;
1844 static void dm_initial_gain(
1845 struct net_device
* dev
)
1847 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1849 static u8 initialized
=0, force_write
=0;
1850 static u32 reset_cnt
=0;
1852 if(dm_digtable
.dig_algorithm_switch
)
1858 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
1860 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
1862 if((dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
) > dm_digtable
.rx_gain_range_max
)
1863 dm_digtable
.cur_ig_value
= dm_digtable
.rx_gain_range_max
;
1864 else if((dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
) < dm_digtable
.rx_gain_range_min
)
1865 dm_digtable
.cur_ig_value
= dm_digtable
.rx_gain_range_min
;
1867 dm_digtable
.cur_ig_value
= dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
;
1869 else //current state is disconnected
1871 if(dm_digtable
.cur_ig_value
== 0)
1872 dm_digtable
.cur_ig_value
= priv
->DefaultInitialGain
[0];
1874 dm_digtable
.cur_ig_value
= dm_digtable
.pre_ig_value
;
1877 else // disconnected -> connected or connected -> disconnected
1879 dm_digtable
.cur_ig_value
= priv
->DefaultInitialGain
[0];
1880 dm_digtable
.pre_ig_value
= 0;
1883 // if silent reset happened, we should rewrite the values back
1884 if(priv
->reset_count
!= reset_cnt
)
1887 reset_cnt
= priv
->reset_count
;
1890 if(dm_digtable
.pre_ig_value
!= read_nic_byte(dev
, rOFDM0_XAAGCCore1
))
1894 if((dm_digtable
.pre_ig_value
!= dm_digtable
.cur_ig_value
)
1895 || !initialized
|| force_write
)
1897 initial_gain
= (u8
)dm_digtable
.cur_ig_value
;
1898 // Set initial gain.
1899 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, initial_gain
);
1900 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, initial_gain
);
1901 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, initial_gain
);
1902 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, initial_gain
);
1903 dm_digtable
.pre_ig_value
= dm_digtable
.cur_ig_value
;
1910 static void dm_pd_th(
1911 struct net_device
* dev
)
1913 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1914 static u8 initialized
=0, force_write
=0;
1915 static u32 reset_cnt
= 0;
1917 if(dm_digtable
.dig_algorithm_switch
)
1923 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
1925 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
1927 if (dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_power_highthresh
)
1928 dm_digtable
.curpd_thstate
= DIG_PD_AT_HIGH_POWER
;
1929 else if ((dm_digtable
.rssi_val
<= dm_digtable
.rssi_low_thresh
))
1930 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
1931 else if ((dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_thresh
) &&
1932 (dm_digtable
.rssi_val
< dm_digtable
.rssi_high_power_lowthresh
))
1933 dm_digtable
.curpd_thstate
= DIG_PD_AT_NORMAL_POWER
;
1935 dm_digtable
.curpd_thstate
= dm_digtable
.prepd_thstate
;
1939 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
1942 else // disconnected -> connected or connected -> disconnected
1944 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
1947 // if silent reset happened, we should rewrite the values back
1948 if(priv
->reset_count
!= reset_cnt
)
1951 reset_cnt
= priv
->reset_count
;
1955 if((dm_digtable
.prepd_thstate
!= dm_digtable
.curpd_thstate
) ||
1956 (initialized
<=3) || force_write
)
1958 if(dm_digtable
.curpd_thstate
== DIG_PD_AT_LOW_POWER
)
1960 // Lower PD_TH for OFDM.
1961 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1963 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1964 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1966 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x40);
1968 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x00);
1970 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1971 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1975 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
1977 else if(dm_digtable
.curpd_thstate
== DIG_PD_AT_NORMAL_POWER
)
1979 // Higher PD_TH for OFDM.
1980 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
1982 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1983 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1985 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
1987 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
1989 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1990 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1994 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
1996 else if(dm_digtable
.curpd_thstate
== DIG_PD_AT_HIGH_POWER
)
1998 // Higher PD_TH for OFDM for high power state.
1999 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2002 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x41);
2004 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x10);
2006 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2007 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2011 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x43);
2013 dm_digtable
.prepd_thstate
= dm_digtable
.curpd_thstate
;
2014 if(initialized
<= 3)
2021 static void dm_cs_ratio(
2022 struct net_device
* dev
)
2024 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2025 static u8 initialized
=0,force_write
=0;
2026 static u32 reset_cnt
= 0;
2028 if(dm_digtable
.dig_algorithm_switch
)
2034 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
2036 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
2038 if ((dm_digtable
.rssi_val
<= dm_digtable
.rssi_low_thresh
))
2039 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2040 else if ((dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_thresh
) )
2041 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_HIGHER
;
2043 dm_digtable
.curcs_ratio_state
= dm_digtable
.precs_ratio_state
;
2047 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2050 else // disconnected -> connected or connected -> disconnected
2052 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2055 // if silent reset happened, we should rewrite the values back
2056 if(priv
->reset_count
!= reset_cnt
)
2059 reset_cnt
= priv
->reset_count
;
2063 if((dm_digtable
.precs_ratio_state
!= dm_digtable
.curcs_ratio_state
) ||
2064 !initialized
|| force_write
)
2066 if(dm_digtable
.curcs_ratio_state
== DIG_CS_RATIO_LOWER
)
2068 // Lower CS ratio for CCK.
2069 write_nic_byte(dev
, 0xa0a, 0x08);
2071 else if(dm_digtable
.curcs_ratio_state
== DIG_CS_RATIO_HIGHER
)
2073 // Higher CS ratio for CCK.
2074 write_nic_byte(dev
, 0xa0a, 0xcd);
2076 dm_digtable
.precs_ratio_state
= dm_digtable
.curcs_ratio_state
;
2082 void dm_init_edca_turbo(struct net_device
*dev
)
2084 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2086 priv
->bcurrent_turbo_EDCA
= false;
2087 priv
->ieee80211
->bis_any_nonbepkts
= false;
2088 priv
->bis_cur_rdlstate
= false;
2092 static void dm_check_edca_turbo(
2093 struct net_device
* dev
)
2095 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2096 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
2097 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2099 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2100 static unsigned long lastTxOkCnt
= 0;
2101 static unsigned long lastRxOkCnt
= 0;
2102 unsigned long curTxOkCnt
= 0;
2103 unsigned long curRxOkCnt
= 0;
2106 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2107 // should follow the settings from QAP. By Bruce, 2007-12-07.
2110 if(priv
->ieee80211
->state
!= IEEE80211_LINKED
)
2111 goto dm_CheckEdcaTurbo_EXIT
;
2113 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2114 if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_DISABLE_EDCA_TURBO
)
2115 goto dm_CheckEdcaTurbo_EXIT
;
2117 // Check the status for current condition.
2118 if(!priv
->ieee80211
->bis_any_nonbepkts
)
2120 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
2121 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
2122 // For RT-AP, we needs to turn it on when Rx>Tx
2123 if(curRxOkCnt
> 4*curTxOkCnt
)
2125 if(!priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
2127 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_DL
[pHTInfo
->IOTPeer
]);
2128 priv
->bis_cur_rdlstate
= true;
2133 if(priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
2135 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_UL
[pHTInfo
->IOTPeer
]);
2136 priv
->bis_cur_rdlstate
= false;
2141 priv
->bcurrent_turbo_EDCA
= true;
2146 // Turn Off EDCA turbo here.
2147 // Restore original EDCA according to the declaration of AP.
2149 if(priv
->bcurrent_turbo_EDCA
)
2155 struct ieee80211_qos_parameters
*qos_parameters
= &priv
->ieee80211
->current_network
.qos_data
.parameters
;
2156 u8 mode
= priv
->ieee80211
->mode
;
2158 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2159 dm_init_edca_turbo(dev
);
2160 u1bAIFS
= qos_parameters
->aifs
[0] * ((mode
&(IEEE_G
|IEEE_N_24G
)) ?9:20) + aSifsTime
;
2161 u4bAcParam
= ((((u32
)(qos_parameters
->tx_op_limit
[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET
)|
2162 (((u32
)(qos_parameters
->cw_max
[0]))<< AC_PARAM_ECW_MAX_OFFSET
)|
2163 (((u32
)(qos_parameters
->cw_min
[0]))<< AC_PARAM_ECW_MIN_OFFSET
)|
2164 ((u32
)u1bAIFS
<< AC_PARAM_AIFS_OFFSET
));
2165 printk("===>u4bAcParam:%x, ", u4bAcParam
);
2166 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2167 write_nic_dword(dev
, EDCAPARA_BE
, u4bAcParam
);
2170 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2172 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2174 PACI_AIFSN pAciAifsn
= (PACI_AIFSN
)&(qos_parameters
->aifs
[0]);
2175 u8 AcmCtrl
= read_nic_byte( dev
, AcmHwCtrl
);
2176 if( pAciAifsn
->f
.ACM
)
2178 AcmCtrl
|= AcmHw_BeqEn
;
2182 AcmCtrl
&= (~AcmHw_BeqEn
);
2185 RT_TRACE( COMP_QOS
,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl
) ;
2186 write_nic_byte(dev
, AcmHwCtrl
, AcmCtrl
);
2189 priv
->bcurrent_turbo_EDCA
= false;
2194 dm_CheckEdcaTurbo_EXIT
:
2195 // Set variables for next time.
2196 priv
->ieee80211
->bis_any_nonbepkts
= false;
2197 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
2198 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
2202 static void dm_init_ctstoself(struct net_device
* dev
)
2204 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
2206 priv
->ieee80211
->bCTSToSelfEnable
= TRUE
;
2207 priv
->ieee80211
->CTSToSelfTH
= CTSToSelfTHVal
;
2210 static void dm_ctstoself(struct net_device
*dev
)
2212 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
2213 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
2214 static unsigned long lastTxOkCnt
= 0;
2215 static unsigned long lastRxOkCnt
= 0;
2216 unsigned long curTxOkCnt
= 0;
2217 unsigned long curRxOkCnt
= 0;
2219 if(priv
->ieee80211
->bCTSToSelfEnable
!= TRUE
)
2221 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
2226 2. Linksys350/Linksys300N
2227 3. <50 disable, >55 enable
2230 if(pHTInfo
->IOTPeer
== HT_IOT_PEER_BROADCOM
)
2232 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
2233 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
2234 if(curRxOkCnt
> 4*curTxOkCnt
) //downlink, disable CTS to self
2236 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
2241 pHTInfo
->IOTAction
|= HT_IOT_ACT_FORCED_CTS2SELF
;
2243 if(priv
->undecorated_smoothed_pwdb
< priv
->ieee80211
->CTSToSelfTH
) // disable CTS to self
2245 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
2247 else if(priv
->undecorated_smoothed_pwdb
>= (priv
->ieee80211
->CTSToSelfTH
+5)) // enable CTS to self
2249 pHTInfo
->IOTAction
|= HT_IOT_ACT_FORCED_CTS2SELF
;
2254 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
2255 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
2261 /* Copy 8187B template for 9xseries */
2263 static void dm_check_rfctrl_gpio(struct net_device
* dev
)
2266 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2269 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
2270 // page 1 register before Lextra bus is enabled cause system fails when resuming
2271 // from S4. 20080218, Emily
2273 // Stop to execute workitem to prevent S3/S4 bug.
2281 queue_delayed_work(priv
->priv_wq
,&priv
->gpio_change_rf_wq
,0);
2287 /* Check if PBC button is pressed. */
2288 static void dm_check_pbc_gpio(struct net_device
*dev
)
2291 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2295 tmp1byte
= read_nic_byte(dev
,GPI
);
2296 if(tmp1byte
== 0xff)
2299 if (tmp1byte
&BIT6
|| tmp1byte
&BIT0
)
2301 // Here we only set bPbcPressed to TRUE
2302 // After trigger PBC, the variable will be set to FALSE
2303 RT_TRACE(COMP_IO
, "CheckPbcGPIO - PBC is pressed\n");
2311 /* PCI will not support workitem call back HW radio on-off control. */
2312 void dm_gpio_change_rf_callback(struct work_struct
*work
)
2314 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
2315 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,gpio_change_rf_wq
);
2316 struct net_device
*dev
= priv
->ieee80211
->dev
;
2318 RT_RF_POWER_STATE eRfPowerStateToSet
;
2319 bool bActuallySet
= false;
2322 RT_TRACE((COMP_INIT
| COMP_POWER
| COMP_RF
),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
2324 // 0x108 GPIO input register is read only
2325 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
2326 tmp1byte
= read_nic_byte(dev
,GPI
);
2328 eRfPowerStateToSet
= (tmp1byte
&BIT1
) ? eRfOn
: eRfOff
;
2330 if (priv
->bHwRadioOff
&& (eRfPowerStateToSet
== eRfOn
)) {
2331 RT_TRACE(COMP_RF
, "gpiochangeRF - HW Radio ON\n");
2333 priv
->bHwRadioOff
= false;
2334 bActuallySet
= true;
2335 } else if ((!priv
->bHwRadioOff
) && (eRfPowerStateToSet
== eRfOff
)) {
2336 RT_TRACE(COMP_RF
, "gpiochangeRF - HW Radio OFF\n");
2337 priv
->bHwRadioOff
= true;
2338 bActuallySet
= true;
2342 priv
->bHwRfOffAction
= 1;
2343 MgntActSet_RF_State(dev
, eRfPowerStateToSet
, RF_CHANGE_BY_HW
);
2344 //DrvIFIndicateCurrentPhyStatus(pAdapter);
2353 /* Check if Current RF RX path is enabled */
2354 void dm_rf_pathcheck_workitemcallback(struct work_struct
*work
)
2356 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
2357 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,rfpath_check_wq
);
2358 struct net_device
*dev
=priv
->ieee80211
->dev
;
2359 //bool bactually_set = false;
2363 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2364 always be the same. We only read 0xc04 now. */
2365 rfpath
= read_nic_byte(dev
, 0xc04);
2367 // Check Bit 0-3, it means if RF A-D is enabled.
2368 for (i
= 0; i
< RF90_PATH_MAX
; i
++)
2370 if (rfpath
& (0x01<<i
))
2371 priv
->brfpath_rxenable
[i
] = 1;
2373 priv
->brfpath_rxenable
[i
] = 0;
2375 if(!DM_RxPathSelTable
.Enable
)
2378 dm_rxpath_sel_byrssi(dev
);
2381 static void dm_init_rxpath_selection(struct net_device
* dev
)
2384 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2385 DM_RxPathSelTable
.Enable
= 1; //default enabled
2386 DM_RxPathSelTable
.SS_TH_low
= RxPathSelection_SS_TH_low
;
2387 DM_RxPathSelTable
.diff_TH
= RxPathSelection_diff_TH
;
2388 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
2389 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_2
;
2391 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_1
;
2392 DM_RxPathSelTable
.DbgMode
= DM_DBG_OFF
;
2393 DM_RxPathSelTable
.disabledRF
= 0;
2396 DM_RxPathSelTable
.rf_rssi
[i
] = 50;
2397 DM_RxPathSelTable
.cck_pwdb_sta
[i
] = -64;
2398 DM_RxPathSelTable
.rf_enable_rssi_th
[i
] = 100;
2402 static void dm_rxpath_sel_byrssi(struct net_device
* dev
)
2404 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2405 u8 i
, max_rssi_index
=0, min_rssi_index
=0, sec_rssi_index
=0, rf_num
=0;
2406 u8 tmp_max_rssi
=0, tmp_min_rssi
=0, tmp_sec_rssi
=0;
2407 u8 cck_default_Rx
=0x2; //RF-C
2408 u8 cck_optional_Rx
=0x3;//RF-D
2409 long tmp_cck_max_pwdb
=0, tmp_cck_min_pwdb
=0, tmp_cck_sec_pwdb
=0;
2410 u8 cck_rx_ver2_max_index
=0, cck_rx_ver2_min_index
=0, cck_rx_ver2_sec_index
=0;
2413 static u8 disabled_rf_cnt
=0, cck_Rx_Path_initialized
=0;
2414 u8 update_cck_rx_path
;
2416 if(priv
->rf_type
!= RF_2T4R
)
2419 if(!cck_Rx_Path_initialized
)
2421 DM_RxPathSelTable
.cck_Rx_path
= (read_nic_byte(dev
, 0xa07)&0xf);
2422 cck_Rx_Path_initialized
= 1;
2425 DM_RxPathSelTable
.disabledRF
= 0xf;
2426 DM_RxPathSelTable
.disabledRF
&=~ (read_nic_byte(dev
, 0xc04));
2428 if(priv
->ieee80211
->mode
== WIRELESS_MODE_B
)
2430 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_2
; //pure B mode, fixed cck version2
2433 //decide max/sec/min rssi index
2434 for (i
=0; i
<RF90_PATH_MAX
; i
++)
2436 if(!DM_RxPathSelTable
.DbgMode
)
2437 DM_RxPathSelTable
.rf_rssi
[i
] = priv
->stats
.rx_rssi_percentage
[i
];
2439 if(priv
->brfpath_rxenable
[i
])
2442 cur_rf_rssi
= DM_RxPathSelTable
.rf_rssi
[i
];
2444 if(rf_num
== 1) // find first enabled rf path and the rssi values
2445 { //initialize, set all rssi index to the same one
2446 max_rssi_index
= min_rssi_index
= sec_rssi_index
= i
;
2447 tmp_max_rssi
= tmp_min_rssi
= tmp_sec_rssi
= cur_rf_rssi
;
2449 else if(rf_num
== 2)
2450 { // we pick up the max index first, and let sec and min to be the same one
2451 if(cur_rf_rssi
>= tmp_max_rssi
)
2453 tmp_max_rssi
= cur_rf_rssi
;
2458 tmp_sec_rssi
= tmp_min_rssi
= cur_rf_rssi
;
2459 sec_rssi_index
= min_rssi_index
= i
;
2464 if(cur_rf_rssi
> tmp_max_rssi
)
2466 tmp_sec_rssi
= tmp_max_rssi
;
2467 sec_rssi_index
= max_rssi_index
;
2468 tmp_max_rssi
= cur_rf_rssi
;
2471 else if(cur_rf_rssi
== tmp_max_rssi
)
2472 { // let sec and min point to the different index
2473 tmp_sec_rssi
= cur_rf_rssi
;
2476 else if((cur_rf_rssi
< tmp_max_rssi
) &&(cur_rf_rssi
> tmp_sec_rssi
))
2478 tmp_sec_rssi
= cur_rf_rssi
;
2481 else if(cur_rf_rssi
== tmp_sec_rssi
)
2483 if(tmp_sec_rssi
== tmp_min_rssi
)
2484 { // let sec and min point to the different index
2485 tmp_sec_rssi
= cur_rf_rssi
;
2490 // This case we don't need to set any index
2493 else if((cur_rf_rssi
< tmp_sec_rssi
) && (cur_rf_rssi
> tmp_min_rssi
))
2495 // This case we don't need to set any index
2497 else if(cur_rf_rssi
== tmp_min_rssi
)
2499 if(tmp_sec_rssi
== tmp_min_rssi
)
2500 { // let sec and min point to the different index
2501 tmp_min_rssi
= cur_rf_rssi
;
2506 // This case we don't need to set any index
2509 else if(cur_rf_rssi
< tmp_min_rssi
)
2511 tmp_min_rssi
= cur_rf_rssi
;
2519 // decide max/sec/min cck pwdb index
2520 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_2
)
2522 for (i
=0; i
<RF90_PATH_MAX
; i
++)
2524 if(priv
->brfpath_rxenable
[i
])
2527 cur_cck_pwdb
= DM_RxPathSelTable
.cck_pwdb_sta
[i
];
2529 if(rf_num
== 1) // find first enabled rf path and the rssi values
2530 { //initialize, set all rssi index to the same one
2531 cck_rx_ver2_max_index
= cck_rx_ver2_min_index
= cck_rx_ver2_sec_index
= i
;
2532 tmp_cck_max_pwdb
= tmp_cck_min_pwdb
= tmp_cck_sec_pwdb
= cur_cck_pwdb
;
2534 else if(rf_num
== 2)
2535 { // we pick up the max index first, and let sec and min to be the same one
2536 if(cur_cck_pwdb
>= tmp_cck_max_pwdb
)
2538 tmp_cck_max_pwdb
= cur_cck_pwdb
;
2539 cck_rx_ver2_max_index
= i
;
2543 tmp_cck_sec_pwdb
= tmp_cck_min_pwdb
= cur_cck_pwdb
;
2544 cck_rx_ver2_sec_index
= cck_rx_ver2_min_index
= i
;
2549 if(cur_cck_pwdb
> tmp_cck_max_pwdb
)
2551 tmp_cck_sec_pwdb
= tmp_cck_max_pwdb
;
2552 cck_rx_ver2_sec_index
= cck_rx_ver2_max_index
;
2553 tmp_cck_max_pwdb
= cur_cck_pwdb
;
2554 cck_rx_ver2_max_index
= i
;
2556 else if(cur_cck_pwdb
== tmp_cck_max_pwdb
)
2557 { // let sec and min point to the different index
2558 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
2559 cck_rx_ver2_sec_index
= i
;
2561 else if((cur_cck_pwdb
< tmp_cck_max_pwdb
) &&(cur_cck_pwdb
> tmp_cck_sec_pwdb
))
2563 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
2564 cck_rx_ver2_sec_index
= i
;
2566 else if(cur_cck_pwdb
== tmp_cck_sec_pwdb
)
2568 if(tmp_cck_sec_pwdb
== tmp_cck_min_pwdb
)
2569 { // let sec and min point to the different index
2570 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
2571 cck_rx_ver2_sec_index
= i
;
2575 // This case we don't need to set any index
2578 else if((cur_cck_pwdb
< tmp_cck_sec_pwdb
) && (cur_cck_pwdb
> tmp_cck_min_pwdb
))
2580 // This case we don't need to set any index
2582 else if(cur_cck_pwdb
== tmp_cck_min_pwdb
)
2584 if(tmp_cck_sec_pwdb
== tmp_cck_min_pwdb
)
2585 { // let sec and min point to the different index
2586 tmp_cck_min_pwdb
= cur_cck_pwdb
;
2587 cck_rx_ver2_min_index
= i
;
2591 // This case we don't need to set any index
2594 else if(cur_cck_pwdb
< tmp_cck_min_pwdb
)
2596 tmp_cck_min_pwdb
= cur_cck_pwdb
;
2597 cck_rx_ver2_min_index
= i
;
2607 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2608 update_cck_rx_path
= 0;
2609 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_2
)
2611 cck_default_Rx
= cck_rx_ver2_max_index
;
2612 cck_optional_Rx
= cck_rx_ver2_sec_index
;
2613 if(tmp_cck_max_pwdb
!= -64)
2614 update_cck_rx_path
= 1;
2617 if(tmp_min_rssi
< DM_RxPathSelTable
.SS_TH_low
&& disabled_rf_cnt
< 2)
2619 if((tmp_max_rssi
- tmp_min_rssi
) >= DM_RxPathSelTable
.diff_TH
)
2621 //record the enabled rssi threshold
2622 DM_RxPathSelTable
.rf_enable_rssi_th
[min_rssi_index
] = tmp_max_rssi
+5;
2623 //disable the BB Rx path, OFDM
2624 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0x1<<min_rssi_index
, 0x0); // 0xc04[3:0]
2625 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0x1<<min_rssi_index
, 0x0); // 0xd04[3:0]
2628 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_1
)
2630 cck_default_Rx
= max_rssi_index
;
2631 cck_optional_Rx
= sec_rssi_index
;
2633 update_cck_rx_path
= 1;
2637 if(update_cck_rx_path
)
2639 DM_RxPathSelTable
.cck_Rx_path
= (cck_default_Rx
<<2)|(cck_optional_Rx
);
2640 rtl8192_setBBreg(dev
, rCCK0_AFESetting
, 0x0f000000, DM_RxPathSelTable
.cck_Rx_path
);
2643 if(DM_RxPathSelTable
.disabledRF
)
2647 if((DM_RxPathSelTable
.disabledRF
>>i
) & 0x1) //disabled rf
2649 if(tmp_max_rssi
>= DM_RxPathSelTable
.rf_enable_rssi_th
[i
])
2651 //enable the BB Rx path
2652 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0x1<<i
, 0x1); // 0xc04[3:0]
2653 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0x1<<i
, 0x1); // 0xd04[3:0]
2654 DM_RxPathSelTable
.rf_enable_rssi_th
[i
] = 100;
2663 * Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2665 static void dm_check_rx_path_selection(struct net_device
*dev
)
2667 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2668 queue_delayed_work(priv
->priv_wq
,&priv
->rfpath_check_wq
,0);
2671 static void dm_init_fsync (struct net_device
*dev
)
2673 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2675 priv
->ieee80211
->fsync_time_interval
= 500;
2676 priv
->ieee80211
->fsync_rate_bitmap
= 0x0f000800;
2677 priv
->ieee80211
->fsync_rssi_threshold
= 30;
2679 priv
->ieee80211
->bfsync_enable
= true;
2681 priv
->ieee80211
->bfsync_enable
= false;
2683 priv
->ieee80211
->fsync_multiple_timeinterval
= 3;
2684 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 100;
2685 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 200;
2686 priv
->ieee80211
->fsync_state
= Default_Fsync
;
2687 priv
->framesyncMonitor
= 1; // current default 0xc38 monitor on
2689 init_timer(&priv
->fsync_timer
);
2690 priv
->fsync_timer
.data
= (unsigned long)dev
;
2691 priv
->fsync_timer
.function
= dm_fsync_timer_callback
;
2695 static void dm_deInit_fsync(struct net_device
*dev
)
2697 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2698 del_timer_sync(&priv
->fsync_timer
);
2701 void dm_fsync_timer_callback(unsigned long data
)
2703 struct net_device
*dev
= (struct net_device
*)data
;
2704 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)data
);
2705 u32 rate_index
, rate_count
= 0, rate_count_diff
=0;
2706 bool bSwitchFromCountDiff
= false;
2707 bool bDoubleTimeInterval
= false;
2709 if( priv
->ieee80211
->state
== IEEE80211_LINKED
&&
2710 priv
->ieee80211
->bfsync_enable
&&
2711 (priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_CDD_FSYNC
))
2713 // Count rate 54, MCS [7], [12, 13, 14, 15]
2715 for(rate_index
= 0; rate_index
<= 27; rate_index
++)
2717 rate_bitmap
= 1 << rate_index
;
2718 if(priv
->ieee80211
->fsync_rate_bitmap
& rate_bitmap
)
2719 rate_count
+= priv
->stats
.received_rate_histogram
[1][rate_index
];
2722 if(rate_count
< priv
->rate_record
)
2723 rate_count_diff
= 0xffffffff - rate_count
+ priv
->rate_record
;
2725 rate_count_diff
= rate_count
- priv
->rate_record
;
2726 if(rate_count_diff
< priv
->rateCountDiffRecord
)
2729 u32 DiffNum
= priv
->rateCountDiffRecord
- rate_count_diff
;
2731 if(DiffNum
>= priv
->ieee80211
->fsync_seconddiff_ratethreshold
)
2732 priv
->ContiuneDiffCount
++;
2734 priv
->ContiuneDiffCount
= 0;
2736 // Contiune count over
2737 if(priv
->ContiuneDiffCount
>=2)
2739 bSwitchFromCountDiff
= true;
2740 priv
->ContiuneDiffCount
= 0;
2745 // Stop contiune count
2746 priv
->ContiuneDiffCount
= 0;
2749 //If Count diff <= FsyncRateCountThreshold
2750 if(rate_count_diff
<= priv
->ieee80211
->fsync_firstdiff_ratethreshold
)
2752 bSwitchFromCountDiff
= true;
2753 priv
->ContiuneDiffCount
= 0;
2755 priv
->rate_record
= rate_count
;
2756 priv
->rateCountDiffRecord
= rate_count_diff
;
2757 RT_TRACE(COMP_HALDM
, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv
->rate_record
, rate_count
, rate_count_diff
, priv
->bswitch_fsync
);
2758 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
2759 if(priv
->undecorated_smoothed_pwdb
> priv
->ieee80211
->fsync_rssi_threshold
&& bSwitchFromCountDiff
)
2761 bDoubleTimeInterval
= true;
2762 priv
->bswitch_fsync
= !priv
->bswitch_fsync
;
2763 if(priv
->bswitch_fsync
)
2766 write_nic_byte(dev
,0xC36, 0x00);
2768 write_nic_byte(dev
,0xC36, 0x1c);
2770 write_nic_byte(dev
, 0xC3e, 0x90);
2775 write_nic_byte(dev
, 0xC36, 0x40);
2777 write_nic_byte(dev
, 0xC36, 0x5c);
2779 write_nic_byte(dev
, 0xC3e, 0x96);
2782 else if(priv
->undecorated_smoothed_pwdb
<= priv
->ieee80211
->fsync_rssi_threshold
)
2784 if(priv
->bswitch_fsync
)
2786 priv
->bswitch_fsync
= false;
2788 write_nic_byte(dev
, 0xC36, 0x40);
2790 write_nic_byte(dev
, 0xC36, 0x5c);
2792 write_nic_byte(dev
, 0xC3e, 0x96);
2795 if(bDoubleTimeInterval
){
2796 if(timer_pending(&priv
->fsync_timer
))
2797 del_timer_sync(&priv
->fsync_timer
);
2798 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
*priv
->ieee80211
->fsync_multiple_timeinterval
);
2799 add_timer(&priv
->fsync_timer
);
2802 if(timer_pending(&priv
->fsync_timer
))
2803 del_timer_sync(&priv
->fsync_timer
);
2804 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
);
2805 add_timer(&priv
->fsync_timer
);
2810 // Let Register return to default value;
2811 if(priv
->bswitch_fsync
)
2813 priv
->bswitch_fsync
= false;
2815 write_nic_byte(dev
, 0xC36, 0x40);
2817 write_nic_byte(dev
, 0xC36, 0x5c);
2819 write_nic_byte(dev
, 0xC3e, 0x96);
2821 priv
->ContiuneDiffCount
= 0;
2823 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x164052cd);
2825 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
2828 RT_TRACE(COMP_HALDM
, "ContiuneDiffCount %d\n", priv
->ContiuneDiffCount
);
2829 RT_TRACE(COMP_HALDM
, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv
->rate_record
, rate_count
, rate_count_diff
, priv
->bswitch_fsync
);
2832 static void dm_StartHWFsync(struct net_device
*dev
)
2834 RT_TRACE(COMP_HALDM
, "%s\n", __FUNCTION__
);
2835 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c12cf);
2836 write_nic_byte(dev
, 0xc3b, 0x41);
2839 static void dm_EndSWFsync(struct net_device
*dev
)
2841 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2843 RT_TRACE(COMP_HALDM
, "%s\n", __FUNCTION__
);
2844 del_timer_sync(&(priv
->fsync_timer
));
2846 // Let Register return to default value;
2847 if(priv
->bswitch_fsync
)
2849 priv
->bswitch_fsync
= false;
2852 write_nic_byte(dev
, 0xC36, 0x40);
2854 write_nic_byte(dev
, 0xC36, 0x5c);
2857 write_nic_byte(dev
, 0xC3e, 0x96);
2860 priv
->ContiuneDiffCount
= 0;
2862 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
2867 static void dm_StartSWFsync(struct net_device
*dev
)
2869 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2873 RT_TRACE(COMP_HALDM
,"%s\n", __FUNCTION__
);
2874 // Initial rate record to zero, start to record.
2875 priv
->rate_record
= 0;
2876 // Initial contiune diff count to zero, start to record.
2877 priv
->ContiuneDiffCount
= 0;
2878 priv
->rateCountDiffRecord
= 0;
2879 priv
->bswitch_fsync
= false;
2881 if(priv
->ieee80211
->mode
== WIRELESS_MODE_N_24G
)
2883 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 600;
2884 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 0xffff;
2888 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 200;
2889 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 200;
2891 for(rateIndex
= 0; rateIndex
<= 27; rateIndex
++)
2893 rateBitmap
= 1 << rateIndex
;
2894 if(priv
->ieee80211
->fsync_rate_bitmap
& rateBitmap
)
2895 priv
->rate_record
+= priv
->stats
.received_rate_histogram
[1][rateIndex
];
2897 if(timer_pending(&priv
->fsync_timer
))
2898 del_timer_sync(&priv
->fsync_timer
);
2899 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
);
2900 add_timer(&priv
->fsync_timer
);
2903 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c12cd);
2908 static void dm_EndHWFsync(struct net_device
*dev
)
2910 RT_TRACE(COMP_HALDM
,"%s\n", __FUNCTION__
);
2911 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
2912 write_nic_byte(dev
, 0xc3b, 0x49);
2916 void dm_check_fsync(struct net_device
*dev
)
2918 #define RegC38_Default 0
2919 #define RegC38_NonFsync_Other_AP 1
2920 #define RegC38_Fsync_AP_BCM 2
2921 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2923 static u8 reg_c38_State
=RegC38_Default
;
2924 static u32 reset_cnt
=0;
2926 RT_TRACE(COMP_HALDM
, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv
->ieee80211
->fsync_rssi_threshold
, priv
->ieee80211
->fsync_time_interval
, priv
->ieee80211
->fsync_multiple_timeinterval
);
2927 RT_TRACE(COMP_HALDM
, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv
->ieee80211
->fsync_rate_bitmap
, priv
->ieee80211
->fsync_firstdiff_ratethreshold
, priv
->ieee80211
->fsync_seconddiff_ratethreshold
);
2929 if( priv
->ieee80211
->state
== IEEE80211_LINKED
&&
2930 (priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_CDD_FSYNC
))
2932 if(priv
->ieee80211
->bfsync_enable
== 0)
2934 switch(priv
->ieee80211
->fsync_state
)
2937 dm_StartHWFsync(dev
);
2938 priv
->ieee80211
->fsync_state
= HW_Fsync
;
2942 dm_StartHWFsync(dev
);
2943 priv
->ieee80211
->fsync_state
= HW_Fsync
;
2952 switch(priv
->ieee80211
->fsync_state
)
2955 dm_StartSWFsync(dev
);
2956 priv
->ieee80211
->fsync_state
= SW_Fsync
;
2960 dm_StartSWFsync(dev
);
2961 priv
->ieee80211
->fsync_state
= SW_Fsync
;
2969 if(priv
->framesyncMonitor
)
2971 if(reg_c38_State
!= RegC38_Fsync_AP_BCM
)
2972 { //For broadcom AP we write different default value
2974 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x15);
2976 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x95);
2979 reg_c38_State
= RegC38_Fsync_AP_BCM
;
2985 switch(priv
->ieee80211
->fsync_state
)
2989 priv
->ieee80211
->fsync_state
= Default_Fsync
;
2993 priv
->ieee80211
->fsync_state
= Default_Fsync
;
3000 if(priv
->framesyncMonitor
)
3002 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
3004 if(priv
->undecorated_smoothed_pwdb
<= RegC38_TH
)
3006 if(reg_c38_State
!= RegC38_NonFsync_Other_AP
)
3009 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x10);
3011 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x90);
3014 reg_c38_State
= RegC38_NonFsync_Other_AP
;
3017 else if(priv
->undecorated_smoothed_pwdb
>= (RegC38_TH
+5))
3021 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
3022 reg_c38_State
= RegC38_Default
;
3030 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
3031 reg_c38_State
= RegC38_Default
;
3036 if(priv
->framesyncMonitor
)
3038 if(priv
->reset_count
!= reset_cnt
)
3039 { //After silent reset, the reg_c38_State will be returned to default value
3040 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
3041 reg_c38_State
= RegC38_Default
;
3042 reset_cnt
= priv
->reset_count
;
3049 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
3050 reg_c38_State
= RegC38_Default
;
3056 * Detect Signal strength to control TX Registry
3057 * Tx Power Control For Near/Far Range
3059 static void dm_init_dynamic_txpower(struct net_device
*dev
)
3061 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3063 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
3064 priv
->ieee80211
->bdynamic_txpower_enable
= true; //Default to enable Tx Power Control
3065 priv
->bLastDTPFlag_High
= false;
3066 priv
->bLastDTPFlag_Low
= false;
3067 priv
->bDynamicTxHighPower
= false;
3068 priv
->bDynamicTxLowPower
= false;
3071 static void dm_dynamic_txpower(struct net_device
*dev
)
3073 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3074 unsigned int txhipower_threshhold
=0;
3075 unsigned int txlowpower_threshold
=0;
3076 if(priv
->ieee80211
->bdynamic_txpower_enable
!= true)
3078 priv
->bDynamicTxHighPower
= false;
3079 priv
->bDynamicTxLowPower
= false;
3082 if((priv
->ieee80211
->current_network
.atheros_cap_exist
) && (priv
->ieee80211
->mode
== IEEE_G
)){
3083 txhipower_threshhold
= TX_POWER_ATHEROAP_THRESH_HIGH
;
3084 txlowpower_threshold
= TX_POWER_ATHEROAP_THRESH_LOW
;
3088 txhipower_threshhold
= TX_POWER_NEAR_FIELD_THRESH_HIGH
;
3089 txlowpower_threshold
= TX_POWER_NEAR_FIELD_THRESH_LOW
;
3092 RT_TRACE(COMP_TXAGC
,"priv->undecorated_smoothed_pwdb = %ld \n" , priv
->undecorated_smoothed_pwdb
);
3094 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
3096 if(priv
->undecorated_smoothed_pwdb
>= txhipower_threshhold
)
3098 priv
->bDynamicTxHighPower
= true;
3099 priv
->bDynamicTxLowPower
= false;
3103 // high power state check
3104 if(priv
->undecorated_smoothed_pwdb
< txlowpower_threshold
&& priv
->bDynamicTxHighPower
== true)
3106 priv
->bDynamicTxHighPower
= false;
3108 // low power state check
3109 if(priv
->undecorated_smoothed_pwdb
< 35)
3111 priv
->bDynamicTxLowPower
= true;
3113 else if(priv
->undecorated_smoothed_pwdb
>= 40)
3115 priv
->bDynamicTxLowPower
= false;
3121 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
3122 priv
->bDynamicTxHighPower
= false;
3123 priv
->bDynamicTxLowPower
= false;
3126 if( (priv
->bDynamicTxHighPower
!= priv
->bLastDTPFlag_High
) ||
3127 (priv
->bDynamicTxLowPower
!= priv
->bLastDTPFlag_Low
) )
3129 RT_TRACE(COMP_TXAGC
,"SetTxPowerLevel8190() channel = %d \n" , priv
->ieee80211
->current_network
.channel
);
3132 rtl8192_phy_setTxPower(dev
,priv
->ieee80211
->current_network
.channel
);
3135 priv
->bLastDTPFlag_High
= priv
->bDynamicTxHighPower
;
3136 priv
->bLastDTPFlag_Low
= priv
->bDynamicTxLowPower
;
3140 //added by vivi, for read tx rate and retrycount
3141 static void dm_check_txrateandretrycount(struct net_device
* dev
)
3143 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3144 struct ieee80211_device
* ieee
= priv
->ieee80211
;
3145 //for initial tx rate
3146 ieee
->softmac_stats
.last_packet_rate
= read_nic_byte(dev
,Initial_Tx_Rate_Reg
);
3147 //for tx tx retry count
3148 ieee
->softmac_stats
.txretrycount
= read_nic_dword(dev
, Tx_Retry_Count_Reg
);
3151 static void dm_send_rssi_tofw(struct net_device
*dev
)
3153 DCMD_TXCMD_T tx_cmd
;
3154 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3156 // If we test chariot, we should stop the TX command ?
3157 // Because 92E will always silent reset when we send tx command. We use register
3158 // 0x1e0(byte) to botify driver.
3159 write_nic_byte(dev
, DRIVER_RSSI
, (u8
)priv
->undecorated_smoothed_pwdb
);
3162 tx_cmd
.Op
= TXCMD_SET_RX_RSSI
;
3164 tx_cmd
.Value
= priv
->undecorated_smoothed_pwdb
;
3166 cmpk_message_handle_tx(dev
, (u8
*)&tx_cmd
,
3167 DESC_PACKET_TYPE_INIT
, sizeof(DCMD_TXCMD_T
));