2 * drivers/ata/sata_fsl.c
4 * Freescale 3.0Gbps SATA device driver
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
27 #include <linux/of_platform.h>
29 /* Controller information */
31 SATA_FSL_QUEUE_DEPTH
= 16,
32 SATA_FSL_MAX_PRD
= 63,
33 SATA_FSL_MAX_PRD_USABLE
= SATA_FSL_MAX_PRD
- 1,
34 SATA_FSL_MAX_PRD_DIRECT
= 16, /* Direct PRDT entries */
36 SATA_FSL_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
37 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
38 ATA_FLAG_PMP
| ATA_FLAG_NCQ
| ATA_FLAG_AN
),
40 SATA_FSL_MAX_CMDS
= SATA_FSL_QUEUE_DEPTH
,
41 SATA_FSL_CMD_HDR_SIZE
= 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE
= (SATA_FSL_MAX_CMDS
* SATA_FSL_CMD_HDR_SIZE
),
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contiguous) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
54 SATA_FSL_CMD_DESC_CFIS_SZ
= 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ
= 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ
= 16,
57 SATA_FSL_CMD_DESC_RSRVD
= 16,
59 SATA_FSL_CMD_DESC_SIZE
= (SATA_FSL_CMD_DESC_CFIS_SZ
+
60 SATA_FSL_CMD_DESC_SFIS_SZ
+
61 SATA_FSL_CMD_DESC_ACMD_SZ
+
62 SATA_FSL_CMD_DESC_RSRVD
+
63 SATA_FSL_MAX_PRD
* 16),
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
=
66 (SATA_FSL_CMD_DESC_CFIS_SZ
+
67 SATA_FSL_CMD_DESC_SFIS_SZ
+
68 SATA_FSL_CMD_DESC_ACMD_SZ
+
69 SATA_FSL_CMD_DESC_RSRVD
),
71 SATA_FSL_CMD_DESC_AR_SZ
= (SATA_FSL_CMD_DESC_SIZE
* SATA_FSL_MAX_CMDS
),
72 SATA_FSL_PORT_PRIV_DMA_SZ
= (SATA_FSL_CMD_SLOT_SIZE
+
73 SATA_FSL_CMD_DESC_AR_SZ
),
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
81 SATA_FSL_MAX_PORTS
= 1,
83 SATA_FSL_IRQ_FLAG
= IRQF_SHARED
,
87 * Host Controller command register set - per port
103 * Host Status Register (HStatus) bitdefs
106 GOING_OFFLINE
= (1 << 30),
107 BIST_ERR
= (1 << 29),
109 FATAL_ERR_HC_MASTER_ERR
= (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX
= (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX
= (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN
= (1 << 13),
113 FATAL_ERR_DATA_OVERRUN
= (1 << 12),
114 FATAL_ERR_CRC_ERR_TX
= (1 << 11),
115 FATAL_ERR_CRC_ERR_RX
= (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX
= (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX
= (1 << 8),
119 FATAL_ERROR_DECODE
= FATAL_ERR_HC_MASTER_ERR
|
120 FATAL_ERR_PARITY_ERR_TX
|
121 FATAL_ERR_PARITY_ERR_RX
|
122 FATAL_ERR_DATA_UNDERRUN
|
123 FATAL_ERR_DATA_OVERRUN
|
124 FATAL_ERR_CRC_ERR_TX
|
125 FATAL_ERR_CRC_ERR_RX
|
126 FATAL_ERR_FIFO_OVRFL_TX
| FATAL_ERR_FIFO_OVRFL_RX
,
128 INT_ON_FATAL_ERR
= (1 << 5),
129 INT_ON_PHYRDY_CHG
= (1 << 4),
131 INT_ON_SIGNATURE_UPDATE
= (1 << 3),
132 INT_ON_SNOTIFY_UPDATE
= (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR
= (1 << 1),
134 INT_ON_CMD_COMPLETE
= 1,
136 INT_ON_ERROR
= INT_ON_FATAL_ERR
| INT_ON_SNOTIFY_UPDATE
|
137 INT_ON_PHYRDY_CHG
| INT_ON_SINGL_DEVICE_ERR
,
140 * Host Control Register (HControl) bitdefs
142 HCONTROL_ONLINE_PHY_RST
= (1 << 31),
143 HCONTROL_FORCE_OFFLINE
= (1 << 30),
144 HCONTROL_PARITY_PROT_MOD
= (1 << 14),
145 HCONTROL_DPATH_PARITY
= (1 << 12),
146 HCONTROL_SNOOP_ENABLE
= (1 << 10),
147 HCONTROL_PMP_ATTACHED
= (1 << 9),
148 HCONTROL_COPYOUT_STATFIS
= (1 << 8),
149 IE_ON_FATAL_ERR
= (1 << 5),
150 IE_ON_PHYRDY_CHG
= (1 << 4),
151 IE_ON_SIGNATURE_UPDATE
= (1 << 3),
152 IE_ON_SNOTIFY_UPDATE
= (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR
= (1 << 1),
154 IE_ON_CMD_COMPLETE
= 1,
156 DEFAULT_PORT_IRQ_ENABLE_MASK
= IE_ON_FATAL_ERR
| IE_ON_PHYRDY_CHG
|
157 IE_ON_SIGNATURE_UPDATE
| IE_ON_SNOTIFY_UPDATE
|
158 IE_ON_SINGL_DEVICE_ERR
| IE_ON_CMD_COMPLETE
,
160 EXT_INDIRECT_SEG_PRD_FLAG
= (1 << 31),
161 DATA_SNOOP_ENABLE
= (1 << 22),
165 * SATA Superset Registers
175 * Control Status Register Set
189 /* PHY (link-layer) configuration control */
191 PHY_BIST_ENABLE
= 0x01,
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
198 struct cmdhdr_tbl_entry
{
206 * Description information bitdefs
209 CMD_DESC_RES
= (1 << 11),
210 VENDOR_SPECIFIC_BIST
= (1 << 10),
211 CMD_DESC_SNOOP_ENABLE
= (1 << 9),
212 FPDMA_QUEUED_CMD
= (1 << 8),
215 ATAPI_CMD
= (1 << 5),
221 struct command_desc
{
226 u32 prdt
[SATA_FSL_MAX_PRD_DIRECT
* 4];
227 u32 prdt_indirect
[(SATA_FSL_MAX_PRD
- SATA_FSL_MAX_PRD_DIRECT
) * 4];
231 * Physical region table descriptor(PRD)
241 * ata_port private data
242 * This is our per-port instance data.
244 struct sata_fsl_port_priv
{
245 struct cmdhdr_tbl_entry
*cmdslot
;
246 dma_addr_t cmdslot_paddr
;
247 struct command_desc
*cmdentry
;
248 dma_addr_t cmdentry_paddr
;
252 * ata_port->host_set private data
254 struct sata_fsl_host_priv
{
255 void __iomem
*hcr_base
;
256 void __iomem
*ssr_base
;
257 void __iomem
*csr_base
;
261 static inline unsigned int sata_fsl_tag(unsigned int tag
,
262 void __iomem
*hcr_base
)
264 /* We let libATA core do actual (queue) tag allocation */
266 /* all non NCQ/queued commands should have tag#0 */
267 if (ata_tag_internal(tag
)) {
268 DPRINTK("mapping internal cmds to tag#0\n");
272 if (unlikely(tag
>= SATA_FSL_QUEUE_DEPTH
)) {
273 DPRINTK("tag %d invalid : out of range\n", tag
);
277 if (unlikely((ioread32(hcr_base
+ CQ
)) & (1 << tag
))) {
278 DPRINTK("tag %d invalid : in use!!\n", tag
);
285 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv
*pp
,
286 unsigned int tag
, u32 desc_info
,
287 u32 data_xfer_len
, u8 num_prde
,
290 dma_addr_t cmd_descriptor_address
;
292 cmd_descriptor_address
= pp
->cmdentry_paddr
+
293 tag
* SATA_FSL_CMD_DESC_SIZE
;
295 /* NOTE: both data_xfer_len & fis_len are Dword counts */
297 pp
->cmdslot
[tag
].cda
= cpu_to_le32(cmd_descriptor_address
);
298 pp
->cmdslot
[tag
].prde_fis_len
=
299 cpu_to_le32((num_prde
<< 16) | (fis_len
<< 2));
300 pp
->cmdslot
[tag
].ttl
= cpu_to_le32(data_xfer_len
& ~0x03);
301 pp
->cmdslot
[tag
].desc_info
= cpu_to_le32(desc_info
| (tag
& 0x1F));
303 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
304 pp
->cmdslot
[tag
].cda
,
305 pp
->cmdslot
[tag
].prde_fis_len
,
306 pp
->cmdslot
[tag
].ttl
, pp
->cmdslot
[tag
].desc_info
);
310 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_desc
,
311 u32
*ttl
, dma_addr_t cmd_desc_paddr
)
313 struct scatterlist
*sg
;
314 unsigned int num_prde
= 0;
318 * NOTE : direct & indirect prdt's are contiguously allocated
320 struct prde
*prd
= (struct prde
*)&((struct command_desc
*)
323 struct prde
*prd_ptr_to_indirect_ext
= NULL
;
324 unsigned indirect_ext_segment_sz
= 0;
325 dma_addr_t indirect_ext_segment_paddr
;
328 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc
, prd
);
330 indirect_ext_segment_paddr
= cmd_desc_paddr
+
331 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
+ SATA_FSL_MAX_PRD_DIRECT
* 16;
333 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
334 dma_addr_t sg_addr
= sg_dma_address(sg
);
335 u32 sg_len
= sg_dma_len(sg
);
337 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
338 (unsigned long long)sg_addr
, sg_len
);
340 /* warn if each s/g element is not dword aligned */
342 ata_port_printk(qc
->ap
, KERN_ERR
,
343 "s/g addr unaligned : 0x%llx\n",
344 (unsigned long long)sg_addr
);
346 ata_port_printk(qc
->ap
, KERN_ERR
,
347 "s/g len unaligned : 0x%x\n", sg_len
);
349 if (num_prde
== (SATA_FSL_MAX_PRD_DIRECT
- 1) &&
350 sg_next(sg
) != NULL
) {
351 VPRINTK("setting indirect prde\n");
352 prd_ptr_to_indirect_ext
= prd
;
353 prd
->dba
= cpu_to_le32(indirect_ext_segment_paddr
);
354 indirect_ext_segment_sz
= 0;
359 ttl_dwords
+= sg_len
;
360 prd
->dba
= cpu_to_le32(sg_addr
);
362 cpu_to_le32(DATA_SNOOP_ENABLE
| (sg_len
& ~0x03));
364 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
365 ttl_dwords
, prd
->dba
, prd
->ddc_and_ext
);
369 if (prd_ptr_to_indirect_ext
)
370 indirect_ext_segment_sz
+= sg_len
;
373 if (prd_ptr_to_indirect_ext
) {
374 /* set indirect extension flag along with indirect ext. size */
375 prd_ptr_to_indirect_ext
->ddc_and_ext
=
376 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG
|
378 (indirect_ext_segment_sz
& ~0x03)));
385 static void sata_fsl_qc_prep(struct ata_queued_cmd
*qc
)
387 struct ata_port
*ap
= qc
->ap
;
388 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
389 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
390 void __iomem
*hcr_base
= host_priv
->hcr_base
;
391 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
392 struct command_desc
*cd
;
393 u32 desc_info
= CMD_DESC_RES
| CMD_DESC_SNOOP_ENABLE
;
398 cd
= (struct command_desc
*)pp
->cmdentry
+ tag
;
399 cd_paddr
= pp
->cmdentry_paddr
+ tag
* SATA_FSL_CMD_DESC_SIZE
;
401 ata_tf_to_fis(&qc
->tf
, qc
->dev
->link
->pmp
, 1, (u8
*) &cd
->cfis
);
403 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
404 cd
->cfis
[0], cd
->cfis
[1], cd
->cfis
[2]);
406 if (qc
->tf
.protocol
== ATA_PROT_NCQ
) {
407 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
408 cd
->cfis
[3], cd
->cfis
[11]);
411 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
412 if (ata_is_atapi(qc
->tf
.protocol
)) {
413 desc_info
|= ATAPI_CMD
;
414 memset((void *)&cd
->acmd
, 0, 32);
415 memcpy((void *)&cd
->acmd
, qc
->cdb
, qc
->dev
->cdb_len
);
418 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
419 num_prde
= sata_fsl_fill_sg(qc
, (void *)cd
,
420 &ttl_dwords
, cd_paddr
);
422 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
423 desc_info
|= FPDMA_QUEUED_CMD
;
425 sata_fsl_setup_cmd_hdr_entry(pp
, tag
, desc_info
, ttl_dwords
,
428 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
429 desc_info
, ttl_dwords
, num_prde
);
432 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd
*qc
)
434 struct ata_port
*ap
= qc
->ap
;
435 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
436 void __iomem
*hcr_base
= host_priv
->hcr_base
;
437 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
439 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
440 ioread32(CQ
+ hcr_base
),
441 ioread32(CA
+ hcr_base
),
442 ioread32(CE
+ hcr_base
), ioread32(CC
+ hcr_base
));
444 iowrite32(qc
->dev
->link
->pmp
, CQPMP
+ hcr_base
);
446 /* Simply queue command to the controller/device */
447 iowrite32(1 << tag
, CQ
+ hcr_base
);
449 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
450 tag
, ioread32(CQ
+ hcr_base
), ioread32(CA
+ hcr_base
));
452 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
453 ioread32(CE
+ hcr_base
),
454 ioread32(DE
+ hcr_base
),
455 ioread32(CC
+ hcr_base
),
456 ioread32(COMMANDSTAT
+ host_priv
->csr_base
));
461 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd
*qc
)
463 struct sata_fsl_port_priv
*pp
= qc
->ap
->private_data
;
464 struct sata_fsl_host_priv
*host_priv
= qc
->ap
->host
->private_data
;
465 void __iomem
*hcr_base
= host_priv
->hcr_base
;
466 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
467 struct command_desc
*cd
;
469 cd
= pp
->cmdentry
+ tag
;
471 ata_tf_from_fis(cd
->sfis
, &qc
->result_tf
);
475 static int sata_fsl_scr_write(struct ata_link
*link
,
476 unsigned int sc_reg_in
, u32 val
)
478 struct sata_fsl_host_priv
*host_priv
= link
->ap
->host
->private_data
;
479 void __iomem
*ssr_base
= host_priv
->ssr_base
;
493 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg
);
495 iowrite32(val
, ssr_base
+ (sc_reg
* 4));
499 static int sata_fsl_scr_read(struct ata_link
*link
,
500 unsigned int sc_reg_in
, u32
*val
)
502 struct sata_fsl_host_priv
*host_priv
= link
->ap
->host
->private_data
;
503 void __iomem
*ssr_base
= host_priv
->ssr_base
;
517 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg
);
519 *val
= ioread32(ssr_base
+ (sc_reg
* 4));
523 static void sata_fsl_freeze(struct ata_port
*ap
)
525 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
526 void __iomem
*hcr_base
= host_priv
->hcr_base
;
529 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
530 ioread32(CQ
+ hcr_base
),
531 ioread32(CA
+ hcr_base
),
532 ioread32(CE
+ hcr_base
), ioread32(DE
+ hcr_base
));
533 VPRINTK("CmdStat = 0x%x\n",
534 ioread32(host_priv
->csr_base
+ COMMANDSTAT
));
536 /* disable interrupts on the controller/port */
537 temp
= ioread32(hcr_base
+ HCONTROL
);
538 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
540 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
541 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
544 static void sata_fsl_thaw(struct ata_port
*ap
)
546 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
547 void __iomem
*hcr_base
= host_priv
->hcr_base
;
550 /* ack. any pending IRQs for this controller/port */
551 temp
= ioread32(hcr_base
+ HSTATUS
);
553 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp
& 0x3F));
556 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
558 /* enable interrupts on the controller/port */
559 temp
= ioread32(hcr_base
+ HCONTROL
);
560 iowrite32((temp
| DEFAULT_PORT_IRQ_ENABLE_MASK
), hcr_base
+ HCONTROL
);
562 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
563 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
566 static void sata_fsl_pmp_attach(struct ata_port
*ap
)
568 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
569 void __iomem
*hcr_base
= host_priv
->hcr_base
;
572 temp
= ioread32(hcr_base
+ HCONTROL
);
573 iowrite32((temp
| HCONTROL_PMP_ATTACHED
), hcr_base
+ HCONTROL
);
576 static void sata_fsl_pmp_detach(struct ata_port
*ap
)
578 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
579 void __iomem
*hcr_base
= host_priv
->hcr_base
;
582 temp
= ioread32(hcr_base
+ HCONTROL
);
583 temp
&= ~HCONTROL_PMP_ATTACHED
;
584 iowrite32(temp
, hcr_base
+ HCONTROL
);
586 /* enable interrupts on the controller/port */
587 temp
= ioread32(hcr_base
+ HCONTROL
);
588 iowrite32((temp
| DEFAULT_PORT_IRQ_ENABLE_MASK
), hcr_base
+ HCONTROL
);
592 static int sata_fsl_port_start(struct ata_port
*ap
)
594 struct device
*dev
= ap
->host
->dev
;
595 struct sata_fsl_port_priv
*pp
;
598 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
599 void __iomem
*hcr_base
= host_priv
->hcr_base
;
602 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
606 mem
= dma_alloc_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
, &mem_dma
,
612 memset(mem
, 0, SATA_FSL_PORT_PRIV_DMA_SZ
);
615 pp
->cmdslot_paddr
= mem_dma
;
617 mem
+= SATA_FSL_CMD_SLOT_SIZE
;
618 mem_dma
+= SATA_FSL_CMD_SLOT_SIZE
;
621 pp
->cmdentry_paddr
= mem_dma
;
623 ap
->private_data
= pp
;
625 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
626 pp
->cmdslot_paddr
, pp
->cmdentry_paddr
);
628 /* Now, update the CHBA register in host controller cmd register set */
629 iowrite32(pp
->cmdslot_paddr
& 0xffffffff, hcr_base
+ CHBA
);
632 * Now, we can bring the controller on-line & also initiate
633 * the COMINIT sequence, we simply return here and the boot-probing
634 * & device discovery process is re-initiated by libATA using a
635 * Softreset EH (dummy) session. Hence, boot probing and device
636 * discovey will be part of sata_fsl_softreset() callback.
639 temp
= ioread32(hcr_base
+ HCONTROL
);
640 iowrite32((temp
| HCONTROL_ONLINE_PHY_RST
), hcr_base
+ HCONTROL
);
642 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
643 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
644 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base
+ CHBA
));
646 #ifdef CONFIG_MPC8315_DS
648 * Workaround for 8315DS board 3gbps link-up issue,
649 * currently limit SATA port to GEN1 speed
651 sata_fsl_scr_read(&ap
->link
, SCR_CONTROL
, &temp
);
654 sata_fsl_scr_write(&ap
->link
, SCR_CONTROL
, temp
);
656 sata_fsl_scr_read(&ap
->link
, SCR_CONTROL
, &temp
);
657 dev_printk(KERN_WARNING
, dev
, "scr_control, speed limited to %x\n",
664 static void sata_fsl_port_stop(struct ata_port
*ap
)
666 struct device
*dev
= ap
->host
->dev
;
667 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
668 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
669 void __iomem
*hcr_base
= host_priv
->hcr_base
;
673 * Force host controller to go off-line, aborting current operations
675 temp
= ioread32(hcr_base
+ HCONTROL
);
676 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
677 temp
|= HCONTROL_FORCE_OFFLINE
;
678 iowrite32(temp
, hcr_base
+ HCONTROL
);
680 /* Poll for controller to go offline - should happen immediately */
681 ata_wait_register(ap
, hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 1);
683 ap
->private_data
= NULL
;
684 dma_free_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
,
685 pp
->cmdslot
, pp
->cmdslot_paddr
);
690 static unsigned int sata_fsl_dev_classify(struct ata_port
*ap
)
692 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
693 void __iomem
*hcr_base
= host_priv
->hcr_base
;
694 struct ata_taskfile tf
;
697 temp
= ioread32(hcr_base
+ SIGNATURE
);
699 VPRINTK("raw sig = 0x%x\n", temp
);
700 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
701 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
703 tf
.lbah
= (temp
>> 24) & 0xff;
704 tf
.lbam
= (temp
>> 16) & 0xff;
705 tf
.lbal
= (temp
>> 8) & 0xff;
706 tf
.nsect
= temp
& 0xff;
708 return ata_dev_classify(&tf
);
711 static int sata_fsl_hardreset(struct ata_link
*link
, unsigned int *class,
712 unsigned long deadline
)
714 struct ata_port
*ap
= link
->ap
;
715 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
716 void __iomem
*hcr_base
= host_priv
->hcr_base
;
719 unsigned long start_jiffies
;
721 DPRINTK("in xx_hardreset\n");
725 * Force host controller to go off-line, aborting current operations
727 temp
= ioread32(hcr_base
+ HCONTROL
);
728 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
729 iowrite32(temp
, hcr_base
+ HCONTROL
);
731 /* Poll for controller to go offline */
732 temp
= ata_wait_register(ap
, hcr_base
+ HSTATUS
, ONLINE
, ONLINE
,
736 ata_port_printk(ap
, KERN_ERR
,
737 "Hardreset failed, not off-lined %d\n", i
);
740 * Try to offline controller atleast twice
746 goto try_offline_again
;
749 DPRINTK("hardreset, controller off-lined\n");
750 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
751 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
754 * PHY reset should remain asserted for atleast 1ms
759 * Now, bring the host controller online again, this can take time
760 * as PHY reset and communication establishment, 1st D2H FIS and
761 * device signature update is done, on safe side assume 500ms
762 * NOTE : Host online status may be indicated immediately!!
765 temp
= ioread32(hcr_base
+ HCONTROL
);
766 temp
|= (HCONTROL_ONLINE_PHY_RST
| HCONTROL_SNOOP_ENABLE
);
767 temp
|= HCONTROL_PMP_ATTACHED
;
768 iowrite32(temp
, hcr_base
+ HCONTROL
);
770 temp
= ata_wait_register(ap
, hcr_base
+ HSTATUS
, ONLINE
, 0, 1, 500);
772 if (!(temp
& ONLINE
)) {
773 ata_port_printk(ap
, KERN_ERR
,
774 "Hardreset failed, not on-lined\n");
778 DPRINTK("hardreset, controller off-lined & on-lined\n");
779 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
780 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
783 * First, wait for the PHYRDY change to occur before waiting for
784 * the signature, and also verify if SStatus indicates device
788 temp
= ata_wait_register(ap
, hcr_base
+ HSTATUS
, 0xFF, 0, 1, 500);
789 if ((!(temp
& 0x10)) || ata_link_offline(link
)) {
790 ata_port_printk(ap
, KERN_WARNING
,
791 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
792 ioread32(hcr_base
+ HSTATUS
));
793 *class = ATA_DEV_NONE
;
798 * Wait for the first D2H from device,i.e,signature update notification
800 start_jiffies
= jiffies
;
801 temp
= ata_wait_register(ap
, hcr_base
+ HSTATUS
, 0xFF, 0x10,
802 500, jiffies_to_msecs(deadline
- start_jiffies
));
804 if ((temp
& 0xFF) != 0x18) {
805 ata_port_printk(ap
, KERN_WARNING
, "No Signature Update\n");
806 *class = ATA_DEV_NONE
;
807 goto do_followup_srst
;
809 ata_port_printk(ap
, KERN_INFO
,
810 "Signature Update detected @ %d msecs\n",
811 jiffies_to_msecs(jiffies
- start_jiffies
));
812 *class = sata_fsl_dev_classify(ap
);
818 * request libATA to perform follow-up softreset
826 static int sata_fsl_softreset(struct ata_link
*link
, unsigned int *class,
827 unsigned long deadline
)
829 struct ata_port
*ap
= link
->ap
;
830 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
831 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
832 void __iomem
*hcr_base
= host_priv
->hcr_base
;
833 int pmp
= sata_srst_pmp(link
);
835 struct ata_taskfile tf
;
839 DPRINTK("in xx_softreset\n");
841 if (ata_link_offline(link
)) {
842 DPRINTK("PHY reports no device\n");
843 *class = ATA_DEV_NONE
;
848 * Send a device reset (SRST) explicitly on command slot #0
849 * Check : will the command queue (reg) be cleared during offlining ??
850 * Also we will be online only if Phy commn. has been established
851 * and device presence has been detected, therefore if we have
852 * reached here, we can send a command to the target device
855 DPRINTK("Sending SRST/device reset\n");
857 ata_tf_init(link
->device
, &tf
);
858 cfis
= (u8
*) &pp
->cmdentry
->cfis
;
860 /* device reset/SRST is a control register update FIS, uses tag0 */
861 sata_fsl_setup_cmd_hdr_entry(pp
, 0,
862 SRST_CMD
| CMD_DESC_RES
| CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
864 tf
.ctl
|= ATA_SRST
; /* setup SRST bit in taskfile control reg */
865 ata_tf_to_fis(&tf
, pmp
, 0, cfis
);
867 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
868 cfis
[0], cfis
[1], cfis
[2], cfis
[3]);
871 * Queue SRST command to the controller/device, ensure that no
872 * other commands are active on the controller/device
875 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
876 ioread32(CQ
+ hcr_base
),
877 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
879 iowrite32(0xFFFF, CC
+ hcr_base
);
880 if (pmp
!= SATA_PMP_CTRL_PORT
)
881 iowrite32(pmp
, CQPMP
+ hcr_base
);
882 iowrite32(1, CQ
+ hcr_base
);
884 temp
= ata_wait_register(ap
, CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
886 ata_port_printk(ap
, KERN_WARNING
, "ATA_SRST issue failed\n");
888 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
889 ioread32(CQ
+ hcr_base
),
890 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
892 sata_fsl_scr_read(&ap
->link
, SCR_ERROR
, &Serror
);
894 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
895 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
896 DPRINTK("Serror = 0x%x\n", Serror
);
903 * SATA device enters reset state after receving a Control register
904 * FIS with SRST bit asserted and it awaits another H2D Control reg.
905 * FIS with SRST bit cleared, then the device does internal diags &
906 * initialization, followed by indicating it's initialization status
907 * using ATA signature D2H register FIS to the host controller.
910 sata_fsl_setup_cmd_hdr_entry(pp
, 0, CMD_DESC_RES
| CMD_DESC_SNOOP_ENABLE
,
913 tf
.ctl
&= ~ATA_SRST
; /* 2nd H2D Ctl. register FIS */
914 ata_tf_to_fis(&tf
, pmp
, 0, cfis
);
916 if (pmp
!= SATA_PMP_CTRL_PORT
)
917 iowrite32(pmp
, CQPMP
+ hcr_base
);
918 iowrite32(1, CQ
+ hcr_base
);
919 ata_msleep(ap
, 150); /* ?? */
922 * The above command would have signalled an interrupt on command
923 * complete, which needs special handling, by clearing the Nth
924 * command bit of the CCreg
926 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
928 DPRINTK("SATA FSL : Now checking device signature\n");
930 *class = ATA_DEV_NONE
;
932 /* Verify if SStatus indicates device presence */
933 if (ata_link_online(link
)) {
935 * if we are here, device presence has been detected,
936 * 1st D2H FIS would have been received, but sfis in
937 * command desc. is not updated, but signature register
938 * would have been updated
941 *class = sata_fsl_dev_classify(ap
);
943 DPRINTK("class = %d\n", *class);
944 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base
+ CC
));
945 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base
+ CE
));
954 static void sata_fsl_error_handler(struct ata_port
*ap
)
957 DPRINTK("in xx_error_handler\n");
958 sata_pmp_error_handler(ap
);
962 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd
*qc
)
964 if (qc
->flags
& ATA_QCFLAG_FAILED
)
965 qc
->err_mask
|= AC_ERR_OTHER
;
968 /* make DMA engine forget about the failed command */
973 static void sata_fsl_error_intr(struct ata_port
*ap
)
975 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
976 void __iomem
*hcr_base
= host_priv
->hcr_base
;
977 u32 hstatus
, dereg
=0, cereg
= 0, SError
= 0;
978 unsigned int err_mask
= 0, action
= 0;
979 int freeze
= 0, abort
=0;
980 struct ata_link
*link
= NULL
;
981 struct ata_queued_cmd
*qc
= NULL
;
982 struct ata_eh_info
*ehi
;
984 hstatus
= ioread32(hcr_base
+ HSTATUS
);
985 cereg
= ioread32(hcr_base
+ CE
);
987 /* first, analyze and record host port events */
989 ehi
= &link
->eh_info
;
990 ata_ehi_clear_desc(ehi
);
993 * Handle & Clear SError
996 sata_fsl_scr_read(&ap
->link
, SCR_ERROR
, &SError
);
997 if (unlikely(SError
& 0xFFFF0000))
998 sata_fsl_scr_write(&ap
->link
, SCR_ERROR
, SError
);
1000 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1001 hstatus
, cereg
, ioread32(hcr_base
+ DE
), SError
);
1003 /* handle fatal errors */
1004 if (hstatus
& FATAL_ERROR_DECODE
) {
1005 ehi
->err_mask
|= AC_ERR_ATA_BUS
;
1006 ehi
->action
|= ATA_EH_SOFTRESET
;
1011 /* Handle SDB FIS receive & notify update */
1012 if (hstatus
& INT_ON_SNOTIFY_UPDATE
)
1013 sata_async_notification(ap
);
1015 /* Handle PHYRDY change notification */
1016 if (hstatus
& INT_ON_PHYRDY_CHG
) {
1017 DPRINTK("SATA FSL: PHYRDY change indication\n");
1019 /* Setup a soft-reset EH action */
1020 ata_ehi_hotplugged(ehi
);
1021 ata_ehi_push_desc(ehi
, "%s", "PHY RDY changed");
1025 /* handle single device errors */
1028 * clear the command error, also clears queue to the device
1029 * in error, and we can (re)issue commands to this device.
1030 * When a device is in error all commands queued into the
1031 * host controller and at the device are considered aborted
1032 * and the queue for that device is stopped. Now, after
1033 * clearing the device error, we can issue commands to the
1034 * device to interrogate it to find the source of the error.
1038 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1039 ioread32(hcr_base
+ CE
), ioread32(hcr_base
+ DE
));
1041 /* find out the offending link and qc */
1042 if (ap
->nr_pmp_links
) {
1043 dereg
= ioread32(hcr_base
+ DE
);
1044 iowrite32(dereg
, hcr_base
+ DE
);
1045 iowrite32(cereg
, hcr_base
+ CE
);
1047 if (dereg
< ap
->nr_pmp_links
) {
1048 link
= &ap
->pmp_link
[dereg
];
1049 ehi
= &link
->eh_info
;
1050 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1052 * We should consider this as non fatal error,
1053 * and TF must be updated as done below.
1056 err_mask
|= AC_ERR_DEV
;
1059 err_mask
|= AC_ERR_HSM
;
1060 action
|= ATA_EH_HARDRESET
;
1064 dereg
= ioread32(hcr_base
+ DE
);
1065 iowrite32(dereg
, hcr_base
+ DE
);
1066 iowrite32(cereg
, hcr_base
+ CE
);
1068 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1070 * We should consider this as non fatal error,
1071 * and TF must be updated as done below.
1073 err_mask
|= AC_ERR_DEV
;
1077 /* record error info */
1079 qc
->err_mask
|= err_mask
;
1081 ehi
->err_mask
|= err_mask
;
1083 ehi
->action
|= action
;
1085 /* freeze or abort */
1087 ata_port_freeze(ap
);
1090 ata_link_abort(qc
->dev
->link
);
1096 static void sata_fsl_host_intr(struct ata_port
*ap
)
1098 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1099 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1100 u32 hstatus
, done_mask
= 0;
1101 struct ata_queued_cmd
*qc
;
1104 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1106 sata_fsl_scr_read(&ap
->link
, SCR_ERROR
, &SError
);
1108 if (unlikely(SError
& 0xFFFF0000)) {
1109 DPRINTK("serror @host_intr : 0x%x\n", SError
);
1110 sata_fsl_error_intr(ap
);
1113 if (unlikely(hstatus
& INT_ON_ERROR
)) {
1114 DPRINTK("error interrupt!!\n");
1115 sata_fsl_error_intr(ap
);
1119 /* Read command completed register */
1120 done_mask
= ioread32(hcr_base
+ CC
);
1122 VPRINTK("Status of all queues :\n");
1123 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1125 ioread32(hcr_base
+ CA
),
1126 ioread32(hcr_base
+ CE
),
1127 ioread32(hcr_base
+ CQ
),
1130 if (done_mask
& ap
->qc_active
) {
1132 /* clear CC bit, this will also complete the interrupt */
1133 iowrite32(done_mask
, hcr_base
+ CC
);
1135 DPRINTK("Status of all queues :\n");
1136 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1137 done_mask
, ioread32(hcr_base
+ CA
),
1138 ioread32(hcr_base
+ CE
));
1140 for (i
= 0; i
< SATA_FSL_QUEUE_DEPTH
; i
++) {
1141 if (done_mask
& (1 << i
))
1143 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1144 i
, ioread32(hcr_base
+ CC
),
1145 ioread32(hcr_base
+ CA
));
1147 ata_qc_complete_multiple(ap
, ap
->qc_active
^ done_mask
);
1150 } else if ((ap
->qc_active
& (1 << ATA_TAG_INTERNAL
))) {
1151 iowrite32(1, hcr_base
+ CC
);
1152 qc
= ata_qc_from_tag(ap
, ATA_TAG_INTERNAL
);
1154 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1155 ioread32(hcr_base
+ CC
));
1158 ata_qc_complete(qc
);
1161 /* Spurious Interrupt!! */
1162 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1163 ioread32(hcr_base
+ CC
));
1164 iowrite32(done_mask
, hcr_base
+ CC
);
1169 static irqreturn_t
sata_fsl_interrupt(int irq
, void *dev_instance
)
1171 struct ata_host
*host
= dev_instance
;
1172 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1173 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1174 u32 interrupt_enables
;
1175 unsigned handled
= 0;
1176 struct ata_port
*ap
;
1178 /* ack. any pending IRQs for this controller/port */
1179 interrupt_enables
= ioread32(hcr_base
+ HSTATUS
);
1180 interrupt_enables
&= 0x3F;
1182 DPRINTK("interrupt status 0x%x\n", interrupt_enables
);
1184 if (!interrupt_enables
)
1187 spin_lock(&host
->lock
);
1189 /* Assuming one port per host controller */
1191 ap
= host
->ports
[0];
1193 sata_fsl_host_intr(ap
);
1195 dev_printk(KERN_WARNING
, host
->dev
,
1196 "interrupt on disabled port 0\n");
1199 iowrite32(interrupt_enables
, hcr_base
+ HSTATUS
);
1202 spin_unlock(&host
->lock
);
1204 return IRQ_RETVAL(handled
);
1208 * Multiple ports are represented by multiple SATA controllers with
1209 * one port per controller
1211 static int sata_fsl_init_controller(struct ata_host
*host
)
1213 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1214 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1218 * NOTE : We cannot bring the controller online before setting
1219 * the CHBA, hence main controller initialization is done as
1220 * part of the port_start() callback
1223 /* ack. any pending IRQs for this controller/port */
1224 temp
= ioread32(hcr_base
+ HSTATUS
);
1226 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
1228 /* Keep interrupts disabled on the controller */
1229 temp
= ioread32(hcr_base
+ HCONTROL
);
1230 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
1232 /* Disable interrupt coalescing control(icc), for the moment */
1233 DPRINTK("icc = 0x%x\n", ioread32(hcr_base
+ ICC
));
1234 iowrite32(0x01000000, hcr_base
+ ICC
);
1236 /* clear error registers, SError is cleared by libATA */
1237 iowrite32(0x00000FFFF, hcr_base
+ CE
);
1238 iowrite32(0x00000FFFF, hcr_base
+ DE
);
1241 * host controller will be brought on-line, during xx_port_start()
1242 * callback, that should also initiate the OOB, COMINIT sequence
1245 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
1246 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
1252 * scsi mid-layer and libata interface structures
1254 static struct scsi_host_template sata_fsl_sht
= {
1255 ATA_NCQ_SHT("sata_fsl"),
1256 .can_queue
= SATA_FSL_QUEUE_DEPTH
,
1257 .sg_tablesize
= SATA_FSL_MAX_PRD_USABLE
,
1258 .dma_boundary
= ATA_DMA_BOUNDARY
,
1261 static struct ata_port_operations sata_fsl_ops
= {
1262 .inherits
= &sata_pmp_port_ops
,
1264 .qc_defer
= ata_std_qc_defer
,
1265 .qc_prep
= sata_fsl_qc_prep
,
1266 .qc_issue
= sata_fsl_qc_issue
,
1267 .qc_fill_rtf
= sata_fsl_qc_fill_rtf
,
1269 .scr_read
= sata_fsl_scr_read
,
1270 .scr_write
= sata_fsl_scr_write
,
1272 .freeze
= sata_fsl_freeze
,
1273 .thaw
= sata_fsl_thaw
,
1274 .softreset
= sata_fsl_softreset
,
1275 .hardreset
= sata_fsl_hardreset
,
1276 .pmp_softreset
= sata_fsl_softreset
,
1277 .error_handler
= sata_fsl_error_handler
,
1278 .post_internal_cmd
= sata_fsl_post_internal_cmd
,
1280 .port_start
= sata_fsl_port_start
,
1281 .port_stop
= sata_fsl_port_stop
,
1283 .pmp_attach
= sata_fsl_pmp_attach
,
1284 .pmp_detach
= sata_fsl_pmp_detach
,
1287 static const struct ata_port_info sata_fsl_port_info
[] = {
1289 .flags
= SATA_FSL_HOST_FLAGS
,
1290 .pio_mask
= ATA_PIO4
,
1291 .udma_mask
= ATA_UDMA6
,
1292 .port_ops
= &sata_fsl_ops
,
1296 static int sata_fsl_probe(struct platform_device
*ofdev
,
1297 const struct of_device_id
*match
)
1299 int retval
= -ENXIO
;
1300 void __iomem
*hcr_base
= NULL
;
1301 void __iomem
*ssr_base
= NULL
;
1302 void __iomem
*csr_base
= NULL
;
1303 struct sata_fsl_host_priv
*host_priv
= NULL
;
1305 struct ata_host
*host
;
1307 struct ata_port_info pi
= sata_fsl_port_info
[0];
1308 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1310 dev_printk(KERN_INFO
, &ofdev
->dev
,
1311 "Sata FSL Platform/CSB Driver init\n");
1313 hcr_base
= of_iomap(ofdev
->dev
.of_node
, 0);
1315 goto error_exit_with_cleanup
;
1317 ssr_base
= hcr_base
+ 0x100;
1318 csr_base
= hcr_base
+ 0x140;
1320 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base
+ TRANSCFG
));
1321 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc
));
1322 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE
);
1324 host_priv
= kzalloc(sizeof(struct sata_fsl_host_priv
), GFP_KERNEL
);
1326 goto error_exit_with_cleanup
;
1328 host_priv
->hcr_base
= hcr_base
;
1329 host_priv
->ssr_base
= ssr_base
;
1330 host_priv
->csr_base
= csr_base
;
1332 irq
= irq_of_parse_and_map(ofdev
->dev
.of_node
, 0);
1334 dev_printk(KERN_ERR
, &ofdev
->dev
, "invalid irq from platform\n");
1335 goto error_exit_with_cleanup
;
1337 host_priv
->irq
= irq
;
1339 /* allocate host structure */
1340 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_FSL_MAX_PORTS
);
1342 /* host->iomap is not used currently */
1343 host
->private_data
= host_priv
;
1345 /* initialize host controller */
1346 sata_fsl_init_controller(host
);
1349 * Now, register with libATA core, this will also initiate the
1350 * device discovery process, invoking our port_start() handler &
1351 * error_handler() to execute a dummy Softreset EH session
1353 ata_host_activate(host
, irq
, sata_fsl_interrupt
, SATA_FSL_IRQ_FLAG
,
1356 dev_set_drvdata(&ofdev
->dev
, host
);
1360 error_exit_with_cleanup
:
1370 static int sata_fsl_remove(struct platform_device
*ofdev
)
1372 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
1373 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1375 ata_host_detach(host
);
1377 dev_set_drvdata(&ofdev
->dev
, NULL
);
1379 irq_dispose_mapping(host_priv
->irq
);
1380 iounmap(host_priv
->hcr_base
);
1387 static int sata_fsl_suspend(struct platform_device
*op
, pm_message_t state
)
1389 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
1390 return ata_host_suspend(host
, state
);
1393 static int sata_fsl_resume(struct platform_device
*op
)
1395 struct ata_host
*host
= dev_get_drvdata(&op
->dev
);
1396 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1398 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1399 struct ata_port
*ap
= host
->ports
[0];
1400 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
1402 ret
= sata_fsl_init_controller(host
);
1404 dev_printk(KERN_ERR
, &op
->dev
,
1405 "Error initialize hardware\n");
1409 /* Recovery the CHBA register in host controller cmd register set */
1410 iowrite32(pp
->cmdslot_paddr
& 0xffffffff, hcr_base
+ CHBA
);
1412 ata_host_resume(host
);
1417 static struct of_device_id fsl_sata_match
[] = {
1419 .compatible
= "fsl,pq-sata",
1424 MODULE_DEVICE_TABLE(of
, fsl_sata_match
);
1426 static struct of_platform_driver fsl_sata_driver
= {
1429 .owner
= THIS_MODULE
,
1430 .of_match_table
= fsl_sata_match
,
1432 .probe
= sata_fsl_probe
,
1433 .remove
= sata_fsl_remove
,
1435 .suspend
= sata_fsl_suspend
,
1436 .resume
= sata_fsl_resume
,
1440 static int __init
sata_fsl_init(void)
1442 of_register_platform_driver(&fsl_sata_driver
);
1446 static void __exit
sata_fsl_exit(void)
1448 of_unregister_platform_driver(&fsl_sata_driver
);
1451 MODULE_LICENSE("GPL");
1452 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1453 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1454 MODULE_VERSION("1.10");
1456 module_init(sata_fsl_init
);
1457 module_exit(sata_fsl_exit
);