2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
61 #include <asm/debug.h>
63 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
64 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
65 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
66 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
67 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
68 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
69 int (*__debugger_dabr_match
)(struct pt_regs
*regs
) __read_mostly
;
70 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
72 EXPORT_SYMBOL(__debugger
);
73 EXPORT_SYMBOL(__debugger_ipi
);
74 EXPORT_SYMBOL(__debugger_bpt
);
75 EXPORT_SYMBOL(__debugger_sstep
);
76 EXPORT_SYMBOL(__debugger_iabr_match
);
77 EXPORT_SYMBOL(__debugger_dabr_match
);
78 EXPORT_SYMBOL(__debugger_fault_handler
);
82 * Trap & Exception support
85 #ifdef CONFIG_PMAC_BACKLIGHT
86 static void pmac_backlight_unblank(void)
88 mutex_lock(&pmac_backlight_mutex
);
90 struct backlight_properties
*props
;
92 props
= &pmac_backlight
->props
;
93 props
->brightness
= props
->max_brightness
;
94 props
->power
= FB_BLANK_UNBLANK
;
95 backlight_update_status(pmac_backlight
);
97 mutex_unlock(&pmac_backlight_mutex
);
100 static inline void pmac_backlight_unblank(void) { }
103 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
104 static int die_owner
= -1;
105 static unsigned int die_nest_count
;
106 static int die_counter
;
108 static unsigned __kprobes
long oops_begin(struct pt_regs
*regs
)
118 /* racy, but better than risking deadlock. */
119 raw_local_irq_save(flags
);
120 cpu
= smp_processor_id();
121 if (!arch_spin_trylock(&die_lock
)) {
122 if (cpu
== die_owner
)
123 /* nested oops. should stop eventually */;
125 arch_spin_lock(&die_lock
);
131 if (machine_is(powermac
))
132 pmac_backlight_unblank();
136 static void __kprobes
oops_end(unsigned long flags
, struct pt_regs
*regs
,
141 add_taint(TAINT_DIE
);
146 /* Nest count reaches zero, release the lock. */
147 arch_spin_unlock(&die_lock
);
148 raw_local_irq_restore(flags
);
150 crash_fadump(regs
, "die oops");
153 * A system reset (0x100) is a request to dump, so we always send
154 * it through the crashdump code.
156 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
160 * We aren't the primary crash CPU. We need to send it
161 * to a holding pattern to avoid it ending up in the panic
164 crash_kexec_secondary(regs
);
171 * While our oops output is serialised by a spinlock, output
172 * from panic() called below can race and corrupt it. If we
173 * know we are going to panic, delay for 1 second so we have a
174 * chance to get clean backtraces from all CPUs that are oopsing.
176 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
177 is_global_init(current
)) {
178 mdelay(MSEC_PER_SEC
);
182 panic("Fatal exception in interrupt");
184 panic("Fatal exception");
188 static int __kprobes
__die(const char *str
, struct pt_regs
*regs
, long err
)
190 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
191 #ifdef CONFIG_PREEMPT
195 printk("SMP NR_CPUS=%d ", NR_CPUS
);
197 #ifdef CONFIG_DEBUG_PAGEALLOC
198 printk("DEBUG_PAGEALLOC ");
203 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
205 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
214 void die(const char *str
, struct pt_regs
*regs
, long err
)
216 unsigned long flags
= oops_begin(regs
);
218 if (__die(str
, regs
, err
))
220 oops_end(flags
, regs
, err
);
223 void user_single_step_siginfo(struct task_struct
*tsk
,
224 struct pt_regs
*regs
, siginfo_t
*info
)
226 memset(info
, 0, sizeof(*info
));
227 info
->si_signo
= SIGTRAP
;
228 info
->si_code
= TRAP_TRACE
;
229 info
->si_addr
= (void __user
*)regs
->nip
;
232 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
235 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
236 "at %08lx nip %08lx lr %08lx code %x\n";
237 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
238 "at %016lx nip %016lx lr %016lx code %x\n";
240 if (!user_mode(regs
)) {
241 die("Exception in kernel mode", regs
, signr
);
245 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
246 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
247 current
->comm
, current
->pid
, signr
,
248 addr
, regs
->nip
, regs
->link
, code
);
251 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
254 memset(&info
, 0, sizeof(info
));
255 info
.si_signo
= signr
;
257 info
.si_addr
= (void __user
*) addr
;
258 force_sig_info(signr
, &info
, current
);
262 void system_reset_exception(struct pt_regs
*regs
)
264 /* See if any machine dependent calls */
265 if (ppc_md
.system_reset_exception
) {
266 if (ppc_md
.system_reset_exception(regs
))
270 die("System Reset", regs
, SIGABRT
);
272 /* Must die if the interrupt is not recoverable */
273 if (!(regs
->msr
& MSR_RI
))
274 panic("Unrecoverable System Reset");
276 /* What should we do here? We could issue a shutdown or hard reset. */
281 * I/O accesses can cause machine checks on powermacs.
282 * Check if the NIP corresponds to the address of a sync
283 * instruction for which there is an entry in the exception
285 * Note that the 601 only takes a machine check on TEA
286 * (transfer error ack) signal assertion, and does not
287 * set any of the top 16 bits of SRR1.
290 static inline int check_io_access(struct pt_regs
*regs
)
293 unsigned long msr
= regs
->msr
;
294 const struct exception_table_entry
*entry
;
295 unsigned int *nip
= (unsigned int *)regs
->nip
;
297 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
298 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
300 * Check that it's a sync instruction, or somewhere
301 * in the twi; isync; nop sequence that inb/inw/inl uses.
302 * As the address is in the exception table
303 * we should be able to read the instr there.
304 * For the debug message, we look at the preceding
307 if (*nip
== 0x60000000) /* nop */
309 else if (*nip
== 0x4c00012c) /* isync */
311 if (*nip
== 0x7c0004ac || (*nip
>> 26) == 3) {
316 rb
= (*nip
>> 11) & 0x1f;
317 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
318 (*nip
& 0x100)? "OUT to": "IN from",
319 regs
->gpr
[rb
] - _IO_BASE
, nip
);
321 regs
->nip
= entry
->fixup
;
325 #endif /* CONFIG_PPC32 */
329 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
330 /* On 4xx, the reason for the machine check or program exception
332 #define get_reason(regs) ((regs)->dsisr)
333 #ifndef CONFIG_FSL_BOOKE
334 #define get_mc_reason(regs) ((regs)->dsisr)
336 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
338 #define REASON_FP ESR_FP
339 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
340 #define REASON_PRIVILEGED ESR_PPR
341 #define REASON_TRAP ESR_PTR
343 /* single-step stuff */
344 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
345 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
348 /* On non-4xx, the reason for the machine check or program
349 exception is in the MSR. */
350 #define get_reason(regs) ((regs)->msr)
351 #define get_mc_reason(regs) ((regs)->msr)
352 #define REASON_FP 0x100000
353 #define REASON_ILLEGAL 0x80000
354 #define REASON_PRIVILEGED 0x40000
355 #define REASON_TRAP 0x20000
357 #define single_stepping(regs) ((regs)->msr & MSR_SE)
358 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
361 #if defined(CONFIG_4xx)
362 int machine_check_4xx(struct pt_regs
*regs
)
364 unsigned long reason
= get_mc_reason(regs
);
366 if (reason
& ESR_IMCP
) {
367 printk("Instruction");
368 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
371 printk(" machine check in kernel mode.\n");
376 int machine_check_440A(struct pt_regs
*regs
)
378 unsigned long reason
= get_mc_reason(regs
);
380 printk("Machine check in kernel mode.\n");
381 if (reason
& ESR_IMCP
){
382 printk("Instruction Synchronous Machine Check exception\n");
383 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
386 u32 mcsr
= mfspr(SPRN_MCSR
);
388 printk("Instruction Read PLB Error\n");
390 printk("Data Read PLB Error\n");
392 printk("Data Write PLB Error\n");
393 if (mcsr
& MCSR_TLBP
)
394 printk("TLB Parity Error\n");
395 if (mcsr
& MCSR_ICP
){
396 flush_instruction_cache();
397 printk("I-Cache Parity Error\n");
399 if (mcsr
& MCSR_DCSP
)
400 printk("D-Cache Search Parity Error\n");
401 if (mcsr
& MCSR_DCFP
)
402 printk("D-Cache Flush Parity Error\n");
403 if (mcsr
& MCSR_IMPE
)
404 printk("Machine Check exception is imprecise\n");
407 mtspr(SPRN_MCSR
, mcsr
);
412 int machine_check_47x(struct pt_regs
*regs
)
414 unsigned long reason
= get_mc_reason(regs
);
417 printk(KERN_ERR
"Machine check in kernel mode.\n");
418 if (reason
& ESR_IMCP
) {
420 "Instruction Synchronous Machine Check exception\n");
421 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
424 mcsr
= mfspr(SPRN_MCSR
);
426 printk(KERN_ERR
"Instruction Read PLB Error\n");
428 printk(KERN_ERR
"Data Read PLB Error\n");
430 printk(KERN_ERR
"Data Write PLB Error\n");
431 if (mcsr
& MCSR_TLBP
)
432 printk(KERN_ERR
"TLB Parity Error\n");
433 if (mcsr
& MCSR_ICP
) {
434 flush_instruction_cache();
435 printk(KERN_ERR
"I-Cache Parity Error\n");
437 if (mcsr
& MCSR_DCSP
)
438 printk(KERN_ERR
"D-Cache Search Parity Error\n");
439 if (mcsr
& PPC47x_MCSR_GPR
)
440 printk(KERN_ERR
"GPR Parity Error\n");
441 if (mcsr
& PPC47x_MCSR_FPR
)
442 printk(KERN_ERR
"FPR Parity Error\n");
443 if (mcsr
& PPC47x_MCSR_IPR
)
444 printk(KERN_ERR
"Machine Check exception is imprecise\n");
447 mtspr(SPRN_MCSR
, mcsr
);
451 #elif defined(CONFIG_E500)
452 int machine_check_e500mc(struct pt_regs
*regs
)
454 unsigned long mcsr
= mfspr(SPRN_MCSR
);
455 unsigned long reason
= mcsr
;
458 if (reason
& MCSR_LD
) {
459 recoverable
= fsl_rio_mcheck_exception(regs
);
460 if (recoverable
== 1)
464 printk("Machine check in kernel mode.\n");
465 printk("Caused by (from MCSR=%lx): ", reason
);
467 if (reason
& MCSR_MCP
)
468 printk("Machine Check Signal\n");
470 if (reason
& MCSR_ICPERR
) {
471 printk("Instruction Cache Parity Error\n");
474 * This is recoverable by invalidating the i-cache.
476 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
477 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
481 * This will generally be accompanied by an instruction
482 * fetch error report -- only treat MCSR_IF as fatal
483 * if it wasn't due to an L1 parity error.
488 if (reason
& MCSR_DCPERR_MC
) {
489 printk("Data Cache Parity Error\n");
492 * In write shadow mode we auto-recover from the error, but it
493 * may still get logged and cause a machine check. We should
494 * only treat the non-write shadow case as non-recoverable.
496 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
500 if (reason
& MCSR_L2MMU_MHIT
) {
501 printk("Hit on multiple TLB entries\n");
505 if (reason
& MCSR_NMI
)
506 printk("Non-maskable interrupt\n");
508 if (reason
& MCSR_IF
) {
509 printk("Instruction Fetch Error Report\n");
513 if (reason
& MCSR_LD
) {
514 printk("Load Error Report\n");
518 if (reason
& MCSR_ST
) {
519 printk("Store Error Report\n");
523 if (reason
& MCSR_LDG
) {
524 printk("Guarded Load Error Report\n");
528 if (reason
& MCSR_TLBSYNC
)
529 printk("Simultaneous tlbsync operations\n");
531 if (reason
& MCSR_BSL2_ERR
) {
532 printk("Level 2 Cache Error\n");
536 if (reason
& MCSR_MAV
) {
539 addr
= mfspr(SPRN_MCAR
);
540 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
542 printk("Machine Check %s Address: %#llx\n",
543 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
547 mtspr(SPRN_MCSR
, mcsr
);
548 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
551 int machine_check_e500(struct pt_regs
*regs
)
553 unsigned long reason
= get_mc_reason(regs
);
555 if (reason
& MCSR_BUS_RBERR
) {
556 if (fsl_rio_mcheck_exception(regs
))
560 printk("Machine check in kernel mode.\n");
561 printk("Caused by (from MCSR=%lx): ", reason
);
563 if (reason
& MCSR_MCP
)
564 printk("Machine Check Signal\n");
565 if (reason
& MCSR_ICPERR
)
566 printk("Instruction Cache Parity Error\n");
567 if (reason
& MCSR_DCP_PERR
)
568 printk("Data Cache Push Parity Error\n");
569 if (reason
& MCSR_DCPERR
)
570 printk("Data Cache Parity Error\n");
571 if (reason
& MCSR_BUS_IAERR
)
572 printk("Bus - Instruction Address Error\n");
573 if (reason
& MCSR_BUS_RAERR
)
574 printk("Bus - Read Address Error\n");
575 if (reason
& MCSR_BUS_WAERR
)
576 printk("Bus - Write Address Error\n");
577 if (reason
& MCSR_BUS_IBERR
)
578 printk("Bus - Instruction Data Error\n");
579 if (reason
& MCSR_BUS_RBERR
)
580 printk("Bus - Read Data Bus Error\n");
581 if (reason
& MCSR_BUS_WBERR
)
582 printk("Bus - Read Data Bus Error\n");
583 if (reason
& MCSR_BUS_IPERR
)
584 printk("Bus - Instruction Parity Error\n");
585 if (reason
& MCSR_BUS_RPERR
)
586 printk("Bus - Read Parity Error\n");
591 int machine_check_generic(struct pt_regs
*regs
)
595 #elif defined(CONFIG_E200)
596 int machine_check_e200(struct pt_regs
*regs
)
598 unsigned long reason
= get_mc_reason(regs
);
600 printk("Machine check in kernel mode.\n");
601 printk("Caused by (from MCSR=%lx): ", reason
);
603 if (reason
& MCSR_MCP
)
604 printk("Machine Check Signal\n");
605 if (reason
& MCSR_CP_PERR
)
606 printk("Cache Push Parity Error\n");
607 if (reason
& MCSR_CPERR
)
608 printk("Cache Parity Error\n");
609 if (reason
& MCSR_EXCP_ERR
)
610 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
611 if (reason
& MCSR_BUS_IRERR
)
612 printk("Bus - Read Bus Error on instruction fetch\n");
613 if (reason
& MCSR_BUS_DRERR
)
614 printk("Bus - Read Bus Error on data load\n");
615 if (reason
& MCSR_BUS_WRERR
)
616 printk("Bus - Write Bus Error on buffered store or cache line push\n");
621 int machine_check_generic(struct pt_regs
*regs
)
623 unsigned long reason
= get_mc_reason(regs
);
625 printk("Machine check in kernel mode.\n");
626 printk("Caused by (from SRR1=%lx): ", reason
);
627 switch (reason
& 0x601F0000) {
629 printk("Machine check signal\n");
631 case 0: /* for 601 */
633 case 0x140000: /* 7450 MSS error and TEA */
634 printk("Transfer error ack signal\n");
637 printk("Data parity error signal\n");
640 printk("Address parity error signal\n");
643 printk("L1 Data Cache error\n");
646 printk("L1 Instruction Cache error\n");
649 printk("L2 data cache parity error\n");
652 printk("Unknown values in msr\n");
656 #endif /* everything else */
658 void machine_check_exception(struct pt_regs
*regs
)
662 __get_cpu_var(irq_stat
).mce_exceptions
++;
664 /* See if any machine dependent calls. In theory, we would want
665 * to call the CPU first, and call the ppc_md. one if the CPU
666 * one returns a positive number. However there is existing code
667 * that assumes the board gets a first chance, so let's keep it
668 * that way for now and fix things later. --BenH.
670 if (ppc_md
.machine_check_exception
)
671 recover
= ppc_md
.machine_check_exception(regs
);
672 else if (cur_cpu_spec
->machine_check
)
673 recover
= cur_cpu_spec
->machine_check(regs
);
678 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
679 /* the qspan pci read routines can cause machine checks -- Cort
681 * yuck !!! that totally needs to go away ! There are better ways
682 * to deal with that than having a wart in the mcheck handler.
685 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
689 if (debugger_fault_handler(regs
))
692 if (check_io_access(regs
))
695 die("Machine check", regs
, SIGBUS
);
697 /* Must die if the interrupt is not recoverable */
698 if (!(regs
->msr
& MSR_RI
))
699 panic("Unrecoverable Machine check");
702 void SMIException(struct pt_regs
*regs
)
704 die("System Management Interrupt", regs
, SIGABRT
);
707 void unknown_exception(struct pt_regs
*regs
)
709 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
710 regs
->nip
, regs
->msr
, regs
->trap
);
712 _exception(SIGTRAP
, regs
, 0, 0);
715 void instruction_breakpoint_exception(struct pt_regs
*regs
)
717 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
718 5, SIGTRAP
) == NOTIFY_STOP
)
720 if (debugger_iabr_match(regs
))
722 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
725 void RunModeException(struct pt_regs
*regs
)
727 _exception(SIGTRAP
, regs
, 0, 0);
730 void __kprobes
single_step_exception(struct pt_regs
*regs
)
732 clear_single_step(regs
);
734 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
735 5, SIGTRAP
) == NOTIFY_STOP
)
737 if (debugger_sstep(regs
))
740 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
744 * After we have successfully emulated an instruction, we have to
745 * check if the instruction was being single-stepped, and if so,
746 * pretend we got a single-step exception. This was pointed out
747 * by Kumar Gala. -- paulus
749 static void emulate_single_step(struct pt_regs
*regs
)
751 if (single_stepping(regs
))
752 single_step_exception(regs
);
755 static inline int __parse_fpscr(unsigned long fpscr
)
759 /* Invalid operation */
760 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
764 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
768 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
772 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
776 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
782 static void parse_fpe(struct pt_regs
*regs
)
786 flush_fp_to_thread(current
);
788 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
790 _exception(SIGFPE
, regs
, code
, regs
->nip
);
794 * Illegal instruction emulation support. Originally written to
795 * provide the PVR to user applications using the mfspr rd, PVR.
796 * Return non-zero if we can't emulate, or -EFAULT if the associated
797 * memory access caused an access fault. Return zero on success.
799 * There are a couple of ways to do this, either "decode" the instruction
800 * or directly match lots of bits. In this case, matching lots of
801 * bits is faster and easier.
804 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
806 u8 rT
= (instword
>> 21) & 0x1f;
807 u8 rA
= (instword
>> 16) & 0x1f;
808 u8 NB_RB
= (instword
>> 11) & 0x1f;
813 /* Early out if we are an invalid form of lswx */
814 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
815 if ((rT
== rA
) || (rT
== NB_RB
))
818 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
820 switch (instword
& PPC_INST_STRING_MASK
) {
824 num_bytes
= regs
->xer
& 0x7f;
828 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
834 while (num_bytes
!= 0)
837 u32 shift
= 8 * (3 - (pos
& 0x3));
839 switch ((instword
& PPC_INST_STRING_MASK
)) {
842 if (get_user(val
, (u8 __user
*)EA
))
844 /* first time updating this reg,
848 regs
->gpr
[rT
] |= val
<< shift
;
852 val
= regs
->gpr
[rT
] >> shift
;
853 if (put_user(val
, (u8 __user
*)EA
))
857 /* move EA to next address */
861 /* manage our position within the register */
872 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
877 ra
= (instword
>> 16) & 0x1f;
878 rs
= (instword
>> 21) & 0x1f;
881 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
882 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
883 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
889 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
891 u8 rT
= (instword
>> 21) & 0x1f;
892 u8 rA
= (instword
>> 16) & 0x1f;
893 u8 rB
= (instword
>> 11) & 0x1f;
894 u8 BC
= (instword
>> 6) & 0x1f;
898 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
899 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
901 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
906 static int emulate_instruction(struct pt_regs
*regs
)
911 if (!user_mode(regs
) || (regs
->msr
& MSR_LE
))
913 CHECK_FULL_REGS(regs
);
915 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
918 /* Emulate the mfspr rD, PVR. */
919 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
920 PPC_WARN_EMULATED(mfpvr
, regs
);
921 rd
= (instword
>> 21) & 0x1f;
922 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
926 /* Emulating the dcba insn is just a no-op. */
927 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
928 PPC_WARN_EMULATED(dcba
, regs
);
932 /* Emulate the mcrxr insn. */
933 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
934 int shift
= (instword
>> 21) & 0x1c;
935 unsigned long msk
= 0xf0000000UL
>> shift
;
937 PPC_WARN_EMULATED(mcrxr
, regs
);
938 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
939 regs
->xer
&= ~0xf0000000UL
;
943 /* Emulate load/store string insn. */
944 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
945 PPC_WARN_EMULATED(string
, regs
);
946 return emulate_string_inst(regs
, instword
);
949 /* Emulate the popcntb (Population Count Bytes) instruction. */
950 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
951 PPC_WARN_EMULATED(popcntb
, regs
);
952 return emulate_popcntb_inst(regs
, instword
);
955 /* Emulate isel (Integer Select) instruction */
956 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
957 PPC_WARN_EMULATED(isel
, regs
);
958 return emulate_isel(regs
, instword
);
962 /* Emulate the mfspr rD, DSCR. */
963 if (((instword
& PPC_INST_MFSPR_DSCR_MASK
) == PPC_INST_MFSPR_DSCR
) &&
964 cpu_has_feature(CPU_FTR_DSCR
)) {
965 PPC_WARN_EMULATED(mfdscr
, regs
);
966 rd
= (instword
>> 21) & 0x1f;
967 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
970 /* Emulate the mtspr DSCR, rD. */
971 if (((instword
& PPC_INST_MTSPR_DSCR_MASK
) == PPC_INST_MTSPR_DSCR
) &&
972 cpu_has_feature(CPU_FTR_DSCR
)) {
973 PPC_WARN_EMULATED(mtdscr
, regs
);
974 rd
= (instword
>> 21) & 0x1f;
975 mtspr(SPRN_DSCR
, regs
->gpr
[rd
]);
976 current
->thread
.dscr_inherit
= 1;
984 int is_valid_bugaddr(unsigned long addr
)
986 return is_kernel_addr(addr
);
989 void __kprobes
program_check_exception(struct pt_regs
*regs
)
991 unsigned int reason
= get_reason(regs
);
992 extern int do_mathemu(struct pt_regs
*regs
);
994 /* We can now get here via a FP Unavailable exception if the core
995 * has no FPU, in that case the reason flags will be 0 */
997 if (reason
& REASON_FP
) {
998 /* IEEE FP exception */
1002 if (reason
& REASON_TRAP
) {
1003 /* Debugger is first in line to stop recursive faults in
1004 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1005 if (debugger_bpt(regs
))
1008 /* trap exception */
1009 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1013 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1014 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1018 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1022 /* We restore the interrupt state now */
1023 if (!arch_irq_disabled_regs(regs
))
1026 #ifdef CONFIG_MATH_EMULATION
1027 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1028 * but there seems to be a hardware bug on the 405GP (RevD)
1029 * that means ESR is sometimes set incorrectly - either to
1030 * ESR_DST (!?) or 0. In the process of chasing this with the
1031 * hardware people - not sure if it can happen on any illegal
1032 * instruction or only on FP instructions, whether there is a
1033 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1034 switch (do_mathemu(regs
)) {
1036 emulate_single_step(regs
);
1040 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
1041 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1045 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1048 /* fall through on any other errors */
1049 #endif /* CONFIG_MATH_EMULATION */
1051 /* Try to emulate it if we should. */
1052 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1053 switch (emulate_instruction(regs
)) {
1056 emulate_single_step(regs
);
1059 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1064 if (reason
& REASON_PRIVILEGED
)
1065 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1067 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1070 void alignment_exception(struct pt_regs
*regs
)
1072 int sig
, code
, fixed
= 0;
1074 /* We restore the interrupt state now */
1075 if (!arch_irq_disabled_regs(regs
))
1078 /* we don't implement logging of alignment exceptions */
1079 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1080 fixed
= fix_alignment(regs
);
1083 regs
->nip
+= 4; /* skip over emulated instruction */
1084 emulate_single_step(regs
);
1088 /* Operand address was bad */
1089 if (fixed
== -EFAULT
) {
1096 if (user_mode(regs
))
1097 _exception(sig
, regs
, code
, regs
->dar
);
1099 bad_page_fault(regs
, regs
->dar
, sig
);
1102 void StackOverflow(struct pt_regs
*regs
)
1104 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1105 current
, regs
->gpr
[1]);
1108 panic("kernel stack overflow");
1111 void nonrecoverable_exception(struct pt_regs
*regs
)
1113 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1114 regs
->nip
, regs
->msr
);
1116 die("nonrecoverable exception", regs
, SIGKILL
);
1119 void trace_syscall(struct pt_regs
*regs
)
1121 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1122 current
, task_pid_nr(current
), regs
->nip
, regs
->link
, regs
->gpr
[0],
1123 regs
->ccr
&0x10000000?"Error=":"", regs
->gpr
[3], print_tainted());
1126 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1128 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1129 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1130 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1133 void altivec_unavailable_exception(struct pt_regs
*regs
)
1135 if (user_mode(regs
)) {
1136 /* A user program has executed an altivec instruction,
1137 but this kernel doesn't support altivec. */
1138 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1142 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1143 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1144 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1147 void vsx_unavailable_exception(struct pt_regs
*regs
)
1149 if (user_mode(regs
)) {
1150 /* A user program has executed an vsx instruction,
1151 but this kernel doesn't support vsx. */
1152 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1156 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1157 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1158 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1161 void performance_monitor_exception(struct pt_regs
*regs
)
1163 __get_cpu_var(irq_stat
).pmu_irqs
++;
1169 void SoftwareEmulation(struct pt_regs
*regs
)
1171 extern int do_mathemu(struct pt_regs
*);
1172 extern int Soft_emulate_8xx(struct pt_regs
*);
1173 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1177 CHECK_FULL_REGS(regs
);
1179 if (!user_mode(regs
)) {
1181 die("Kernel Mode Software FPU Emulation", regs
, SIGFPE
);
1184 #ifdef CONFIG_MATH_EMULATION
1185 errcode
= do_mathemu(regs
);
1187 PPC_WARN_EMULATED(math
, regs
);
1191 emulate_single_step(regs
);
1195 code
= __parse_fpscr(current
->thread
.fpscr
.val
);
1196 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1200 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1203 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1207 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1208 errcode
= Soft_emulate_8xx(regs
);
1210 PPC_WARN_EMULATED(8xx
, regs
);
1214 emulate_single_step(regs
);
1217 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1220 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1224 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1227 #endif /* CONFIG_8xx */
1229 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1230 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1234 * Determine the cause of the debug event, clear the
1235 * event flags and send a trap to the handler. Torez
1237 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1238 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1239 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1240 current
->thread
.dbcr2
&= ~DBCR2_DAC12MODE
;
1242 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1245 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1246 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1247 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1250 } else if (debug_status
& DBSR_IAC1
) {
1251 current
->thread
.dbcr0
&= ~DBCR0_IAC1
;
1252 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1253 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1256 } else if (debug_status
& DBSR_IAC2
) {
1257 current
->thread
.dbcr0
&= ~DBCR0_IAC2
;
1258 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1261 } else if (debug_status
& DBSR_IAC3
) {
1262 current
->thread
.dbcr0
&= ~DBCR0_IAC3
;
1263 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1264 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1267 } else if (debug_status
& DBSR_IAC4
) {
1268 current
->thread
.dbcr0
&= ~DBCR0_IAC4
;
1269 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1274 * At the point this routine was called, the MSR(DE) was turned off.
1275 * Check all other debug flags and see if that bit needs to be turned
1278 if (DBCR_ACTIVE_EVENTS(current
->thread
.dbcr0
, current
->thread
.dbcr1
))
1279 regs
->msr
|= MSR_DE
;
1281 /* Make sure the IDM flag is off */
1282 current
->thread
.dbcr0
&= ~DBCR0_IDM
;
1285 mtspr(SPRN_DBCR0
, current
->thread
.dbcr0
);
1288 void __kprobes
DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1290 current
->thread
.dbsr
= debug_status
;
1292 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1293 * on server, it stops on the target of the branch. In order to simulate
1294 * the server behaviour, we thus restart right away with a single step
1295 * instead of stopping here when hitting a BT
1297 if (debug_status
& DBSR_BT
) {
1298 regs
->msr
&= ~MSR_DE
;
1301 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1302 /* Clear the BT event */
1303 mtspr(SPRN_DBSR
, DBSR_BT
);
1305 /* Do the single step trick only when coming from userspace */
1306 if (user_mode(regs
)) {
1307 current
->thread
.dbcr0
&= ~DBCR0_BT
;
1308 current
->thread
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1309 regs
->msr
|= MSR_DE
;
1313 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1314 5, SIGTRAP
) == NOTIFY_STOP
) {
1317 if (debugger_sstep(regs
))
1319 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1320 regs
->msr
&= ~MSR_DE
;
1322 /* Disable instruction completion */
1323 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1324 /* Clear the instruction completion event */
1325 mtspr(SPRN_DBSR
, DBSR_IC
);
1327 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1328 5, SIGTRAP
) == NOTIFY_STOP
) {
1332 if (debugger_sstep(regs
))
1335 if (user_mode(regs
)) {
1336 current
->thread
.dbcr0
&= ~DBCR0_IC
;
1337 if (DBCR_ACTIVE_EVENTS(current
->thread
.dbcr0
,
1338 current
->thread
.dbcr1
))
1339 regs
->msr
|= MSR_DE
;
1341 /* Make sure the IDM bit is off */
1342 current
->thread
.dbcr0
&= ~DBCR0_IDM
;
1345 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1347 handle_debug(regs
, debug_status
);
1349 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1351 #if !defined(CONFIG_TAU_INT)
1352 void TAUException(struct pt_regs
*regs
)
1354 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1355 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1357 #endif /* CONFIG_INT_TAU */
1359 #ifdef CONFIG_ALTIVEC
1360 void altivec_assist_exception(struct pt_regs
*regs
)
1364 if (!user_mode(regs
)) {
1365 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1366 " at %lx\n", regs
->nip
);
1367 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1370 flush_altivec_to_thread(current
);
1372 PPC_WARN_EMULATED(altivec
, regs
);
1373 err
= emulate_altivec(regs
);
1375 regs
->nip
+= 4; /* skip emulated instruction */
1376 emulate_single_step(regs
);
1380 if (err
== -EFAULT
) {
1381 /* got an error reading the instruction */
1382 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1384 /* didn't recognize the instruction */
1385 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1386 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1387 "in %s at %lx\n", current
->comm
, regs
->nip
);
1388 current
->thread
.vscr
.u
[3] |= 0x10000;
1391 #endif /* CONFIG_ALTIVEC */
1394 void vsx_assist_exception(struct pt_regs
*regs
)
1396 if (!user_mode(regs
)) {
1397 printk(KERN_EMERG
"VSX assist exception in kernel mode"
1398 " at %lx\n", regs
->nip
);
1399 die("Kernel VSX assist exception", regs
, SIGILL
);
1402 flush_vsx_to_thread(current
);
1403 printk(KERN_INFO
"VSX assist not supported at %lx\n", regs
->nip
);
1404 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1406 #endif /* CONFIG_VSX */
1408 #ifdef CONFIG_FSL_BOOKE
1409 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1410 unsigned long error_code
)
1412 /* We treat cache locking instructions from the user
1413 * as priv ops, in the future we could try to do
1416 if (error_code
& (ESR_DLK
|ESR_ILK
))
1417 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1420 #endif /* CONFIG_FSL_BOOKE */
1423 void SPEFloatingPointException(struct pt_regs
*regs
)
1425 extern int do_spe_mathemu(struct pt_regs
*regs
);
1426 unsigned long spefscr
;
1431 flush_spe_to_thread(current
);
1433 spefscr
= current
->thread
.spefscr
;
1434 fpexc_mode
= current
->thread
.fpexc_mode
;
1436 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1439 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1442 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1444 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1447 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1450 err
= do_spe_mathemu(regs
);
1452 regs
->nip
+= 4; /* skip emulated instruction */
1453 emulate_single_step(regs
);
1457 if (err
== -EFAULT
) {
1458 /* got an error reading the instruction */
1459 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1460 } else if (err
== -EINVAL
) {
1461 /* didn't recognize the instruction */
1462 printk(KERN_ERR
"unrecognized spe instruction "
1463 "in %s at %lx\n", current
->comm
, regs
->nip
);
1465 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1471 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1473 extern int speround_handler(struct pt_regs
*regs
);
1477 if (regs
->msr
& MSR_SPE
)
1478 giveup_spe(current
);
1482 err
= speround_handler(regs
);
1484 regs
->nip
+= 4; /* skip emulated instruction */
1485 emulate_single_step(regs
);
1489 if (err
== -EFAULT
) {
1490 /* got an error reading the instruction */
1491 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1492 } else if (err
== -EINVAL
) {
1493 /* didn't recognize the instruction */
1494 printk(KERN_ERR
"unrecognized spe instruction "
1495 "in %s at %lx\n", current
->comm
, regs
->nip
);
1497 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1504 * We enter here if we get an unrecoverable exception, that is, one
1505 * that happened at a point where the RI (recoverable interrupt) bit
1506 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1507 * we therefore lost state by taking this exception.
1509 void unrecoverable_exception(struct pt_regs
*regs
)
1511 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1512 regs
->trap
, regs
->nip
);
1513 die("Unrecoverable exception", regs
, SIGABRT
);
1516 #ifdef CONFIG_BOOKE_WDT
1518 * Default handler for a Watchdog exception,
1519 * spins until a reboot occurs
1521 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1523 /* Generic WatchdogHandler, implement your own */
1524 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1528 void WatchdogException(struct pt_regs
*regs
)
1530 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1531 WatchdogHandler(regs
);
1536 * We enter here if we discover during exception entry that we are
1537 * running in supervisor mode with a userspace value in the stack pointer.
1539 void kernel_bad_stack(struct pt_regs
*regs
)
1541 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1542 regs
->gpr
[1], regs
->nip
);
1543 die("Bad kernel stack pointer", regs
, SIGABRT
);
1546 void __init
trap_init(void)
1551 #ifdef CONFIG_PPC_EMULATED_STATS
1553 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1555 struct ppc_emulated ppc_emulated
= {
1556 #ifdef CONFIG_ALTIVEC
1557 WARN_EMULATED_SETUP(altivec
),
1559 WARN_EMULATED_SETUP(dcba
),
1560 WARN_EMULATED_SETUP(dcbz
),
1561 WARN_EMULATED_SETUP(fp_pair
),
1562 WARN_EMULATED_SETUP(isel
),
1563 WARN_EMULATED_SETUP(mcrxr
),
1564 WARN_EMULATED_SETUP(mfpvr
),
1565 WARN_EMULATED_SETUP(multiple
),
1566 WARN_EMULATED_SETUP(popcntb
),
1567 WARN_EMULATED_SETUP(spe
),
1568 WARN_EMULATED_SETUP(string
),
1569 WARN_EMULATED_SETUP(unaligned
),
1570 #ifdef CONFIG_MATH_EMULATION
1571 WARN_EMULATED_SETUP(math
),
1572 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1573 WARN_EMULATED_SETUP(8xx
),
1576 WARN_EMULATED_SETUP(vsx
),
1579 WARN_EMULATED_SETUP(mfdscr
),
1580 WARN_EMULATED_SETUP(mtdscr
),
1584 u32 ppc_warn_emulated
;
1586 void ppc_warn_emulated_print(const char *type
)
1588 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
1592 static int __init
ppc_warn_emulated_init(void)
1594 struct dentry
*dir
, *d
;
1596 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
1598 if (!powerpc_debugfs_root
)
1601 dir
= debugfs_create_dir("emulated_instructions",
1602 powerpc_debugfs_root
);
1606 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
1607 &ppc_warn_emulated
);
1611 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
1612 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
1613 (u32
*)&entries
[i
].val
.counter
);
1621 debugfs_remove_recursive(dir
);
1625 device_initcall(ppc_warn_emulated_init
);
1627 #endif /* CONFIG_PPC_EMULATED_STATS */