4 * High-speed serial driver for NVIDIA Tegra SoCs
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/serial_core.h>
40 #include <linux/serial_reg.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/termios.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
47 #include <linux/clk/tegra.h>
49 #define TEGRA_UART_TYPE "TEGRA_UART"
50 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
51 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
53 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
54 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
55 #define TEGRA_UART_IER_EORD 0x20
56 #define TEGRA_UART_MCR_RTS_EN 0x40
57 #define TEGRA_UART_MCR_CTS_EN 0x20
58 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
59 UART_LSR_PE | UART_LSR_FE)
60 #define TEGRA_UART_IRDA_CSR 0x08
61 #define TEGRA_UART_SIR_ENABLED 0x80
63 #define TEGRA_UART_TX_PIO 1
64 #define TEGRA_UART_TX_DMA 2
65 #define TEGRA_UART_MIN_DMA 16
66 #define TEGRA_UART_FIFO_SIZE 32
69 * Tx fifo trigger level setting in tegra uart is in
70 * reverse way then conventional uart.
72 #define TEGRA_UART_TX_TRIG_16B 0x00
73 #define TEGRA_UART_TX_TRIG_8B 0x10
74 #define TEGRA_UART_TX_TRIG_4B 0x20
75 #define TEGRA_UART_TX_TRIG_1B 0x30
77 #define TEGRA_UART_MAXIMUM 5
79 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
80 #define TEGRA_UART_DEFAULT_BAUD 115200
81 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
83 /* Tx transfer mode */
84 #define TEGRA_TX_PIO 1
85 #define TEGRA_TX_DMA 2
88 * tegra_uart_chip_data: SOC specific data.
90 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
91 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
92 * Tegra30 does not allow this.
93 * @support_clk_src_div: Clock source support the clock divider.
95 struct tegra_uart_chip_data
{
96 bool tx_fifo_full_status
;
97 bool allow_txfifo_reset_fifo_mode
;
98 bool support_clk_src_div
;
101 struct tegra_uart_port
{
102 struct uart_port uport
;
103 const struct tegra_uart_chip_data
*cdata
;
105 struct clk
*uart_clk
;
106 unsigned int current_baud
;
108 /* Register shadow */
109 unsigned long fcr_shadow
;
110 unsigned long mcr_shadow
;
111 unsigned long lcr_shadow
;
112 unsigned long ier_shadow
;
116 unsigned int tx_bytes
;
118 bool enable_modem_interrupt
;
125 struct dma_chan
*rx_dma_chan
;
126 struct dma_chan
*tx_dma_chan
;
127 dma_addr_t rx_dma_buf_phys
;
128 dma_addr_t tx_dma_buf_phys
;
129 unsigned char *rx_dma_buf_virt
;
130 unsigned char *tx_dma_buf_virt
;
131 struct dma_async_tx_descriptor
*tx_dma_desc
;
132 struct dma_async_tx_descriptor
*rx_dma_desc
;
133 dma_cookie_t tx_cookie
;
134 dma_cookie_t rx_cookie
;
135 int tx_bytes_requested
;
136 int rx_bytes_requested
;
139 static void tegra_uart_start_next_tx(struct tegra_uart_port
*tup
);
140 static int tegra_uart_start_rx_dma(struct tegra_uart_port
*tup
);
142 static inline unsigned long tegra_uart_read(struct tegra_uart_port
*tup
,
145 return readl(tup
->uport
.membase
+ (reg
<< tup
->uport
.regshift
));
148 static inline void tegra_uart_write(struct tegra_uart_port
*tup
, unsigned val
,
151 writel(val
, tup
->uport
.membase
+ (reg
<< tup
->uport
.regshift
));
154 static inline struct tegra_uart_port
*to_tegra_uport(struct uart_port
*u
)
156 return container_of(u
, struct tegra_uart_port
, uport
);
159 static unsigned int tegra_uart_get_mctrl(struct uart_port
*u
)
161 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
164 * RI - Ring detector is active
165 * CD/DCD/CAR - Carrier detect is always active. For some reason
166 * linux has different names for carrier detect.
167 * DSR - Data Set ready is active as the hardware doesn't support it.
168 * Don't know if the linux support this yet?
169 * CTS - Clear to send. Always set to active, as the hardware handles
172 if (tup
->enable_modem_interrupt
)
173 return TIOCM_RI
| TIOCM_CD
| TIOCM_DSR
| TIOCM_CTS
;
177 static void set_rts(struct tegra_uart_port
*tup
, bool active
)
181 mcr
= tup
->mcr_shadow
;
183 mcr
|= TEGRA_UART_MCR_RTS_EN
;
185 mcr
&= ~TEGRA_UART_MCR_RTS_EN
;
186 if (mcr
!= tup
->mcr_shadow
) {
187 tegra_uart_write(tup
, mcr
, UART_MCR
);
188 tup
->mcr_shadow
= mcr
;
193 static void set_dtr(struct tegra_uart_port
*tup
, bool active
)
197 mcr
= tup
->mcr_shadow
;
201 mcr
&= ~UART_MCR_DTR
;
202 if (mcr
!= tup
->mcr_shadow
) {
203 tegra_uart_write(tup
, mcr
, UART_MCR
);
204 tup
->mcr_shadow
= mcr
;
209 static void tegra_uart_set_mctrl(struct uart_port
*u
, unsigned int mctrl
)
211 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
215 mcr
= tup
->mcr_shadow
;
216 tup
->rts_active
= !!(mctrl
& TIOCM_RTS
);
217 set_rts(tup
, tup
->rts_active
);
219 dtr_enable
= !!(mctrl
& TIOCM_DTR
);
220 set_dtr(tup
, dtr_enable
);
224 static void tegra_uart_break_ctl(struct uart_port
*u
, int break_ctl
)
226 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
229 lcr
= tup
->lcr_shadow
;
233 lcr
&= ~UART_LCR_SBC
;
234 tegra_uart_write(tup
, lcr
, UART_LCR
);
235 tup
->lcr_shadow
= lcr
;
238 /* Wait for a symbol-time. */
239 static void tegra_uart_wait_sym_time(struct tegra_uart_port
*tup
,
242 if (tup
->current_baud
)
243 udelay(DIV_ROUND_UP(syms
* tup
->symb_bit
* 1000000,
247 static void tegra_uart_fifo_reset(struct tegra_uart_port
*tup
, u8 fcr_bits
)
249 unsigned long fcr
= tup
->fcr_shadow
;
251 if (tup
->cdata
->allow_txfifo_reset_fifo_mode
) {
252 fcr
|= fcr_bits
& (UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
253 tegra_uart_write(tup
, fcr
, UART_FCR
);
255 fcr
&= ~UART_FCR_ENABLE_FIFO
;
256 tegra_uart_write(tup
, fcr
, UART_FCR
);
258 fcr
|= fcr_bits
& (UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
259 tegra_uart_write(tup
, fcr
, UART_FCR
);
260 fcr
|= UART_FCR_ENABLE_FIFO
;
261 tegra_uart_write(tup
, fcr
, UART_FCR
);
264 /* Dummy read to ensure the write is posted */
265 tegra_uart_read(tup
, UART_SCR
);
267 /* Wait for the flush to propagate. */
268 tegra_uart_wait_sym_time(tup
, 1);
271 static int tegra_set_baudrate(struct tegra_uart_port
*tup
, unsigned int baud
)
274 unsigned int divisor
;
278 if (tup
->current_baud
== baud
)
281 if (tup
->cdata
->support_clk_src_div
) {
283 ret
= clk_set_rate(tup
->uart_clk
, rate
);
285 dev_err(tup
->uport
.dev
,
286 "clk_set_rate() failed for rate %lu\n", rate
);
291 rate
= clk_get_rate(tup
->uart_clk
);
292 divisor
= DIV_ROUND_CLOSEST(rate
, baud
* 16);
295 lcr
= tup
->lcr_shadow
;
296 lcr
|= UART_LCR_DLAB
;
297 tegra_uart_write(tup
, lcr
, UART_LCR
);
299 tegra_uart_write(tup
, divisor
& 0xFF, UART_TX
);
300 tegra_uart_write(tup
, ((divisor
>> 8) & 0xFF), UART_IER
);
302 lcr
&= ~UART_LCR_DLAB
;
303 tegra_uart_write(tup
, lcr
, UART_LCR
);
305 /* Dummy read to ensure the write is posted */
306 tegra_uart_read(tup
, UART_SCR
);
308 tup
->current_baud
= baud
;
310 /* wait two character intervals at new rate */
311 tegra_uart_wait_sym_time(tup
, 2);
315 static char tegra_uart_decode_rx_error(struct tegra_uart_port
*tup
,
318 char flag
= TTY_NORMAL
;
320 if (unlikely(lsr
& TEGRA_UART_LSR_ANY
)) {
321 if (lsr
& UART_LSR_OE
) {
324 tup
->uport
.icount
.overrun
++;
325 dev_err(tup
->uport
.dev
, "Got overrun errors\n");
326 } else if (lsr
& UART_LSR_PE
) {
329 tup
->uport
.icount
.parity
++;
330 dev_err(tup
->uport
.dev
, "Got Parity errors\n");
331 } else if (lsr
& UART_LSR_FE
) {
333 tup
->uport
.icount
.frame
++;
334 dev_err(tup
->uport
.dev
, "Got frame errors\n");
335 } else if (lsr
& UART_LSR_BI
) {
336 dev_err(tup
->uport
.dev
, "Got Break\n");
337 tup
->uport
.icount
.brk
++;
338 /* If FIFO read error without any data, reset Rx FIFO */
339 if (!(lsr
& UART_LSR_DR
) && (lsr
& UART_LSR_FIFOE
))
340 tegra_uart_fifo_reset(tup
, UART_FCR_CLEAR_RCVR
);
346 static int tegra_uart_request_port(struct uart_port
*u
)
351 static void tegra_uart_release_port(struct uart_port
*u
)
353 /* Nothing to do here */
356 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port
*tup
, int max_bytes
)
358 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
361 for (i
= 0; i
< max_bytes
; i
++) {
362 BUG_ON(uart_circ_empty(xmit
));
363 if (tup
->cdata
->tx_fifo_full_status
) {
364 unsigned long lsr
= tegra_uart_read(tup
, UART_LSR
);
365 if ((lsr
& TEGRA_UART_LSR_TXFIFO_FULL
))
368 tegra_uart_write(tup
, xmit
->buf
[xmit
->tail
], UART_TX
);
369 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
370 tup
->uport
.icount
.tx
++;
374 static void tegra_uart_start_pio_tx(struct tegra_uart_port
*tup
,
377 if (bytes
> TEGRA_UART_MIN_DMA
)
378 bytes
= TEGRA_UART_MIN_DMA
;
380 tup
->tx_in_progress
= TEGRA_UART_TX_PIO
;
381 tup
->tx_bytes
= bytes
;
382 tup
->ier_shadow
|= UART_IER_THRI
;
383 tegra_uart_write(tup
, tup
->ier_shadow
, UART_IER
);
386 static void tegra_uart_tx_dma_complete(void *args
)
388 struct tegra_uart_port
*tup
= args
;
389 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
390 struct dma_tx_state state
;
394 dmaengine_tx_status(tup
->tx_dma_chan
, tup
->rx_cookie
, &state
);
395 count
= tup
->tx_bytes_requested
- state
.residue
;
396 async_tx_ack(tup
->tx_dma_desc
);
397 spin_lock_irqsave(&tup
->uport
.lock
, flags
);
398 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
399 tup
->tx_in_progress
= 0;
400 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
401 uart_write_wakeup(&tup
->uport
);
402 tegra_uart_start_next_tx(tup
);
403 spin_unlock_irqrestore(&tup
->uport
.lock
, flags
);
406 static int tegra_uart_start_tx_dma(struct tegra_uart_port
*tup
,
409 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
410 dma_addr_t tx_phys_addr
;
412 dma_sync_single_for_device(tup
->uport
.dev
, tup
->tx_dma_buf_phys
,
413 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
415 tup
->tx_bytes
= count
& ~(0xF);
416 tx_phys_addr
= tup
->tx_dma_buf_phys
+ xmit
->tail
;
417 tup
->tx_dma_desc
= dmaengine_prep_slave_single(tup
->tx_dma_chan
,
418 tx_phys_addr
, tup
->tx_bytes
, DMA_MEM_TO_DEV
,
420 if (!tup
->tx_dma_desc
) {
421 dev_err(tup
->uport
.dev
, "Not able to get desc for Tx\n");
425 tup
->tx_dma_desc
->callback
= tegra_uart_tx_dma_complete
;
426 tup
->tx_dma_desc
->callback_param
= tup
;
427 tup
->tx_in_progress
= TEGRA_UART_TX_DMA
;
428 tup
->tx_bytes_requested
= tup
->tx_bytes
;
429 tup
->tx_cookie
= dmaengine_submit(tup
->tx_dma_desc
);
430 dma_async_issue_pending(tup
->tx_dma_chan
);
434 static void tegra_uart_start_next_tx(struct tegra_uart_port
*tup
)
438 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
440 tail
= (unsigned long)&xmit
->buf
[xmit
->tail
];
441 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
445 if (count
< TEGRA_UART_MIN_DMA
)
446 tegra_uart_start_pio_tx(tup
, count
);
447 else if (BYTES_TO_ALIGN(tail
) > 0)
448 tegra_uart_start_pio_tx(tup
, BYTES_TO_ALIGN(tail
));
450 tegra_uart_start_tx_dma(tup
, count
);
453 /* Called by serial core driver with u->lock taken. */
454 static void tegra_uart_start_tx(struct uart_port
*u
)
456 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
457 struct circ_buf
*xmit
= &u
->state
->xmit
;
459 if (!uart_circ_empty(xmit
) && !tup
->tx_in_progress
)
460 tegra_uart_start_next_tx(tup
);
463 static unsigned int tegra_uart_tx_empty(struct uart_port
*u
)
465 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
466 unsigned int ret
= 0;
469 spin_lock_irqsave(&u
->lock
, flags
);
470 if (!tup
->tx_in_progress
) {
471 unsigned long lsr
= tegra_uart_read(tup
, UART_LSR
);
472 if ((lsr
& TX_EMPTY_STATUS
) == TX_EMPTY_STATUS
)
475 spin_unlock_irqrestore(&u
->lock
, flags
);
479 static void tegra_uart_stop_tx(struct uart_port
*u
)
481 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
482 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
483 struct dma_tx_state state
;
486 dmaengine_terminate_all(tup
->tx_dma_chan
);
487 dmaengine_tx_status(tup
->tx_dma_chan
, tup
->tx_cookie
, &state
);
488 count
= tup
->tx_bytes_requested
- state
.residue
;
489 async_tx_ack(tup
->tx_dma_desc
);
490 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
491 tup
->tx_in_progress
= 0;
495 static void tegra_uart_handle_tx_pio(struct tegra_uart_port
*tup
)
497 struct circ_buf
*xmit
= &tup
->uport
.state
->xmit
;
499 tegra_uart_fill_tx_fifo(tup
, tup
->tx_bytes
);
500 tup
->tx_in_progress
= 0;
501 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
502 uart_write_wakeup(&tup
->uport
);
503 tegra_uart_start_next_tx(tup
);
507 static void tegra_uart_handle_rx_pio(struct tegra_uart_port
*tup
,
508 struct tty_port
*tty
)
511 char flag
= TTY_NORMAL
;
512 unsigned long lsr
= 0;
515 lsr
= tegra_uart_read(tup
, UART_LSR
);
516 if (!(lsr
& UART_LSR_DR
))
519 flag
= tegra_uart_decode_rx_error(tup
, lsr
);
520 ch
= (unsigned char) tegra_uart_read(tup
, UART_RX
);
521 tup
->uport
.icount
.rx
++;
523 if (!uart_handle_sysrq_char(&tup
->uport
, ch
) && tty
)
524 tty_insert_flip_char(tty
, ch
, flag
);
530 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port
*tup
,
531 struct tty_port
*tty
, int count
)
535 tup
->uport
.icount
.rx
+= count
;
537 dev_err(tup
->uport
.dev
, "No tty port\n");
540 dma_sync_single_for_cpu(tup
->uport
.dev
, tup
->rx_dma_buf_phys
,
541 TEGRA_UART_RX_DMA_BUFFER_SIZE
, DMA_FROM_DEVICE
);
542 copied
= tty_insert_flip_string(tty
,
543 ((unsigned char *)(tup
->rx_dma_buf_virt
)), count
);
544 if (copied
!= count
) {
546 dev_err(tup
->uport
.dev
, "RxData copy to tty layer failed\n");
548 dma_sync_single_for_device(tup
->uport
.dev
, tup
->rx_dma_buf_phys
,
549 TEGRA_UART_RX_DMA_BUFFER_SIZE
, DMA_TO_DEVICE
);
552 static void tegra_uart_rx_dma_complete(void *args
)
554 struct tegra_uart_port
*tup
= args
;
555 struct uart_port
*u
= &tup
->uport
;
556 int count
= tup
->rx_bytes_requested
;
557 struct tty_struct
*tty
= tty_port_tty_get(&tup
->uport
.state
->port
);
558 struct tty_port
*port
= &u
->state
->port
;
561 async_tx_ack(tup
->rx_dma_desc
);
562 spin_lock_irqsave(&u
->lock
, flags
);
564 /* Deactivate flow control to stop sender */
568 /* If we are here, DMA is stopped */
570 tegra_uart_copy_rx_to_tty(tup
, port
, count
);
572 tegra_uart_handle_rx_pio(tup
, port
);
574 spin_unlock_irqrestore(&u
->lock
, flags
);
575 tty_flip_buffer_push(port
);
576 spin_lock_irqsave(&u
->lock
, flags
);
579 tegra_uart_start_rx_dma(tup
);
581 /* Activate flow control to start transfer */
585 spin_unlock_irqrestore(&u
->lock
, flags
);
588 static void tegra_uart_handle_rx_dma(struct tegra_uart_port
*tup
,
589 unsigned long *flags
)
591 struct dma_tx_state state
;
592 struct tty_struct
*tty
= tty_port_tty_get(&tup
->uport
.state
->port
);
593 struct tty_port
*port
= &tup
->uport
.state
->port
;
594 struct uart_port
*u
= &tup
->uport
;
597 /* Deactivate flow control to stop sender */
601 dmaengine_terminate_all(tup
->rx_dma_chan
);
602 dmaengine_tx_status(tup
->rx_dma_chan
, tup
->rx_cookie
, &state
);
603 count
= tup
->rx_bytes_requested
- state
.residue
;
605 /* If we are here, DMA is stopped */
607 tegra_uart_copy_rx_to_tty(tup
, port
, count
);
609 tegra_uart_handle_rx_pio(tup
, port
);
611 spin_unlock_irqrestore(&u
->lock
, *flags
);
612 tty_flip_buffer_push(port
);
613 spin_lock_irqsave(&u
->lock
, *flags
);
616 tegra_uart_start_rx_dma(tup
);
622 static int tegra_uart_start_rx_dma(struct tegra_uart_port
*tup
)
624 unsigned int count
= TEGRA_UART_RX_DMA_BUFFER_SIZE
;
626 tup
->rx_dma_desc
= dmaengine_prep_slave_single(tup
->rx_dma_chan
,
627 tup
->rx_dma_buf_phys
, count
, DMA_DEV_TO_MEM
,
629 if (!tup
->rx_dma_desc
) {
630 dev_err(tup
->uport
.dev
, "Not able to get desc for Rx\n");
634 tup
->rx_dma_desc
->callback
= tegra_uart_rx_dma_complete
;
635 tup
->rx_dma_desc
->callback_param
= tup
;
636 dma_sync_single_for_device(tup
->uport
.dev
, tup
->rx_dma_buf_phys
,
637 count
, DMA_TO_DEVICE
);
638 tup
->rx_bytes_requested
= count
;
639 tup
->rx_cookie
= dmaengine_submit(tup
->rx_dma_desc
);
640 dma_async_issue_pending(tup
->rx_dma_chan
);
644 static void tegra_uart_handle_modem_signal_change(struct uart_port
*u
)
646 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
649 msr
= tegra_uart_read(tup
, UART_MSR
);
650 if (!(msr
& UART_MSR_ANY_DELTA
))
653 if (msr
& UART_MSR_TERI
)
654 tup
->uport
.icount
.rng
++;
655 if (msr
& UART_MSR_DDSR
)
656 tup
->uport
.icount
.dsr
++;
657 /* We may only get DDCD when HW init and reset */
658 if (msr
& UART_MSR_DDCD
)
659 uart_handle_dcd_change(&tup
->uport
, msr
& UART_MSR_DCD
);
660 /* Will start/stop_tx accordingly */
661 if (msr
& UART_MSR_DCTS
)
662 uart_handle_cts_change(&tup
->uport
, msr
& UART_MSR_CTS
);
666 static irqreturn_t
tegra_uart_isr(int irq
, void *data
)
668 struct tegra_uart_port
*tup
= data
;
669 struct uart_port
*u
= &tup
->uport
;
672 bool is_rx_int
= false;
675 spin_lock_irqsave(&u
->lock
, flags
);
677 iir
= tegra_uart_read(tup
, UART_IIR
);
678 if (iir
& UART_IIR_NO_INT
) {
680 tegra_uart_handle_rx_dma(tup
, &flags
);
681 if (tup
->rx_in_progress
) {
682 ier
= tup
->ier_shadow
;
683 ier
|= (UART_IER_RLSI
| UART_IER_RTOIE
|
684 TEGRA_UART_IER_EORD
);
685 tup
->ier_shadow
= ier
;
686 tegra_uart_write(tup
, ier
, UART_IER
);
689 spin_unlock_irqrestore(&u
->lock
, flags
);
693 switch ((iir
>> 1) & 0x7) {
694 case 0: /* Modem signal change interrupt */
695 tegra_uart_handle_modem_signal_change(u
);
698 case 1: /* Transmit interrupt only triggered when using PIO */
699 tup
->ier_shadow
&= ~UART_IER_THRI
;
700 tegra_uart_write(tup
, tup
->ier_shadow
, UART_IER
);
701 tegra_uart_handle_tx_pio(tup
);
704 case 4: /* End of data */
705 case 6: /* Rx timeout */
706 case 2: /* Receive */
709 /* Disable Rx interrupts */
710 ier
= tup
->ier_shadow
;
712 tegra_uart_write(tup
, ier
, UART_IER
);
713 ier
&= ~(UART_IER_RDI
| UART_IER_RLSI
|
714 UART_IER_RTOIE
| TEGRA_UART_IER_EORD
);
715 tup
->ier_shadow
= ier
;
716 tegra_uart_write(tup
, ier
, UART_IER
);
720 case 3: /* Receive error */
721 tegra_uart_decode_rx_error(tup
,
722 tegra_uart_read(tup
, UART_LSR
));
725 case 5: /* break nothing to handle */
726 case 7: /* break nothing to handle */
732 static void tegra_uart_stop_rx(struct uart_port
*u
)
734 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
735 struct tty_struct
*tty
;
736 struct tty_port
*port
= &u
->state
->port
;
737 struct dma_tx_state state
;
744 if (!tup
->rx_in_progress
)
747 tty
= tty_port_tty_get(&tup
->uport
.state
->port
);
749 tegra_uart_wait_sym_time(tup
, 1); /* wait a character interval */
751 ier
= tup
->ier_shadow
;
752 ier
&= ~(UART_IER_RDI
| UART_IER_RLSI
| UART_IER_RTOIE
|
753 TEGRA_UART_IER_EORD
);
754 tup
->ier_shadow
= ier
;
755 tegra_uart_write(tup
, ier
, UART_IER
);
756 tup
->rx_in_progress
= 0;
757 if (tup
->rx_dma_chan
) {
758 dmaengine_terminate_all(tup
->rx_dma_chan
);
759 dmaengine_tx_status(tup
->rx_dma_chan
, tup
->rx_cookie
, &state
);
760 async_tx_ack(tup
->rx_dma_desc
);
761 count
= tup
->rx_bytes_requested
- state
.residue
;
762 tegra_uart_copy_rx_to_tty(tup
, port
, count
);
763 tegra_uart_handle_rx_pio(tup
, port
);
765 tegra_uart_handle_rx_pio(tup
, port
);
768 tty_flip_buffer_push(port
);
774 static void tegra_uart_hw_deinit(struct tegra_uart_port
*tup
)
777 unsigned long char_time
= DIV_ROUND_UP(10000000, tup
->current_baud
);
778 unsigned long fifo_empty_time
= tup
->uport
.fifosize
* char_time
;
779 unsigned long wait_time
;
784 /* Disable interrupts */
785 tegra_uart_write(tup
, 0, UART_IER
);
787 lsr
= tegra_uart_read(tup
, UART_LSR
);
788 if ((lsr
& UART_LSR_TEMT
) != UART_LSR_TEMT
) {
789 msr
= tegra_uart_read(tup
, UART_MSR
);
790 mcr
= tegra_uart_read(tup
, UART_MCR
);
791 if ((mcr
& TEGRA_UART_MCR_CTS_EN
) && (msr
& UART_MSR_CTS
))
792 dev_err(tup
->uport
.dev
,
793 "Tx Fifo not empty, CTS disabled, waiting\n");
795 /* Wait for Tx fifo to be empty */
796 while ((lsr
& UART_LSR_TEMT
) != UART_LSR_TEMT
) {
797 wait_time
= min(fifo_empty_time
, 100lu);
799 fifo_empty_time
-= wait_time
;
800 if (!fifo_empty_time
) {
801 msr
= tegra_uart_read(tup
, UART_MSR
);
802 mcr
= tegra_uart_read(tup
, UART_MCR
);
803 if ((mcr
& TEGRA_UART_MCR_CTS_EN
) &&
804 (msr
& UART_MSR_CTS
))
805 dev_err(tup
->uport
.dev
,
806 "Slave not ready\n");
809 lsr
= tegra_uart_read(tup
, UART_LSR
);
813 spin_lock_irqsave(&tup
->uport
.lock
, flags
);
814 /* Reset the Rx and Tx FIFOs */
815 tegra_uart_fifo_reset(tup
, UART_FCR_CLEAR_XMIT
| UART_FCR_CLEAR_RCVR
);
816 tup
->current_baud
= 0;
817 spin_unlock_irqrestore(&tup
->uport
.lock
, flags
);
819 clk_disable_unprepare(tup
->uart_clk
);
822 static int tegra_uart_hw_init(struct tegra_uart_port
*tup
)
830 tup
->current_baud
= 0;
832 clk_prepare_enable(tup
->uart_clk
);
834 /* Reset the UART controller to clear all previous status.*/
835 tegra_periph_reset_assert(tup
->uart_clk
);
837 tegra_periph_reset_deassert(tup
->uart_clk
);
839 tup
->rx_in_progress
= 0;
840 tup
->tx_in_progress
= 0;
843 * Set the trigger level
847 * For receive, this will interrupt the CPU after that many number of
848 * bytes are received, for the remaining bytes the receive timeout
849 * interrupt is received. Rx high watermark is set to 4.
851 * For transmit, if the trasnmit interrupt is enabled, this will
852 * interrupt the CPU when the number of entries in the FIFO reaches the
853 * low watermark. Tx low watermark is set to 16 bytes.
857 * Set the Tx trigger to 16. This should match the DMA burst size that
858 * programmed in the DMA registers.
860 tup
->fcr_shadow
= UART_FCR_ENABLE_FIFO
;
861 tup
->fcr_shadow
|= UART_FCR_R_TRIG_01
;
862 tup
->fcr_shadow
|= TEGRA_UART_TX_TRIG_16B
;
863 tegra_uart_write(tup
, tup
->fcr_shadow
, UART_FCR
);
866 * Initialize the UART with default configuration
867 * (115200, N, 8, 1) so that the receive DMA buffer may be
870 tup
->lcr_shadow
= TEGRA_UART_DEFAULT_LSR
;
871 tegra_set_baudrate(tup
, TEGRA_UART_DEFAULT_BAUD
);
872 tup
->fcr_shadow
|= UART_FCR_DMA_SELECT
;
873 tegra_uart_write(tup
, tup
->fcr_shadow
, UART_FCR
);
875 ret
= tegra_uart_start_rx_dma(tup
);
877 dev_err(tup
->uport
.dev
, "Not able to start Rx DMA\n");
880 tup
->rx_in_progress
= 1;
883 * Enable IE_RXS for the receive status interrupts like line errros.
884 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
886 * If using DMA mode, enable EORD instead of receive interrupt which
887 * will interrupt after the UART is done with the receive instead of
888 * the interrupt when the FIFO "threshold" is reached.
890 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
891 * the DATA is sitting in the FIFO and couldn't be transferred to the
892 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
893 * triggered when there is a pause of the incomming data stream for 4
896 * For pauses in the data which is not aligned to 4 bytes, we get
897 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
900 tup
->ier_shadow
= UART_IER_RLSI
| UART_IER_RTOIE
| TEGRA_UART_IER_EORD
;
901 tegra_uart_write(tup
, tup
->ier_shadow
, UART_IER
);
905 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port
*tup
,
908 struct dma_chan
*dma_chan
;
909 unsigned char *dma_buf
;
912 struct dma_slave_config dma_sconfig
;
916 dma_cap_set(DMA_SLAVE
, mask
);
917 dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
919 dev_err(tup
->uport
.dev
,
920 "Dma channel is not available, will try later\n");
921 return -EPROBE_DEFER
;
925 dma_buf
= dma_alloc_coherent(tup
->uport
.dev
,
926 TEGRA_UART_RX_DMA_BUFFER_SIZE
,
927 &dma_phys
, GFP_KERNEL
);
929 dev_err(tup
->uport
.dev
,
930 "Not able to allocate the dma buffer\n");
931 dma_release_channel(dma_chan
);
935 dma_phys
= dma_map_single(tup
->uport
.dev
,
936 tup
->uport
.state
->xmit
.buf
, UART_XMIT_SIZE
,
938 dma_buf
= tup
->uport
.state
->xmit
.buf
;
941 dma_sconfig
.slave_id
= tup
->dma_req_sel
;
943 dma_sconfig
.src_addr
= tup
->uport
.mapbase
;
944 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
945 dma_sconfig
.src_maxburst
= 4;
947 dma_sconfig
.dst_addr
= tup
->uport
.mapbase
;
948 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
949 dma_sconfig
.dst_maxburst
= 16;
952 ret
= dmaengine_slave_config(dma_chan
, &dma_sconfig
);
954 dev_err(tup
->uport
.dev
,
955 "Dma slave config failed, err = %d\n", ret
);
960 tup
->rx_dma_chan
= dma_chan
;
961 tup
->rx_dma_buf_virt
= dma_buf
;
962 tup
->rx_dma_buf_phys
= dma_phys
;
964 tup
->tx_dma_chan
= dma_chan
;
965 tup
->tx_dma_buf_virt
= dma_buf
;
966 tup
->tx_dma_buf_phys
= dma_phys
;
971 dma_release_channel(dma_chan
);
975 static void tegra_uart_dma_channel_free(struct tegra_uart_port
*tup
,
978 struct dma_chan
*dma_chan
;
981 dma_free_coherent(tup
->uport
.dev
, TEGRA_UART_RX_DMA_BUFFER_SIZE
,
982 tup
->rx_dma_buf_virt
, tup
->rx_dma_buf_phys
);
983 dma_chan
= tup
->rx_dma_chan
;
984 tup
->rx_dma_chan
= NULL
;
985 tup
->rx_dma_buf_phys
= 0;
986 tup
->rx_dma_buf_virt
= NULL
;
988 dma_unmap_single(tup
->uport
.dev
, tup
->tx_dma_buf_phys
,
989 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
990 dma_chan
= tup
->tx_dma_chan
;
991 tup
->tx_dma_chan
= NULL
;
992 tup
->tx_dma_buf_phys
= 0;
993 tup
->tx_dma_buf_virt
= NULL
;
995 dma_release_channel(dma_chan
);
998 static int tegra_uart_startup(struct uart_port
*u
)
1000 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
1003 ret
= tegra_uart_dma_channel_allocate(tup
, false);
1005 dev_err(u
->dev
, "Tx Dma allocation failed, err = %d\n", ret
);
1009 ret
= tegra_uart_dma_channel_allocate(tup
, true);
1011 dev_err(u
->dev
, "Rx Dma allocation failed, err = %d\n", ret
);
1015 ret
= tegra_uart_hw_init(tup
);
1017 dev_err(u
->dev
, "Uart HW init failed, err = %d\n", ret
);
1021 ret
= request_irq(u
->irq
, tegra_uart_isr
, 0,
1022 dev_name(u
->dev
), tup
);
1024 dev_err(u
->dev
, "Failed to register ISR for IRQ %d\n", u
->irq
);
1030 tegra_uart_dma_channel_free(tup
, true);
1032 tegra_uart_dma_channel_free(tup
, false);
1036 static void tegra_uart_shutdown(struct uart_port
*u
)
1038 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
1040 tegra_uart_hw_deinit(tup
);
1042 tup
->rx_in_progress
= 0;
1043 tup
->tx_in_progress
= 0;
1045 tegra_uart_dma_channel_free(tup
, true);
1046 tegra_uart_dma_channel_free(tup
, false);
1047 free_irq(u
->irq
, tup
);
1050 static void tegra_uart_enable_ms(struct uart_port
*u
)
1052 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
1054 if (tup
->enable_modem_interrupt
) {
1055 tup
->ier_shadow
|= UART_IER_MSI
;
1056 tegra_uart_write(tup
, tup
->ier_shadow
, UART_IER
);
1060 static void tegra_uart_set_termios(struct uart_port
*u
,
1061 struct ktermios
*termios
, struct ktermios
*oldtermios
)
1063 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
1065 unsigned long flags
;
1068 struct clk
*parent_clk
= clk_get_parent(tup
->uart_clk
);
1069 unsigned long parent_clk_rate
= clk_get_rate(parent_clk
);
1070 int max_divider
= (tup
->cdata
->support_clk_src_div
) ? 0x7FFF : 0xFFFF;
1073 spin_lock_irqsave(&u
->lock
, flags
);
1075 /* Changing configuration, it is safe to stop any rx now */
1076 if (tup
->rts_active
)
1077 set_rts(tup
, false);
1079 /* Clear all interrupts as configuration is going to be change */
1080 tegra_uart_write(tup
, tup
->ier_shadow
| UART_IER_RDI
, UART_IER
);
1081 tegra_uart_read(tup
, UART_IER
);
1082 tegra_uart_write(tup
, 0, UART_IER
);
1083 tegra_uart_read(tup
, UART_IER
);
1086 lcr
= tup
->lcr_shadow
;
1087 lcr
&= ~UART_LCR_PARITY
;
1089 /* CMSPAR isn't supported by this driver */
1090 termios
->c_cflag
&= ~CMSPAR
;
1092 if ((termios
->c_cflag
& PARENB
) == PARENB
) {
1094 if (termios
->c_cflag
& PARODD
) {
1095 lcr
|= UART_LCR_PARITY
;
1096 lcr
&= ~UART_LCR_EPAR
;
1097 lcr
&= ~UART_LCR_SPAR
;
1099 lcr
|= UART_LCR_PARITY
;
1100 lcr
|= UART_LCR_EPAR
;
1101 lcr
&= ~UART_LCR_SPAR
;
1105 lcr
&= ~UART_LCR_WLEN8
;
1106 switch (termios
->c_cflag
& CSIZE
) {
1108 lcr
|= UART_LCR_WLEN5
;
1112 lcr
|= UART_LCR_WLEN6
;
1116 lcr
|= UART_LCR_WLEN7
;
1120 lcr
|= UART_LCR_WLEN8
;
1126 if (termios
->c_cflag
& CSTOPB
) {
1127 lcr
|= UART_LCR_STOP
;
1130 lcr
&= ~UART_LCR_STOP
;
1134 tegra_uart_write(tup
, lcr
, UART_LCR
);
1135 tup
->lcr_shadow
= lcr
;
1136 tup
->symb_bit
= symb_bit
;
1139 baud
= uart_get_baud_rate(u
, termios
, oldtermios
,
1140 parent_clk_rate
/max_divider
,
1141 parent_clk_rate
/16);
1142 spin_unlock_irqrestore(&u
->lock
, flags
);
1143 tegra_set_baudrate(tup
, baud
);
1144 if (tty_termios_baud_rate(termios
))
1145 tty_termios_encode_baud_rate(termios
, baud
, baud
);
1146 spin_lock_irqsave(&u
->lock
, flags
);
1149 if (termios
->c_cflag
& CRTSCTS
) {
1150 tup
->mcr_shadow
|= TEGRA_UART_MCR_CTS_EN
;
1151 tup
->mcr_shadow
&= ~TEGRA_UART_MCR_RTS_EN
;
1152 tegra_uart_write(tup
, tup
->mcr_shadow
, UART_MCR
);
1153 /* if top layer has asked to set rts active then do so here */
1154 if (tup
->rts_active
)
1157 tup
->mcr_shadow
&= ~TEGRA_UART_MCR_CTS_EN
;
1158 tup
->mcr_shadow
&= ~TEGRA_UART_MCR_RTS_EN
;
1159 tegra_uart_write(tup
, tup
->mcr_shadow
, UART_MCR
);
1162 /* update the port timeout based on new settings */
1163 uart_update_timeout(u
, termios
->c_cflag
, baud
);
1165 /* Make sure all write has completed */
1166 tegra_uart_read(tup
, UART_IER
);
1168 /* Reenable interrupt */
1169 tegra_uart_write(tup
, tup
->ier_shadow
, UART_IER
);
1170 tegra_uart_read(tup
, UART_IER
);
1172 spin_unlock_irqrestore(&u
->lock
, flags
);
1177 * Flush any TX data submitted for DMA and PIO. Called when the
1178 * TX circular buffer is reset.
1180 static void tegra_uart_flush_buffer(struct uart_port
*u
)
1182 struct tegra_uart_port
*tup
= to_tegra_uport(u
);
1185 if (tup
->tx_dma_chan
)
1186 dmaengine_terminate_all(tup
->tx_dma_chan
);
1190 static const char *tegra_uart_type(struct uart_port
*u
)
1192 return TEGRA_UART_TYPE
;
1195 static struct uart_ops tegra_uart_ops
= {
1196 .tx_empty
= tegra_uart_tx_empty
,
1197 .set_mctrl
= tegra_uart_set_mctrl
,
1198 .get_mctrl
= tegra_uart_get_mctrl
,
1199 .stop_tx
= tegra_uart_stop_tx
,
1200 .start_tx
= tegra_uart_start_tx
,
1201 .stop_rx
= tegra_uart_stop_rx
,
1202 .flush_buffer
= tegra_uart_flush_buffer
,
1203 .enable_ms
= tegra_uart_enable_ms
,
1204 .break_ctl
= tegra_uart_break_ctl
,
1205 .startup
= tegra_uart_startup
,
1206 .shutdown
= tegra_uart_shutdown
,
1207 .set_termios
= tegra_uart_set_termios
,
1208 .type
= tegra_uart_type
,
1209 .request_port
= tegra_uart_request_port
,
1210 .release_port
= tegra_uart_release_port
,
1213 static struct uart_driver tegra_uart_driver
= {
1214 .owner
= THIS_MODULE
,
1215 .driver_name
= "tegra_hsuart",
1216 .dev_name
= "ttyTHS",
1218 .nr
= TEGRA_UART_MAXIMUM
,
1221 static int tegra_uart_parse_dt(struct platform_device
*pdev
,
1222 struct tegra_uart_port
*tup
)
1224 struct device_node
*np
= pdev
->dev
.of_node
;
1228 if (of_property_read_u32_array(np
, "nvidia,dma-request-selector",
1230 tup
->dma_req_sel
= of_dma
[1];
1232 dev_err(&pdev
->dev
, "missing dma requestor in device tree\n");
1236 port
= of_alias_get_id(np
, "serial");
1238 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", port
);
1241 tup
->uport
.line
= port
;
1243 tup
->enable_modem_interrupt
= of_property_read_bool(np
,
1244 "nvidia,enable-modem-interrupt");
1248 static struct tegra_uart_chip_data tegra20_uart_chip_data
= {
1249 .tx_fifo_full_status
= false,
1250 .allow_txfifo_reset_fifo_mode
= true,
1251 .support_clk_src_div
= false,
1254 static struct tegra_uart_chip_data tegra30_uart_chip_data
= {
1255 .tx_fifo_full_status
= true,
1256 .allow_txfifo_reset_fifo_mode
= false,
1257 .support_clk_src_div
= true,
1260 static struct of_device_id tegra_uart_of_match
[] = {
1262 .compatible
= "nvidia,tegra30-hsuart",
1263 .data
= &tegra30_uart_chip_data
,
1265 .compatible
= "nvidia,tegra20-hsuart",
1266 .data
= &tegra20_uart_chip_data
,
1270 MODULE_DEVICE_TABLE(of
, tegra_uart_of_match
);
1272 static int tegra_uart_probe(struct platform_device
*pdev
)
1274 struct tegra_uart_port
*tup
;
1275 struct uart_port
*u
;
1276 struct resource
*resource
;
1278 const struct tegra_uart_chip_data
*cdata
;
1279 const struct of_device_id
*match
;
1281 match
= of_match_device(tegra_uart_of_match
, &pdev
->dev
);
1283 dev_err(&pdev
->dev
, "Error: No device match found\n");
1286 cdata
= match
->data
;
1288 tup
= devm_kzalloc(&pdev
->dev
, sizeof(*tup
), GFP_KERNEL
);
1290 dev_err(&pdev
->dev
, "Failed to allocate memory for tup\n");
1294 ret
= tegra_uart_parse_dt(pdev
, tup
);
1299 u
->dev
= &pdev
->dev
;
1300 u
->ops
= &tegra_uart_ops
;
1301 u
->type
= PORT_TEGRA
;
1305 platform_set_drvdata(pdev
, tup
);
1306 resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1308 dev_err(&pdev
->dev
, "No IO memory resource\n");
1312 u
->mapbase
= resource
->start
;
1313 u
->membase
= devm_ioremap_resource(&pdev
->dev
, resource
);
1314 if (IS_ERR(u
->membase
))
1315 return PTR_ERR(u
->membase
);
1317 tup
->uart_clk
= devm_clk_get(&pdev
->dev
, NULL
);
1318 if (IS_ERR(tup
->uart_clk
)) {
1319 dev_err(&pdev
->dev
, "Couldn't get the clock\n");
1320 return PTR_ERR(tup
->uart_clk
);
1323 u
->iotype
= UPIO_MEM32
;
1324 u
->irq
= platform_get_irq(pdev
, 0);
1326 ret
= uart_add_one_port(&tegra_uart_driver
, u
);
1328 dev_err(&pdev
->dev
, "Failed to add uart port, err %d\n", ret
);
1334 static int tegra_uart_remove(struct platform_device
*pdev
)
1336 struct tegra_uart_port
*tup
= platform_get_drvdata(pdev
);
1337 struct uart_port
*u
= &tup
->uport
;
1339 uart_remove_one_port(&tegra_uart_driver
, u
);
1343 #ifdef CONFIG_PM_SLEEP
1344 static int tegra_uart_suspend(struct device
*dev
)
1346 struct tegra_uart_port
*tup
= dev_get_drvdata(dev
);
1347 struct uart_port
*u
= &tup
->uport
;
1349 return uart_suspend_port(&tegra_uart_driver
, u
);
1352 static int tegra_uart_resume(struct device
*dev
)
1354 struct tegra_uart_port
*tup
= dev_get_drvdata(dev
);
1355 struct uart_port
*u
= &tup
->uport
;
1357 return uart_resume_port(&tegra_uart_driver
, u
);
1361 static const struct dev_pm_ops tegra_uart_pm_ops
= {
1362 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend
, tegra_uart_resume
)
1365 static struct platform_driver tegra_uart_platform_driver
= {
1366 .probe
= tegra_uart_probe
,
1367 .remove
= tegra_uart_remove
,
1369 .name
= "serial-tegra",
1370 .of_match_table
= tegra_uart_of_match
,
1371 .pm
= &tegra_uart_pm_ops
,
1375 static int __init
tegra_uart_init(void)
1379 ret
= uart_register_driver(&tegra_uart_driver
);
1381 pr_err("Could not register %s driver\n",
1382 tegra_uart_driver
.driver_name
);
1386 ret
= platform_driver_register(&tegra_uart_platform_driver
);
1388 pr_err("Uart platform driver register failed, e = %d\n", ret
);
1389 uart_unregister_driver(&tegra_uart_driver
);
1395 static void __exit
tegra_uart_exit(void)
1397 pr_info("Unloading tegra uart driver\n");
1398 platform_driver_unregister(&tegra_uart_platform_driver
);
1399 uart_unregister_driver(&tegra_uart_driver
);
1402 module_init(tegra_uart_init
);
1403 module_exit(tegra_uart_exit
);
1405 MODULE_ALIAS("platform:serial-tegra");
1406 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1407 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1408 MODULE_LICENSE("GPL v2");