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[MIPS] Alchemy: kill useless #include's, #define's and extern's
[linux-2.6.git] / arch / mips / au1000 / common / dbdma.c
blob53377dfc0640da33d85db3b7f47db242872ca5b1
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/interrupt.h>
37 #include <linux/module.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-au1x00/au1xxx_dbdma.h>
40
41 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
42
43 /*
44 * The Descriptor Based DMA supports up to 16 channels.
45 *
46 * There are 32 devices defined. We keep an internal structure
47 * of devices using these channels, along with additional
48 * information.
49 *
50 * We allocate the descriptors and allow access to them through various
51 * functions. The drivers allocate the data buffers and assign them
52 * to the descriptors.
53 */
54 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
55
56 /* I couldn't find a macro that did this......
57 */
58 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
59
60 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
61 static int dbdma_initialized=0;
62 static void au1xxx_dbdma_init(void);
63
64 static dbdev_tab_t dbdev_tab[] = {
65 #ifdef CONFIG_SOC_AU1550
66 /* UARTS */
67 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
68 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
69 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
70 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
71
72 /* EXT DMA */
73 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
74 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
76 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
77
78 /* USB DEV */
79 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
80 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
82 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
83 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
84 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
85
86 /* PSC 0 */
87 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
88 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
89
90 /* PSC 1 */
91 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
92 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
93
94 /* PSC 2 */
95 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
96 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
97
98 /* PSC 3 */
99 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
100 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
101
102 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
103 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
104
105 /* MAC 0 */
106 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
107 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
108
109 /* MAC 1 */
110 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
111 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
112
113 #endif /* CONFIG_SOC_AU1550 */
114
115 #ifdef CONFIG_SOC_AU1200
116 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
117 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
118 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
119 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
120
121 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
122 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
123
124 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
125 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
127 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
128
129 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
130 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
131 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
132 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
133
134 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
135 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
136
137 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
138 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
139 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
140
141 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
142 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
143 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
144
145 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
146 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
147 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
148 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149
150 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
151
152 #endif // CONFIG_SOC_AU1200
153
154 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
156
157 /* Provide 16 user definable device types */
158 { ~0, 0, 0, 0, 0, 0, 0 },
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 { ~0, 0, 0, 0, 0, 0, 0 },
174 };
175
176 #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
177
178 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
179
180 static dbdev_tab_t *
181 find_dbdev_id(u32 id)
182 {
183 int i;
184 dbdev_tab_t *p;
185 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
186 p = &dbdev_tab[i];
187 if (p->dev_id == id)
188 return p;
189 }
190 return NULL;
191 }
192
193 void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
194 {
195 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
196 }
197 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
198
199 u32
200 au1xxx_ddma_add_device(dbdev_tab_t *dev)
201 {
202 u32 ret = 0;
203 dbdev_tab_t *p=NULL;
204 static u16 new_id=0x1000;
205
206 p = find_dbdev_id(~0);
207 if ( NULL != p )
208 {
209 memcpy(p, dev, sizeof(dbdev_tab_t));
210 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
211 ret = p->dev_id;
212 new_id++;
213 #if 0
214 printk("add_device: id:%x flags:%x padd:%x\n",
215 p->dev_id, p->dev_flags, p->dev_physaddr );
216 #endif
217 }
218
219 return ret;
220 }
221 EXPORT_SYMBOL(au1xxx_ddma_add_device);
222
223 /* Allocate a channel and return a non-zero descriptor if successful.
224 */
225 u32
226 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
227 void (*callback)(int, void *), void *callparam)
228 {
229 unsigned long flags;
230 u32 used, chan, rv;
231 u32 dcp;
232 int i;
233 dbdev_tab_t *stp, *dtp;
234 chan_tab_t *ctp;
235 au1x_dma_chan_t *cp;
236
237 /* We do the intialization on the first channel allocation.
238 * We have to wait because of the interrupt handler initialization
239 * which can't be done successfully during board set up.
240 */
241 if (!dbdma_initialized)
242 au1xxx_dbdma_init();
243 dbdma_initialized = 1;
244
245 if ((stp = find_dbdev_id(srcid)) == NULL)
246 return 0;
247 if ((dtp = find_dbdev_id(destid)) == NULL)
248 return 0;
249
250 used = 0;
251 rv = 0;
252
253 /* Check to see if we can get both channels.
254 */
255 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
256 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
257 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
258 /* Got source */
259 stp->dev_flags |= DEV_FLAGS_INUSE;
260 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
261 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
262 /* Got destination */
263 dtp->dev_flags |= DEV_FLAGS_INUSE;
264 }
265 else {
266 /* Can't get dest. Release src.
267 */
268 stp->dev_flags &= ~DEV_FLAGS_INUSE;
269 used++;
270 }
271 }
272 else {
273 used++;
274 }
275 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
276
277 if (!used) {
278 /* Let's see if we can allocate a channel for it.
279 */
280 ctp = NULL;
281 chan = 0;
282 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
283 for (i=0; i<NUM_DBDMA_CHANS; i++) {
284 if (chan_tab_ptr[i] == NULL) {
285 /* If kmalloc fails, it is caught below same
286 * as a channel not available.
287 */
288 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
289 chan_tab_ptr[i] = ctp;
290 break;
291 }
292 }
293 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
294
295 if (ctp != NULL) {
296 memset(ctp, 0, sizeof(chan_tab_t));
297 ctp->chan_index = chan = i;
298 dcp = DDMA_CHANNEL_BASE;
299 dcp += (0x0100 * chan);
300 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
301 cp = (au1x_dma_chan_t *)dcp;
302 ctp->chan_src = stp;
303 ctp->chan_dest = dtp;
304 ctp->chan_callback = callback;
305 ctp->chan_callparam = callparam;
306
307 /* Initialize channel configuration.
308 */
309 i = 0;
310 if (stp->dev_intlevel)
311 i |= DDMA_CFG_SED;
312 if (stp->dev_intpolarity)
313 i |= DDMA_CFG_SP;
314 if (dtp->dev_intlevel)
315 i |= DDMA_CFG_DED;
316 if (dtp->dev_intpolarity)
317 i |= DDMA_CFG_DP;
318 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
319 (dtp->dev_flags & DEV_FLAGS_SYNC))
320 i |= DDMA_CFG_SYNC;
321 cp->ddma_cfg = i;
322 au_sync();
323
324 /* Return a non-zero value that can be used to
325 * find the channel information in subsequent
326 * operations.
327 */
328 rv = (u32)(&chan_tab_ptr[chan]);
329 }
330 else {
331 /* Release devices */
332 stp->dev_flags &= ~DEV_FLAGS_INUSE;
333 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
334 }
335 }
336 return rv;
337 }
338 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
339
340 /* Set the device width if source or destination is a FIFO.
341 * Should be 8, 16, or 32 bits.
342 */
343 u32
344 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
345 {
346 u32 rv;
347 chan_tab_t *ctp;
348 dbdev_tab_t *stp, *dtp;
349
350 ctp = *((chan_tab_t **)chanid);
351 stp = ctp->chan_src;
352 dtp = ctp->chan_dest;
353 rv = 0;
354
355 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
356 rv = stp->dev_devwidth;
357 stp->dev_devwidth = bits;
358 }
359 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
360 rv = dtp->dev_devwidth;
361 dtp->dev_devwidth = bits;
362 }
363
364 return rv;
365 }
366 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
367
368 /* Allocate a descriptor ring, initializing as much as possible.
369 */
370 u32
371 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
372 {
373 int i;
374 u32 desc_base, srcid, destid;
375 u32 cmd0, cmd1, src1, dest1;
376 u32 src0, dest0;
377 chan_tab_t *ctp;
378 dbdev_tab_t *stp, *dtp;
379 au1x_ddma_desc_t *dp;
380
381 /* I guess we could check this to be within the
382 * range of the table......
383 */
384 ctp = *((chan_tab_t **)chanid);
385 stp = ctp->chan_src;
386 dtp = ctp->chan_dest;
387
388 /* The descriptors must be 32-byte aligned. There is a
389 * possibility the allocation will give us such an address,
390 * and if we try that first we are likely to not waste larger
391 * slabs of memory.
392 */
393 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
394 GFP_KERNEL|GFP_DMA);
395 if (desc_base == 0)
396 return 0;
397
398 if (desc_base & 0x1f) {
399 /* Lost....do it again, allocate extra, and round
400 * the address base.
401 */
402 kfree((const void *)desc_base);
403 i = entries * sizeof(au1x_ddma_desc_t);
404 i += (sizeof(au1x_ddma_desc_t) - 1);
405 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
406 return 0;
407
408 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
409 }
410 dp = (au1x_ddma_desc_t *)desc_base;
411
412 /* Keep track of the base descriptor.
413 */
414 ctp->chan_desc_base = dp;
415
416 /* Initialize the rings with as much information as we know.
417 */
418 srcid = stp->dev_id;
419 destid = dtp->dev_id;
420
421 cmd0 = cmd1 = src1 = dest1 = 0;
422 src0 = dest0 = 0;
423
424 cmd0 |= DSCR_CMD0_SID(srcid);
425 cmd0 |= DSCR_CMD0_DID(destid);
426 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
427 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
428
429 /* is it mem to mem transfer? */
430 if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
431 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
432 cmd0 |= DSCR_CMD0_MEM;
433 }
434
435 switch (stp->dev_devwidth) {
436 case 8:
437 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
438 break;
439 case 16:
440 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
441 break;
442 case 32:
443 default:
444 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
445 break;
446 }
447
448 switch (dtp->dev_devwidth) {
449 case 8:
450 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
451 break;
452 case 16:
453 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
454 break;
455 case 32:
456 default:
457 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
458 break;
459 }
460
461 /* If the device is marked as an in/out FIFO, ensure it is
462 * set non-coherent.
463 */
464 if (stp->dev_flags & DEV_FLAGS_IN)
465 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
466 if (dtp->dev_flags & DEV_FLAGS_OUT)
467 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
468
469 /* Set up source1. For now, assume no stride and increment.
470 * A channel attribute update can change this later.
471 */
472 switch (stp->dev_tsize) {
473 case 1:
474 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
475 break;
476 case 2:
477 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
478 break;
479 case 4:
480 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
481 break;
482 case 8:
483 default:
484 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
485 break;
486 }
487
488 /* If source input is fifo, set static address.
489 */
490 if (stp->dev_flags & DEV_FLAGS_IN) {
491 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
492 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
493 else
494 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
495
496 }
497 if (stp->dev_physaddr)
498 src0 = stp->dev_physaddr;
499
500 /* Set up dest1. For now, assume no stride and increment.
501 * A channel attribute update can change this later.
502 */
503 switch (dtp->dev_tsize) {
504 case 1:
505 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
506 break;
507 case 2:
508 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
509 break;
510 case 4:
511 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
512 break;
513 case 8:
514 default:
515 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
516 break;
517 }
518
519 /* If destination output is fifo, set static address.
520 */
521 if (dtp->dev_flags & DEV_FLAGS_OUT) {
522 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
523 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
524 else
525 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
526 }
527 if (dtp->dev_physaddr)
528 dest0 = dtp->dev_physaddr;
529
530 #if 0
531 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
532 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
533 #endif
534 for (i=0; i<entries; i++) {
535 dp->dscr_cmd0 = cmd0;
536 dp->dscr_cmd1 = cmd1;
537 dp->dscr_source0 = src0;
538 dp->dscr_source1 = src1;
539 dp->dscr_dest0 = dest0;
540 dp->dscr_dest1 = dest1;
541 dp->dscr_stat = 0;
542 dp->sw_context = 0;
543 dp->sw_status = 0;
544 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
545 dp++;
546 }
547
548 /* Make last descrptor point to the first.
549 */
550 dp--;
551 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
552 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
553
554 return (u32)(ctp->chan_desc_base);
555 }
556 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
557
558 /* Put a source buffer into the DMA ring.
559 * This updates the source pointer and byte count. Normally used
560 * for memory to fifo transfers.
561 */
562 u32
563 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
564 {
565 chan_tab_t *ctp;
566 au1x_ddma_desc_t *dp;
567
568 /* I guess we could check this to be within the
569 * range of the table......
570 */
571 ctp = *((chan_tab_t **)chanid);
572
573 /* We should have multiple callers for a particular channel,
574 * an interrupt doesn't affect this pointer nor the descriptor,
575 * so no locking should be needed.
576 */
577 dp = ctp->put_ptr;
578
579 /* If the descriptor is valid, we are way ahead of the DMA
580 * engine, so just return an error condition.
581 */
582 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
583 return 0;
584 }
585
586 /* Load up buffer address and byte count.
587 */
588 dp->dscr_source0 = virt_to_phys(buf);
589 dp->dscr_cmd1 = nbytes;
590 /* Check flags */
591 if (flags & DDMA_FLAGS_IE)
592 dp->dscr_cmd0 |= DSCR_CMD0_IE;
593 if (flags & DDMA_FLAGS_NOIE)
594 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
595
596 /*
597 * There is an errata on the Au1200/Au1550 parts that could result
598 * in "stale" data being DMA'd. It has to do with the snoop logic on
599 * the dache eviction buffer. NONCOHERENT_IO is on by default for
600 * these parts. If it is fixedin the future, these dma_cache_inv will
601 * just be nothing more than empty macros. See io.h.
602 * */
603 dma_cache_wback_inv((unsigned long)buf, nbytes);
604 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
605 au_sync();
606 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
607 ctp->chan_ptr->ddma_dbell = 0;
608
609 /* Get next descriptor pointer.
610 */
611 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
612
613 /* return something not zero.
614 */
615 return nbytes;
616 }
617 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
618
619 /* Put a destination buffer into the DMA ring.
620 * This updates the destination pointer and byte count. Normally used
621 * to place an empty buffer into the ring for fifo to memory transfers.
622 */
623 u32
624 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
625 {
626 chan_tab_t *ctp;
627 au1x_ddma_desc_t *dp;
628
629 /* I guess we could check this to be within the
630 * range of the table......
631 */
632 ctp = *((chan_tab_t **)chanid);
633
634 /* We should have multiple callers for a particular channel,
635 * an interrupt doesn't affect this pointer nor the descriptor,
636 * so no locking should be needed.
637 */
638 dp = ctp->put_ptr;
639
640 /* If the descriptor is valid, we are way ahead of the DMA
641 * engine, so just return an error condition.
642 */
643 if (dp->dscr_cmd0 & DSCR_CMD0_V)
644 return 0;
645
646 /* Load up buffer address and byte count */
647
648 /* Check flags */
649 if (flags & DDMA_FLAGS_IE)
650 dp->dscr_cmd0 |= DSCR_CMD0_IE;
651 if (flags & DDMA_FLAGS_NOIE)
652 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
653
654 dp->dscr_dest0 = virt_to_phys(buf);
655 dp->dscr_cmd1 = nbytes;
656 #if 0
657 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
658 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
659 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
660 #endif
661 /*
662 * There is an errata on the Au1200/Au1550 parts that could result in
663 * "stale" data being DMA'd. It has to do with the snoop logic on the
664 * dache eviction buffer. NONCOHERENT_IO is on by default for these
665 * parts. If it is fixedin the future, these dma_cache_inv will just
666 * be nothing more than empty macros. See io.h.
667 * */
668 dma_cache_inv((unsigned long)buf, nbytes);
669 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
670 au_sync();
671 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
672 ctp->chan_ptr->ddma_dbell = 0;
673
674 /* Get next descriptor pointer.
675 */
676 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
677
678 /* return something not zero.
679 */
680 return nbytes;
681 }
682 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
683
684 /* Get a destination buffer into the DMA ring.
685 * Normally used to get a full buffer from the ring during fifo
686 * to memory transfers. This does not set the valid bit, you will
687 * have to put another destination buffer to keep the DMA going.
688 */
689 u32
690 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
691 {
692 chan_tab_t *ctp;
693 au1x_ddma_desc_t *dp;
694 u32 rv;
695
696 /* I guess we could check this to be within the
697 * range of the table......
698 */
699 ctp = *((chan_tab_t **)chanid);
700
701 /* We should have multiple callers for a particular channel,
702 * an interrupt doesn't affect this pointer nor the descriptor,
703 * so no locking should be needed.
704 */
705 dp = ctp->get_ptr;
706
707 /* If the descriptor is valid, we are way ahead of the DMA
708 * engine, so just return an error condition.
709 */
710 if (dp->dscr_cmd0 & DSCR_CMD0_V)
711 return 0;
712
713 /* Return buffer address and byte count.
714 */
715 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
716 *nbytes = dp->dscr_cmd1;
717 rv = dp->dscr_stat;
718
719 /* Get next descriptor pointer.
720 */
721 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
722
723 /* return something not zero.
724 */
725 return rv;
726 }
727
728 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
729
730 void
731 au1xxx_dbdma_stop(u32 chanid)
732 {
733 chan_tab_t *ctp;
734 au1x_dma_chan_t *cp;
735 int halt_timeout = 0;
736
737 ctp = *((chan_tab_t **)chanid);
738
739 cp = ctp->chan_ptr;
740 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
741 au_sync();
742 while (!(cp->ddma_stat & DDMA_STAT_H)) {
743 udelay(1);
744 halt_timeout++;
745 if (halt_timeout > 100) {
746 printk("warning: DMA channel won't halt\n");
747 break;
748 }
749 }
750 /* clear current desc valid and doorbell */
751 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
752 au_sync();
753 }
754 EXPORT_SYMBOL(au1xxx_dbdma_stop);
755
756 /* Start using the current descriptor pointer. If the dbdma encounters
757 * a not valid descriptor, it will stop. In this case, we can just
758 * continue by adding a buffer to the list and starting again.
759 */
760 void
761 au1xxx_dbdma_start(u32 chanid)
762 {
763 chan_tab_t *ctp;
764 au1x_dma_chan_t *cp;
765
766 ctp = *((chan_tab_t **)chanid);
767 cp = ctp->chan_ptr;
768 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
769 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
770 au_sync();
771 cp->ddma_dbell = 0;
772 au_sync();
773 }
774 EXPORT_SYMBOL(au1xxx_dbdma_start);
775
776 void
777 au1xxx_dbdma_reset(u32 chanid)
778 {
779 chan_tab_t *ctp;
780 au1x_ddma_desc_t *dp;
781
782 au1xxx_dbdma_stop(chanid);
783
784 ctp = *((chan_tab_t **)chanid);
785 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
786
787 /* Run through the descriptors and reset the valid indicator.
788 */
789 dp = ctp->chan_desc_base;
790
791 do {
792 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
793 /* reset our SW status -- this is used to determine
794 * if a descriptor is in use by upper level SW. Since
795 * posting can reset 'V' bit.
796 */
797 dp->sw_status = 0;
798 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
799 } while (dp != ctp->chan_desc_base);
800 }
801 EXPORT_SYMBOL(au1xxx_dbdma_reset);
802
803 u32
804 au1xxx_get_dma_residue(u32 chanid)
805 {
806 chan_tab_t *ctp;
807 au1x_dma_chan_t *cp;
808 u32 rv;
809
810 ctp = *((chan_tab_t **)chanid);
811 cp = ctp->chan_ptr;
812
813 /* This is only valid if the channel is stopped.
814 */
815 rv = cp->ddma_bytecnt;
816 au_sync();
817
818 return rv;
819 }
820
821 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
822
823 void
824 au1xxx_dbdma_chan_free(u32 chanid)
825 {
826 chan_tab_t *ctp;
827 dbdev_tab_t *stp, *dtp;
828
829 ctp = *((chan_tab_t **)chanid);
830 stp = ctp->chan_src;
831 dtp = ctp->chan_dest;
832
833 au1xxx_dbdma_stop(chanid);
834
835 kfree((void *)ctp->chan_desc_base);
836
837 stp->dev_flags &= ~DEV_FLAGS_INUSE;
838 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
839 chan_tab_ptr[ctp->chan_index] = NULL;
840
841 kfree(ctp);
842 }
843 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
844
845 static irqreturn_t
846 dbdma_interrupt(int irq, void *dev_id)
847 {
848 u32 intstat;
849 u32 chan_index;
850 chan_tab_t *ctp;
851 au1x_ddma_desc_t *dp;
852 au1x_dma_chan_t *cp;
853
854 intstat = dbdma_gptr->ddma_intstat;
855 au_sync();
856 chan_index = __ffs(intstat);
857
858 ctp = chan_tab_ptr[chan_index];
859 cp = ctp->chan_ptr;
860 dp = ctp->cur_ptr;
861
862 /* Reset interrupt.
863 */
864 cp->ddma_irq = 0;
865 au_sync();
866
867 if (ctp->chan_callback)
868 (ctp->chan_callback)(irq, ctp->chan_callparam);
869
870 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
871 return IRQ_RETVAL(1);
872 }
873
874 static void au1xxx_dbdma_init(void)
875 {
876 int irq_nr;
877
878 dbdma_gptr->ddma_config = 0;
879 dbdma_gptr->ddma_throttle = 0;
880 dbdma_gptr->ddma_inten = 0xffff;
881 au_sync();
882
883 #if defined(CONFIG_SOC_AU1550)
884 irq_nr = AU1550_DDMA_INT;
885 #elif defined(CONFIG_SOC_AU1200)
886 irq_nr = AU1200_DDMA_INT;
887 #else
888 #error Unknown Au1x00 SOC
889 #endif
890
891 if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
892 "Au1xxx dbdma", (void *)dbdma_gptr))
893 printk("Can't get 1550 dbdma irq");
894 }
895
896 void
897 au1xxx_dbdma_dump(u32 chanid)
898 {
899 chan_tab_t *ctp;
900 au1x_ddma_desc_t *dp;
901 dbdev_tab_t *stp, *dtp;
902 au1x_dma_chan_t *cp;
903 u32 i = 0;
904
905 ctp = *((chan_tab_t **)chanid);
906 stp = ctp->chan_src;
907 dtp = ctp->chan_dest;
908 cp = ctp->chan_ptr;
909
910 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
911 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
912 printk("desc base %x, get %x, put %x, cur %x\n",
913 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
914 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
915
916 printk("dbdma chan %x\n", (u32)cp);
917 printk("cfg %08x, desptr %08x, statptr %08x\n",
918 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
919 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
920 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
921
922
923 /* Run through the descriptors
924 */
925 dp = ctp->chan_desc_base;
926
927 do {
928 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
929 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
930 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
931 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
932 printk("stat %08x, nxtptr %08x\n",
933 dp->dscr_stat, dp->dscr_nxtptr);
934 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
935 } while (dp != ctp->chan_desc_base);
936 }
937
938 /* Put a descriptor into the DMA ring.
939 * This updates the source/destination pointers and byte count.
940 */
941 u32
942 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
943 {
944 chan_tab_t *ctp;
945 au1x_ddma_desc_t *dp;
946 u32 nbytes=0;
947
948 /* I guess we could check this to be within the
949 * range of the table......
950 */
951 ctp = *((chan_tab_t **)chanid);
952
953 /* We should have multiple callers for a particular channel,
954 * an interrupt doesn't affect this pointer nor the descriptor,
955 * so no locking should be needed.
956 */
957 dp = ctp->put_ptr;
958
959 /* If the descriptor is valid, we are way ahead of the DMA
960 * engine, so just return an error condition.
961 */
962 if (dp->dscr_cmd0 & DSCR_CMD0_V)
963 return 0;
964
965 /* Load up buffer addresses and byte count.
966 */
967 dp->dscr_dest0 = dscr->dscr_dest0;
968 dp->dscr_source0 = dscr->dscr_source0;
969 dp->dscr_dest1 = dscr->dscr_dest1;
970 dp->dscr_source1 = dscr->dscr_source1;
971 dp->dscr_cmd1 = dscr->dscr_cmd1;
972 nbytes = dscr->dscr_cmd1;
973 /* Allow the caller to specifiy if an interrupt is generated */
974 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
975 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
976 ctp->chan_ptr->ddma_dbell = 0;
977
978 /* Get next descriptor pointer.
979 */
980 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
981
982 /* return something not zero.
983 */
984 return nbytes;
985 }
986
987 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
988
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