2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names
[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names
);
33 int isa_dma_bridge_buggy
;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
37 EXPORT_SYMBOL(pci_pci_problems
);
39 unsigned int pci_pm_d3_delay
;
41 static void pci_pme_list_scan(struct work_struct
*work
);
43 static LIST_HEAD(pci_pme_list
);
44 static DEFINE_MUTEX(pci_pme_list_mutex
);
45 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
47 struct pci_pme_device
{
48 struct list_head list
;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
56 unsigned int delay
= dev
->d3_delay
;
58 if (delay
< pci_pm_d3_delay
)
59 delay
= pci_pm_d3_delay
;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported
= 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
72 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
78 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
80 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
89 u8 pci_cache_line_size
;
92 * If we set up a device for bus mastering, we need to check the latency
93 * timer as certain BIOSes forget to set it properly.
95 unsigned int pcibios_max_latency
= 255;
97 /* If set, the PCIe ARI capability will not be used. */
98 static bool pcie_ari_disabled
;
101 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
102 * @bus: pointer to PCI bus structure to search
104 * Given a PCI bus, returns the highest PCI bus number present in the set
105 * including the given PCI bus and its list of child PCI buses.
107 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
109 struct list_head
*tmp
;
110 unsigned char max
, n
;
112 max
= bus
->subordinate
;
113 list_for_each(tmp
, &bus
->children
) {
114 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
120 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
122 #ifdef CONFIG_HAS_IOMEM
123 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
126 * Make sure the BAR is actually a memory resource, not an IO resource
128 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
132 return ioremap_nocache(pci_resource_start(pdev
, bar
),
133 pci_resource_len(pdev
, bar
));
135 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
140 * pci_max_busnr - returns maximum PCI bus number
142 * Returns the highest PCI bus number present in the system global list of
145 unsigned char __devinit
148 struct pci_bus
*bus
= NULL
;
149 unsigned char max
, n
;
152 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
153 n
= pci_bus_max_busnr(bus
);
162 #define PCI_FIND_CAP_TTL 48
164 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
165 u8 pos
, int cap
, int *ttl
)
170 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
174 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
180 pos
+= PCI_CAP_LIST_NEXT
;
185 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
188 int ttl
= PCI_FIND_CAP_TTL
;
190 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
193 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
195 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
196 pos
+ PCI_CAP_LIST_NEXT
, cap
);
198 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
200 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
201 unsigned int devfn
, u8 hdr_type
)
205 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
206 if (!(status
& PCI_STATUS_CAP_LIST
))
210 case PCI_HEADER_TYPE_NORMAL
:
211 case PCI_HEADER_TYPE_BRIDGE
:
212 return PCI_CAPABILITY_LIST
;
213 case PCI_HEADER_TYPE_CARDBUS
:
214 return PCI_CB_CAPABILITY_LIST
;
223 * pci_find_capability - query for devices' capabilities
224 * @dev: PCI device to query
225 * @cap: capability code
227 * Tell if a device supports a given PCI capability.
228 * Returns the address of the requested capability structure within the
229 * device's PCI configuration space or 0 in case the device does not
230 * support it. Possible values for @cap:
232 * %PCI_CAP_ID_PM Power Management
233 * %PCI_CAP_ID_AGP Accelerated Graphics Port
234 * %PCI_CAP_ID_VPD Vital Product Data
235 * %PCI_CAP_ID_SLOTID Slot Identification
236 * %PCI_CAP_ID_MSI Message Signalled Interrupts
237 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
238 * %PCI_CAP_ID_PCIX PCI-X
239 * %PCI_CAP_ID_EXP PCI Express
241 int pci_find_capability(struct pci_dev
*dev
, int cap
)
245 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
247 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
253 * pci_bus_find_capability - query for devices' capabilities
254 * @bus: the PCI bus to query
255 * @devfn: PCI device to query
256 * @cap: capability code
258 * Like pci_find_capability() but works for pci devices that do not have a
259 * pci_dev structure set up yet.
261 * Returns the address of the requested capability structure within the
262 * device's PCI configuration space or 0 in case the device does not
265 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
270 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
272 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
274 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
280 * pci_find_ext_capability - Find an extended capability
281 * @dev: PCI device to query
282 * @cap: capability code
284 * Returns the address of the requested extended capability structure
285 * within the device's PCI configuration space or 0 if the device does
286 * not support it. Possible values for @cap:
288 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
289 * %PCI_EXT_CAP_ID_VC Virtual Channel
290 * %PCI_EXT_CAP_ID_DSN Device Serial Number
291 * %PCI_EXT_CAP_ID_PWR Power Budgeting
293 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
297 int pos
= PCI_CFG_SPACE_SIZE
;
299 /* minimum 8 bytes per capability */
300 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
302 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
305 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
309 * If we have no capabilities, this is indicated by cap ID,
310 * cap version and next pointer all being 0.
316 if (PCI_EXT_CAP_ID(header
) == cap
)
319 pos
= PCI_EXT_CAP_NEXT(header
);
320 if (pos
< PCI_CFG_SPACE_SIZE
)
323 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
329 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
332 * pci_bus_find_ext_capability - find an extended capability
333 * @bus: the PCI bus to query
334 * @devfn: PCI device to query
335 * @cap: capability code
337 * Like pci_find_ext_capability() but works for pci devices that do not have a
338 * pci_dev structure set up yet.
340 * Returns the address of the requested capability structure within the
341 * device's PCI configuration space or 0 in case the device does not
344 int pci_bus_find_ext_capability(struct pci_bus
*bus
, unsigned int devfn
,
349 int pos
= PCI_CFG_SPACE_SIZE
;
351 /* minimum 8 bytes per capability */
352 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
354 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
356 if (header
== 0xffffffff || header
== 0)
360 if (PCI_EXT_CAP_ID(header
) == cap
)
363 pos
= PCI_EXT_CAP_NEXT(header
);
364 if (pos
< PCI_CFG_SPACE_SIZE
)
367 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
374 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
376 int rc
, ttl
= PCI_FIND_CAP_TTL
;
379 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
380 mask
= HT_3BIT_CAP_MASK
;
382 mask
= HT_5BIT_CAP_MASK
;
384 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
385 PCI_CAP_ID_HT
, &ttl
);
387 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
388 if (rc
!= PCIBIOS_SUCCESSFUL
)
391 if ((cap
& mask
) == ht_cap
)
394 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
395 pos
+ PCI_CAP_LIST_NEXT
,
396 PCI_CAP_ID_HT
, &ttl
);
402 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
403 * @dev: PCI device to query
404 * @pos: Position from which to continue searching
405 * @ht_cap: Hypertransport capability code
407 * To be used in conjunction with pci_find_ht_capability() to search for
408 * all capabilities matching @ht_cap. @pos should always be a value returned
409 * from pci_find_ht_capability().
411 * NB. To be 100% safe against broken PCI devices, the caller should take
412 * steps to avoid an infinite loop.
414 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
416 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
418 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
421 * pci_find_ht_capability - query a device's Hypertransport capabilities
422 * @dev: PCI device to query
423 * @ht_cap: Hypertransport capability code
425 * Tell if a device supports a given Hypertransport capability.
426 * Returns an address within the device's PCI configuration space
427 * or 0 in case the device does not support the request capability.
428 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
429 * which has a Hypertransport capability matching @ht_cap.
431 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
435 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
437 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
441 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
444 * pci_find_parent_resource - return resource region of parent bus of given region
445 * @dev: PCI device structure contains resources to be searched
446 * @res: child resource record for which parent is sought
448 * For given resource region of given device, return the resource
449 * region of parent bus the given region is contained in or where
450 * it should be allocated from.
453 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
455 const struct pci_bus
*bus
= dev
->bus
;
457 struct resource
*best
= NULL
, *r
;
459 pci_bus_for_each_resource(bus
, r
, i
) {
462 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
463 continue; /* Not contained */
464 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
465 continue; /* Wrong type */
466 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
467 return r
; /* Exact match */
468 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
469 if (r
->flags
& IORESOURCE_PREFETCH
)
471 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
479 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
480 * @dev: PCI device to have its BARs restored
482 * Restore the BAR values for a given device, so as to make it
483 * accessible by its driver.
486 pci_restore_bars(struct pci_dev
*dev
)
490 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
491 pci_update_resource(dev
, i
);
494 static struct pci_platform_pm_ops
*pci_platform_pm
;
496 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
498 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
499 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
501 pci_platform_pm
= ops
;
505 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
507 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
510 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
513 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
516 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
518 return pci_platform_pm
?
519 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
522 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
524 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
527 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
529 return pci_platform_pm
?
530 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
533 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
535 return pci_platform_pm
?
536 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
540 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
542 * @dev: PCI device to handle.
543 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
546 * -EINVAL if the requested state is invalid.
547 * -EIO if device does not support PCI PM or its PM capabilities register has a
548 * wrong version, or device doesn't support the requested state.
549 * 0 if device already is in the requested state.
550 * 0 if device's power state has been successfully changed.
552 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
555 bool need_restore
= false;
557 /* Check if we're already there */
558 if (dev
->current_state
== state
)
564 if (state
< PCI_D0
|| state
> PCI_D3hot
)
567 /* Validate current state:
568 * Can enter D0 from any state, but if we can only go deeper
569 * to sleep if we're already in a low power state
571 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
572 && dev
->current_state
> state
) {
573 dev_err(&dev
->dev
, "invalid power transition "
574 "(from state %d to %d)\n", dev
->current_state
, state
);
578 /* check if this device supports the desired state */
579 if ((state
== PCI_D1
&& !dev
->d1_support
)
580 || (state
== PCI_D2
&& !dev
->d2_support
))
583 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
585 /* If we're (effectively) in D3, force entire word to 0.
586 * This doesn't affect PME_Status, disables PME_En, and
587 * sets PowerState to 0.
589 switch (dev
->current_state
) {
593 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
598 case PCI_UNKNOWN
: /* Boot-up */
599 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
600 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
602 /* Fall-through: force to D0 */
608 /* enter specified state */
609 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
611 /* Mandatory power management transition delays */
612 /* see PCI PM 1.1 5.6.1 table 18 */
613 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
614 pci_dev_d3_sleep(dev
);
615 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
616 udelay(PCI_PM_D2_DELAY
);
618 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
619 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
620 if (dev
->current_state
!= state
&& printk_ratelimit())
621 dev_info(&dev
->dev
, "Refused to change power state, "
622 "currently in D%d\n", dev
->current_state
);
624 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
625 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
626 * from D3hot to D0 _may_ perform an internal reset, thereby
627 * going to "D0 Uninitialized" rather than "D0 Initialized".
628 * For example, at least some versions of the 3c905B and the
629 * 3c556B exhibit this behaviour.
631 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
632 * devices in a D3hot state at boot. Consequently, we need to
633 * restore at least the BARs so that the device will be
634 * accessible to its driver.
637 pci_restore_bars(dev
);
640 pcie_aspm_pm_state_change(dev
->bus
->self
);
646 * pci_update_current_state - Read PCI power state of given device from its
647 * PCI PM registers and cache it
648 * @dev: PCI device to handle.
649 * @state: State to cache in case the device doesn't have the PM capability
651 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
656 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
657 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
659 dev
->current_state
= state
;
664 * pci_platform_power_transition - Use platform to change device power state
665 * @dev: PCI device to handle.
666 * @state: State to put the device into.
668 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
672 if (platform_pci_power_manageable(dev
)) {
673 error
= platform_pci_set_power_state(dev
, state
);
675 pci_update_current_state(dev
, state
);
676 /* Fall back to PCI_D0 if native PM is not supported */
678 dev
->current_state
= PCI_D0
;
681 /* Fall back to PCI_D0 if native PM is not supported */
683 dev
->current_state
= PCI_D0
;
690 * __pci_start_power_transition - Start power transition of a PCI device
691 * @dev: PCI device to handle.
692 * @state: State to put the device into.
694 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
697 pci_platform_power_transition(dev
, PCI_D0
);
701 * __pci_complete_power_transition - Complete power transition of a PCI device
702 * @dev: PCI device to handle.
703 * @state: State to put the device into.
705 * This function should not be called directly by device drivers.
707 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
709 return state
>= PCI_D0
?
710 pci_platform_power_transition(dev
, state
) : -EINVAL
;
712 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
715 * pci_set_power_state - Set the power state of a PCI device
716 * @dev: PCI device to handle.
717 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
719 * Transition a device to a new power state, using the platform firmware and/or
720 * the device's PCI PM registers.
723 * -EINVAL if the requested state is invalid.
724 * -EIO if device does not support PCI PM or its PM capabilities register has a
725 * wrong version, or device doesn't support the requested state.
726 * 0 if device already is in the requested state.
727 * 0 if device's power state has been successfully changed.
729 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
733 /* bound the state we're entering */
734 if (state
> PCI_D3hot
)
736 else if (state
< PCI_D0
)
738 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
740 * If the device or the parent bridge do not support PCI PM,
741 * ignore the request if we're doing anything other than putting
742 * it into D0 (which would only happen on boot).
746 __pci_start_power_transition(dev
, state
);
748 /* This device is quirked not to be put into D3, so
749 don't put it in D3 */
750 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
753 error
= pci_raw_set_power_state(dev
, state
);
755 if (!__pci_complete_power_transition(dev
, state
))
758 * When aspm_policy is "powersave" this call ensures
759 * that ASPM is configured.
761 if (!error
&& dev
->bus
->self
)
762 pcie_aspm_powersave_config_link(dev
->bus
->self
);
768 * pci_choose_state - Choose the power state of a PCI device
769 * @dev: PCI device to be suspended
770 * @state: target sleep state for the whole system. This is the value
771 * that is passed to suspend() function.
773 * Returns PCI power state suitable for given device and given system
777 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
781 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
784 ret
= platform_pci_choose_state(dev
);
785 if (ret
!= PCI_POWER_ERROR
)
788 switch (state
.event
) {
791 case PM_EVENT_FREEZE
:
792 case PM_EVENT_PRETHAW
:
793 /* REVISIT both freeze and pre-thaw "should" use D0 */
794 case PM_EVENT_SUSPEND
:
795 case PM_EVENT_HIBERNATE
:
798 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
805 EXPORT_SYMBOL(pci_choose_state
);
807 #define PCI_EXP_SAVE_REGS 7
809 #define pcie_cap_has_devctl(type, flags) 1
810 #define pcie_cap_has_lnkctl(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
812 (type == PCI_EXP_TYPE_ROOT_PORT || \
813 type == PCI_EXP_TYPE_ENDPOINT || \
814 type == PCI_EXP_TYPE_LEG_END))
815 #define pcie_cap_has_sltctl(type, flags) \
816 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
817 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
818 (type == PCI_EXP_TYPE_DOWNSTREAM && \
819 (flags & PCI_EXP_FLAGS_SLOT))))
820 #define pcie_cap_has_rtctl(type, flags) \
821 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
822 (type == PCI_EXP_TYPE_ROOT_PORT || \
823 type == PCI_EXP_TYPE_RC_EC))
824 #define pcie_cap_has_devctl2(type, flags) \
825 ((flags & PCI_EXP_FLAGS_VERS) > 1)
826 #define pcie_cap_has_lnkctl2(type, flags) \
827 ((flags & PCI_EXP_FLAGS_VERS) > 1)
828 #define pcie_cap_has_sltctl2(type, flags) \
829 ((flags & PCI_EXP_FLAGS_VERS) > 1)
831 static struct pci_cap_saved_state
*pci_find_saved_cap(
832 struct pci_dev
*pci_dev
, char cap
)
834 struct pci_cap_saved_state
*tmp
;
835 struct hlist_node
*pos
;
837 hlist_for_each_entry(tmp
, pos
, &pci_dev
->saved_cap_space
, next
) {
838 if (tmp
->cap
.cap_nr
== cap
)
844 static int pci_save_pcie_state(struct pci_dev
*dev
)
847 struct pci_cap_saved_state
*save_state
;
851 pos
= pci_pcie_cap(dev
);
855 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
857 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
860 cap
= (u16
*)&save_state
->cap
.data
[0];
862 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
864 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
865 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
866 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
867 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
868 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
869 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
870 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
871 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
872 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
873 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
874 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
875 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
876 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
877 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
882 static void pci_restore_pcie_state(struct pci_dev
*dev
)
885 struct pci_cap_saved_state
*save_state
;
889 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
890 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
891 if (!save_state
|| pos
<= 0)
893 cap
= (u16
*)&save_state
->cap
.data
[0];
895 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
897 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
898 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
899 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
900 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
901 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
902 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
903 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
904 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
905 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
906 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
907 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
908 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
909 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
910 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
914 static int pci_save_pcix_state(struct pci_dev
*dev
)
917 struct pci_cap_saved_state
*save_state
;
919 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
923 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
925 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
929 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
930 (u16
*)save_state
->cap
.data
);
935 static void pci_restore_pcix_state(struct pci_dev
*dev
)
938 struct pci_cap_saved_state
*save_state
;
941 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
942 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
943 if (!save_state
|| pos
<= 0)
945 cap
= (u16
*)&save_state
->cap
.data
[0];
947 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
952 * pci_save_state - save the PCI configuration space of a device before suspending
953 * @dev: - PCI device that we're dealing with
956 pci_save_state(struct pci_dev
*dev
)
959 /* XXX: 100% dword access ok here? */
960 for (i
= 0; i
< 16; i
++)
961 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
962 dev
->state_saved
= true;
963 if ((i
= pci_save_pcie_state(dev
)) != 0)
965 if ((i
= pci_save_pcix_state(dev
)) != 0)
971 * pci_restore_state - Restore the saved state of a PCI device
972 * @dev: - PCI device that we're dealing with
974 void pci_restore_state(struct pci_dev
*dev
)
980 if (!dev
->state_saved
)
983 /* PCI Express register must be restored first */
984 pci_restore_pcie_state(dev
);
985 pci_restore_ats_state(dev
);
988 * The Base Address register should be programmed before the command
991 for (i
= 15; i
>= 0; i
--) {
992 pci_read_config_dword(dev
, i
* 4, &val
);
994 while (tries
&& val
!= dev
->saved_config_space
[i
]) {
995 dev_dbg(&dev
->dev
, "restoring config "
996 "space at offset %#x (was %#x, writing %#x)\n",
997 i
, val
, (int)dev
->saved_config_space
[i
]);
998 pci_write_config_dword(dev
,i
* 4,
999 dev
->saved_config_space
[i
]);
1000 pci_read_config_dword(dev
, i
* 4, &val
);
1005 pci_restore_pcix_state(dev
);
1006 pci_restore_msi_state(dev
);
1007 pci_restore_iov_state(dev
);
1009 dev
->state_saved
= false;
1012 struct pci_saved_state
{
1013 u32 config_space
[16];
1014 struct pci_cap_saved_data cap
[0];
1018 * pci_store_saved_state - Allocate and return an opaque struct containing
1019 * the device saved state.
1020 * @dev: PCI device that we're dealing with
1022 * Rerturn NULL if no state or error.
1024 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1026 struct pci_saved_state
*state
;
1027 struct pci_cap_saved_state
*tmp
;
1028 struct pci_cap_saved_data
*cap
;
1029 struct hlist_node
*pos
;
1032 if (!dev
->state_saved
)
1035 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1037 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
)
1038 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1040 state
= kzalloc(size
, GFP_KERNEL
);
1044 memcpy(state
->config_space
, dev
->saved_config_space
,
1045 sizeof(state
->config_space
));
1048 hlist_for_each_entry(tmp
, pos
, &dev
->saved_cap_space
, next
) {
1049 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1050 memcpy(cap
, &tmp
->cap
, len
);
1051 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1053 /* Empty cap_save terminates list */
1057 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1060 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1061 * @dev: PCI device that we're dealing with
1062 * @state: Saved state returned from pci_store_saved_state()
1064 int pci_load_saved_state(struct pci_dev
*dev
, struct pci_saved_state
*state
)
1066 struct pci_cap_saved_data
*cap
;
1068 dev
->state_saved
= false;
1073 memcpy(dev
->saved_config_space
, state
->config_space
,
1074 sizeof(state
->config_space
));
1078 struct pci_cap_saved_state
*tmp
;
1080 tmp
= pci_find_saved_cap(dev
, cap
->cap_nr
);
1081 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1084 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1085 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1086 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1089 dev
->state_saved
= true;
1092 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1095 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1096 * and free the memory allocated for it.
1097 * @dev: PCI device that we're dealing with
1098 * @state: Pointer to saved state returned from pci_store_saved_state()
1100 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1101 struct pci_saved_state
**state
)
1103 int ret
= pci_load_saved_state(dev
, *state
);
1108 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1110 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1114 err
= pci_set_power_state(dev
, PCI_D0
);
1115 if (err
< 0 && err
!= -EIO
)
1117 err
= pcibios_enable_device(dev
, bars
);
1120 pci_fixup_device(pci_fixup_enable
, dev
);
1126 * pci_reenable_device - Resume abandoned device
1127 * @dev: PCI device to be resumed
1129 * Note this function is a backend of pci_default_resume and is not supposed
1130 * to be called by normal code, write proper resume handler and use it instead.
1132 int pci_reenable_device(struct pci_dev
*dev
)
1134 if (pci_is_enabled(dev
))
1135 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1139 static int __pci_enable_device_flags(struct pci_dev
*dev
,
1140 resource_size_t flags
)
1146 * Power state could be unknown at this point, either due to a fresh
1147 * boot or a device removal call. So get the current power state
1148 * so that things like MSI message writing will behave as expected
1149 * (e.g. if the device really is in D0 at enable time).
1153 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1154 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1157 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
1158 return 0; /* already enabled */
1160 /* only skip sriov related */
1161 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1162 if (dev
->resource
[i
].flags
& flags
)
1164 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1165 if (dev
->resource
[i
].flags
& flags
)
1168 err
= do_pci_enable_device(dev
, bars
);
1170 atomic_dec(&dev
->enable_cnt
);
1175 * pci_enable_device_io - Initialize a device for use with IO space
1176 * @dev: PCI device to be initialized
1178 * Initialize device before it's used by a driver. Ask low-level code
1179 * to enable I/O resources. Wake up the device if it was suspended.
1180 * Beware, this function can fail.
1182 int pci_enable_device_io(struct pci_dev
*dev
)
1184 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1188 * pci_enable_device_mem - Initialize a device for use with Memory space
1189 * @dev: PCI device to be initialized
1191 * Initialize device before it's used by a driver. Ask low-level code
1192 * to enable Memory resources. Wake up the device if it was suspended.
1193 * Beware, this function can fail.
1195 int pci_enable_device_mem(struct pci_dev
*dev
)
1197 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1201 * pci_enable_device - Initialize device before it's used by a driver.
1202 * @dev: PCI device to be initialized
1204 * Initialize device before it's used by a driver. Ask low-level code
1205 * to enable I/O and memory. Wake up the device if it was suspended.
1206 * Beware, this function can fail.
1208 * Note we don't actually enable the device many times if we call
1209 * this function repeatedly (we just increment the count).
1211 int pci_enable_device(struct pci_dev
*dev
)
1213 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1217 * Managed PCI resources. This manages device on/off, intx/msi/msix
1218 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1219 * there's no need to track it separately. pci_devres is initialized
1220 * when a device is enabled using managed PCI device enable interface.
1223 unsigned int enabled
:1;
1224 unsigned int pinned
:1;
1225 unsigned int orig_intx
:1;
1226 unsigned int restore_intx
:1;
1230 static void pcim_release(struct device
*gendev
, void *res
)
1232 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1233 struct pci_devres
*this = res
;
1236 if (dev
->msi_enabled
)
1237 pci_disable_msi(dev
);
1238 if (dev
->msix_enabled
)
1239 pci_disable_msix(dev
);
1241 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1242 if (this->region_mask
& (1 << i
))
1243 pci_release_region(dev
, i
);
1245 if (this->restore_intx
)
1246 pci_intx(dev
, this->orig_intx
);
1248 if (this->enabled
&& !this->pinned
)
1249 pci_disable_device(dev
);
1252 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1254 struct pci_devres
*dr
, *new_dr
;
1256 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1260 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1263 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1266 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1268 if (pci_is_managed(pdev
))
1269 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1274 * pcim_enable_device - Managed pci_enable_device()
1275 * @pdev: PCI device to be initialized
1277 * Managed pci_enable_device().
1279 int pcim_enable_device(struct pci_dev
*pdev
)
1281 struct pci_devres
*dr
;
1284 dr
= get_pci_dr(pdev
);
1290 rc
= pci_enable_device(pdev
);
1292 pdev
->is_managed
= 1;
1299 * pcim_pin_device - Pin managed PCI device
1300 * @pdev: PCI device to pin
1302 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1303 * driver detach. @pdev must have been enabled with
1304 * pcim_enable_device().
1306 void pcim_pin_device(struct pci_dev
*pdev
)
1308 struct pci_devres
*dr
;
1310 dr
= find_pci_dr(pdev
);
1311 WARN_ON(!dr
|| !dr
->enabled
);
1317 * pcibios_disable_device - disable arch specific PCI resources for device dev
1318 * @dev: the PCI device to disable
1320 * Disables architecture specific PCI resources for the device. This
1321 * is the default implementation. Architecture implementations can
1324 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1326 static void do_pci_disable_device(struct pci_dev
*dev
)
1330 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1331 if (pci_command
& PCI_COMMAND_MASTER
) {
1332 pci_command
&= ~PCI_COMMAND_MASTER
;
1333 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1336 pcibios_disable_device(dev
);
1340 * pci_disable_enabled_device - Disable device without updating enable_cnt
1341 * @dev: PCI device to disable
1343 * NOTE: This function is a backend of PCI power management routines and is
1344 * not supposed to be called drivers.
1346 void pci_disable_enabled_device(struct pci_dev
*dev
)
1348 if (pci_is_enabled(dev
))
1349 do_pci_disable_device(dev
);
1353 * pci_disable_device - Disable PCI device after use
1354 * @dev: PCI device to be disabled
1356 * Signal to the system that the PCI device is not in use by the system
1357 * anymore. This only involves disabling PCI bus-mastering, if active.
1359 * Note we don't actually disable the device until all callers of
1360 * pci_enable_device() have called pci_disable_device().
1363 pci_disable_device(struct pci_dev
*dev
)
1365 struct pci_devres
*dr
;
1367 dr
= find_pci_dr(dev
);
1371 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1374 do_pci_disable_device(dev
);
1376 dev
->is_busmaster
= 0;
1380 * pcibios_set_pcie_reset_state - set reset state for device dev
1381 * @dev: the PCIe device reset
1382 * @state: Reset state to enter into
1385 * Sets the PCIe reset state for the device. This is the default
1386 * implementation. Architecture implementations can override this.
1388 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1389 enum pcie_reset_state state
)
1395 * pci_set_pcie_reset_state - set reset state for device dev
1396 * @dev: the PCIe device reset
1397 * @state: Reset state to enter into
1400 * Sets the PCI reset state for the device.
1402 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1404 return pcibios_set_pcie_reset_state(dev
, state
);
1408 * pci_check_pme_status - Check if given device has generated PME.
1409 * @dev: Device to check.
1411 * Check the PME status of the device and if set, clear it and clear PME enable
1412 * (if set). Return 'true' if PME status and PME enable were both set or
1413 * 'false' otherwise.
1415 bool pci_check_pme_status(struct pci_dev
*dev
)
1424 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1425 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1426 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1429 /* Clear PME status. */
1430 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1431 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1432 /* Disable PME to avoid interrupt flood. */
1433 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1437 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1443 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1444 * @dev: Device to handle.
1445 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1447 * Check if @dev has generated PME and queue a resume request for it in that
1450 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1452 if (pme_poll_reset
&& dev
->pme_poll
)
1453 dev
->pme_poll
= false;
1455 if (pci_check_pme_status(dev
)) {
1456 pci_wakeup_event(dev
);
1457 pm_request_resume(&dev
->dev
);
1463 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1464 * @bus: Top bus of the subtree to walk.
1466 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1469 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1473 * pci_pme_capable - check the capability of PCI device to generate PME#
1474 * @dev: PCI device to handle.
1475 * @state: PCI state from which device will issue PME#.
1477 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1482 return !!(dev
->pme_support
& (1 << state
));
1485 static void pci_pme_list_scan(struct work_struct
*work
)
1487 struct pci_pme_device
*pme_dev
, *n
;
1489 mutex_lock(&pci_pme_list_mutex
);
1490 if (!list_empty(&pci_pme_list
)) {
1491 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1492 if (pme_dev
->dev
->pme_poll
) {
1493 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1495 list_del(&pme_dev
->list
);
1499 if (!list_empty(&pci_pme_list
))
1500 schedule_delayed_work(&pci_pme_work
,
1501 msecs_to_jiffies(PME_TIMEOUT
));
1503 mutex_unlock(&pci_pme_list_mutex
);
1507 * pci_pme_active - enable or disable PCI device's PME# function
1508 * @dev: PCI device to handle.
1509 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1511 * The caller must verify that the device is capable of generating PME# before
1512 * calling this function with @enable equal to 'true'.
1514 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1521 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1522 /* Clear PME_Status by writing 1 to it and enable PME# */
1523 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1525 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1527 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1529 /* PCI (as opposed to PCIe) PME requires that the device have
1530 its PME# line hooked up correctly. Not all hardware vendors
1531 do this, so the PME never gets delivered and the device
1532 remains asleep. The easiest way around this is to
1533 periodically walk the list of suspended devices and check
1534 whether any have their PME flag set. The assumption is that
1535 we'll wake up often enough anyway that this won't be a huge
1536 hit, and the power savings from the devices will still be a
1539 if (dev
->pme_poll
) {
1540 struct pci_pme_device
*pme_dev
;
1542 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1547 mutex_lock(&pci_pme_list_mutex
);
1548 list_add(&pme_dev
->list
, &pci_pme_list
);
1549 if (list_is_singular(&pci_pme_list
))
1550 schedule_delayed_work(&pci_pme_work
,
1551 msecs_to_jiffies(PME_TIMEOUT
));
1552 mutex_unlock(&pci_pme_list_mutex
);
1554 mutex_lock(&pci_pme_list_mutex
);
1555 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1556 if (pme_dev
->dev
== dev
) {
1557 list_del(&pme_dev
->list
);
1562 mutex_unlock(&pci_pme_list_mutex
);
1567 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1571 * __pci_enable_wake - enable PCI device as wakeup event source
1572 * @dev: PCI device affected
1573 * @state: PCI state from which device will issue wakeup events
1574 * @runtime: True if the events are to be generated at run time
1575 * @enable: True to enable event generation; false to disable
1577 * This enables the device as a wakeup event source, or disables it.
1578 * When such events involves platform-specific hooks, those hooks are
1579 * called automatically by this routine.
1581 * Devices with legacy power management (no standard PCI PM capabilities)
1582 * always require such platform hooks.
1585 * 0 is returned on success
1586 * -EINVAL is returned if device is not supposed to wake up the system
1587 * Error code depending on the platform is returned if both the platform and
1588 * the native mechanism fail to enable the generation of wake-up events
1590 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1591 bool runtime
, bool enable
)
1595 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1598 /* Don't do the same thing twice in a row for one device. */
1599 if (!!enable
== !!dev
->wakeup_prepared
)
1603 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1604 * Anderson we should be doing PME# wake enable followed by ACPI wake
1605 * enable. To disable wake-up we call the platform first, for symmetry.
1611 if (pci_pme_capable(dev
, state
))
1612 pci_pme_active(dev
, true);
1615 error
= runtime
? platform_pci_run_wake(dev
, true) :
1616 platform_pci_sleep_wake(dev
, true);
1620 dev
->wakeup_prepared
= true;
1623 platform_pci_run_wake(dev
, false);
1625 platform_pci_sleep_wake(dev
, false);
1626 pci_pme_active(dev
, false);
1627 dev
->wakeup_prepared
= false;
1632 EXPORT_SYMBOL(__pci_enable_wake
);
1635 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1636 * @dev: PCI device to prepare
1637 * @enable: True to enable wake-up event generation; false to disable
1639 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1640 * and this function allows them to set that up cleanly - pci_enable_wake()
1641 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1642 * ordering constraints.
1644 * This function only returns error code if the device is not capable of
1645 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1646 * enable wake-up power for it.
1648 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1650 return pci_pme_capable(dev
, PCI_D3cold
) ?
1651 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1652 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1656 * pci_target_state - find an appropriate low power state for a given PCI dev
1659 * Use underlying platform code to find a supported low power state for @dev.
1660 * If the platform can't manage @dev, return the deepest state from which it
1661 * can generate wake events, based on any available PME info.
1663 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1665 pci_power_t target_state
= PCI_D3hot
;
1667 if (platform_pci_power_manageable(dev
)) {
1669 * Call the platform to choose the target state of the device
1670 * and enable wake-up from this state if supported.
1672 pci_power_t state
= platform_pci_choose_state(dev
);
1675 case PCI_POWER_ERROR
:
1680 if (pci_no_d1d2(dev
))
1683 target_state
= state
;
1685 } else if (!dev
->pm_cap
) {
1686 target_state
= PCI_D0
;
1687 } else if (device_may_wakeup(&dev
->dev
)) {
1689 * Find the deepest state from which the device can generate
1690 * wake-up events, make it the target state and enable device
1693 if (dev
->pme_support
) {
1695 && !(dev
->pme_support
& (1 << target_state
)))
1700 return target_state
;
1704 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1705 * @dev: Device to handle.
1707 * Choose the power state appropriate for the device depending on whether
1708 * it can wake up the system and/or is power manageable by the platform
1709 * (PCI_D3hot is the default) and put the device into that state.
1711 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1713 pci_power_t target_state
= pci_target_state(dev
);
1716 if (target_state
== PCI_POWER_ERROR
)
1719 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1721 error
= pci_set_power_state(dev
, target_state
);
1724 pci_enable_wake(dev
, target_state
, false);
1730 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1731 * @dev: Device to handle.
1733 * Disable device's system wake-up capability and put it into D0.
1735 int pci_back_from_sleep(struct pci_dev
*dev
)
1737 pci_enable_wake(dev
, PCI_D0
, false);
1738 return pci_set_power_state(dev
, PCI_D0
);
1742 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1743 * @dev: PCI device being suspended.
1745 * Prepare @dev to generate wake-up events at run time and put it into a low
1748 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1750 pci_power_t target_state
= pci_target_state(dev
);
1753 if (target_state
== PCI_POWER_ERROR
)
1756 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1758 error
= pci_set_power_state(dev
, target_state
);
1761 __pci_enable_wake(dev
, target_state
, true, false);
1767 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1768 * @dev: Device to check.
1770 * Return true if the device itself is cabable of generating wake-up events
1771 * (through the platform or using the native PCIe PME) or if the device supports
1772 * PME and one of its upstream bridges can generate wake-up events.
1774 bool pci_dev_run_wake(struct pci_dev
*dev
)
1776 struct pci_bus
*bus
= dev
->bus
;
1778 if (device_run_wake(&dev
->dev
))
1781 if (!dev
->pme_support
)
1784 while (bus
->parent
) {
1785 struct pci_dev
*bridge
= bus
->self
;
1787 if (device_run_wake(&bridge
->dev
))
1793 /* We have reached the root bus. */
1795 return device_run_wake(bus
->bridge
);
1799 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1802 * pci_pm_init - Initialize PM functions of given PCI device
1803 * @dev: PCI device to handle.
1805 void pci_pm_init(struct pci_dev
*dev
)
1810 pm_runtime_forbid(&dev
->dev
);
1811 device_enable_async_suspend(&dev
->dev
);
1812 dev
->wakeup_prepared
= false;
1816 /* find PCI PM capability in list */
1817 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1820 /* Check device's ability to generate PME# */
1821 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1823 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1824 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1825 pmc
& PCI_PM_CAP_VER_MASK
);
1830 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1832 dev
->d1_support
= false;
1833 dev
->d2_support
= false;
1834 if (!pci_no_d1d2(dev
)) {
1835 if (pmc
& PCI_PM_CAP_D1
)
1836 dev
->d1_support
= true;
1837 if (pmc
& PCI_PM_CAP_D2
)
1838 dev
->d2_support
= true;
1840 if (dev
->d1_support
|| dev
->d2_support
)
1841 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1842 dev
->d1_support
? " D1" : "",
1843 dev
->d2_support
? " D2" : "");
1846 pmc
&= PCI_PM_CAP_PME_MASK
;
1848 dev_printk(KERN_DEBUG
, &dev
->dev
,
1849 "PME# supported from%s%s%s%s%s\n",
1850 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1851 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1852 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1853 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1854 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1855 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1856 dev
->pme_poll
= true;
1858 * Make device's PM flags reflect the wake-up capability, but
1859 * let the user space enable it to wake up the system as needed.
1861 device_set_wakeup_capable(&dev
->dev
, true);
1862 /* Disable the PME# generation functionality */
1863 pci_pme_active(dev
, false);
1865 dev
->pme_support
= 0;
1870 * platform_pci_wakeup_init - init platform wakeup if present
1873 * Some devices don't have PCI PM caps but can still generate wakeup
1874 * events through platform methods (like ACPI events). If @dev supports
1875 * platform wakeup events, set the device flag to indicate as much. This
1876 * may be redundant if the device also supports PCI PM caps, but double
1877 * initialization should be safe in that case.
1879 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1881 if (!platform_pci_can_wakeup(dev
))
1884 device_set_wakeup_capable(&dev
->dev
, true);
1885 platform_pci_sleep_wake(dev
, false);
1888 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
1889 struct pci_cap_saved_state
*new_cap
)
1891 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
1895 * pci_add_save_buffer - allocate buffer for saving given capability registers
1896 * @dev: the PCI device
1897 * @cap: the capability to allocate the buffer for
1898 * @size: requested size of the buffer
1900 static int pci_add_cap_save_buffer(
1901 struct pci_dev
*dev
, char cap
, unsigned int size
)
1904 struct pci_cap_saved_state
*save_state
;
1906 pos
= pci_find_capability(dev
, cap
);
1910 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1914 save_state
->cap
.cap_nr
= cap
;
1915 save_state
->cap
.size
= size
;
1916 pci_add_saved_cap(dev
, save_state
);
1922 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1923 * @dev: the PCI device
1925 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1929 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1930 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1933 "unable to preallocate PCI Express save buffer\n");
1935 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1938 "unable to preallocate PCI-X save buffer\n");
1941 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
1943 struct pci_cap_saved_state
*tmp
;
1944 struct hlist_node
*pos
, *n
;
1946 hlist_for_each_entry_safe(tmp
, pos
, n
, &dev
->saved_cap_space
, next
)
1951 * pci_enable_ari - enable ARI forwarding if hardware support it
1952 * @dev: the PCI device
1954 void pci_enable_ari(struct pci_dev
*dev
)
1959 struct pci_dev
*bridge
;
1961 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
1964 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1968 bridge
= dev
->bus
->self
;
1969 if (!bridge
|| !pci_is_pcie(bridge
))
1972 pos
= pci_pcie_cap(bridge
);
1976 /* ARI is a PCIe v2 feature */
1977 pci_read_config_word(bridge
, pos
+ PCI_EXP_FLAGS
, &flags
);
1978 if ((flags
& PCI_EXP_FLAGS_VERS
) < 2)
1981 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1982 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1985 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1986 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1987 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1989 bridge
->ari_enabled
= 1;
1993 * pci_enable_ido - enable ID-based ordering on a device
1994 * @dev: the PCI device
1995 * @type: which types of IDO to enable
1997 * Enable ID-based ordering on @dev. @type can contain the bits
1998 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1999 * which types of transactions are allowed to be re-ordered.
2001 void pci_enable_ido(struct pci_dev
*dev
, unsigned long type
)
2006 pos
= pci_pcie_cap(dev
);
2010 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2011 if (type
& PCI_EXP_IDO_REQUEST
)
2012 ctrl
|= PCI_EXP_IDO_REQ_EN
;
2013 if (type
& PCI_EXP_IDO_COMPLETION
)
2014 ctrl
|= PCI_EXP_IDO_CMP_EN
;
2015 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2017 EXPORT_SYMBOL(pci_enable_ido
);
2020 * pci_disable_ido - disable ID-based ordering on a device
2021 * @dev: the PCI device
2022 * @type: which types of IDO to disable
2024 void pci_disable_ido(struct pci_dev
*dev
, unsigned long type
)
2029 if (!pci_is_pcie(dev
))
2032 pos
= pci_pcie_cap(dev
);
2036 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2037 if (type
& PCI_EXP_IDO_REQUEST
)
2038 ctrl
&= ~PCI_EXP_IDO_REQ_EN
;
2039 if (type
& PCI_EXP_IDO_COMPLETION
)
2040 ctrl
&= ~PCI_EXP_IDO_CMP_EN
;
2041 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2043 EXPORT_SYMBOL(pci_disable_ido
);
2046 * pci_enable_obff - enable optimized buffer flush/fill
2048 * @type: type of signaling to use
2050 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2051 * signaling if possible, falling back to message signaling only if
2052 * WAKE# isn't supported. @type should indicate whether the PCIe link
2053 * be brought out of L0s or L1 to send the message. It should be either
2054 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2056 * If your device can benefit from receiving all messages, even at the
2057 * power cost of bringing the link back up from a low power state, use
2058 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2062 * Zero on success, appropriate error number on failure.
2064 int pci_enable_obff(struct pci_dev
*dev
, enum pci_obff_signal_type type
)
2071 if (!pci_is_pcie(dev
))
2074 pos
= pci_pcie_cap(dev
);
2078 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2079 if (!(cap
& PCI_EXP_OBFF_MASK
))
2080 return -ENOTSUPP
; /* no OBFF support at all */
2082 /* Make sure the topology supports OBFF as well */
2084 ret
= pci_enable_obff(dev
->bus
->self
, type
);
2089 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2090 if (cap
& PCI_EXP_OBFF_WAKE
)
2091 ctrl
|= PCI_EXP_OBFF_WAKE_EN
;
2094 case PCI_EXP_OBFF_SIGNAL_L0
:
2095 if (!(ctrl
& PCI_EXP_OBFF_WAKE_EN
))
2096 ctrl
|= PCI_EXP_OBFF_MSGA_EN
;
2098 case PCI_EXP_OBFF_SIGNAL_ALWAYS
:
2099 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2100 ctrl
|= PCI_EXP_OBFF_MSGB_EN
;
2103 WARN(1, "bad OBFF signal type\n");
2107 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2111 EXPORT_SYMBOL(pci_enable_obff
);
2114 * pci_disable_obff - disable optimized buffer flush/fill
2117 * Disable OBFF on @dev.
2119 void pci_disable_obff(struct pci_dev
*dev
)
2124 if (!pci_is_pcie(dev
))
2127 pos
= pci_pcie_cap(dev
);
2131 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2132 ctrl
&= ~PCI_EXP_OBFF_WAKE_EN
;
2133 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2135 EXPORT_SYMBOL(pci_disable_obff
);
2138 * pci_ltr_supported - check whether a device supports LTR
2142 * True if @dev supports latency tolerance reporting, false otherwise.
2144 bool pci_ltr_supported(struct pci_dev
*dev
)
2149 if (!pci_is_pcie(dev
))
2152 pos
= pci_pcie_cap(dev
);
2156 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
2158 return cap
& PCI_EXP_DEVCAP2_LTR
;
2160 EXPORT_SYMBOL(pci_ltr_supported
);
2163 * pci_enable_ltr - enable latency tolerance reporting
2166 * Enable LTR on @dev if possible, which means enabling it first on
2170 * Zero on success, errno on failure.
2172 int pci_enable_ltr(struct pci_dev
*dev
)
2178 if (!pci_ltr_supported(dev
))
2181 pos
= pci_pcie_cap(dev
);
2185 /* Only primary function can enable/disable LTR */
2186 if (PCI_FUNC(dev
->devfn
) != 0)
2189 /* Enable upstream ports first */
2191 ret
= pci_enable_ltr(dev
->bus
->self
);
2196 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2197 ctrl
|= PCI_EXP_LTR_EN
;
2198 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2202 EXPORT_SYMBOL(pci_enable_ltr
);
2205 * pci_disable_ltr - disable latency tolerance reporting
2208 void pci_disable_ltr(struct pci_dev
*dev
)
2213 if (!pci_ltr_supported(dev
))
2216 pos
= pci_pcie_cap(dev
);
2220 /* Only primary function can enable/disable LTR */
2221 if (PCI_FUNC(dev
->devfn
) != 0)
2224 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
2225 ctrl
&= ~PCI_EXP_LTR_EN
;
2226 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
2228 EXPORT_SYMBOL(pci_disable_ltr
);
2230 static int __pci_ltr_scale(int *val
)
2234 while (*val
> 1023) {
2235 *val
= (*val
+ 31) / 32;
2242 * pci_set_ltr - set LTR latency values
2244 * @snoop_lat_ns: snoop latency in nanoseconds
2245 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2247 * Figure out the scale and set the LTR values accordingly.
2249 int pci_set_ltr(struct pci_dev
*dev
, int snoop_lat_ns
, int nosnoop_lat_ns
)
2251 int pos
, ret
, snoop_scale
, nosnoop_scale
;
2254 if (!pci_ltr_supported(dev
))
2257 snoop_scale
= __pci_ltr_scale(&snoop_lat_ns
);
2258 nosnoop_scale
= __pci_ltr_scale(&nosnoop_lat_ns
);
2260 if (snoop_lat_ns
> PCI_LTR_VALUE_MASK
||
2261 nosnoop_lat_ns
> PCI_LTR_VALUE_MASK
)
2264 if ((snoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)) ||
2265 (nosnoop_scale
> (PCI_LTR_SCALE_MASK
>> PCI_LTR_SCALE_SHIFT
)))
2268 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
2272 val
= (snoop_scale
<< PCI_LTR_SCALE_SHIFT
) | snoop_lat_ns
;
2273 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, val
);
2277 val
= (nosnoop_scale
<< PCI_LTR_SCALE_SHIFT
) | nosnoop_lat_ns
;
2278 ret
= pci_write_config_word(dev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, val
);
2284 EXPORT_SYMBOL(pci_set_ltr
);
2286 static int pci_acs_enable
;
2289 * pci_request_acs - ask for ACS to be enabled if supported
2291 void pci_request_acs(void)
2297 * pci_enable_acs - enable ACS if hardware support it
2298 * @dev: the PCI device
2300 void pci_enable_acs(struct pci_dev
*dev
)
2306 if (!pci_acs_enable
)
2309 if (!pci_is_pcie(dev
))
2312 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2316 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2317 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2319 /* Source Validation */
2320 ctrl
|= (cap
& PCI_ACS_SV
);
2322 /* P2P Request Redirect */
2323 ctrl
|= (cap
& PCI_ACS_RR
);
2325 /* P2P Completion Redirect */
2326 ctrl
|= (cap
& PCI_ACS_CR
);
2328 /* Upstream Forwarding */
2329 ctrl
|= (cap
& PCI_ACS_UF
);
2331 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2335 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2336 * @dev: the PCI device
2337 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2339 * Perform INTx swizzling for a device behind one level of bridge. This is
2340 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2341 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2342 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2343 * the PCI Express Base Specification, Revision 2.1)
2345 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
2349 if (pci_ari_enabled(dev
->bus
))
2352 slot
= PCI_SLOT(dev
->devfn
);
2354 return (((pin
- 1) + slot
) % 4) + 1;
2358 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2366 while (!pci_is_root_bus(dev
->bus
)) {
2367 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2368 dev
= dev
->bus
->self
;
2375 * pci_common_swizzle - swizzle INTx all the way to root bridge
2376 * @dev: the PCI device
2377 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2379 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2380 * bridges all the way up to a PCI root bus.
2382 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2386 while (!pci_is_root_bus(dev
->bus
)) {
2387 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2388 dev
= dev
->bus
->self
;
2391 return PCI_SLOT(dev
->devfn
);
2395 * pci_release_region - Release a PCI bar
2396 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2397 * @bar: BAR to release
2399 * Releases the PCI I/O and memory resources previously reserved by a
2400 * successful call to pci_request_region. Call this function only
2401 * after all use of the PCI regions has ceased.
2403 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2405 struct pci_devres
*dr
;
2407 if (pci_resource_len(pdev
, bar
) == 0)
2409 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2410 release_region(pci_resource_start(pdev
, bar
),
2411 pci_resource_len(pdev
, bar
));
2412 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2413 release_mem_region(pci_resource_start(pdev
, bar
),
2414 pci_resource_len(pdev
, bar
));
2416 dr
= find_pci_dr(pdev
);
2418 dr
->region_mask
&= ~(1 << bar
);
2422 * __pci_request_region - Reserved PCI I/O and memory resource
2423 * @pdev: PCI device whose resources are to be reserved
2424 * @bar: BAR to be reserved
2425 * @res_name: Name to be associated with resource.
2426 * @exclusive: whether the region access is exclusive or not
2428 * Mark the PCI region associated with PCI device @pdev BR @bar as
2429 * being reserved by owner @res_name. Do not access any
2430 * address inside the PCI regions unless this call returns
2433 * If @exclusive is set, then the region is marked so that userspace
2434 * is explicitly not allowed to map the resource via /dev/mem or
2435 * sysfs MMIO access.
2437 * Returns 0 on success, or %EBUSY on error. A warning
2438 * message is also printed on failure.
2440 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2443 struct pci_devres
*dr
;
2445 if (pci_resource_len(pdev
, bar
) == 0)
2448 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2449 if (!request_region(pci_resource_start(pdev
, bar
),
2450 pci_resource_len(pdev
, bar
), res_name
))
2453 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2454 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2455 pci_resource_len(pdev
, bar
), res_name
,
2460 dr
= find_pci_dr(pdev
);
2462 dr
->region_mask
|= 1 << bar
;
2467 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2468 &pdev
->resource
[bar
]);
2473 * pci_request_region - Reserve PCI I/O and memory resource
2474 * @pdev: PCI device whose resources are to be reserved
2475 * @bar: BAR to be reserved
2476 * @res_name: Name to be associated with resource
2478 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2479 * being reserved by owner @res_name. Do not access any
2480 * address inside the PCI regions unless this call returns
2483 * Returns 0 on success, or %EBUSY on error. A warning
2484 * message is also printed on failure.
2486 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2488 return __pci_request_region(pdev
, bar
, res_name
, 0);
2492 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2493 * @pdev: PCI device whose resources are to be reserved
2494 * @bar: BAR to be reserved
2495 * @res_name: Name to be associated with resource.
2497 * Mark the PCI region associated with PCI device @pdev BR @bar as
2498 * being reserved by owner @res_name. Do not access any
2499 * address inside the PCI regions unless this call returns
2502 * Returns 0 on success, or %EBUSY on error. A warning
2503 * message is also printed on failure.
2505 * The key difference that _exclusive makes it that userspace is
2506 * explicitly not allowed to map the resource via /dev/mem or
2509 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2511 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2514 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2515 * @pdev: PCI device whose resources were previously reserved
2516 * @bars: Bitmask of BARs to be released
2518 * Release selected PCI I/O and memory resources previously reserved.
2519 * Call this function only after all use of the PCI regions has ceased.
2521 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2525 for (i
= 0; i
< 6; i
++)
2526 if (bars
& (1 << i
))
2527 pci_release_region(pdev
, i
);
2530 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2531 const char *res_name
, int excl
)
2535 for (i
= 0; i
< 6; i
++)
2536 if (bars
& (1 << i
))
2537 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2543 if (bars
& (1 << i
))
2544 pci_release_region(pdev
, i
);
2551 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2552 * @pdev: PCI device whose resources are to be reserved
2553 * @bars: Bitmask of BARs to be requested
2554 * @res_name: Name to be associated with resource
2556 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2557 const char *res_name
)
2559 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2562 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2563 int bars
, const char *res_name
)
2565 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2566 IORESOURCE_EXCLUSIVE
);
2570 * pci_release_regions - Release reserved PCI I/O and memory resources
2571 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2573 * Releases all PCI I/O and memory resources previously reserved by a
2574 * successful call to pci_request_regions. Call this function only
2575 * after all use of the PCI regions has ceased.
2578 void pci_release_regions(struct pci_dev
*pdev
)
2580 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2584 * pci_request_regions - Reserved PCI I/O and memory resources
2585 * @pdev: PCI device whose resources are to be reserved
2586 * @res_name: Name to be associated with resource.
2588 * Mark all PCI regions associated with PCI device @pdev as
2589 * being reserved by owner @res_name. Do not access any
2590 * address inside the PCI regions unless this call returns
2593 * Returns 0 on success, or %EBUSY on error. A warning
2594 * message is also printed on failure.
2596 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2598 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2602 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2603 * @pdev: PCI device whose resources are to be reserved
2604 * @res_name: Name to be associated with resource.
2606 * Mark all PCI regions associated with PCI device @pdev as
2607 * being reserved by owner @res_name. Do not access any
2608 * address inside the PCI regions unless this call returns
2611 * pci_request_regions_exclusive() will mark the region so that
2612 * /dev/mem and the sysfs MMIO access will not be allowed.
2614 * Returns 0 on success, or %EBUSY on error. A warning
2615 * message is also printed on failure.
2617 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2619 return pci_request_selected_regions_exclusive(pdev
,
2620 ((1 << 6) - 1), res_name
);
2623 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2627 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2629 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2631 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2632 if (cmd
!= old_cmd
) {
2633 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2634 enable
? "enabling" : "disabling");
2635 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2637 dev
->is_busmaster
= enable
;
2641 * pcibios_set_master - enable PCI bus-mastering for device dev
2642 * @dev: the PCI device to enable
2644 * Enables PCI bus-mastering for the device. This is the default
2645 * implementation. Architecture specific implementations can override
2646 * this if necessary.
2648 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2652 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2653 if (pci_is_pcie(dev
))
2656 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2658 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2659 else if (lat
> pcibios_max_latency
)
2660 lat
= pcibios_max_latency
;
2663 dev_printk(KERN_DEBUG
, &dev
->dev
, "setting latency timer to %d\n", lat
);
2664 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2668 * pci_set_master - enables bus-mastering for device dev
2669 * @dev: the PCI device to enable
2671 * Enables bus-mastering on the device and calls pcibios_set_master()
2672 * to do the needed arch specific settings.
2674 void pci_set_master(struct pci_dev
*dev
)
2676 __pci_set_master(dev
, true);
2677 pcibios_set_master(dev
);
2681 * pci_clear_master - disables bus-mastering for device dev
2682 * @dev: the PCI device to disable
2684 void pci_clear_master(struct pci_dev
*dev
)
2686 __pci_set_master(dev
, false);
2690 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2691 * @dev: the PCI device for which MWI is to be enabled
2693 * Helper function for pci_set_mwi.
2694 * Originally copied from drivers/net/acenic.c.
2695 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2697 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2699 int pci_set_cacheline_size(struct pci_dev
*dev
)
2703 if (!pci_cache_line_size
)
2706 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2707 equal to or multiple of the right value. */
2708 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2709 if (cacheline_size
>= pci_cache_line_size
&&
2710 (cacheline_size
% pci_cache_line_size
) == 0)
2713 /* Write the correct value. */
2714 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2716 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2717 if (cacheline_size
== pci_cache_line_size
)
2720 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2721 "supported\n", pci_cache_line_size
<< 2);
2725 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2727 #ifdef PCI_DISABLE_MWI
2728 int pci_set_mwi(struct pci_dev
*dev
)
2733 int pci_try_set_mwi(struct pci_dev
*dev
)
2738 void pci_clear_mwi(struct pci_dev
*dev
)
2745 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2746 * @dev: the PCI device for which MWI is enabled
2748 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2750 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2753 pci_set_mwi(struct pci_dev
*dev
)
2758 rc
= pci_set_cacheline_size(dev
);
2762 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2763 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2764 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2765 cmd
|= PCI_COMMAND_INVALIDATE
;
2766 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2773 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2774 * @dev: the PCI device for which MWI is enabled
2776 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2777 * Callers are not required to check the return value.
2779 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2781 int pci_try_set_mwi(struct pci_dev
*dev
)
2783 int rc
= pci_set_mwi(dev
);
2788 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2789 * @dev: the PCI device to disable
2791 * Disables PCI Memory-Write-Invalidate transaction on the device
2794 pci_clear_mwi(struct pci_dev
*dev
)
2798 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2799 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2800 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2801 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2804 #endif /* ! PCI_DISABLE_MWI */
2807 * pci_intx - enables/disables PCI INTx for device dev
2808 * @pdev: the PCI device to operate on
2809 * @enable: boolean: whether to enable or disable PCI INTx
2811 * Enables/disables PCI INTx for device dev
2814 pci_intx(struct pci_dev
*pdev
, int enable
)
2816 u16 pci_command
, new;
2818 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2821 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2823 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2826 if (new != pci_command
) {
2827 struct pci_devres
*dr
;
2829 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2831 dr
= find_pci_dr(pdev
);
2832 if (dr
&& !dr
->restore_intx
) {
2833 dr
->restore_intx
= 1;
2834 dr
->orig_intx
= !enable
;
2840 * pci_intx_mask_supported - probe for INTx masking support
2841 * @dev: the PCI device to operate on
2843 * Check if the device dev support INTx masking via the config space
2846 bool pci_intx_mask_supported(struct pci_dev
*dev
)
2848 bool mask_supported
= false;
2851 pci_cfg_access_lock(dev
);
2853 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
2854 pci_write_config_word(dev
, PCI_COMMAND
,
2855 orig
^ PCI_COMMAND_INTX_DISABLE
);
2856 pci_read_config_word(dev
, PCI_COMMAND
, &new);
2859 * There's no way to protect against hardware bugs or detect them
2860 * reliably, but as long as we know what the value should be, let's
2861 * go ahead and check it.
2863 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
2864 dev_err(&dev
->dev
, "Command register changed from "
2865 "0x%x to 0x%x: driver or hardware bug?\n", orig
, new);
2866 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
2867 mask_supported
= true;
2868 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
2871 pci_cfg_access_unlock(dev
);
2872 return mask_supported
;
2874 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
2876 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
2878 struct pci_bus
*bus
= dev
->bus
;
2879 bool mask_updated
= true;
2880 u32 cmd_status_dword
;
2881 u16 origcmd
, newcmd
;
2882 unsigned long flags
;
2886 * We do a single dword read to retrieve both command and status.
2887 * Document assumptions that make this possible.
2889 BUILD_BUG_ON(PCI_COMMAND
% 4);
2890 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
2892 raw_spin_lock_irqsave(&pci_lock
, flags
);
2894 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
2896 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
2899 * Check interrupt status register to see whether our device
2900 * triggered the interrupt (when masking) or the next IRQ is
2901 * already pending (when unmasking).
2903 if (mask
!= irq_pending
) {
2904 mask_updated
= false;
2908 origcmd
= cmd_status_dword
;
2909 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
2911 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
2912 if (newcmd
!= origcmd
)
2913 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
2916 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
2918 return mask_updated
;
2922 * pci_check_and_mask_intx - mask INTx on pending interrupt
2923 * @dev: the PCI device to operate on
2925 * Check if the device dev has its INTx line asserted, mask it and
2926 * return true in that case. False is returned if not interrupt was
2929 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
2931 return pci_check_and_set_intx_mask(dev
, true);
2933 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
2936 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2937 * @dev: the PCI device to operate on
2939 * Check if the device dev has its INTx line asserted, unmask it if not
2940 * and return true. False is returned and the mask remains active if
2941 * there was still an interrupt pending.
2943 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
2945 return pci_check_and_set_intx_mask(dev
, false);
2947 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
2950 * pci_msi_off - disables any msi or msix capabilities
2951 * @dev: the PCI device to operate on
2953 * If you want to use msi see pci_enable_msi and friends.
2954 * This is a lower level primitive that allows us to disable
2955 * msi operation at the device level.
2957 void pci_msi_off(struct pci_dev
*dev
)
2962 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2964 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2965 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2966 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2968 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2970 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2971 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2972 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2975 EXPORT_SYMBOL_GPL(pci_msi_off
);
2977 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2979 return dma_set_max_seg_size(&dev
->dev
, size
);
2981 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2983 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2985 return dma_set_seg_boundary(&dev
->dev
, mask
);
2987 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2989 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2994 u16 status
, control
;
2996 pos
= pci_pcie_cap(dev
);
3000 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
3001 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3007 /* Wait for Transaction Pending bit clean */
3008 for (i
= 0; i
< 4; i
++) {
3010 msleep((1 << (i
- 1)) * 100);
3012 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
3013 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
3017 dev_err(&dev
->dev
, "transaction is not cleared; "
3018 "proceeding with reset anyway\n");
3021 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
3022 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
3023 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
3030 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3037 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3041 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3042 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3048 /* Wait for Transaction Pending bit clean */
3049 for (i
= 0; i
< 4; i
++) {
3051 msleep((1 << (i
- 1)) * 100);
3053 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
3054 if (!(status
& PCI_AF_STATUS_TP
))
3058 dev_err(&dev
->dev
, "transaction is not cleared; "
3059 "proceeding with reset anyway\n");
3062 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3069 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3070 * @dev: Device to reset.
3071 * @probe: If set, only check if the device can be reset this way.
3073 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3074 * unset, it will be reinitialized internally when going from PCI_D3hot to
3075 * PCI_D0. If that's the case and the device is not in a low-power state
3076 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3078 * NOTE: This causes the caller to sleep for twice the device power transition
3079 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3080 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3081 * Moreover, only devices in D0 can be reset by this function.
3083 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3090 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3091 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3097 if (dev
->current_state
!= PCI_D0
)
3100 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3102 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3103 pci_dev_d3_sleep(dev
);
3105 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3107 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3108 pci_dev_d3_sleep(dev
);
3113 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3116 struct pci_dev
*pdev
;
3118 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
3121 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3128 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
3129 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3130 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3133 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3134 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
3140 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3147 pci_cfg_access_lock(dev
);
3148 /* block PM suspend, driver probe, etc. */
3149 device_lock(&dev
->dev
);
3152 rc
= pci_dev_specific_reset(dev
, probe
);
3156 rc
= pcie_flr(dev
, probe
);
3160 rc
= pci_af_flr(dev
, probe
);
3164 rc
= pci_pm_reset(dev
, probe
);
3168 rc
= pci_parent_bus_reset(dev
, probe
);
3171 device_unlock(&dev
->dev
);
3172 pci_cfg_access_unlock(dev
);
3179 * __pci_reset_function - reset a PCI device function
3180 * @dev: PCI device to reset
3182 * Some devices allow an individual function to be reset without affecting
3183 * other functions in the same device. The PCI device must be responsive
3184 * to PCI config space in order to use this function.
3186 * The device function is presumed to be unused when this function is called.
3187 * Resetting the device will make the contents of PCI configuration space
3188 * random, so any caller of this must be prepared to reinitialise the
3189 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3192 * Returns 0 if the device function was successfully reset or negative if the
3193 * device doesn't support resetting a single function.
3195 int __pci_reset_function(struct pci_dev
*dev
)
3197 return pci_dev_reset(dev
, 0);
3199 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3202 * __pci_reset_function_locked - reset a PCI device function while holding
3203 * the @dev mutex lock.
3204 * @dev: PCI device to reset
3206 * Some devices allow an individual function to be reset without affecting
3207 * other functions in the same device. The PCI device must be responsive
3208 * to PCI config space in order to use this function.
3210 * The device function is presumed to be unused and the caller is holding
3211 * the device mutex lock when this function is called.
3212 * Resetting the device will make the contents of PCI configuration space
3213 * random, so any caller of this must be prepared to reinitialise the
3214 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3217 * Returns 0 if the device function was successfully reset or negative if the
3218 * device doesn't support resetting a single function.
3220 int __pci_reset_function_locked(struct pci_dev
*dev
)
3222 return pci_dev_reset(dev
, 1);
3224 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3227 * pci_probe_reset_function - check whether the device can be safely reset
3228 * @dev: PCI device to reset
3230 * Some devices allow an individual function to be reset without affecting
3231 * other functions in the same device. The PCI device must be responsive
3232 * to PCI config space in order to use this function.
3234 * Returns 0 if the device function can be reset or negative if the
3235 * device doesn't support resetting a single function.
3237 int pci_probe_reset_function(struct pci_dev
*dev
)
3239 return pci_dev_reset(dev
, 1);
3243 * pci_reset_function - quiesce and reset a PCI device function
3244 * @dev: PCI device to reset
3246 * Some devices allow an individual function to be reset without affecting
3247 * other functions in the same device. The PCI device must be responsive
3248 * to PCI config space in order to use this function.
3250 * This function does not just reset the PCI portion of a device, but
3251 * clears all the state associated with the device. This function differs
3252 * from __pci_reset_function in that it saves and restores device state
3255 * Returns 0 if the device function was successfully reset or negative if the
3256 * device doesn't support resetting a single function.
3258 int pci_reset_function(struct pci_dev
*dev
)
3262 rc
= pci_dev_reset(dev
, 1);
3266 pci_save_state(dev
);
3269 * both INTx and MSI are disabled after the Interrupt Disable bit
3270 * is set and the Bus Master bit is cleared.
3272 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3274 rc
= pci_dev_reset(dev
, 0);
3276 pci_restore_state(dev
);
3280 EXPORT_SYMBOL_GPL(pci_reset_function
);
3283 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3284 * @dev: PCI device to query
3286 * Returns mmrbc: maximum designed memory read count in bytes
3287 * or appropriate error value.
3289 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3294 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3298 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3301 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3303 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3306 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3307 * @dev: PCI device to query
3309 * Returns mmrbc: maximum memory read count in bytes
3310 * or appropriate error value.
3312 int pcix_get_mmrbc(struct pci_dev
*dev
)
3317 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3321 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3324 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3326 EXPORT_SYMBOL(pcix_get_mmrbc
);
3329 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3330 * @dev: PCI device to query
3331 * @mmrbc: maximum memory read count in bytes
3332 * valid values are 512, 1024, 2048, 4096
3334 * If possible sets maximum memory read byte count, some bridges have erratas
3335 * that prevent this.
3337 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
3343 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
3346 v
= ffs(mmrbc
) - 10;
3348 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3352 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3355 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
3358 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3361 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
3363 if (v
> o
&& dev
->bus
&&
3364 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
3367 cmd
&= ~PCI_X_CMD_MAX_READ
;
3369 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
3374 EXPORT_SYMBOL(pcix_set_mmrbc
);
3377 * pcie_get_readrq - get PCI Express read request size
3378 * @dev: PCI device to query
3380 * Returns maximum memory read request in bytes
3381 * or appropriate error value.
3383 int pcie_get_readrq(struct pci_dev
*dev
)
3388 cap
= pci_pcie_cap(dev
);
3392 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3394 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
3398 EXPORT_SYMBOL(pcie_get_readrq
);
3401 * pcie_set_readrq - set PCI Express maximum memory read request
3402 * @dev: PCI device to query
3403 * @rq: maximum memory read count in bytes
3404 * valid values are 128, 256, 512, 1024, 2048, 4096
3406 * If possible sets maximum memory read request in bytes
3408 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
3410 int cap
, err
= -EINVAL
;
3413 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
3416 cap
= pci_pcie_cap(dev
);
3420 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3424 * If using the "performance" PCIe config, we clamp the
3425 * read rq size to the max packet size to prevent the
3426 * host bridge generating requests larger than we can
3429 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
3430 int mps
= pcie_get_mps(dev
);
3438 v
= (ffs(rq
) - 8) << 12;
3440 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
3441 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
3443 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3449 EXPORT_SYMBOL(pcie_set_readrq
);
3452 * pcie_get_mps - get PCI Express maximum payload size
3453 * @dev: PCI device to query
3455 * Returns maximum payload size in bytes
3456 * or appropriate error value.
3458 int pcie_get_mps(struct pci_dev
*dev
)
3463 cap
= pci_pcie_cap(dev
);
3467 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3469 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
3475 * pcie_set_mps - set PCI Express maximum payload size
3476 * @dev: PCI device to query
3477 * @mps: maximum payload size in bytes
3478 * valid values are 128, 256, 512, 1024, 2048, 4096
3480 * If possible sets maximum payload size
3482 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
3484 int cap
, err
= -EINVAL
;
3487 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
3491 if (v
> dev
->pcie_mpss
)
3495 cap
= pci_pcie_cap(dev
);
3499 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3503 if ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) != v
) {
3504 ctl
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
3506 err
= pci_write_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3513 * pci_select_bars - Make BAR mask from the type of resource
3514 * @dev: the PCI device for which BAR mask is made
3515 * @flags: resource type mask to be selected
3517 * This helper routine makes bar mask from the type of resource.
3519 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
3522 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
3523 if (pci_resource_flags(dev
, i
) & flags
)
3529 * pci_resource_bar - get position of the BAR associated with a resource
3530 * @dev: the PCI device
3531 * @resno: the resource number
3532 * @type: the BAR type to be filled in
3534 * Returns BAR position in config space, or 0 if the BAR is invalid.
3536 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
3540 if (resno
< PCI_ROM_RESOURCE
) {
3541 *type
= pci_bar_unknown
;
3542 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
3543 } else if (resno
== PCI_ROM_RESOURCE
) {
3544 *type
= pci_bar_mem32
;
3545 return dev
->rom_base_reg
;
3546 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
3547 /* device specific resource */
3548 reg
= pci_iov_resource_bar(dev
, resno
, type
);
3553 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
3557 /* Some architectures require additional programming to enable VGA */
3558 static arch_set_vga_state_t arch_set_vga_state
;
3560 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
3562 arch_set_vga_state
= func
; /* NULL disables */
3565 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
3566 unsigned int command_bits
, u32 flags
)
3568 if (arch_set_vga_state
)
3569 return arch_set_vga_state(dev
, decode
, command_bits
,
3575 * pci_set_vga_state - set VGA decode state on device and parents if requested
3576 * @dev: the PCI device
3577 * @decode: true = enable decoding, false = disable decoding
3578 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3579 * @flags: traverse ancestors and change bridges
3580 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3582 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
3583 unsigned int command_bits
, u32 flags
)
3585 struct pci_bus
*bus
;
3586 struct pci_dev
*bridge
;
3590 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) & (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
3592 /* ARCH specific VGA enables */
3593 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
3597 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
3598 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3600 cmd
|= command_bits
;
3602 cmd
&= ~command_bits
;
3603 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3606 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
3613 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3616 cmd
|= PCI_BRIDGE_CTL_VGA
;
3618 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
3619 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
3627 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3628 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
3629 static DEFINE_SPINLOCK(resource_alignment_lock
);
3632 * pci_specified_resource_alignment - get resource alignment specified by user.
3633 * @dev: the PCI device to get
3635 * RETURNS: Resource alignment if it is specified.
3636 * Zero if it is not specified.
3638 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
3640 int seg
, bus
, slot
, func
, align_order
, count
;
3641 resource_size_t align
= 0;
3644 spin_lock(&resource_alignment_lock
);
3645 p
= resource_alignment_param
;
3648 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
3654 if (sscanf(p
, "%x:%x:%x.%x%n",
3655 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
3657 if (sscanf(p
, "%x:%x.%x%n",
3658 &bus
, &slot
, &func
, &count
) != 3) {
3659 /* Invalid format */
3660 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
3666 if (seg
== pci_domain_nr(dev
->bus
) &&
3667 bus
== dev
->bus
->number
&&
3668 slot
== PCI_SLOT(dev
->devfn
) &&
3669 func
== PCI_FUNC(dev
->devfn
)) {
3670 if (align_order
== -1) {
3673 align
= 1 << align_order
;
3678 if (*p
!= ';' && *p
!= ',') {
3679 /* End of param or invalid format */
3684 spin_unlock(&resource_alignment_lock
);
3689 * pci_is_reassigndev - check if specified PCI is target device to reassign
3690 * @dev: the PCI device to check
3692 * RETURNS: non-zero for PCI device is a target device to reassign,
3695 int pci_is_reassigndev(struct pci_dev
*dev
)
3697 return (pci_specified_resource_alignment(dev
) != 0);
3701 * This function disables memory decoding and releases memory resources
3702 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3703 * It also rounds up size to specified alignment.
3704 * Later on, the kernel will assign page-aligned memory resource back
3707 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
3711 resource_size_t align
, size
;
3714 if (!pci_is_reassigndev(dev
))
3717 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
3718 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
3720 "Can't reassign resources to host bridge.\n");
3725 "Disabling memory decoding and releasing memory resources.\n");
3726 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
3727 command
&= ~PCI_COMMAND_MEMORY
;
3728 pci_write_config_word(dev
, PCI_COMMAND
, command
);
3730 align
= pci_specified_resource_alignment(dev
);
3731 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
3732 r
= &dev
->resource
[i
];
3733 if (!(r
->flags
& IORESOURCE_MEM
))
3735 size
= resource_size(r
);
3739 "Rounding up size of resource #%d to %#llx.\n",
3740 i
, (unsigned long long)size
);
3745 /* Need to disable bridge's resource window,
3746 * to enable the kernel to reassign new resource
3749 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
3750 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
3751 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
3752 r
= &dev
->resource
[i
];
3753 if (!(r
->flags
& IORESOURCE_MEM
))
3755 r
->end
= resource_size(r
) - 1;
3758 pci_disable_bridge_window(dev
);
3762 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
3764 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
3765 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
3766 spin_lock(&resource_alignment_lock
);
3767 strncpy(resource_alignment_param
, buf
, count
);
3768 resource_alignment_param
[count
] = '\0';
3769 spin_unlock(&resource_alignment_lock
);
3773 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
3776 spin_lock(&resource_alignment_lock
);
3777 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
3778 spin_unlock(&resource_alignment_lock
);
3782 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
3784 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
3787 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
3788 const char *buf
, size_t count
)
3790 return pci_set_resource_alignment_param(buf
, count
);
3793 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
3794 pci_resource_alignment_store
);
3796 static int __init
pci_resource_alignment_sysfs_init(void)
3798 return bus_create_file(&pci_bus_type
,
3799 &bus_attr_resource_alignment
);
3802 late_initcall(pci_resource_alignment_sysfs_init
);
3804 static void __devinit
pci_no_domains(void)
3806 #ifdef CONFIG_PCI_DOMAINS
3807 pci_domains_supported
= 0;
3812 * pci_ext_cfg_enabled - can we access extended PCI config space?
3813 * @dev: The PCI device of the root bridge.
3815 * Returns 1 if we can access PCI extended config space (offsets
3816 * greater than 0xff). This is the default implementation. Architecture
3817 * implementations can override this.
3819 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
3824 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
3827 EXPORT_SYMBOL(pci_fixup_cardbus
);
3829 static int __init
pci_setup(char *str
)
3832 char *k
= strchr(str
, ',');
3835 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
3836 if (!strcmp(str
, "nomsi")) {
3838 } else if (!strcmp(str
, "noaer")) {
3840 } else if (!strncmp(str
, "realloc=", 8)) {
3841 pci_realloc_get_opt(str
+ 8);
3842 } else if (!strncmp(str
, "realloc", 7)) {
3843 pci_realloc_get_opt("on");
3844 } else if (!strcmp(str
, "nodomains")) {
3846 } else if (!strncmp(str
, "noari", 5)) {
3847 pcie_ari_disabled
= true;
3848 } else if (!strncmp(str
, "cbiosize=", 9)) {
3849 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
3850 } else if (!strncmp(str
, "cbmemsize=", 10)) {
3851 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
3852 } else if (!strncmp(str
, "resource_alignment=", 19)) {
3853 pci_set_resource_alignment_param(str
+ 19,
3855 } else if (!strncmp(str
, "ecrc=", 5)) {
3856 pcie_ecrc_get_policy(str
+ 5);
3857 } else if (!strncmp(str
, "hpiosize=", 9)) {
3858 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
3859 } else if (!strncmp(str
, "hpmemsize=", 10)) {
3860 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
3861 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
3862 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
3863 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
3864 pcie_bus_config
= PCIE_BUS_SAFE
;
3865 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
3866 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
3867 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
3868 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
3870 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
3878 early_param("pci", pci_setup
);
3880 EXPORT_SYMBOL(pci_reenable_device
);
3881 EXPORT_SYMBOL(pci_enable_device_io
);
3882 EXPORT_SYMBOL(pci_enable_device_mem
);
3883 EXPORT_SYMBOL(pci_enable_device
);
3884 EXPORT_SYMBOL(pcim_enable_device
);
3885 EXPORT_SYMBOL(pcim_pin_device
);
3886 EXPORT_SYMBOL(pci_disable_device
);
3887 EXPORT_SYMBOL(pci_find_capability
);
3888 EXPORT_SYMBOL(pci_bus_find_capability
);
3889 EXPORT_SYMBOL(pci_release_regions
);
3890 EXPORT_SYMBOL(pci_request_regions
);
3891 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3892 EXPORT_SYMBOL(pci_release_region
);
3893 EXPORT_SYMBOL(pci_request_region
);
3894 EXPORT_SYMBOL(pci_request_region_exclusive
);
3895 EXPORT_SYMBOL(pci_release_selected_regions
);
3896 EXPORT_SYMBOL(pci_request_selected_regions
);
3897 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3898 EXPORT_SYMBOL(pci_set_master
);
3899 EXPORT_SYMBOL(pci_clear_master
);
3900 EXPORT_SYMBOL(pci_set_mwi
);
3901 EXPORT_SYMBOL(pci_try_set_mwi
);
3902 EXPORT_SYMBOL(pci_clear_mwi
);
3903 EXPORT_SYMBOL_GPL(pci_intx
);
3904 EXPORT_SYMBOL(pci_assign_resource
);
3905 EXPORT_SYMBOL(pci_find_parent_resource
);
3906 EXPORT_SYMBOL(pci_select_bars
);
3908 EXPORT_SYMBOL(pci_set_power_state
);
3909 EXPORT_SYMBOL(pci_save_state
);
3910 EXPORT_SYMBOL(pci_restore_state
);
3911 EXPORT_SYMBOL(pci_pme_capable
);
3912 EXPORT_SYMBOL(pci_pme_active
);
3913 EXPORT_SYMBOL(pci_wake_from_d3
);
3914 EXPORT_SYMBOL(pci_target_state
);
3915 EXPORT_SYMBOL(pci_prepare_to_sleep
);
3916 EXPORT_SYMBOL(pci_back_from_sleep
);
3917 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);