drivers/staging/brcm80211/brcmsmac/types.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _BRCM_TYPES_H_
  18 #define _BRCM_TYPES_H_
  19
  20 #include <linux/types.h>
  21
  22 /* Bus types */
  23 #define SI_BUS                  0       /* SOC Interconnect */
  24 #define PCI_BUS                 1       /* PCI target */
  25 #define SDIO_BUS                3       /* SDIO target */
  26 #define JTAG_BUS                4       /* JTAG */
  27 #define USB_BUS                 5       /* USB (does not support R/W REG) */
  28 #define SPI_BUS                 6       /* gSPI target */
  29 #define RPC_BUS                 7       /* RPC target */
  30
  31 #define WL_CHAN_FREQ_RANGE_2G      0
  32 #define WL_CHAN_FREQ_RANGE_5GL     1
  33 #define WL_CHAN_FREQ_RANGE_5GM     2
  34 #define WL_CHAN_FREQ_RANGE_5GH     3
  35
  36 #define MAX_DMA_SEGS 4
  37
  38 /* boardflags */
  39 #define BFL_PACTRL              0x00000002      /* Board has gpio 9 controlling the PA */
  40 #define BFL_NOPLLDOWN           0x00000020      /* Not ok to power down the chip pll and oscillator */
  41 #define BFL_FEM                 0x00000800      /* Board supports the Front End Module */
  42 #define BFL_EXTLNA              0x00001000      /* Board has an external LNA in 2.4GHz band */
  43 #define BFL_NOPA                0x00010000      /* Board has no PA */
  44 #define BFL_BUCKBOOST           0x00200000      /* Power topology uses BUCKBOOST */
  45 #define BFL_FEM_BT              0x00400000      /* Board has FEM and switch to share antenna w/ BT */
  46 #define BFL_NOCBUCK             0x00800000      /* Power topology doesn't use CBUCK */
  47 #define BFL_PALDO               0x02000000      /* Power topology uses PALDO */
  48 #define BFL_EXTLNA_5GHz         0x10000000      /* Board has an external LNA in 5GHz band */
  49
  50 /* boardflags2 */
  51 #define BFL2_RXBB_INT_REG_DIS   0x00000001      /* Board has an external rxbb regulator */
  52 #define BFL2_APLL_WAR           0x00000002      /* Flag to implement alternative A-band PLL settings */
  53 #define BFL2_TXPWRCTRL_EN       0x00000004      /* Board permits enabling TX Power Control */
  54 #define BFL2_2X4_DIV            0x00000008      /* Board supports the 2X4 diversity switch */
  55 #define BFL2_5G_PWRGAIN         0x00000010      /* Board supports 5G band power gain */
  56 #define BFL2_PCIEWAR_OVR        0x00000020      /* Board overrides ASPM and Clkreq settings */
  57 #define BFL2_LEGACY             0x00000080
  58 #define BFL2_SKWRKFEM_BRD       0x00000100      /* 4321mcm93 board uses Skyworks FEM */
  59 #define BFL2_SPUR_WAR           0x00000200      /* Board has a WAR for clock-harmonic spurs */
  60 #define BFL2_GPLL_WAR           0x00000400      /* Flag to narrow G-band PLL loop b/w */
  61 #define BFL2_SINGLEANT_CCK      0x00001000      /* Tx CCK pkts on Ant 0 only */
  62 #define BFL2_2G_SPUR_WAR        0x00002000      /* WAR to reduce and avoid clock-harmonic spurs in 2G */
  63 #define BFL2_GPLL_WAR2          0x00010000      /* Flag to widen G-band PLL loop b/w */
  64 #define BFL2_IPALVLSHIFT_3P3    0x00020000
  65 #define BFL2_INTERNDET_TXIQCAL  0x00040000      /* Use internal envelope detector for TX IQCAL */
  66 #define BFL2_XTALBUFOUTEN       0x00080000      /* Keep the buffered Xtal output from radio "ON"
  67                                                  * Most drivers will turn it off without this flag
  68                                                  * to save power.
  69                                                  */
  70
  71 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
  72 #define BOARD_GPIO_PACTRL       0x200   /* bit 9 controls the PA on new 4306 boards */
  73 #define BOARD_GPIO_12           0x1000  /* gpio 12 */
  74 #define BOARD_GPIO_13           0x2000  /* gpio 13 */
  75
  76 /* **** Core type/rev defaults **** */
  77 #define D11CONF         0x0fffffb0      /* Supported  D11 revs: 4, 5, 7-27
  78                                          * also need to update wlc.h MAXCOREREV
  79                                          */
  80
  81 #define NCONF           0x000001ff      /* Supported nphy revs:
  82                                          *      0       4321a0
  83                                          *      1       4321a1
  84                                          *      2       4321b0/b1/c0/c1
  85                                          *      3       4322a0
  86                                          *      4       4322a1
  87                                          *      5       4716a0
  88                                          *      6       43222a0, 43224a0
  89                                          *      7       43226a0
  90                                          *      8       5357a0, 43236a0
  91                                          */
  92
  93 #define LCNCONF         0x00000007      /* Supported lcnphy revs:
  94                                          *      0       4313a0, 4336a0, 4330a0
  95                                          *      1
  96                                          *      2       4330a0
  97                                          */
  98
  99 #define SSLPNCONF       0x0000000f      /* Supported sslpnphy revs:
 100                                          *      0       4329a0/k0
 101                                          *      1       4329b0/4329C0
 102                                          *      2       4319a0
 103                                          *      3       5356a0
 104                                          */
 105
 106 /********************************************************************
 107  * Phy/Core Configuration.  Defines macros to to check core phy/rev *
 108  * compile-time configuration.  Defines default core support.       *
 109  * ******************************************************************
 110  */
 111
 112 /* Basic macros to check a configuration bitmask */
 113
 114 #define CONF_HAS(config, val)   ((config) & (1 << (val)))
 115 #define CONF_MSK(config, mask)  ((config) & (mask))
 116 #define MSK_RANGE(low, hi)      ((1 << ((hi)+1)) - (1 << (low)))
 117 #define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
 118
 119 #define CONF_IS(config, val)    ((config) == (1 << (val)))
 120 #define CONF_GE(config, val)    ((config) & (0-(1 << (val))))
 121 #define CONF_GT(config, val)    ((config) & (0-2*(1 << (val))))
 122 #define CONF_LT(config, val)    ((config) & ((1 << (val))-1))
 123 #define CONF_LE(config, val)    ((config) & (2*(1 << (val))-1))
 124
 125 /* Wrappers for some of the above, specific to config constants */
 126
 127 #define NCONF_HAS(val)  CONF_HAS(NCONF, val)
 128 #define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
 129 #define NCONF_IS(val)   CONF_IS(NCONF, val)
 130 #define NCONF_GE(val)   CONF_GE(NCONF, val)
 131 #define NCONF_GT(val)   CONF_GT(NCONF, val)
 132 #define NCONF_LT(val)   CONF_LT(NCONF, val)
 133 #define NCONF_LE(val)   CONF_LE(NCONF, val)
 134
 135 #define LCNCONF_HAS(val)        CONF_HAS(LCNCONF, val)
 136 #define LCNCONF_MSK(mask)       CONF_MSK(LCNCONF, mask)
 137 #define LCNCONF_IS(val)         CONF_IS(LCNCONF, val)
 138 #define LCNCONF_GE(val)         CONF_GE(LCNCONF, val)
 139 #define LCNCONF_GT(val)         CONF_GT(LCNCONF, val)
 140 #define LCNCONF_LT(val)         CONF_LT(LCNCONF, val)
 141 #define LCNCONF_LE(val)         CONF_LE(LCNCONF, val)
 142
 143 #define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
 144 #define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
 145 #define D11CONF_IS(val) CONF_IS(D11CONF, val)
 146 #define D11CONF_GE(val) CONF_GE(D11CONF, val)
 147 #define D11CONF_GT(val) CONF_GT(D11CONF, val)
 148 #define D11CONF_LT(val) CONF_LT(D11CONF, val)
 149 #define D11CONF_LE(val) CONF_LE(D11CONF, val)
 150
 151 #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
 152 #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
 153
 154 #define NREV_IS(var, val)       (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
 155 #define NREV_GE(var, val)       (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
 156 #define NREV_GT(var, val)       (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
 157 #define NREV_LT(var, val)       (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
 158 #define NREV_LE(var, val)       (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
 159
 160 #define LCNREV_IS(var, val)     (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
 161 #define LCNREV_GE(var, val)     (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
 162 #define LCNREV_GT(var, val)     (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
 163 #define LCNREV_LT(var, val)     (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
 164 #define LCNREV_LE(var, val)     (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
 165
 166 #define D11REV_IS(var, val)     (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
 167 #define D11REV_GE(var, val)     (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
 168 #define D11REV_GT(var, val)     (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
 169 #define D11REV_LT(var, val)     (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
 170 #define D11REV_LE(var, val)     (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
 171
 172 #define PHYTYPE_IS(var, val)    (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
 173
 174 /* Finally, early-exit from switch case if anyone wants it... */
 175
 176 #define CASECHECK(config, val)  if (!(CONF_HAS(config, val))) break
 177 #define CASEMSK(config, mask)   if (!(CONF_MSK(config, mask))) break
 178
 179 /* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
 180
 181 #define _PHYCONF_N (1 << PHY_TYPE_N)
 182 #define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
 183 #define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
 184
 185 #define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
 186
 187 /* Utility macro to identify 802.11n (HT) capable PHYs */
 188 #define PHYTYPE_11N_CAP(phytype) \
 189         (PHYTYPE_IS(phytype, PHY_TYPE_N) ||     \
 190          PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
 191          PHYTYPE_IS(phytype, PHY_TYPE_SSN))
 192
 193 /* Last but not least: shorter wlc-specific var checks */
 194 #define WLCISNPHY(band)         PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
 195 #define WLCISLCNPHY(band)       PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
 196 #define WLCISSSLPNPHY(band)     PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
 197
 198 #define WLC_PHY_11N_CAP(band)   PHYTYPE_11N_CAP((band)->phytype)
 199
 200 /**********************************************************************
 201  * ------------- End of Core phy/rev configuration. ----------------- *
 202  * ********************************************************************
 203  */
 204
 205 /*************************************************
 206  * Defaults for tunables (e.g. sizing constants)
 207  *
 208  * For each new tunable, add a member to the end
 209  * of struct brcms_tunables in brcms_c_pub.h to enable
 210  * runtime checks of tunable values. (Directly
 211  * using the macros in code invalidates ROM code)
 212  *
 213  * ***********************************************
 214  */
 215 #define NTXD            256     /* Max # of entries in Tx FIFO based on 4kb page size */
 216 #define NRXD            256     /* Max # of entries in Rx FIFO based on 4kb page size */
 217 #define NRXBUFPOST      32      /* try to keep this # rbufs posted to the chip */
 218 #define MAXSCB          32      /* Maximum SCBs in cache for STA */
 219 #define AMPDU_NUM_MPDU          16      /* max allowed number of mpdus in an ampdu (2 streams) */
 220
 221 /* Count of packet callback structures. either of following
 222  * 1. Set to the number of SCBs since a STA
 223  * can queue up a rate callback for each IBSS STA it knows about, and an AP can
 224  * queue up an "are you there?" Null Data callback for each associated STA
 225  * 2. controlled by tunable config file
 226  */
 227 #define MAXPKTCB        MAXSCB  /* Max number of packet callbacks */
 228
 229 /* NetBSD also needs to keep track of this */
 230 #define WLC_MAX_UCODE_BSS       (16)    /* Number of BSS handled in ucode bcn/prb */
 231 #define WLC_MAX_UCODE_BSS4      (4)     /* Number of BSS handled in sw bcn/prb */
 232 #define WLC_MAXBSSCFG           (1)     /* max # BSS configs */
 233 #define MAXBSS          64      /* max # available networks */
 234 #define WLC_DATAHIWAT           50      /* data msg txq hiwat mark */
 235 #define WLC_AMPDUDATAHIWAT 255
 236
 237 /* bounded rx loops */
 238 #define RXBND           8       /* max # frames to process in brcms_c_recv() */
 239 #define TXSBND          8       /* max # tx status to process in wlc_txstatus() */
 240
 241 #define WLBANDINITFN(_fn)       _fn
 242
 243 #define BAND_5G(bt)     ((bt) == WLC_BAND_5G)
 244 #define BAND_2G(bt)     ((bt) == WLC_BAND_2G)
 245
 246 #define BCMMSG(dev, fmt, args...)               \
 247 do {                                            \
 248         if (brcm_msg_level & LOG_TRACE_VAL)     \
 249                 wiphy_err(dev, "%s: " fmt, __func__, ##args);   \
 250 } while (0)
 251
 252 #define WL_ERROR_ON()           (brcm_msg_level & LOG_ERROR_VAL)
 253
 254 /* register access macros */
 255 #ifndef __BIG_ENDIAN
 256 #ifndef __mips__
 257 #define R_REG(r) \
 258         ({\
 259                 sizeof(*(r)) == sizeof(u8) ? \
 260                 readb((u8 *)(r)) : \
 261                 sizeof(*(r)) == sizeof(u16) ? readw((u16 *)(r)) : \
 262                 readl((u32 *)(r)); \
 263         })
 264 #else                           /* __mips__ */
 265 #define R_REG(r) \
 266         ({ \
 267                 __typeof(*(r)) __osl_v; \
 268                 __asm__ __volatile__("sync"); \
 269                 switch (sizeof(*(r))) { \
 270                 case sizeof(u8): \
 271                         __osl_v = readb((u8 *)(r)); \
 272                         break; \
 273                 case sizeof(u16): \
 274                         __osl_v = readw((u16 *)(r)); \
 275                         break; \
 276                 case sizeof(u32): \
 277                         __osl_v = \
 278                         readl((u32 *)(r)); \
 279                         break; \
 280                 } \
 281                 __asm__ __volatile__("sync"); \
 282                 __osl_v; \
 283         })
 284 #endif                          /* __mips__ */
 285
 286 #define W_REG(r, v) do { \
 287                 switch (sizeof(*(r))) { \
 288                 case sizeof(u8): \
 289                         writeb((u8)(v), (u8 *)(r)); break; \
 290                 case sizeof(u16): \
 291                         writew((u16)(v), (u16 *)(r)); break; \
 292                 case sizeof(u32): \
 293                         writel((u32)(v), (u32 *)(r)); break; \
 294                 }; \
 295         } while (0)
 296 #else                           /* __BIG_ENDIAN */
 297 #define R_REG(r) \
 298         ({ \
 299                 __typeof(*(r)) __osl_v; \
 300                 switch (sizeof(*(r))) { \
 301                 case sizeof(u8): \
 302                         __osl_v = \
 303                         readb((u8 *)((r)^3)); \
 304                         break; \
 305                 case sizeof(u16): \
 306                         __osl_v = \
 307                         readw((u16 *)((r)^2)); \
 308                         break; \
 309                 case sizeof(u32): \
 310                         __osl_v = readl((u32 *)(r)); \
 311                         break; \
 312                 } \
 313                 __osl_v; \
 314         })
 315
 316 #define W_REG(r, v) do { \
 317                 switch (sizeof(*(r))) { \
 318                 case sizeof(u8):        \
 319                         writeb((u8)(v), \
 320                         (u8 *)((r)^3)); break; \
 321                 case sizeof(u16):       \
 322                         writew((u16)(v), \
 323                         (u16 *)((r)^2)); break; \
 324                 case sizeof(u32):       \
 325                         writel((u32)(v), \
 326                         (u32 *)(r)); break; \
 327                 } \
 328         } while (0)
 329 #endif                          /* __BIG_ENDIAN */
 330
 331 #ifdef __mips__
 332 /*
 333  * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
 334  * transactions. As a fix, a read after write is performed on certain places
 335  * in the code. Older chips and the newer 5357 family don't require this fix.
 336  */
 337 #define W_REG_FLUSH(r, v)       ({ W_REG((r), (v)); (void)R_REG(r); })
 338 #else
 339 #define W_REG_FLUSH(r, v)       W_REG((r), (v))
 340 #endif                          /* __mips__ */
 341
 342 #define AND_REG(r, v)   W_REG((r), R_REG(r) & (v))
 343 #define OR_REG(r, v)    W_REG((r), R_REG(r) | (v))
 344
 345 #define SET_REG(r, mask, val) \
 346                 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
 347
 348 /* multi-bool data type: set of bools, mbool is true if any is set */
 349 typedef u32 mbool;
 350 #define mboolset(mb, bit)               ((mb) |= (bit)) /* set one bool */
 351 #define mboolclr(mb, bit)               ((mb) &= ~(bit))        /* clear one bool */
 352 #define mboolisset(mb, bit)             (((mb) & (bit)) != 0)   /* true if one bool is set */
 353 #define mboolmaskset(mb, mask, val)     ((mb) = (((mb) & ~(mask)) | (val)))
 354
 355 /* forward declarations */
 356 struct wiphy;
 357 struct ieee80211_sta;
 358 struct ieee80211_tx_queue_params;
 359 struct brcms_info;
 360 struct brcms_c_info;
 361 struct brcms_c_hw_info;
 362 struct brcms_c_if;
 363 struct brcmu_iovar;
 364 struct brcmu_strbuf;
 365 struct brcms_c_txq_info;
 366 struct brcms_c_band;
 367 struct dma_pub;
 368 struct si_pub;
 369 struct tx_status;
 370 struct d11rxhdr;
 371 struct brcms_d11rxhdr;
 372 struct txpwr_limits;
 373
 374 typedef volatile struct intctrlregs intctrlregs_t;
 375 typedef volatile struct pio2regs pio2regs_t;
 376 typedef volatile struct pio2regp pio2regp_t;
 377 typedef volatile struct pio4regs pio4regs_t;
 378 typedef volatile struct pio4regp pio4regp_t;
 379 typedef volatile struct fifo64 fifo64_t;
 380 typedef volatile struct d11regs d11regs_t;
 381 typedef volatile struct dma32diag dma32diag_t;
 382 typedef volatile struct dma64regs dma64regs_t;
 383 typedef struct brcms_rateset wlc_rateset_t;
 384 typedef u32 ratespec_t;
 385 typedef struct tx_power tx_power_t;
 386 typedef struct chanvec chanvec_t;
 387 typedef struct phy_pub wlc_phy_t;
 388 typedef struct phy_info phy_info_t;
 389 typedef s32 fixed;
 390 typedef struct _cs32 cs32;
 391 typedef volatile union pmqreg pmqreg_t;
 392
 393 /* brcm_msg_level is a bit vector with defs in defs.h */
 394 extern u32 brcm_msg_level;
 395
 396 #endif                          /* _BRCM_TYPES_H_ */