2 * arch/arm/mach-dove/pcie.c
4 * PCIe functions for Marvell Dove 88AP510 SoC
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/mbus.h>
14 #include <video/vga.h>
15 #include <asm/mach/pci.h>
16 #include <asm/mach/arch.h>
17 #include <asm/setup.h>
18 #include <asm/delay.h>
19 #include <plat/pcie.h>
20 #include <mach/irqs.h>
21 #include <mach/bridge-regs.h>
29 char io_space_name
[16];
30 char mem_space_name
[16];
31 struct resource res
[2];
34 static struct pcie_port pcie_port
[2];
35 static int num_pcie_ports
;
38 static int __init
dove_pcie_setup(int nr
, struct pci_sys_data
*sys
)
42 if (nr
>= num_pcie_ports
)
46 pp
->root_bus_nr
= sys
->busnr
;
49 * Generic PCIe unit setup.
51 orion_pcie_set_local_bus_nr(pp
->base
, sys
->busnr
);
53 orion_pcie_setup(pp
->base
, &dove_mbus_dram_info
);
58 snprintf(pp
->io_space_name
, sizeof(pp
->io_space_name
),
59 "PCIe %d I/O", pp
->index
);
60 pp
->io_space_name
[sizeof(pp
->io_space_name
) - 1] = 0;
61 pp
->res
[0].name
= pp
->io_space_name
;
63 pp
->res
[0].start
= DOVE_PCIE0_IO_PHYS_BASE
;
64 pp
->res
[0].end
= pp
->res
[0].start
+ DOVE_PCIE0_IO_SIZE
- 1;
66 pp
->res
[0].start
= DOVE_PCIE1_IO_PHYS_BASE
;
67 pp
->res
[0].end
= pp
->res
[0].start
+ DOVE_PCIE1_IO_SIZE
- 1;
69 pp
->res
[0].flags
= IORESOURCE_IO
;
70 if (request_resource(&ioport_resource
, &pp
->res
[0]))
71 panic("Request PCIe IO resource failed\n");
72 sys
->resource
[0] = &pp
->res
[0];
77 snprintf(pp
->mem_space_name
, sizeof(pp
->mem_space_name
),
78 "PCIe %d MEM", pp
->index
);
79 pp
->mem_space_name
[sizeof(pp
->mem_space_name
) - 1] = 0;
80 pp
->res
[1].name
= pp
->mem_space_name
;
82 pp
->res
[1].start
= DOVE_PCIE0_MEM_PHYS_BASE
;
83 pp
->res
[1].end
= pp
->res
[1].start
+ DOVE_PCIE0_MEM_SIZE
- 1;
85 pp
->res
[1].start
= DOVE_PCIE1_MEM_PHYS_BASE
;
86 pp
->res
[1].end
= pp
->res
[1].start
+ DOVE_PCIE1_MEM_SIZE
- 1;
88 pp
->res
[1].flags
= IORESOURCE_MEM
;
89 if (request_resource(&iomem_resource
, &pp
->res
[1]))
90 panic("Request PCIe Memory resource failed\n");
91 sys
->resource
[1] = &pp
->res
[1];
93 sys
->resource
[2] = NULL
;
98 static struct pcie_port
*bus_to_port(int bus
)
102 for (i
= num_pcie_ports
- 1; i
>= 0; i
--) {
103 int rbus
= pcie_port
[i
].root_bus_nr
;
104 if (rbus
!= -1 && rbus
<= bus
)
108 return i
>= 0 ? pcie_port
+ i
: NULL
;
111 static int pcie_valid_config(struct pcie_port
*pp
, int bus
, int dev
)
114 * Don't go out when trying to access nonexisting devices
117 if (bus
== pp
->root_bus_nr
&& dev
> 1)
123 static int pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
126 struct pcie_port
*pp
= bus_to_port(bus
->number
);
130 if (pcie_valid_config(pp
, bus
->number
, PCI_SLOT(devfn
)) == 0) {
132 return PCIBIOS_DEVICE_NOT_FOUND
;
135 spin_lock_irqsave(&pp
->conf_lock
, flags
);
136 ret
= orion_pcie_rd_conf(pp
->base
, bus
, devfn
, where
, size
, val
);
137 spin_unlock_irqrestore(&pp
->conf_lock
, flags
);
142 static int pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
143 int where
, int size
, u32 val
)
145 struct pcie_port
*pp
= bus_to_port(bus
->number
);
149 if (pcie_valid_config(pp
, bus
->number
, PCI_SLOT(devfn
)) == 0)
150 return PCIBIOS_DEVICE_NOT_FOUND
;
152 spin_lock_irqsave(&pp
->conf_lock
, flags
);
153 ret
= orion_pcie_wr_conf(pp
->base
, bus
, devfn
, where
, size
, val
);
154 spin_unlock_irqrestore(&pp
->conf_lock
, flags
);
159 static struct pci_ops pcie_ops
= {
160 .read
= pcie_rd_conf
,
161 .write
= pcie_wr_conf
,
164 static void __devinit
rc_pci_fixup(struct pci_dev
*dev
)
167 * Prevent enumeration of root complex.
169 if (dev
->bus
->parent
== NULL
&& dev
->devfn
== 0) {
172 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
173 dev
->resource
[i
].start
= 0;
174 dev
->resource
[i
].end
= 0;
175 dev
->resource
[i
].flags
= 0;
179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL
, PCI_ANY_ID
, rc_pci_fixup
);
181 static struct pci_bus __init
*
182 dove_pcie_scan_bus(int nr
, struct pci_sys_data
*sys
)
186 if (nr
< num_pcie_ports
) {
187 bus
= pci_scan_bus(sys
->busnr
, &pcie_ops
, sys
);
196 static int __init
dove_pcie_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
198 struct pcie_port
*pp
= bus_to_port(dev
->bus
->number
);
200 return pp
->index
? IRQ_DOVE_PCIE1
: IRQ_DOVE_PCIE0
;
203 static struct hw_pci dove_pci __initdata
= {
205 .swizzle
= pci_std_swizzle
,
206 .setup
= dove_pcie_setup
,
207 .scan
= dove_pcie_scan_bus
,
208 .map_irq
= dove_pcie_map_irq
,
211 static void __init
add_pcie_port(int index
, unsigned long base
)
213 printk(KERN_INFO
"Dove PCIe port %d: ", index
);
215 if (orion_pcie_link_up((void __iomem
*)base
)) {
216 struct pcie_port
*pp
= &pcie_port
[num_pcie_ports
++];
218 printk(KERN_INFO
"link up\n");
221 pp
->root_bus_nr
= -1;
222 pp
->base
= (void __iomem
*)base
;
223 spin_lock_init(&pp
->conf_lock
);
224 memset(pp
->res
, 0, sizeof(pp
->res
));
226 printk(KERN_INFO
"link down, ignoring\n");
230 void __init
dove_pcie_init(int init_port0
, int init_port1
)
232 vga_base
= DOVE_PCIE0_MEM_PHYS_BASE
;
235 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE
);
238 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE
);
240 pci_common_init(&dove_pci
);