2 * linux/drivers/i2c/chips/twl4030-power.c
4 * Handle TWL4030 Power initialization
6 * Copyright (C) 2008 Nokia Corporation
7 * Copyright (C) 2006 Texas Instruments, Inc
9 * Written by Kalle Jokiniemi
10 * Peter De Schrijver <peter.de-schrijver@nokia.com>
11 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file "COPYING" in the main directory of this
15 * archive for more details.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/module.h>
29 #include <linux/i2c/twl.h>
30 #include <linux/platform_device.h>
32 #include <asm/mach-types.h>
34 static u8 twl4030_start_script_address
= 0x2b;
36 #define PWR_P1_SW_EVENTS 0x10
37 #define PWR_DEVOFF (1 << 0)
38 #define SEQ_OFFSYNC (1 << 0)
40 #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
41 #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
43 /* resource - hfclk */
44 #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
47 #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
48 #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
49 #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
50 #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
51 #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
52 #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
54 #define LVL_WAKEUP 0x08
56 #define ENABLE_WARMRESET (1<<4)
58 #define END_OF_SCRIPT 0x3f
60 #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
61 #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
62 #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
63 #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
64 #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
65 #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
67 /* resource configuration registers
68 <RESOURCE>_DEV_GRP at address 'n+0'
69 <RESOURCE>_TYPE at address 'n+1'
70 <RESOURCE>_REMAP at address 'n+2'
71 <RESOURCE>_DEDICATED at address 'n+3'
73 #define DEV_GRP_OFFSET 0
75 #define REMAP_OFFSET 2
76 #define DEDICATED_OFFSET 3
78 /* Bit positions in the registers */
80 /* <RESOURCE>_DEV_GRP */
81 #define DEV_GRP_SHIFT 5
82 #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
86 #define TYPE_MASK (7 << TYPE_SHIFT)
88 #define TYPE2_MASK (3 << TYPE2_SHIFT)
90 /* <RESOURCE>_REMAP */
91 #define SLEEP_STATE_SHIFT 0
92 #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
93 #define OFF_STATE_SHIFT 4
94 #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
96 static u8 res_config_addrs
[] = {
107 [RES_VINTANA1
] = 0x3f,
108 [RES_VINTANA2
] = 0x43,
109 [RES_VINTDIG
] = 0x47,
113 [RES_VUSB_1V5
] = 0x71,
114 [RES_VUSB_1V8
] = 0x74,
115 [RES_VUSB_3V1
] = 0x77,
118 [RES_NRES_PWRON
] = 0x82,
121 [RES_HFCLKOUT
] = 0x8b,
122 [RES_32KCLKOUT
] = 0x8e,
124 [RES_MAIN_REF
] = 0x94,
127 static int twl4030_write_script_byte(u8 address
, u8 byte
)
131 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, address
, R_MEMORY_ADDRESS
);
134 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, byte
, R_MEMORY_DATA
);
139 static int twl4030_write_script_ins(u8 address
, u16 pmb_message
,
145 err
= twl4030_write_script_byte(address
++, pmb_message
>> 8);
148 err
= twl4030_write_script_byte(address
++, pmb_message
& 0xff);
151 err
= twl4030_write_script_byte(address
++, delay
);
154 err
= twl4030_write_script_byte(address
++, next
);
159 static int twl4030_write_script(u8 address
, struct twl4030_ins
*script
,
164 for (; len
; len
--, address
++, script
++) {
166 err
= twl4030_write_script_ins(address
,
173 err
= twl4030_write_script_ins(address
,
184 static int twl4030_config_wakeup3_sequence(u8 address
)
189 /* Set SLEEP to ACTIVE SEQ address for P3 */
190 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, address
, R_SEQ_ADD_S2A3
);
194 /* P3 LVL_WAKEUP should be on LEVEL */
195 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &data
, R_P3_SW_EVENTS
);
199 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, data
, R_P3_SW_EVENTS
);
202 pr_err("TWL4030 wakeup sequence for P3 config error\n");
206 static int twl4030_config_wakeup12_sequence(u8 address
)
211 /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
212 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, address
, R_SEQ_ADD_S2A12
);
216 /* P1/P2 LVL_WAKEUP should be on LEVEL */
217 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &data
, R_P1_SW_EVENTS
);
222 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, data
, R_P1_SW_EVENTS
);
226 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &data
, R_P2_SW_EVENTS
);
231 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, data
, R_P2_SW_EVENTS
);
235 if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
236 /* Disabling AC charger effect on sleep-active transitions */
237 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &data
,
238 R_CFG_P1_TRANSITION
);
242 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, data
,
243 R_CFG_P1_TRANSITION
);
250 pr_err("TWL4030 wakeup sequence for P1 and P2" \
255 static int twl4030_config_sleep_sequence(u8 address
)
259 /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
260 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, address
, R_SEQ_ADD_A2S
);
263 pr_err("TWL4030 sleep sequence config error\n");
268 static int twl4030_config_warmreset_sequence(u8 address
)
273 /* Set WARM RESET SEQ address for P1 */
274 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, address
, R_SEQ_ADD_WARM
);
278 /* P1/P2/P3 enable WARMRESET */
279 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &rd_data
, R_P1_SW_EVENTS
);
283 rd_data
|= ENABLE_WARMRESET
;
284 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, rd_data
, R_P1_SW_EVENTS
);
288 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &rd_data
, R_P2_SW_EVENTS
);
292 rd_data
|= ENABLE_WARMRESET
;
293 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, rd_data
, R_P2_SW_EVENTS
);
297 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &rd_data
, R_P3_SW_EVENTS
);
301 rd_data
|= ENABLE_WARMRESET
;
302 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, rd_data
, R_P3_SW_EVENTS
);
305 pr_err("TWL4030 warmreset seq config error\n");
309 static int twl4030_configure_resource(struct twl4030_resconfig
*rconfig
)
317 if (rconfig
->resource
> TOTAL_RESOURCES
) {
318 pr_err("TWL4030 Resource %d does not exist\n",
323 rconfig_addr
= res_config_addrs
[rconfig
->resource
];
325 /* Set resource group */
326 err
= twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER
, &grp
,
327 rconfig_addr
+ DEV_GRP_OFFSET
);
329 pr_err("TWL4030 Resource %d group could not be read\n",
334 if (rconfig
->devgroup
!= TWL4030_RESCONFIG_UNDEF
) {
335 grp
&= ~DEV_GRP_MASK
;
336 grp
|= rconfig
->devgroup
<< DEV_GRP_SHIFT
;
337 err
= twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER
,
338 grp
, rconfig_addr
+ DEV_GRP_OFFSET
);
340 pr_err("TWL4030 failed to program devgroup\n");
345 /* Set resource types */
346 err
= twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER
, &type
,
347 rconfig_addr
+ TYPE_OFFSET
);
349 pr_err("TWL4030 Resource %d type could not be read\n",
354 if (rconfig
->type
!= TWL4030_RESCONFIG_UNDEF
) {
356 type
|= rconfig
->type
<< TYPE_SHIFT
;
359 if (rconfig
->type2
!= TWL4030_RESCONFIG_UNDEF
) {
361 type
|= rconfig
->type2
<< TYPE2_SHIFT
;
364 err
= twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER
,
365 type
, rconfig_addr
+ TYPE_OFFSET
);
367 pr_err("TWL4030 failed to program resource type\n");
371 /* Set remap states */
372 err
= twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER
, &remap
,
373 rconfig_addr
+ REMAP_OFFSET
);
375 pr_err("TWL4030 Resource %d remap could not be read\n",
380 if (rconfig
->remap_off
!= TWL4030_RESCONFIG_UNDEF
) {
381 remap
&= ~OFF_STATE_MASK
;
382 remap
|= rconfig
->remap_off
<< OFF_STATE_SHIFT
;
385 if (rconfig
->remap_sleep
!= TWL4030_RESCONFIG_UNDEF
) {
386 remap
&= ~SLEEP_STATE_MASK
;
387 remap
|= rconfig
->remap_sleep
<< SLEEP_STATE_SHIFT
;
390 err
= twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER
,
392 rconfig_addr
+ REMAP_OFFSET
);
394 pr_err("TWL4030 failed to program remap\n");
401 static int load_twl4030_script(struct twl4030_script
*tscript
,
407 /* Make sure the script isn't going beyond last valid address (0x3f) */
408 if ((address
+ tscript
->size
) > END_OF_SCRIPT
) {
409 pr_err("TWL4030 scripts too big error\n");
413 err
= twl4030_write_script(address
, tscript
->script
, tscript
->size
);
417 if (tscript
->flags
& TWL4030_WRST_SCRIPT
) {
418 err
= twl4030_config_warmreset_sequence(address
);
422 if (tscript
->flags
& TWL4030_WAKEUP12_SCRIPT
) {
423 err
= twl4030_config_wakeup12_sequence(address
);
428 if (tscript
->flags
& TWL4030_WAKEUP3_SCRIPT
) {
429 err
= twl4030_config_wakeup3_sequence(address
);
433 if (tscript
->flags
& TWL4030_SLEEP_SCRIPT
) {
435 pr_warning("TWL4030: Bad order of scripts (sleep "\
436 "script before wakeup) Leads to boot"\
437 "failure on some boards\n");
438 err
= twl4030_config_sleep_sequence(address
);
444 int twl4030_remove_script(u8 flags
)
448 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, TWL4030_PM_MASTER_KEY_CFG1
,
449 TWL4030_PM_MASTER_PROTECT_KEY
);
451 pr_err("twl4030: unable to unlock PROTECT_KEY\n");
455 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, TWL4030_PM_MASTER_KEY_CFG2
,
456 TWL4030_PM_MASTER_PROTECT_KEY
);
458 pr_err("twl4030: unable to unlock PROTECT_KEY\n");
462 if (flags
& TWL4030_WRST_SCRIPT
) {
463 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, END_OF_SCRIPT
,
468 if (flags
& TWL4030_WAKEUP12_SCRIPT
) {
469 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, END_OF_SCRIPT
,
474 if (flags
& TWL4030_WAKEUP3_SCRIPT
) {
475 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, END_OF_SCRIPT
,
480 if (flags
& TWL4030_SLEEP_SCRIPT
) {
481 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, END_OF_SCRIPT
,
487 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, 0,
488 TWL4030_PM_MASTER_PROTECT_KEY
);
490 pr_err("TWL4030 Unable to relock registers\n");
496 * In master mode, start the power off sequence.
497 * After a successful execution, TWL shuts down the power to the SoC
498 * and all peripherals connected to it.
500 void twl4030_power_off(void)
504 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, PWR_DEVOFF
,
505 TWL4030_PM_MASTER_P1_SW_EVENTS
);
507 pr_err("TWL4030 Unable to power off\n");
510 void twl4030_power_init(struct twl4030_power_data
*twl4030_scripts
)
514 struct twl4030_resconfig
*resconfig
;
515 u8 val
, address
= twl4030_start_script_address
;
517 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, TWL4030_PM_MASTER_KEY_CFG1
,
518 TWL4030_PM_MASTER_PROTECT_KEY
);
522 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, TWL4030_PM_MASTER_KEY_CFG2
,
523 TWL4030_PM_MASTER_PROTECT_KEY
);
527 for (i
= 0; i
< twl4030_scripts
->num
; i
++) {
528 err
= load_twl4030_script(twl4030_scripts
->scripts
[i
], address
);
531 address
+= twl4030_scripts
->scripts
[i
]->size
;
534 resconfig
= twl4030_scripts
->resource_config
;
536 while (resconfig
->resource
) {
537 err
= twl4030_configure_resource(resconfig
);
545 /* Board has to be wired properly to use this feature */
546 if (twl4030_scripts
->use_poweroff
&& !pm_power_off
) {
547 /* Default for SEQ_OFFSYNC is set, lets ensure this */
548 err
= twl_i2c_read_u8(TWL_MODULE_PM_MASTER
, &val
,
549 TWL4030_PM_MASTER_CFG_P123_TRANSITION
);
551 pr_warning("TWL4030 Unable to read registers\n");
553 } else if (!(val
& SEQ_OFFSYNC
)) {
555 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, val
,
556 TWL4030_PM_MASTER_CFG_P123_TRANSITION
);
558 pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
563 pm_power_off
= twl4030_power_off
;
567 err
= twl_i2c_write_u8(TWL_MODULE_PM_MASTER
, 0,
568 TWL4030_PM_MASTER_PROTECT_KEY
);
570 pr_err("TWL4030 Unable to relock registers\n");
575 pr_err("TWL4030 Unable to unlock registers\n");
579 pr_err("TWL4030 failed to load scripts\n");
583 pr_err("TWL4030 failed to configure resource\n");