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HWPOISON: Add simple debugfs interface to inject hwpoison on arbitary PFNs
[linux-2.6.git] / drivers / spi / spi_s3c24xx.c
blob3f3119d760db71fc653b75e77615ce8069b7c300
1 /* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
23
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
26
27 #include <asm/io.h>
28 #include <asm/dma.h>
29 #include <mach/hardware.h>
30
31 #include <plat/regs-spi.h>
32 #include <mach/spi.h>
33
34 struct s3c24xx_spi {
35 /* bitbang has to be first */
36 struct spi_bitbang bitbang;
37 struct completion done;
38
39 void __iomem *regs;
40 int irq;
41 int len;
42 int count;
43
44 void (*set_cs)(struct s3c2410_spi_info *spi,
45 int cs, int pol);
46
47 /* data buffers */
48 const unsigned char *tx;
49 unsigned char *rx;
50
51 struct clk *clk;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
55 struct device *dev;
56 struct s3c2410_spi_info *pdata;
57 };
58
59 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
61
62 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
63 {
64 return spi_master_get_devdata(sdev->master);
65 }
66
67 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
68 {
69 gpio_set_value(spi->pin_cs, pol);
70 }
71
72 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
73 {
74 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int spcon;
77
78 switch (value) {
79 case BITBANG_CS_INACTIVE:
80 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
81 break;
82
83 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON);
85
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
88 else
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
90
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
93 else
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
95
96 spcon |= S3C2410_SPCON_ENSCK;
97
98 /* write new configration */
99
100 writeb(spcon, hw->regs + S3C2410_SPCON);
101 hw->set_cs(hw->pdata, spi->chip_select, cspol);
102
103 break;
104 }
105 }
106
107 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
108 struct spi_transfer *t)
109 {
110 struct s3c24xx_spi *hw = to_hw(spi);
111 unsigned int bpw;
112 unsigned int hz;
113 unsigned int div;
114 unsigned long clk;
115
116 bpw = t ? t->bits_per_word : spi->bits_per_word;
117 hz = t ? t->speed_hz : spi->max_speed_hz;
118
119 if (!bpw)
120 bpw = 8;
121
122 if (!hz)
123 hz = spi->max_speed_hz;
124
125 if (bpw != 8) {
126 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
127 return -EINVAL;
128 }
129
130 clk = clk_get_rate(hw->clk);
131 div = DIV_ROUND_UP(clk, hz * 2) - 1;
132
133 if (div > 255)
134 div = 255;
135
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (wanted %d, got %ld)\n",
137 div, hz, clk / (2 * (div + 1)));
138
139
140 writeb(div, hw->regs + S3C2410_SPPRE);
141
142 spin_lock(&hw->bitbang.lock);
143 if (!hw->bitbang.busy) {
144 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
145 /* need to ndelay for 0.5 clocktick ? */
146 }
147 spin_unlock(&hw->bitbang.lock);
148
149 return 0;
150 }
151
152 static int s3c24xx_spi_setup(struct spi_device *spi)
153 {
154 int ret;
155
156 ret = s3c24xx_spi_setupxfer(spi, NULL);
157 if (ret < 0) {
158 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
159 return ret;
160 }
161
162 return 0;
163 }
164
165 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
166 {
167 return hw->tx ? hw->tx[count] : 0;
168 }
169
170 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
171 {
172 struct s3c24xx_spi *hw = to_hw(spi);
173
174 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
175 t->tx_buf, t->rx_buf, t->len);
176
177 hw->tx = t->tx_buf;
178 hw->rx = t->rx_buf;
179 hw->len = t->len;
180 hw->count = 0;
181
182 init_completion(&hw->done);
183
184 /* send the first byte */
185 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
186
187 wait_for_completion(&hw->done);
188
189 return hw->count;
190 }
191
192 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
193 {
194 struct s3c24xx_spi *hw = dev;
195 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
196 unsigned int count = hw->count;
197
198 if (spsta & S3C2410_SPSTA_DCOL) {
199 dev_dbg(hw->dev, "data-collision\n");
200 complete(&hw->done);
201 goto irq_done;
202 }
203
204 if (!(spsta & S3C2410_SPSTA_READY)) {
205 dev_dbg(hw->dev, "spi not ready for tx?\n");
206 complete(&hw->done);
207 goto irq_done;
208 }
209
210 hw->count++;
211
212 if (hw->rx)
213 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
214
215 count++;
216
217 if (count < hw->len)
218 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
219 else
220 complete(&hw->done);
221
222 irq_done:
223 return IRQ_HANDLED;
224 }
225
226 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
227 {
228 /* for the moment, permanently enable the clock */
229
230 clk_enable(hw->clk);
231
232 /* program defaults into the registers */
233
234 writeb(0xff, hw->regs + S3C2410_SPPRE);
235 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
236 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
237
238 if (hw->pdata) {
239 if (hw->set_cs == s3c24xx_spi_gpiocs)
240 gpio_direction_output(hw->pdata->pin_cs, 1);
241
242 if (hw->pdata->gpio_setup)
243 hw->pdata->gpio_setup(hw->pdata, 1);
244 }
245 }
246
247 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
248 {
249 struct s3c2410_spi_info *pdata;
250 struct s3c24xx_spi *hw;
251 struct spi_master *master;
252 struct resource *res;
253 int err = 0;
254
255 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
256 if (master == NULL) {
257 dev_err(&pdev->dev, "No memory for spi_master\n");
258 err = -ENOMEM;
259 goto err_nomem;
260 }
261
262 hw = spi_master_get_devdata(master);
263 memset(hw, 0, sizeof(struct s3c24xx_spi));
264
265 hw->master = spi_master_get(master);
266 hw->pdata = pdata = pdev->dev.platform_data;
267 hw->dev = &pdev->dev;
268
269 if (pdata == NULL) {
270 dev_err(&pdev->dev, "No platform data supplied\n");
271 err = -ENOENT;
272 goto err_no_pdata;
273 }
274
275 platform_set_drvdata(pdev, hw);
276 init_completion(&hw->done);
277
278 /* setup the master state. */
279
280 /* the spi->mode bits understood by this driver: */
281 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
282
283 master->num_chipselect = hw->pdata->num_cs;
284 master->bus_num = pdata->bus_num;
285
286 /* setup the state for the bitbang driver */
287
288 hw->bitbang.master = hw->master;
289 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
290 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
291 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
292 hw->bitbang.master->setup = s3c24xx_spi_setup;
293
294 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
295
296 /* find and map our resources */
297
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (res == NULL) {
300 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
301 err = -ENOENT;
302 goto err_no_iores;
303 }
304
305 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
306 pdev->name);
307
308 if (hw->ioarea == NULL) {
309 dev_err(&pdev->dev, "Cannot reserve region\n");
310 err = -ENXIO;
311 goto err_no_iores;
312 }
313
314 hw->regs = ioremap(res->start, (res->end - res->start)+1);
315 if (hw->regs == NULL) {
316 dev_err(&pdev->dev, "Cannot map IO\n");
317 err = -ENXIO;
318 goto err_no_iomap;
319 }
320
321 hw->irq = platform_get_irq(pdev, 0);
322 if (hw->irq < 0) {
323 dev_err(&pdev->dev, "No IRQ specified\n");
324 err = -ENOENT;
325 goto err_no_irq;
326 }
327
328 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
329 if (err) {
330 dev_err(&pdev->dev, "Cannot claim IRQ\n");
331 goto err_no_irq;
332 }
333
334 hw->clk = clk_get(&pdev->dev, "spi");
335 if (IS_ERR(hw->clk)) {
336 dev_err(&pdev->dev, "No clock for device\n");
337 err = PTR_ERR(hw->clk);
338 goto err_no_clk;
339 }
340
341 /* setup any gpio we can */
342
343 if (!pdata->set_cs) {
344 if (pdata->pin_cs < 0) {
345 dev_err(&pdev->dev, "No chipselect pin\n");
346 goto err_register;
347 }
348
349 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
350 if (err) {
351 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
352 goto err_register;
353 }
354
355 hw->set_cs = s3c24xx_spi_gpiocs;
356 gpio_direction_output(pdata->pin_cs, 1);
357 } else
358 hw->set_cs = pdata->set_cs;
359
360 s3c24xx_spi_initialsetup(hw);
361
362 /* register our spi controller */
363
364 err = spi_bitbang_start(&hw->bitbang);
365 if (err) {
366 dev_err(&pdev->dev, "Failed to register SPI master\n");
367 goto err_register;
368 }
369
370 return 0;
371
372 err_register:
373 if (hw->set_cs == s3c24xx_spi_gpiocs)
374 gpio_free(pdata->pin_cs);
375
376 clk_disable(hw->clk);
377 clk_put(hw->clk);
378
379 err_no_clk:
380 free_irq(hw->irq, hw);
381
382 err_no_irq:
383 iounmap(hw->regs);
384
385 err_no_iomap:
386 release_resource(hw->ioarea);
387 kfree(hw->ioarea);
388
389 err_no_iores:
390 err_no_pdata:
391 spi_master_put(hw->master);;
392
393 err_nomem:
394 return err;
395 }
396
397 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
398 {
399 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
400
401 platform_set_drvdata(dev, NULL);
402
403 spi_unregister_master(hw->master);
404
405 clk_disable(hw->clk);
406 clk_put(hw->clk);
407
408 free_irq(hw->irq, hw);
409 iounmap(hw->regs);
410
411 if (hw->set_cs == s3c24xx_spi_gpiocs)
412 gpio_free(hw->pdata->pin_cs);
413
414 release_resource(hw->ioarea);
415 kfree(hw->ioarea);
416
417 spi_master_put(hw->master);
418 return 0;
419 }
420
421
422 #ifdef CONFIG_PM
423
424 static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
425 {
426 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
427
428 if (hw->pdata && hw->pdata->gpio_setup)
429 hw->pdata->gpio_setup(hw->pdata, 0);
430
431 clk_disable(hw->clk);
432 return 0;
433 }
434
435 static int s3c24xx_spi_resume(struct platform_device *pdev)
436 {
437 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
438
439 s3c24xx_spi_initialsetup(hw);
440 return 0;
441 }
442
443 #else
444 #define s3c24xx_spi_suspend NULL
445 #define s3c24xx_spi_resume NULL
446 #endif
447
448 MODULE_ALIAS("platform:s3c2410-spi");
449 static struct platform_driver s3c24xx_spi_driver = {
450 .remove = __exit_p(s3c24xx_spi_remove),
451 .suspend = s3c24xx_spi_suspend,
452 .resume = s3c24xx_spi_resume,
453 .driver = {
454 .name = "s3c2410-spi",
455 .owner = THIS_MODULE,
456 },
457 };
458
459 static int __init s3c24xx_spi_init(void)
460 {
461 return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
462 }
463
464 static void __exit s3c24xx_spi_exit(void)
465 {
466 platform_driver_unregister(&s3c24xx_spi_driver);
467 }
468
469 module_init(s3c24xx_spi_init);
470 module_exit(s3c24xx_spi_exit);
471
472 MODULE_DESCRIPTION("S3C24XX SPI Driver");
473 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
474 MODULE_LICENSE("GPL");
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