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x86: add comments to processor.h
[linux-2.6.git] / include / asm-x86 / processor.h
blob1f9501a3849321a8a87c8960394d638be51f73a0
1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* migration helpers, for KVM - will be removed in 2.6.25: */
7 #include <asm/vm86.h>
8 #define Xgt_desc_struct desc_ptr
9
10 /* Forward declaration, a strange C thing */
11 struct task_struct;
12 struct mm_struct;
13
14 #include <asm/vm86.h>
15 #include <asm/math_emu.h>
16 #include <asm/segment.h>
17 #include <asm/types.h>
18 #include <asm/sigcontext.h>
19 #include <asm/current.h>
20 #include <asm/cpufeature.h>
21 #include <asm/system.h>
22 #include <asm/page.h>
23 #include <asm/percpu.h>
24 #include <asm/msr.h>
25 #include <asm/desc_defs.h>
26 #include <asm/nops.h>
27
28 #include <linux/personality.h>
29 #include <linux/cpumask.h>
30 #include <linux/cache.h>
31 #include <linux/threads.h>
32 #include <linux/init.h>
33
34 /*
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
37 */
38 static inline void *current_text_addr(void)
39 {
40 void *pc;
41
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
43
44 return pc;
45 }
46
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
50 #else
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 #endif
54
55 /*
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
59 */
60
61 struct cpuinfo_x86 {
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
64 __u8 x86_model;
65 __u8 x86_mask;
66 #ifdef CONFIG_X86_32
67 char wp_works_ok; /* It doesn't on 386's */
68
69 /* Problems on some 486Dx4's and old 386's: */
70 char hlt_works_ok;
71 char hard_math;
72 char rfu;
73 char fdiv_bug;
74 char f00f_bug;
75 char coma_bug;
76 char pad0;
77 #else
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
79 int x86_tlbsize;
80 __u8 x86_virt_bits;
81 __u8 x86_phys_bits;
82 /* CPUID returned core id bits: */
83 __u8 x86_coreid_bits;
84 /* Max extended CPUID function supported: */
85 __u32 extended_cpuid_level;
86 #endif
87 /* Maximum supported CPUID level, -1=no CPUID: */
88 int cpuid_level;
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
93 int x86_cache_size;
94 int x86_cache_alignment; /* In bytes */
95 int x86_power;
96 unsigned long loops_per_jiffy;
97 #ifdef CONFIG_SMP
98 /* cpus sharing the last level cache: */
99 cpumask_t llc_shared_map;
100 #endif
101 /* cpuid returned max cores value: */
102 u16 x86_max_cores;
103 u16 apicid;
104 u16 x86_clflush_size;
105 #ifdef CONFIG_SMP
106 /* number of cores as seen by the OS: */
107 u16 booted_cores;
108 /* Physical processor id: */
109 u16 phys_proc_id;
110 /* Core id: */
111 u16 cpu_core_id;
112 /* Index into per_cpu list: */
113 u16 cpu_index;
114 #endif
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
116
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_NEXGEN 4
122 #define X86_VENDOR_CENTAUR 5
123 #define X86_VENDOR_TRANSMETA 7
124 #define X86_VENDOR_NSC 8
125 #define X86_VENDOR_NUM 9
126
127 #define X86_VENDOR_UNKNOWN 0xff
128
129 /*
130 * capabilities of CPUs
131 */
132 extern struct cpuinfo_x86 boot_cpu_data;
133 extern struct cpuinfo_x86 new_cpu_data;
134
135 extern struct tss_struct doublefault_tss;
136 extern __u32 cleared_cpu_caps[NCAPINTS];
137
138 #ifdef CONFIG_SMP
139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
141 #define current_cpu_data cpu_data(smp_processor_id())
142 #else
143 #define cpu_data(cpu) boot_cpu_data
144 #define current_cpu_data boot_cpu_data
145 #endif
146
147 static inline int hlt_works(int cpu)
148 {
149 #ifdef CONFIG_X86_32
150 return cpu_data(cpu).hlt_works_ok;
151 #else
152 return 1;
153 #endif
154 }
155
156 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157
158 extern void cpu_detect(struct cpuinfo_x86 *c);
159
160 extern void identify_cpu(struct cpuinfo_x86 *);
161 extern void identify_boot_cpu(void);
162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
163 extern void print_cpu_info(struct cpuinfo_x86 *);
164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
166 extern unsigned short num_cache_leaves;
167
168 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
169 extern void detect_ht(struct cpuinfo_x86 *c);
170 #else
171 static inline void detect_ht(struct cpuinfo_x86 *c) {}
172 #endif
173
174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
175 unsigned int *ecx, unsigned int *edx)
176 {
177 /* ecx is often an input as well as an output. */
178 __asm__("cpuid"
179 : "=a" (*eax),
180 "=b" (*ebx),
181 "=c" (*ecx),
182 "=d" (*edx)
183 : "0" (*eax), "2" (*ecx));
184 }
185
186 static inline void load_cr3(pgd_t *pgdir)
187 {
188 write_cr3(__pa(pgdir));
189 }
190
191 #ifdef CONFIG_X86_32
192 /* This is the TSS defined by the hardware. */
193 struct x86_hw_tss {
194 unsigned short back_link, __blh;
195 unsigned long sp0;
196 unsigned short ss0, __ss0h;
197 unsigned long sp1;
198 /* ss1 caches MSR_IA32_SYSENTER_CS: */
199 unsigned short ss1, __ss1h;
200 unsigned long sp2;
201 unsigned short ss2, __ss2h;
202 unsigned long __cr3;
203 unsigned long ip;
204 unsigned long flags;
205 unsigned long ax;
206 unsigned long cx;
207 unsigned long dx;
208 unsigned long bx;
209 unsigned long sp;
210 unsigned long bp;
211 unsigned long si;
212 unsigned long di;
213 unsigned short es, __esh;
214 unsigned short cs, __csh;
215 unsigned short ss, __ssh;
216 unsigned short ds, __dsh;
217 unsigned short fs, __fsh;
218 unsigned short gs, __gsh;
219 unsigned short ldt, __ldth;
220 unsigned short trace;
221 unsigned short io_bitmap_base;
222
223 } __attribute__((packed));
224 #else
225 struct x86_hw_tss {
226 u32 reserved1;
227 u64 sp0;
228 u64 sp1;
229 u64 sp2;
230 u64 reserved2;
231 u64 ist[7];
232 u32 reserved3;
233 u32 reserved4;
234 u16 reserved5;
235 u16 io_bitmap_base;
236
237 } __attribute__((packed)) ____cacheline_aligned;
238 #endif
239
240 /*
241 * IO-bitmap sizes:
242 */
243 #define IO_BITMAP_BITS 65536
244 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
245 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
246 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
247 #define INVALID_IO_BITMAP_OFFSET 0x8000
248 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
249
250 struct tss_struct {
251 /*
252 * The hardware state:
253 */
254 struct x86_hw_tss x86_tss;
255
256 /*
257 * The extra 1 is there because the CPU will access an
258 * additional byte beyond the end of the IO permission
259 * bitmap. The extra byte must be all 1 bits, and must
260 * be within the limit.
261 */
262 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
263 /*
264 * Cache the current maximum and the last task that used the bitmap:
265 */
266 unsigned long io_bitmap_max;
267 struct thread_struct *io_bitmap_owner;
268
269 /*
270 * Pad the TSS to be cacheline-aligned (size is 0x100):
271 */
272 unsigned long __cacheline_filler[35];
273 /*
274 * .. and then another 0x100 bytes for the emergency kernel stack:
275 */
276 unsigned long stack[64];
277
278 } __attribute__((packed));
279
280 DECLARE_PER_CPU(struct tss_struct, init_tss);
281
282 /*
283 * Save the original ist values for checking stack pointers during debugging
284 */
285 struct orig_ist {
286 unsigned long ist[7];
287 };
288
289 #define MXCSR_DEFAULT 0x1f80
290
291 struct i387_fsave_struct {
292 u32 cwd; /* FPU Control Word */
293 u32 swd; /* FPU Status Word */
294 u32 twd; /* FPU Tag Word */
295 u32 fip; /* FPU IP Offset */
296 u32 fcs; /* FPU IP Selector */
297 u32 foo; /* FPU Operand Pointer Offset */
298 u32 fos; /* FPU Operand Pointer Selector */
299
300 /* 8*10 bytes for each FP-reg = 80 bytes: */
301 u32 st_space[20];
302
303 /* Software status information [not touched by FSAVE ]: */
304 u32 status;
305 };
306
307 struct i387_fxsave_struct {
308 u16 cwd; /* Control Word */
309 u16 swd; /* Status Word */
310 u16 twd; /* Tag Word */
311 u16 fop; /* Last Instruction Opcode */
312 union {
313 struct {
314 u64 rip; /* Instruction Pointer */
315 u64 rdp; /* Data Pointer */
316 };
317 struct {
318 u32 fip; /* FPU IP Offset */
319 u32 fcs; /* FPU IP Selector */
320 u32 foo; /* FPU Operand Offset */
321 u32 fos; /* FPU Operand Selector */
322 };
323 };
324 u32 mxcsr; /* MXCSR Register State */
325 u32 mxcsr_mask; /* MXCSR Mask */
326
327 /* 8*16 bytes for each FP-reg = 128 bytes: */
328 u32 st_space[32];
329
330 /* 16*16 bytes for each XMM-reg = 256 bytes: */
331 u32 xmm_space[64];
332
333 u32 padding[24];
334
335 } __attribute__((aligned(16)));
336
337 struct i387_soft_struct {
338 u32 cwd;
339 u32 swd;
340 u32 twd;
341 u32 fip;
342 u32 fcs;
343 u32 foo;
344 u32 fos;
345 /* 8*10 bytes for each FP-reg = 80 bytes: */
346 u32 st_space[20];
347 u8 ftop;
348 u8 changed;
349 u8 lookahead;
350 u8 no_update;
351 u8 rm;
352 u8 alimit;
353 struct info *info;
354 u32 entry_eip;
355 };
356
357 union i387_union {
358 struct i387_fsave_struct fsave;
359 struct i387_fxsave_struct fxsave;
360 struct i387_soft_struct soft;
361 };
362
363 #ifdef CONFIG_X86_64
364 DECLARE_PER_CPU(struct orig_ist, orig_ist);
365 #endif
366
367 extern void print_cpu_info(struct cpuinfo_x86 *);
368 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
369 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
370 extern unsigned short num_cache_leaves;
371
372 struct thread_struct {
373 /* Cached TLS descriptors: */
374 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
375 unsigned long sp0;
376 unsigned long sp;
377 #ifdef CONFIG_X86_32
378 unsigned long sysenter_cs;
379 #else
380 unsigned long usersp; /* Copy from PDA */
381 unsigned short es;
382 unsigned short ds;
383 unsigned short fsindex;
384 unsigned short gsindex;
385 #endif
386 unsigned long ip;
387 unsigned long fs;
388 unsigned long gs;
389 /* Hardware debugging registers: */
390 unsigned long debugreg0;
391 unsigned long debugreg1;
392 unsigned long debugreg2;
393 unsigned long debugreg3;
394 unsigned long debugreg6;
395 unsigned long debugreg7;
396 /* Fault info: */
397 unsigned long cr2;
398 unsigned long trap_no;
399 unsigned long error_code;
400 /* Floating point info: */
401 union i387_union i387 __attribute__((aligned(16)));;
402 #ifdef CONFIG_X86_32
403 /* Virtual 86 mode info */
404 struct vm86_struct __user *vm86_info;
405 unsigned long screen_bitmap;
406 unsigned long v86flags;
407 unsigned long v86mask;
408 unsigned long saved_sp0;
409 unsigned int saved_fs;
410 unsigned int saved_gs;
411 #endif
412 /* IO permissions: */
413 unsigned long *io_bitmap_ptr;
414 unsigned long iopl;
415 /* Max allowed port in the bitmap, in bytes: */
416 unsigned io_bitmap_max;
417 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
418 unsigned long debugctlmsr;
419 /* Debug Store - if not 0 points to a DS Save Area configuration;
420 * goes into MSR_IA32_DS_AREA */
421 unsigned long ds_area_msr;
422 };
423
424 static inline unsigned long native_get_debugreg(int regno)
425 {
426 unsigned long val = 0; /* Damn you, gcc! */
427
428 switch (regno) {
429 case 0:
430 asm("mov %%db0, %0" :"=r" (val)); break;
431 case 1:
432 asm("mov %%db1, %0" :"=r" (val)); break;
433 case 2:
434 asm("mov %%db2, %0" :"=r" (val)); break;
435 case 3:
436 asm("mov %%db3, %0" :"=r" (val)); break;
437 case 6:
438 asm("mov %%db6, %0" :"=r" (val)); break;
439 case 7:
440 asm("mov %%db7, %0" :"=r" (val)); break;
441 default:
442 BUG();
443 }
444 return val;
445 }
446
447 static inline void native_set_debugreg(int regno, unsigned long value)
448 {
449 switch (regno) {
450 case 0:
451 asm("mov %0, %%db0" ::"r" (value));
452 break;
453 case 1:
454 asm("mov %0, %%db1" ::"r" (value));
455 break;
456 case 2:
457 asm("mov %0, %%db2" ::"r" (value));
458 break;
459 case 3:
460 asm("mov %0, %%db3" ::"r" (value));
461 break;
462 case 6:
463 asm("mov %0, %%db6" ::"r" (value));
464 break;
465 case 7:
466 asm("mov %0, %%db7" ::"r" (value));
467 break;
468 default:
469 BUG();
470 }
471 }
472
473 /*
474 * Set IOPL bits in EFLAGS from given mask
475 */
476 static inline void native_set_iopl_mask(unsigned mask)
477 {
478 #ifdef CONFIG_X86_32
479 unsigned int reg;
480
481 __asm__ __volatile__ ("pushfl;"
482 "popl %0;"
483 "andl %1, %0;"
484 "orl %2, %0;"
485 "pushl %0;"
486 "popfl"
487 : "=&r" (reg)
488 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
489 #endif
490 }
491
492 static inline void
493 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
494 {
495 tss->x86_tss.sp0 = thread->sp0;
496 #ifdef CONFIG_X86_32
497 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
498 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
499 tss->x86_tss.ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
501 }
502 #endif
503 }
504
505 static inline void native_swapgs(void)
506 {
507 #ifdef CONFIG_X86_64
508 asm volatile("swapgs" ::: "memory");
509 #endif
510 }
511
512 #ifdef CONFIG_PARAVIRT
513 #include <asm/paravirt.h>
514 #else
515 #define __cpuid native_cpuid
516 #define paravirt_enabled() 0
517
518 /*
519 * These special macros can be used to get or set a debugging register
520 */
521 #define get_debugreg(var, register) \
522 (var) = native_get_debugreg(register)
523 #define set_debugreg(value, register) \
524 native_set_debugreg(register, value)
525
526 static inline void
527 load_sp0(struct tss_struct *tss, struct thread_struct *thread)
528 {
529 native_load_sp0(tss, thread);
530 }
531
532 #define set_iopl_mask native_set_iopl_mask
533 #define SWAPGS swapgs
534 #endif /* CONFIG_PARAVIRT */
535
536 /*
537 * Save the cr4 feature set we're using (ie
538 * Pentium 4MB enable and PPro Global page
539 * enable), so that any CPU's that boot up
540 * after us can get the correct flags.
541 */
542 extern unsigned long mmu_cr4_features;
543
544 static inline void set_in_cr4(unsigned long mask)
545 {
546 unsigned cr4;
547
548 mmu_cr4_features |= mask;
549 cr4 = read_cr4();
550 cr4 |= mask;
551 write_cr4(cr4);
552 }
553
554 static inline void clear_in_cr4(unsigned long mask)
555 {
556 unsigned cr4;
557
558 mmu_cr4_features &= ~mask;
559 cr4 = read_cr4();
560 cr4 &= ~mask;
561 write_cr4(cr4);
562 }
563
564 struct microcode_header {
565 unsigned int hdrver;
566 unsigned int rev;
567 unsigned int date;
568 unsigned int sig;
569 unsigned int cksum;
570 unsigned int ldrver;
571 unsigned int pf;
572 unsigned int datasize;
573 unsigned int totalsize;
574 unsigned int reserved[3];
575 };
576
577 struct microcode {
578 struct microcode_header hdr;
579 unsigned int bits[0];
580 };
581
582 typedef struct microcode microcode_t;
583 typedef struct microcode_header microcode_header_t;
584
585 /* microcode format is extended from prescott processors */
586 struct extended_signature {
587 unsigned int sig;
588 unsigned int pf;
589 unsigned int cksum;
590 };
591
592 struct extended_sigtable {
593 unsigned int count;
594 unsigned int cksum;
595 unsigned int reserved[3];
596 struct extended_signature sigs[0];
597 };
598
599 typedef struct {
600 unsigned long seg;
601 } mm_segment_t;
602
603
604 /*
605 * create a kernel thread without removing it from tasklists
606 */
607 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
608
609 /* Free all resources held by a thread. */
610 extern void release_thread(struct task_struct *);
611
612 /* Prepare to copy thread state - unlazy all lazy state */
613 extern void prepare_to_copy(struct task_struct *tsk);
614
615 unsigned long get_wchan(struct task_struct *p);
616
617 /*
618 * Generic CPUID function
619 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
620 * resulting in stale register contents being returned.
621 */
622 static inline void cpuid(unsigned int op,
623 unsigned int *eax, unsigned int *ebx,
624 unsigned int *ecx, unsigned int *edx)
625 {
626 *eax = op;
627 *ecx = 0;
628 __cpuid(eax, ebx, ecx, edx);
629 }
630
631 /* Some CPUID calls want 'count' to be placed in ecx */
632 static inline void cpuid_count(unsigned int op, int count,
633 unsigned int *eax, unsigned int *ebx,
634 unsigned int *ecx, unsigned int *edx)
635 {
636 *eax = op;
637 *ecx = count;
638 __cpuid(eax, ebx, ecx, edx);
639 }
640
641 /*
642 * CPUID functions returning a single datum
643 */
644 static inline unsigned int cpuid_eax(unsigned int op)
645 {
646 unsigned int eax, ebx, ecx, edx;
647
648 cpuid(op, &eax, &ebx, &ecx, &edx);
649
650 return eax;
651 }
652
653 static inline unsigned int cpuid_ebx(unsigned int op)
654 {
655 unsigned int eax, ebx, ecx, edx;
656
657 cpuid(op, &eax, &ebx, &ecx, &edx);
658
659 return ebx;
660 }
661
662 static inline unsigned int cpuid_ecx(unsigned int op)
663 {
664 unsigned int eax, ebx, ecx, edx;
665
666 cpuid(op, &eax, &ebx, &ecx, &edx);
667
668 return ecx;
669 }
670
671 static inline unsigned int cpuid_edx(unsigned int op)
672 {
673 unsigned int eax, ebx, ecx, edx;
674
675 cpuid(op, &eax, &ebx, &ecx, &edx);
676
677 return edx;
678 }
679
680 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
681 static inline void rep_nop(void)
682 {
683 __asm__ __volatile__("rep; nop" ::: "memory");
684 }
685
686 static inline void cpu_relax(void)
687 {
688 rep_nop();
689 }
690
691 /* Stop speculative execution: */
692 static inline void sync_core(void)
693 {
694 int tmp;
695
696 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
697 : "ebx", "ecx", "edx", "memory");
698 }
699
700 static inline void
701 __monitor(const void *eax, unsigned long ecx, unsigned long edx)
702 {
703 /* "monitor %eax, %ecx, %edx;" */
704 asm volatile(
705 ".byte 0x0f, 0x01, 0xc8;"
706 :: "a" (eax), "c" (ecx), "d"(edx));
707 }
708
709 static inline void __mwait(unsigned long eax, unsigned long ecx)
710 {
711 /* "mwait %eax, %ecx;" */
712 asm volatile(
713 ".byte 0x0f, 0x01, 0xc9;"
714 :: "a" (eax), "c" (ecx));
715 }
716
717 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
718 {
719 /* "mwait %eax, %ecx;" */
720 asm volatile(
721 "sti; .byte 0x0f, 0x01, 0xc9;"
722 :: "a" (eax), "c" (ecx));
723 }
724
725 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
726
727 extern int force_mwait;
728
729 extern void select_idle_routine(const struct cpuinfo_x86 *c);
730
731 extern unsigned long boot_option_idle_override;
732
733 extern void enable_sep_cpu(void);
734 extern int sysenter_setup(void);
735
736 /* Defined in head.S */
737 extern struct desc_ptr early_gdt_descr;
738
739 extern void cpu_set_gdt(int);
740 extern void switch_to_new_gdt(void);
741 extern void cpu_init(void);
742 extern void init_gdt(int cpu);
743
744 /*
745 * from system description table in BIOS. Mostly for MCA use, but
746 * others may find it useful:
747 */
748 extern unsigned int machine_id;
749 extern unsigned int machine_submodel_id;
750 extern unsigned int BIOS_revision;
751
752 /* Boot loader type from the setup header: */
753 extern int bootloader_type;
754
755 extern char ignore_fpu_irq;
756
757 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
758 #define ARCH_HAS_PREFETCHW
759 #define ARCH_HAS_SPINLOCK_PREFETCH
760
761 #ifdef CONFIG_X86_32
762 # define BASE_PREFETCH ASM_NOP4
763 # define ARCH_HAS_PREFETCH
764 #else
765 # define BASE_PREFETCH "prefetcht0 (%1)"
766 #endif
767
768 /*
769 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
770 *
771 * It's not worth to care about 3dnow prefetches for the K6
772 * because they are microcoded there and very slow.
773 */
774 static inline void prefetch(const void *x)
775 {
776 alternative_input(BASE_PREFETCH,
777 "prefetchnta (%1)",
778 X86_FEATURE_XMM,
779 "r" (x));
780 }
781
782 /*
783 * 3dnow prefetch to get an exclusive cache line.
784 * Useful for spinlocks to avoid one state transition in the
785 * cache coherency protocol:
786 */
787 static inline void prefetchw(const void *x)
788 {
789 alternative_input(BASE_PREFETCH,
790 "prefetchw (%1)",
791 X86_FEATURE_3DNOW,
792 "r" (x));
793 }
794
795 static inline void spin_lock_prefetch(const void *x)
796 {
797 prefetchw(x);
798 }
799
800 #ifdef CONFIG_X86_32
801 /*
802 * User space process size: 3GB (default).
803 */
804 #define TASK_SIZE PAGE_OFFSET
805 #define STACK_TOP TASK_SIZE
806 #define STACK_TOP_MAX STACK_TOP
807
808 #define INIT_THREAD { \
809 .sp0 = sizeof(init_stack) + (long)&init_stack, \
810 .vm86_info = NULL, \
811 .sysenter_cs = __KERNEL_CS, \
812 .io_bitmap_ptr = NULL, \
813 .fs = __KERNEL_PERCPU, \
814 }
815
816 /*
817 * Note that the .io_bitmap member must be extra-big. This is because
818 * the CPU will access an additional byte beyond the end of the IO
819 * permission bitmap. The extra byte must be all 1 bits, and must
820 * be within the limit.
821 */
822 #define INIT_TSS { \
823 .x86_tss = { \
824 .sp0 = sizeof(init_stack) + (long)&init_stack, \
825 .ss0 = __KERNEL_DS, \
826 .ss1 = __KERNEL_CS, \
827 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
828 }, \
829 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
830 }
831
832 extern unsigned long thread_saved_pc(struct task_struct *tsk);
833
834 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
835 #define KSTK_TOP(info) \
836 ({ \
837 unsigned long *__ptr = (unsigned long *)(info); \
838 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
839 })
840
841 /*
842 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
843 * This is necessary to guarantee that the entire "struct pt_regs"
844 * is accessable even if the CPU haven't stored the SS/ESP registers
845 * on the stack (interrupt gate does not save these registers
846 * when switching to the same priv ring).
847 * Therefore beware: accessing the ss/esp fields of the
848 * "struct pt_regs" is possible, but they may contain the
849 * completely wrong values.
850 */
851 #define task_pt_regs(task) \
852 ({ \
853 struct pt_regs *__regs__; \
854 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
855 __regs__ - 1; \
856 })
857
858 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
859
860 #else
861 /*
862 * User space process size. 47bits minus one guard page.
863 */
864 #define TASK_SIZE64 (0x800000000000UL - 4096)
865
866 /* This decides where the kernel will search for a free chunk of vm
867 * space during mmap's.
868 */
869 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
870 0xc0000000 : 0xFFFFe000)
871
872 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
873 IA32_PAGE_OFFSET : TASK_SIZE64)
874 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
875 IA32_PAGE_OFFSET : TASK_SIZE64)
876
877 #define STACK_TOP TASK_SIZE
878 #define STACK_TOP_MAX TASK_SIZE64
879
880 #define INIT_THREAD { \
881 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
882 }
883
884 #define INIT_TSS { \
885 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
886 }
887
888 /*
889 * Return saved PC of a blocked thread.
890 * What is this good for? it will be always the scheduler or ret_from_fork.
891 */
892 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
893
894 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
895 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
896 #endif /* CONFIG_X86_64 */
897
898 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
899 unsigned long new_sp);
900
901 /*
902 * This decides where the kernel will search for a free chunk of vm
903 * space during mmap's.
904 */
905 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
906
907 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
908
909 #endif
Linus' kernel tree