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rtl8192se: Update copyright dates
[linux-2.6.git] / drivers / net / wireless / rtlwifi / rtl8192se / phy.c
blobadfac569b67c46e27881645798015614fc8bfb0a
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include "../wifi.h"
33 #include "../pci.h"
34 #include "../ps.h"
35 #include "reg.h"
36 #include "def.h"
37 #include "phy.h"
38 #include "rf.h"
39 #include "dm.h"
40 #include "fw.h"
41 #include "hw.h"
42 #include "table.h"
43
44 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
45 {
46 u32 i;
47
48 for (i = 0; i <= 31; i++) {
49 if (((bitmask >> i) & 0x1) == 1)
50 break;
51 }
52
53 return i;
54 }
55
56 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
57 {
58 struct rtl_priv *rtlpriv = rtl_priv(hw);
59 u32 returnvalue = 0, originalvalue, bitshift;
60
61 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
62 regaddr, bitmask);
63
64 originalvalue = rtl_read_dword(rtlpriv, regaddr);
65 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
66 returnvalue = (originalvalue & bitmask) >> bitshift;
67
68 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
69 bitmask, regaddr, originalvalue);
70
71 return returnvalue;
72
73 }
74
75 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
76 u32 data)
77 {
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 u32 originalvalue, bitshift;
80
81 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
82 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
83 regaddr, bitmask, data);
84
85 if (bitmask != MASKDWORD) {
86 originalvalue = rtl_read_dword(rtlpriv, regaddr);
87 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
88 data = ((originalvalue & (~bitmask)) | (data << bitshift));
89 }
90
91 rtl_write_dword(rtlpriv, regaddr, data);
92
93 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
94 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
95 regaddr, bitmask, data);
96
97 }
98
99 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
100 enum radio_path rfpath, u32 offset)
101 {
102
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct rtl_phy *rtlphy = &(rtlpriv->phy);
105 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
106 u32 newoffset;
107 u32 tmplong, tmplong2;
108 u8 rfpi_enable = 0;
109 u32 retvalue = 0;
110
111 offset &= 0x3f;
112 newoffset = offset;
113
114 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
115
116 if (rfpath == RF90_PATH_A)
117 tmplong2 = tmplong;
118 else
119 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
120
121 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
122 BLSSI_READEDGE;
123
124 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
125 tmplong & (~BLSSI_READEDGE));
126
127 mdelay(1);
128
129 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
130 mdelay(1);
131
132 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
133 BLSSI_READEDGE);
134 mdelay(1);
135
136 if (rfpath == RF90_PATH_A)
137 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
138 BIT(8));
139 else if (rfpath == RF90_PATH_B)
140 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
141 BIT(8));
142
143 if (rfpi_enable)
144 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
145 BLSSI_READBACK_DATA);
146 else
147 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
148 BLSSI_READBACK_DATA);
149
150 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
151 BLSSI_READBACK_DATA);
152
153 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
154 rfpath, pphyreg->rflssi_readback, retvalue);
155
156 return retvalue;
157
158 }
159
160 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
161 enum radio_path rfpath, u32 offset,
162 u32 data)
163 {
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
165 struct rtl_phy *rtlphy = &(rtlpriv->phy);
166 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
167 u32 data_and_addr = 0;
168 u32 newoffset;
169
170 offset &= 0x3f;
171 newoffset = offset;
172
173 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
174 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
175
176 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
177 rfpath, pphyreg->rf3wire_offset, data_and_addr);
178 }
179
180
181 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
182 u32 regaddr, u32 bitmask)
183 {
184 struct rtl_priv *rtlpriv = rtl_priv(hw);
185 u32 original_value, readback_value, bitshift;
186
187 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
188 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
189 regaddr, rfpath, bitmask);
190
191 spin_lock(&rtlpriv->locks.rf_lock);
192
193 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
194
195 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
196 readback_value = (original_value & bitmask) >> bitshift;
197
198 spin_unlock(&rtlpriv->locks.rf_lock);
199
200 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
201 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
202 regaddr, rfpath, bitmask, original_value);
203
204 return readback_value;
205 }
206
207 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
208 u32 regaddr, u32 bitmask, u32 data)
209 {
210 struct rtl_priv *rtlpriv = rtl_priv(hw);
211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
212 u32 original_value, bitshift;
213
214 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
215 return;
216
217 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
218 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
219 regaddr, bitmask, data, rfpath);
220
221 spin_lock(&rtlpriv->locks.rf_lock);
222
223 if (bitmask != RFREG_OFFSET_MASK) {
224 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
225 regaddr);
226 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
227 data = ((original_value & (~bitmask)) | (data << bitshift));
228 }
229
230 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
231
232 spin_unlock(&rtlpriv->locks.rf_lock);
233
234 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
235 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
236 regaddr, bitmask, data, rfpath);
237
238 }
239
240 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
241 u8 operation)
242 {
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
245
246 if (!is_hal_stop(rtlhal)) {
247 switch (operation) {
248 case SCAN_OPT_BACKUP:
249 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
250 break;
251 case SCAN_OPT_RESTORE:
252 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
253 break;
254 default:
255 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
256 "Unknown operation\n");
257 break;
258 }
259 }
260 }
261
262 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
263 enum nl80211_channel_type ch_type)
264 {
265 struct rtl_priv *rtlpriv = rtl_priv(hw);
266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
267 struct rtl_phy *rtlphy = &(rtlpriv->phy);
268 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
269 u8 reg_bw_opmode;
270
271 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
272 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
273 "20MHz" : "40MHz");
274
275 if (rtlphy->set_bwmode_inprogress)
276 return;
277 if (is_hal_stop(rtlhal))
278 return;
279
280 rtlphy->set_bwmode_inprogress = true;
281
282 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
283 /* dummy read */
284 rtl_read_byte(rtlpriv, RRSR + 2);
285
286 switch (rtlphy->current_chan_bw) {
287 case HT_CHANNEL_WIDTH_20:
288 reg_bw_opmode |= BW_OPMODE_20MHZ;
289 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
290 break;
291 case HT_CHANNEL_WIDTH_20_40:
292 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
293 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
294 break;
295 default:
296 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
297 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
298 break;
299 }
300
301 switch (rtlphy->current_chan_bw) {
302 case HT_CHANNEL_WIDTH_20:
303 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
304 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
305
306 if (rtlhal->version >= VERSION_8192S_BCUT)
307 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
308 break;
309 case HT_CHANNEL_WIDTH_20_40:
310 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
311 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
312
313 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
314 (mac->cur_40_prime_sc >> 1));
315 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
316
317 if (rtlhal->version >= VERSION_8192S_BCUT)
318 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
319 break;
320 default:
321 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
322 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
323 break;
324 }
325
326 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
327 rtlphy->set_bwmode_inprogress = false;
328 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
329 }
330
331 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
332 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
333 u32 para1, u32 para2, u32 msdelay)
334 {
335 struct swchnlcmd *pcmd;
336
337 if (cmdtable == NULL) {
338 RT_ASSERT(false, "cmdtable cannot be NULL\n");
339 return false;
340 }
341
342 if (cmdtableidx >= cmdtablesz)
343 return false;
344
345 pcmd = cmdtable + cmdtableidx;
346 pcmd->cmdid = cmdid;
347 pcmd->para1 = para1;
348 pcmd->para2 = para2;
349 pcmd->msdelay = msdelay;
350
351 return true;
352 }
353
354 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
355 u8 channel, u8 *stage, u8 *step, u32 *delay)
356 {
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358 struct rtl_phy *rtlphy = &(rtlpriv->phy);
359 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
360 u32 precommoncmdcnt;
361 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
362 u32 postcommoncmdcnt;
363 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
364 u32 rfdependcmdcnt;
365 struct swchnlcmd *currentcmd = NULL;
366 u8 rfpath;
367 u8 num_total_rfpath = rtlphy->num_total_rfpath;
368
369 precommoncmdcnt = 0;
370 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
371 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
372 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
373 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
374
375 postcommoncmdcnt = 0;
376
377 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
378 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
379
380 rfdependcmdcnt = 0;
381
382 RT_ASSERT((channel >= 1 && channel <= 14),
383 "invalid channel for Zebra: %d\n", channel);
384
385 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
386 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
387 RF_CHNLBW, channel, 10);
388
389 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
390 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
391
392 do {
393 switch (*stage) {
394 case 0:
395 currentcmd = &precommoncmd[*step];
396 break;
397 case 1:
398 currentcmd = &rfdependcmd[*step];
399 break;
400 case 2:
401 currentcmd = &postcommoncmd[*step];
402 break;
403 }
404
405 if (currentcmd->cmdid == CMDID_END) {
406 if ((*stage) == 2) {
407 return true;
408 } else {
409 (*stage)++;
410 (*step) = 0;
411 continue;
412 }
413 }
414
415 switch (currentcmd->cmdid) {
416 case CMDID_SET_TXPOWEROWER_LEVEL:
417 rtl92s_phy_set_txpower(hw, channel);
418 break;
419 case CMDID_WRITEPORT_ULONG:
420 rtl_write_dword(rtlpriv, currentcmd->para1,
421 currentcmd->para2);
422 break;
423 case CMDID_WRITEPORT_USHORT:
424 rtl_write_word(rtlpriv, currentcmd->para1,
425 (u16)currentcmd->para2);
426 break;
427 case CMDID_WRITEPORT_UCHAR:
428 rtl_write_byte(rtlpriv, currentcmd->para1,
429 (u8)currentcmd->para2);
430 break;
431 case CMDID_RF_WRITEREG:
432 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
433 rtlphy->rfreg_chnlval[rfpath] =
434 ((rtlphy->rfreg_chnlval[rfpath] &
435 0xfffffc00) | currentcmd->para2);
436 rtl_set_rfreg(hw, (enum radio_path)rfpath,
437 currentcmd->para1,
438 RFREG_OFFSET_MASK,
439 rtlphy->rfreg_chnlval[rfpath]);
440 }
441 break;
442 default:
443 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
444 "switch case not processed\n");
445 break;
446 }
447
448 break;
449 } while (true);
450
451 (*delay) = currentcmd->msdelay;
452 (*step)++;
453 return false;
454 }
455
456 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
457 {
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
460 struct rtl_phy *rtlphy = &(rtlpriv->phy);
461 u32 delay;
462 bool ret;
463
464 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
465 rtlphy->current_channel);
466
467 if (rtlphy->sw_chnl_inprogress)
468 return 0;
469
470 if (rtlphy->set_bwmode_inprogress)
471 return 0;
472
473 if (is_hal_stop(rtlhal))
474 return 0;
475
476 rtlphy->sw_chnl_inprogress = true;
477 rtlphy->sw_chnl_stage = 0;
478 rtlphy->sw_chnl_step = 0;
479
480 do {
481 if (!rtlphy->sw_chnl_inprogress)
482 break;
483
484 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
485 rtlphy->current_channel,
486 &rtlphy->sw_chnl_stage,
487 &rtlphy->sw_chnl_step, &delay);
488 if (!ret) {
489 if (delay > 0)
490 mdelay(delay);
491 else
492 continue;
493 } else {
494 rtlphy->sw_chnl_inprogress = false;
495 }
496 break;
497 } while (true);
498
499 rtlphy->sw_chnl_inprogress = false;
500
501 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
502
503 return 1;
504 }
505
506 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
507 {
508 struct rtl_priv *rtlpriv = rtl_priv(hw);
509 u8 u1btmp;
510
511 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
512 u1btmp |= BIT(0);
513
514 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
515 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
516 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
517 rtl_write_word(rtlpriv, CMDR, 0x57FC);
518 udelay(100);
519
520 rtl_write_word(rtlpriv, CMDR, 0x77FC);
521 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
522 udelay(10);
523
524 rtl_write_word(rtlpriv, CMDR, 0x37FC);
525 udelay(10);
526
527 rtl_write_word(rtlpriv, CMDR, 0x77FC);
528 udelay(10);
529
530 rtl_write_word(rtlpriv, CMDR, 0x57FC);
531
532 /* we should chnge GPIO to input mode
533 * this will drop away current about 25mA*/
534 rtl8192se_gpiobit3_cfg_inputmode(hw);
535 }
536
537 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
538 enum rf_pwrstate rfpwr_state)
539 {
540 struct rtl_priv *rtlpriv = rtl_priv(hw);
541 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
542 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
543 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
544 bool bresult = true;
545 u8 i, queue_id;
546 struct rtl8192_tx_ring *ring = NULL;
547
548 if (rfpwr_state == ppsc->rfpwr_state)
549 return false;
550
551 switch (rfpwr_state) {
552 case ERFON:{
553 if ((ppsc->rfpwr_state == ERFOFF) &&
554 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
555
556 bool rtstatus;
557 u32 InitializeCount = 0;
558 do {
559 InitializeCount++;
560 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
561 "IPS Set eRf nic enable\n");
562 rtstatus = rtl_ps_enable_nic(hw);
563 } while ((rtstatus != true) &&
564 (InitializeCount < 10));
565
566 RT_CLEAR_PS_LEVEL(ppsc,
567 RT_RF_OFF_LEVL_HALT_NIC);
568 } else {
569 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
570 "awake, sleeped:%d ms state_inap:%x\n",
571 jiffies_to_msecs(jiffies -
572 ppsc->
573 last_sleep_jiffies),
574 rtlpriv->psc.state_inap);
575 ppsc->last_awake_jiffies = jiffies;
576 rtl_write_word(rtlpriv, CMDR, 0x37FC);
577 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
578 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
579 }
580
581 if (mac->link_state == MAC80211_LINKED)
582 rtlpriv->cfg->ops->led_control(hw,
583 LED_CTL_LINK);
584 else
585 rtlpriv->cfg->ops->led_control(hw,
586 LED_CTL_NO_LINK);
587 break;
588 }
589 case ERFOFF:{
590 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
591 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
592 "IPS Set eRf nic disable\n");
593 rtl_ps_disable_nic(hw);
594 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
595 } else {
596 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
597 rtlpriv->cfg->ops->led_control(hw,
598 LED_CTL_NO_LINK);
599 else
600 rtlpriv->cfg->ops->led_control(hw,
601 LED_CTL_POWER_OFF);
602 }
603 break;
604 }
605 case ERFSLEEP:
606 if (ppsc->rfpwr_state == ERFOFF)
607 return false;
608
609 for (queue_id = 0, i = 0;
610 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
611 ring = &pcipriv->dev.tx_ring[queue_id];
612 if (skb_queue_len(&ring->queue) == 0 ||
613 queue_id == BEACON_QUEUE) {
614 queue_id++;
615 continue;
616 } else {
617 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
618 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
619 i + 1, queue_id,
620 skb_queue_len(&ring->queue));
621
622 udelay(10);
623 i++;
624 }
625
626 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
627 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
628 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
629 MAX_DOZE_WAITING_TIMES_9x,
630 queue_id,
631 skb_queue_len(&ring->queue));
632 break;
633 }
634 }
635
636 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
637 "Set ERFSLEEP awaked:%d ms\n",
638 jiffies_to_msecs(jiffies -
639 ppsc->last_awake_jiffies));
640
641 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
642 "sleep awaked:%d ms state_inap:%x\n",
643 jiffies_to_msecs(jiffies -
644 ppsc->last_awake_jiffies),
645 rtlpriv->psc.state_inap);
646 ppsc->last_sleep_jiffies = jiffies;
647 _rtl92se_phy_set_rf_sleep(hw);
648 break;
649 default:
650 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
651 "switch case not processed\n");
652 bresult = false;
653 break;
654 }
655
656 if (bresult)
657 ppsc->rfpwr_state = rfpwr_state;
658
659 return bresult;
660 }
661
662 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
663 enum radio_path rfpath)
664 {
665 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
666 bool rtstatus = true;
667 u32 tmpval = 0;
668
669 /* If inferiority IC, we have to increase the PA bias current */
670 if (rtlhal->ic_class != IC_INFERIORITY_A) {
671 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
672 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
673 }
674
675 return rtstatus;
676 }
677
678 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
679 u32 reg_addr, u32 bitmask, u32 data)
680 {
681 struct rtl_priv *rtlpriv = rtl_priv(hw);
682 struct rtl_phy *rtlphy = &(rtlpriv->phy);
683
684 if (reg_addr == RTXAGC_RATE18_06)
685 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
686 data;
687 if (reg_addr == RTXAGC_RATE54_24)
688 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
689 data;
690 if (reg_addr == RTXAGC_CCK_MCS32)
691 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
692 data;
693 if (reg_addr == RTXAGC_MCS03_MCS00)
694 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
695 data;
696 if (reg_addr == RTXAGC_MCS07_MCS04)
697 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
698 data;
699 if (reg_addr == RTXAGC_MCS11_MCS08)
700 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
701 data;
702 if (reg_addr == RTXAGC_MCS15_MCS12) {
703 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
704 data;
705 rtlphy->pwrgroup_cnt++;
706 }
707 }
708
709 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
710 {
711 struct rtl_priv *rtlpriv = rtl_priv(hw);
712 struct rtl_phy *rtlphy = &(rtlpriv->phy);
713
714 /*RF Interface Sowrtware Control */
715 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
716 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
717 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
718 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
719
720 /* RF Interface Readback Value */
721 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
722 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
723 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
724 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
725
726 /* RF Interface Output (and Enable) */
727 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
728 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
729 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
730 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
731
732 /* RF Interface (Output and) Enable */
733 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
734 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
735 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
736 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
737
738 /* Addr of LSSI. Wirte RF register by driver */
739 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
740 RFPGA0_XA_LSSIPARAMETER;
741 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
742 RFPGA0_XB_LSSIPARAMETER;
743 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
744 RFPGA0_XC_LSSIPARAMETER;
745 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
746 RFPGA0_XD_LSSIPARAMETER;
747
748 /* RF parameter */
749 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
750 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
751 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
752 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
753
754 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
755 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
756 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
757 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
758 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
759
760 /* Tranceiver A~D HSSI Parameter-1 */
761 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
762 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
763 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
764 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
765
766 /* Tranceiver A~D HSSI Parameter-2 */
767 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
768 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
769 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
770 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
771
772 /* RF switch Control */
773 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
774 RFPGA0_XAB_SWITCHCONTROL;
775 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
776 RFPGA0_XAB_SWITCHCONTROL;
777 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
778 RFPGA0_XCD_SWITCHCONTROL;
779 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
780 RFPGA0_XCD_SWITCHCONTROL;
781
782 /* AGC control 1 */
783 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
784 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
785 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
786 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
787
788 /* AGC control 2 */
789 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
790 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
791 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
792 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
793
794 /* RX AFE control 1 */
795 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
796 ROFDM0_XARXIQIMBALANCE;
797 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
798 ROFDM0_XBRXIQIMBALANCE;
799 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
800 ROFDM0_XCRXIQIMBALANCE;
801 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
802 ROFDM0_XDRXIQIMBALANCE;
803
804 /* RX AFE control 1 */
805 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
806 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
807 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
808 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
809
810 /* Tx AFE control 1 */
811 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
812 ROFDM0_XATXIQIMBALANCE;
813 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
814 ROFDM0_XBTXIQIMBALANCE;
815 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
816 ROFDM0_XCTXIQIMBALANCE;
817 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
818 ROFDM0_XDTXIQIMBALANCE;
819
820 /* Tx AFE control 2 */
821 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
822 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
823 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
824 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
825
826 /* Tranceiver LSSI Readback */
827 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
828 RFPGA0_XA_LSSIREADBACK;
829 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
830 RFPGA0_XB_LSSIREADBACK;
831 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
832 RFPGA0_XC_LSSIREADBACK;
833 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
834 RFPGA0_XD_LSSIREADBACK;
835
836 /* Tranceiver LSSI Readback PI mode */
837 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
838 TRANSCEIVERA_HSPI_READBACK;
839 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
840 TRANSCEIVERB_HSPI_READBACK;
841 }
842
843
844 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
845 {
846 int i;
847 u32 *phy_reg_table;
848 u32 *agc_table;
849 u16 phy_reg_len, agc_len;
850
851 agc_len = AGCTAB_ARRAYLENGTH;
852 agc_table = rtl8192seagctab_array;
853 /* Default RF_type: 2T2R */
854 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
855 phy_reg_table = rtl8192sephy_reg_2t2rarray;
856
857 if (configtype == BASEBAND_CONFIG_PHY_REG) {
858 for (i = 0; i < phy_reg_len; i = i + 2) {
859 if (phy_reg_table[i] == 0xfe)
860 mdelay(50);
861 else if (phy_reg_table[i] == 0xfd)
862 mdelay(5);
863 else if (phy_reg_table[i] == 0xfc)
864 mdelay(1);
865 else if (phy_reg_table[i] == 0xfb)
866 udelay(50);
867 else if (phy_reg_table[i] == 0xfa)
868 udelay(5);
869 else if (phy_reg_table[i] == 0xf9)
870 udelay(1);
871
872 /* Add delay for ECS T20 & LG malow platform, */
873 udelay(1);
874
875 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
876 phy_reg_table[i + 1]);
877 }
878 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
879 for (i = 0; i < agc_len; i = i + 2) {
880 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
881 agc_table[i + 1]);
882
883 /* Add delay for ECS T20 & LG malow platform */
884 udelay(1);
885 }
886 }
887
888 return true;
889 }
890
891 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
892 u8 configtype)
893 {
894 struct rtl_priv *rtlpriv = rtl_priv(hw);
895 struct rtl_phy *rtlphy = &(rtlpriv->phy);
896 u32 *phy_regarray2xtxr_table;
897 u16 phy_regarray2xtxr_len;
898 int i;
899
900 if (rtlphy->rf_type == RF_1T1R) {
901 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
902 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
903 } else if (rtlphy->rf_type == RF_1T2R) {
904 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
905 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
906 } else {
907 return false;
908 }
909
910 if (configtype == BASEBAND_CONFIG_PHY_REG) {
911 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
912 if (phy_regarray2xtxr_table[i] == 0xfe)
913 mdelay(50);
914 else if (phy_regarray2xtxr_table[i] == 0xfd)
915 mdelay(5);
916 else if (phy_regarray2xtxr_table[i] == 0xfc)
917 mdelay(1);
918 else if (phy_regarray2xtxr_table[i] == 0xfb)
919 udelay(50);
920 else if (phy_regarray2xtxr_table[i] == 0xfa)
921 udelay(5);
922 else if (phy_regarray2xtxr_table[i] == 0xf9)
923 udelay(1);
924
925 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
926 phy_regarray2xtxr_table[i + 1],
927 phy_regarray2xtxr_table[i + 2]);
928 }
929 }
930
931 return true;
932 }
933
934 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
935 u8 configtype)
936 {
937 int i;
938 u32 *phy_table_pg;
939 u16 phy_pg_len;
940
941 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
942 phy_table_pg = rtl8192sephy_reg_array_pg;
943
944 if (configtype == BASEBAND_CONFIG_PHY_REG) {
945 for (i = 0; i < phy_pg_len; i = i + 3) {
946 if (phy_table_pg[i] == 0xfe)
947 mdelay(50);
948 else if (phy_table_pg[i] == 0xfd)
949 mdelay(5);
950 else if (phy_table_pg[i] == 0xfc)
951 mdelay(1);
952 else if (phy_table_pg[i] == 0xfb)
953 udelay(50);
954 else if (phy_table_pg[i] == 0xfa)
955 udelay(5);
956 else if (phy_table_pg[i] == 0xf9)
957 udelay(1);
958
959 _rtl92s_store_pwrindex_diffrate_offset(hw,
960 phy_table_pg[i],
961 phy_table_pg[i + 1],
962 phy_table_pg[i + 2]);
963 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
964 phy_table_pg[i + 1],
965 phy_table_pg[i + 2]);
966 }
967 }
968
969 return true;
970 }
971
972 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
973 {
974 struct rtl_priv *rtlpriv = rtl_priv(hw);
975 struct rtl_phy *rtlphy = &(rtlpriv->phy);
976 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
977 bool rtstatus = true;
978
979 /* 1. Read PHY_REG.TXT BB INIT!! */
980 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
981 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
982 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
983 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
984
985 if (rtlphy->rf_type != RF_2T2R &&
986 rtlphy->rf_type != RF_2T2R_GREEN)
987 /* so we should reconfig BB reg with the right
988 * PHY parameters. */
989 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
990 BASEBAND_CONFIG_PHY_REG);
991 } else {
992 rtstatus = false;
993 }
994
995 if (rtstatus != true) {
996 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
997 "Write BB Reg Fail!!\n");
998 goto phy_BB8190_Config_ParaFile_Fail;
999 }
1000
1001 /* 2. If EEPROM or EFUSE autoload OK, We must config by
1002 * PHY_REG_PG.txt */
1003 if (rtlefuse->autoload_failflag == false) {
1004 rtlphy->pwrgroup_cnt = 0;
1005
1006 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
1007 BASEBAND_CONFIG_PHY_REG);
1008 }
1009 if (rtstatus != true) {
1010 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1011 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
1012 goto phy_BB8190_Config_ParaFile_Fail;
1013 }
1014
1015 /* 3. BB AGC table Initialization */
1016 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1017
1018 if (rtstatus != true) {
1019 pr_err("%s(): AGC Table Fail\n", __func__);
1020 goto phy_BB8190_Config_ParaFile_Fail;
1021 }
1022
1023 /* Check if the CCK HighPower is turned ON. */
1024 /* This is used to calculate PWDB. */
1025 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
1026 RFPGA0_XA_HSSIPARAMETER2, 0x200));
1027
1028 phy_BB8190_Config_ParaFile_Fail:
1029 return rtstatus;
1030 }
1031
1032 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1033 {
1034 struct rtl_priv *rtlpriv = rtl_priv(hw);
1035 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1036 int i;
1037 bool rtstatus = true;
1038 u32 *radio_a_table;
1039 u32 *radio_b_table;
1040 u16 radio_a_tblen, radio_b_tblen;
1041
1042 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
1043 radio_a_table = rtl8192seradioa_1t_array;
1044
1045 /* Using Green mode array table for RF_2T2R_GREEN */
1046 if (rtlphy->rf_type == RF_2T2R_GREEN) {
1047 radio_b_table = rtl8192seradiob_gm_array;
1048 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
1049 } else {
1050 radio_b_table = rtl8192seradiob_array;
1051 radio_b_tblen = RADIOB_ARRAYLENGTH;
1052 }
1053
1054 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1055 rtstatus = true;
1056
1057 switch (rfpath) {
1058 case RF90_PATH_A:
1059 for (i = 0; i < radio_a_tblen; i = i + 2) {
1060 if (radio_a_table[i] == 0xfe)
1061 /* Delay specific ms. Only RF configuration
1062 * requires delay. */
1063 mdelay(50);
1064 else if (radio_a_table[i] == 0xfd)
1065 mdelay(5);
1066 else if (radio_a_table[i] == 0xfc)
1067 mdelay(1);
1068 else if (radio_a_table[i] == 0xfb)
1069 udelay(50);
1070 else if (radio_a_table[i] == 0xfa)
1071 udelay(5);
1072 else if (radio_a_table[i] == 0xf9)
1073 udelay(1);
1074 else
1075 rtl92s_phy_set_rf_reg(hw, rfpath,
1076 radio_a_table[i],
1077 MASK20BITS,
1078 radio_a_table[i + 1]);
1079
1080 /* Add delay for ECS T20 & LG malow platform */
1081 udelay(1);
1082 }
1083
1084 /* PA Bias current for inferiority IC */
1085 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1086 break;
1087 case RF90_PATH_B:
1088 for (i = 0; i < radio_b_tblen; i = i + 2) {
1089 if (radio_b_table[i] == 0xfe)
1090 /* Delay specific ms. Only RF configuration
1091 * requires delay.*/
1092 mdelay(50);
1093 else if (radio_b_table[i] == 0xfd)
1094 mdelay(5);
1095 else if (radio_b_table[i] == 0xfc)
1096 mdelay(1);
1097 else if (radio_b_table[i] == 0xfb)
1098 udelay(50);
1099 else if (radio_b_table[i] == 0xfa)
1100 udelay(5);
1101 else if (radio_b_table[i] == 0xf9)
1102 udelay(1);
1103 else
1104 rtl92s_phy_set_rf_reg(hw, rfpath,
1105 radio_b_table[i],
1106 MASK20BITS,
1107 radio_b_table[i + 1]);
1108
1109 /* Add delay for ECS T20 & LG malow platform */
1110 udelay(1);
1111 }
1112 break;
1113 case RF90_PATH_C:
1114 ;
1115 break;
1116 case RF90_PATH_D:
1117 ;
1118 break;
1119 default:
1120 break;
1121 }
1122
1123 return rtstatus;
1124 }
1125
1126
1127 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1128 {
1129 struct rtl_priv *rtlpriv = rtl_priv(hw);
1130 u32 i;
1131 u32 arraylength;
1132 u32 *ptraArray;
1133
1134 arraylength = MAC_2T_ARRAYLENGTH;
1135 ptraArray = rtl8192semac_2t_array;
1136
1137 for (i = 0; i < arraylength; i = i + 2)
1138 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1139
1140 return true;
1141 }
1142
1143
1144 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1145 {
1146 struct rtl_priv *rtlpriv = rtl_priv(hw);
1147 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1148 bool rtstatus = true;
1149 u8 pathmap, index, rf_num = 0;
1150 u8 path1, path2;
1151
1152 _rtl92s_phy_init_register_definition(hw);
1153
1154 /* Config BB and AGC */
1155 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1156
1157
1158 /* Check BB/RF confiuration setting. */
1159 /* We only need to configure RF which is turned on. */
1160 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1161 mdelay(10);
1162 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1163 pathmap = path1 | path2;
1164
1165 rtlphy->rf_pathmap = pathmap;
1166 for (index = 0; index < 4; index++) {
1167 if ((pathmap >> index) & 0x1)
1168 rf_num++;
1169 }
1170
1171 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1172 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1173 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1174 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1176 "RF_Type(%x) does not match RF_Num(%x)!!\n",
1177 rtlphy->rf_type, rf_num);
1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1179 "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1180 path1, path2, pathmap);
1181 }
1182
1183 return rtstatus;
1184 }
1185
1186 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1187 {
1188 struct rtl_priv *rtlpriv = rtl_priv(hw);
1189 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1190
1191 /* Initialize general global value */
1192 if (rtlphy->rf_type == RF_1T1R)
1193 rtlphy->num_total_rfpath = 1;
1194 else
1195 rtlphy->num_total_rfpath = 2;
1196
1197 /* Config BB and RF */
1198 return rtl92s_phy_rf6052_config(hw);
1199 }
1200
1201 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1202 {
1203 struct rtl_priv *rtlpriv = rtl_priv(hw);
1204 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1205
1206 /* read rx initial gain */
1207 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1208 ROFDM0_XAAGCCORE1, MASKBYTE0);
1209 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1210 ROFDM0_XBAGCCORE1, MASKBYTE0);
1211 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1212 ROFDM0_XCAGCCORE1, MASKBYTE0);
1213 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1214 ROFDM0_XDAGCCORE1, MASKBYTE0);
1215 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1216 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1217 rtlphy->default_initialgain[0],
1218 rtlphy->default_initialgain[1],
1219 rtlphy->default_initialgain[2],
1220 rtlphy->default_initialgain[3]);
1221
1222 /* read framesync */
1223 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1224 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1225 MASKDWORD);
1226 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1227 "Default framesync (0x%x) = 0x%x\n",
1228 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1229
1230 }
1231
1232 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1233 u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1234 {
1235 struct rtl_priv *rtlpriv = rtl_priv(hw);
1236 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1237 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1238 u8 index = (channel - 1);
1239
1240 /* 1. CCK */
1241 /* RF-A */
1242 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1243 /* RF-B */
1244 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1245
1246 /* 2. OFDM for 1T or 2T */
1247 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1248 /* Read HT 40 OFDM TX power */
1249 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1250 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1251 } else if (rtlphy->rf_type == RF_2T2R) {
1252 /* Read HT 40 OFDM TX power */
1253 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1254 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1255 }
1256 }
1257
1258 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1259 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1260 {
1261 struct rtl_priv *rtlpriv = rtl_priv(hw);
1262 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1263
1264 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1265 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1266 }
1267
1268 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1269 {
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1272 /* [0]:RF-A, [1]:RF-B */
1273 u8 cckpowerlevel[2], ofdmpowerLevel[2];
1274
1275 if (rtlefuse->txpwr_fromeprom == false)
1276 return;
1277
1278 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1279 * but the RF-B Tx Power must be calculated by the antenna diff.
1280 * So we have to rewrite Antenna gain offset register here.
1281 * Please refer to BB register 0x80c
1282 * 1. For CCK.
1283 * 2. For OFDM 1T or 2T */
1284 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1285 &ofdmpowerLevel[0]);
1286
1287 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1288 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1289 channel, cckpowerlevel[0], cckpowerlevel[1],
1290 ofdmpowerLevel[0], ofdmpowerLevel[1]);
1291
1292 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1293 &ofdmpowerLevel[0]);
1294
1295 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1296 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1297
1298 }
1299
1300 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1301 {
1302 struct rtl_priv *rtlpriv = rtl_priv(hw);
1303 u16 pollingcnt = 10000;
1304 u32 tmpvalue;
1305
1306 /* Make sure that CMD IO has be accepted by FW. */
1307 do {
1308 udelay(10);
1309
1310 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1311 if (tmpvalue == 0)
1312 break;
1313 } while (--pollingcnt);
1314
1315 if (pollingcnt == 0)
1316 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1317 }
1318
1319
1320 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1321 {
1322 struct rtl_priv *rtlpriv = rtl_priv(hw);
1323 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1324 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1325 u32 input, current_aid = 0;
1326
1327 if (is_hal_stop(rtlhal))
1328 return;
1329
1330 /* We re-map RA related CMD IO to combinational ones */
1331 /* if FW version is v.52 or later. */
1332 switch (rtlhal->current_fwcmd_io) {
1333 case FW_CMD_RA_REFRESH_N:
1334 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1335 break;
1336 case FW_CMD_RA_REFRESH_BG:
1337 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1338 break;
1339 default:
1340 break;
1341 }
1342
1343 switch (rtlhal->current_fwcmd_io) {
1344 case FW_CMD_RA_RESET:
1345 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1346 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1347 rtl92s_phy_chk_fwcmd_iodone(hw);
1348 break;
1349 case FW_CMD_RA_ACTIVE:
1350 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1351 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1352 rtl92s_phy_chk_fwcmd_iodone(hw);
1353 break;
1354 case FW_CMD_RA_REFRESH_N:
1355 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1356 input = FW_RA_REFRESH;
1357 rtl_write_dword(rtlpriv, WFM5, input);
1358 rtl92s_phy_chk_fwcmd_iodone(hw);
1359 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1360 rtl92s_phy_chk_fwcmd_iodone(hw);
1361 break;
1362 case FW_CMD_RA_REFRESH_BG:
1363 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1364 "FW_CMD_RA_REFRESH_BG\n");
1365 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1366 rtl92s_phy_chk_fwcmd_iodone(hw);
1367 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1368 rtl92s_phy_chk_fwcmd_iodone(hw);
1369 break;
1370 case FW_CMD_RA_REFRESH_N_COMB:
1371 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1372 "FW_CMD_RA_REFRESH_N_COMB\n");
1373 input = FW_RA_IOT_N_COMB;
1374 rtl_write_dword(rtlpriv, WFM5, input);
1375 rtl92s_phy_chk_fwcmd_iodone(hw);
1376 break;
1377 case FW_CMD_RA_REFRESH_BG_COMB:
1378 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1379 "FW_CMD_RA_REFRESH_BG_COMB\n");
1380 input = FW_RA_IOT_BG_COMB;
1381 rtl_write_dword(rtlpriv, WFM5, input);
1382 rtl92s_phy_chk_fwcmd_iodone(hw);
1383 break;
1384 case FW_CMD_IQK_ENABLE:
1385 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1386 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1387 rtl92s_phy_chk_fwcmd_iodone(hw);
1388 break;
1389 case FW_CMD_PAUSE_DM_BY_SCAN:
1390 /* Lower initial gain */
1391 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1392 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1393 /* CCA threshold */
1394 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1395 break;
1396 case FW_CMD_RESUME_DM_BY_SCAN:
1397 /* CCA threshold */
1398 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1399 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1400 break;
1401 case FW_CMD_HIGH_PWR_DISABLE:
1402 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1403 break;
1404
1405 /* Lower initial gain */
1406 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1407 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1408 /* CCA threshold */
1409 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1410 break;
1411 case FW_CMD_HIGH_PWR_ENABLE:
1412 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1413 rtlpriv->dm.dynamic_txpower_enable)
1414 break;
1415
1416 /* CCA threshold */
1417 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1418 break;
1419 case FW_CMD_LPS_ENTER:
1420 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1421 current_aid = rtlpriv->mac80211.assoc_id;
1422 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1423 ((current_aid | 0xc000) << 8)));
1424 rtl92s_phy_chk_fwcmd_iodone(hw);
1425 /* FW set TXOP disable here, so disable EDCA
1426 * turbo mode until driver leave LPS */
1427 break;
1428 case FW_CMD_LPS_LEAVE:
1429 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1430 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1431 rtl92s_phy_chk_fwcmd_iodone(hw);
1432 break;
1433 case FW_CMD_ADD_A2_ENTRY:
1434 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1435 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1436 rtl92s_phy_chk_fwcmd_iodone(hw);
1437 break;
1438 case FW_CMD_CTRL_DM_BY_DRIVER:
1439 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1440 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1441 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1442 rtl92s_phy_chk_fwcmd_iodone(hw);
1443 break;
1444
1445 default:
1446 break;
1447 }
1448
1449 rtl92s_phy_chk_fwcmd_iodone(hw);
1450
1451 /* Clear FW CMD operation flag. */
1452 rtlhal->set_fwcmd_inprogress = false;
1453 }
1454
1455 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1456 {
1457 struct rtl_priv *rtlpriv = rtl_priv(hw);
1458 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1459 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1460 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1461 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1462 bool bPostProcessing = false;
1463
1464 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1465 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1466 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1467
1468 do {
1469 /* We re-map to combined FW CMD ones if firmware version */
1470 /* is v.53 or later. */
1471 switch (fw_cmdio) {
1472 case FW_CMD_RA_REFRESH_N:
1473 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1474 break;
1475 case FW_CMD_RA_REFRESH_BG:
1476 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1477 break;
1478 default:
1479 break;
1480 }
1481
1482 /* If firmware version is v.62 or later,
1483 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1484 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1485 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1486 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1487 }
1488
1489
1490 /* We shall revise all FW Cmd IO into Reg0x364
1491 * DM map table in the future. */
1492 switch (fw_cmdio) {
1493 case FW_CMD_RA_INIT:
1494 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1495 fw_cmdmap |= FW_RA_INIT_CTL;
1496 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1497 /* Clear control flag to sync with FW. */
1498 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1499 break;
1500 case FW_CMD_DIG_DISABLE:
1501 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1502 "Set DIG disable!!\n");
1503 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1504 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1505 break;
1506 case FW_CMD_DIG_ENABLE:
1507 case FW_CMD_DIG_RESUME:
1508 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1509 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1510 "Set DIG enable or resume!!\n");
1511 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1512 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1513 }
1514 break;
1515 case FW_CMD_DIG_HALT:
1516 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1517 "Set DIG halt!!\n");
1518 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1519 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1520 break;
1521 case FW_CMD_TXPWR_TRACK_THERMAL: {
1522 u8 thermalval = 0;
1523 fw_cmdmap |= FW_PWR_TRK_CTL;
1524
1525 /* Clear FW parameter in terms of thermal parts. */
1526 fw_param &= FW_PWR_TRK_PARAM_CLR;
1527
1528 thermalval = rtlpriv->dm.thermalvalue;
1529 fw_param |= ((thermalval << 24) |
1530 (rtlefuse->thermalmeter[0] << 16));
1531
1532 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1533 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1534 fw_cmdmap, fw_param);
1535
1536 FW_CMD_PARA_SET(rtlpriv, fw_param);
1537 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1538
1539 /* Clear control flag to sync with FW. */
1540 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1541 }
1542 break;
1543 /* The following FW CMDs are only compatible to
1544 * v.53 or later. */
1545 case FW_CMD_RA_REFRESH_N_COMB:
1546 fw_cmdmap |= FW_RA_N_CTL;
1547
1548 /* Clear RA BG mode control. */
1549 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1550
1551 /* Clear FW parameter in terms of RA parts. */
1552 fw_param &= FW_RA_PARAM_CLR;
1553
1554 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1555 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1556 fw_cmdmap, fw_param);
1557
1558 FW_CMD_PARA_SET(rtlpriv, fw_param);
1559 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1560
1561 /* Clear control flag to sync with FW. */
1562 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1563 break;
1564 case FW_CMD_RA_REFRESH_BG_COMB:
1565 fw_cmdmap |= FW_RA_BG_CTL;
1566
1567 /* Clear RA n-mode control. */
1568 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1569 /* Clear FW parameter in terms of RA parts. */
1570 fw_param &= FW_RA_PARAM_CLR;
1571
1572 FW_CMD_PARA_SET(rtlpriv, fw_param);
1573 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1574
1575 /* Clear control flag to sync with FW. */
1576 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1577 break;
1578 case FW_CMD_IQK_ENABLE:
1579 fw_cmdmap |= FW_IQK_CTL;
1580 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1581 /* Clear control flag to sync with FW. */
1582 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1583 break;
1584 /* The following FW CMD is compatible to v.62 or later. */
1585 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1586 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1587 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1588 break;
1589 /* The followed FW Cmds needs post-processing later. */
1590 case FW_CMD_RESUME_DM_BY_SCAN:
1591 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1592 FW_HIGH_PWR_ENABLE_CTL |
1593 FW_SS_CTL);
1594
1595 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1596 !digtable.dig_enable_flag)
1597 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1598
1599 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1600 rtlpriv->dm.dynamic_txpower_enable)
1601 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1602
1603 if ((digtable.dig_ext_port_stage ==
1604 DIG_EXT_PORT_STAGE_0) ||
1605 (digtable.dig_ext_port_stage ==
1606 DIG_EXT_PORT_STAGE_1))
1607 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1608
1609 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1610 bPostProcessing = true;
1611 break;
1612 case FW_CMD_PAUSE_DM_BY_SCAN:
1613 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1614 FW_HIGH_PWR_ENABLE_CTL |
1615 FW_SS_CTL);
1616 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1617 bPostProcessing = true;
1618 break;
1619 case FW_CMD_HIGH_PWR_DISABLE:
1620 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1621 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1622 bPostProcessing = true;
1623 break;
1624 case FW_CMD_HIGH_PWR_ENABLE:
1625 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1626 (rtlpriv->dm.dynamic_txpower_enable != true)) {
1627 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1628 FW_SS_CTL);
1629 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1630 bPostProcessing = true;
1631 }
1632 break;
1633 case FW_CMD_DIG_MODE_FA:
1634 fw_cmdmap |= FW_FA_CTL;
1635 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1636 break;
1637 case FW_CMD_DIG_MODE_SS:
1638 fw_cmdmap &= ~FW_FA_CTL;
1639 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1640 break;
1641 case FW_CMD_PAPE_CONTROL:
1642 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1643 "[FW CMD] Set PAPE Control\n");
1644 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1645
1646 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1647 break;
1648 default:
1649 /* Pass to original FW CMD processing callback
1650 * routine. */
1651 bPostProcessing = true;
1652 break;
1653 }
1654 } while (false);
1655
1656 /* We shall post processing these FW CMD if
1657 * variable bPostProcessing is set. */
1658 if (bPostProcessing && !rtlhal->set_fwcmd_inprogress) {
1659 rtlhal->set_fwcmd_inprogress = true;
1660 /* Update current FW Cmd for callback use. */
1661 rtlhal->current_fwcmd_io = fw_cmdio;
1662 } else {
1663 return false;
1664 }
1665
1666 _rtl92s_phy_set_fwcmd_io(hw);
1667 return true;
1668 }
1669
1670 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1671 {
1672 struct rtl_priv *rtlpriv = rtl_priv(hw);
1673 u32 delay = 100;
1674 u8 regu1;
1675
1676 regu1 = rtl_read_byte(rtlpriv, 0x554);
1677 while ((regu1 & BIT(5)) && (delay > 0)) {
1678 regu1 = rtl_read_byte(rtlpriv, 0x554);
1679 delay--;
1680 /* We delay only 50us to prevent
1681 * being scheduled out. */
1682 udelay(50);
1683 }
1684 }
1685
1686 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1687 {
1688 struct rtl_priv *rtlpriv = rtl_priv(hw);
1689 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1690
1691 /* The way to be capable to switch clock request
1692 * when the PG setting does not support clock request.
1693 * This is the backdoor solution to switch clock
1694 * request before ASPM or D3. */
1695 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1696 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1697
1698 /* Switch EPHY parameter!!!! */
1699 rtl_write_word(rtlpriv, 0x550, 0x1000);
1700 rtl_write_byte(rtlpriv, 0x554, 0x20);
1701 _rtl92s_phy_check_ephy_switchready(hw);
1702
1703 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1704 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1705 _rtl92s_phy_check_ephy_switchready(hw);
1706
1707 rtl_write_word(rtlpriv, 0x550, 0xff80);
1708 rtl_write_byte(rtlpriv, 0x554, 0x39);
1709 _rtl92s_phy_check_ephy_switchready(hw);
1710
1711 /* Delay L1 enter time */
1712 if (ppsc->support_aspm && !ppsc->support_backdoor)
1713 rtl_write_byte(rtlpriv, 0x560, 0x40);
1714 else
1715 rtl_write_byte(rtlpriv, 0x560, 0x00);
1716
1717 }
1718
1719 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 BeaconInterval)
1720 {
1721 struct rtl_priv *rtlpriv = rtl_priv(hw);
1722 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | (BeaconInterval << 8));
1723 }
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