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x86: Stop including <linux/delay.h> in two asm header files
[linux-2.6.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
blobd2cf39bc5ecfcba30d95f0da9a998546aa92098a
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27
28 #include <asm/uv/uv_mmrs.h>
29 #include <asm/uv/uv_hub.h>
30 #include <asm/current.h>
31 #include <asm/pgtable.h>
32 #include <asm/uv/bios.h>
33 #include <asm/uv/uv.h>
34 #include <asm/apic.h>
35 #include <asm/ipi.h>
36 #include <asm/smp.h>
37 #include <asm/x86_init.h>
38
39 DEFINE_PER_CPU(int, x2apic_extra_bits);
40
41 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
42
43 static enum uv_system_type uv_system_type;
44 static u64 gru_start_paddr, gru_end_paddr;
45 static union uvh_apicid uvh_apicid;
46 int uv_min_hub_revision_id;
47 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
48 unsigned int uv_apicid_hibits;
49 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
50 static DEFINE_SPINLOCK(uv_nmi_lock);
51
52 static unsigned long __init uv_early_read_mmr(unsigned long addr)
53 {
54 unsigned long val, *mmr;
55
56 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
57 val = *mmr;
58 early_iounmap(mmr, sizeof(*mmr));
59 return val;
60 }
61
62 static inline bool is_GRU_range(u64 start, u64 end)
63 {
64 return start >= gru_start_paddr && end <= gru_end_paddr;
65 }
66
67 static bool uv_is_untracked_pat_range(u64 start, u64 end)
68 {
69 return is_ISA_range(start, end) || is_GRU_range(start, end);
70 }
71
72 static int __init early_get_pnodeid(void)
73 {
74 union uvh_node_id_u node_id;
75 union uvh_rh_gam_config_mmr_u m_n_config;
76 int pnode;
77
78 /* Currently, all blades have same revision number */
79 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
80 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
81 uv_min_hub_revision_id = node_id.s.revision;
82
83 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
84 return pnode;
85 }
86
87 static void __init early_get_apic_pnode_shift(void)
88 {
89 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
90 if (!uvh_apicid.v)
91 /*
92 * Old bios, use default value
93 */
94 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
95 }
96
97 /*
98 * Add an extra bit as dictated by bios to the destination apicid of
99 * interrupts potentially passing through the UV HUB. This prevents
100 * a deadlock between interrupts and IO port operations.
101 */
102 static void __init uv_set_apicid_hibit(void)
103 {
104 union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
105
106 apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
107 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
108 }
109
110 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
111 {
112 int pnodeid;
113
114 if (!strcmp(oem_id, "SGI")) {
115 pnodeid = early_get_pnodeid();
116 early_get_apic_pnode_shift();
117 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
118 x86_platform.nmi_init = uv_nmi_init;
119 if (!strcmp(oem_table_id, "UVL"))
120 uv_system_type = UV_LEGACY_APIC;
121 else if (!strcmp(oem_table_id, "UVX"))
122 uv_system_type = UV_X2APIC;
123 else if (!strcmp(oem_table_id, "UVH")) {
124 __this_cpu_write(x2apic_extra_bits,
125 pnodeid << uvh_apicid.s.pnode_shift);
126 uv_system_type = UV_NON_UNIQUE_APIC;
127 uv_set_apicid_hibit();
128 return 1;
129 }
130 }
131 return 0;
132 }
133
134 enum uv_system_type get_uv_system_type(void)
135 {
136 return uv_system_type;
137 }
138
139 int is_uv_system(void)
140 {
141 return uv_system_type != UV_NONE;
142 }
143 EXPORT_SYMBOL_GPL(is_uv_system);
144
145 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
146 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
147
148 struct uv_blade_info *uv_blade_info;
149 EXPORT_SYMBOL_GPL(uv_blade_info);
150
151 short *uv_node_to_blade;
152 EXPORT_SYMBOL_GPL(uv_node_to_blade);
153
154 short *uv_cpu_to_blade;
155 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
156
157 short uv_possible_blades;
158 EXPORT_SYMBOL_GPL(uv_possible_blades);
159
160 unsigned long sn_rtc_cycles_per_second;
161 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
162
163 static const struct cpumask *uv_target_cpus(void)
164 {
165 return cpu_online_mask;
166 }
167
168 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
169 {
170 cpumask_clear(retmask);
171 cpumask_set_cpu(cpu, retmask);
172 }
173
174 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
175 {
176 #ifdef CONFIG_SMP
177 unsigned long val;
178 int pnode;
179
180 pnode = uv_apicid_to_pnode(phys_apicid);
181 phys_apicid |= uv_apicid_hibits;
182 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
183 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
184 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
185 APIC_DM_INIT;
186 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
187 mdelay(10);
188
189 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
190 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
191 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
192 APIC_DM_STARTUP;
193 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
194
195 atomic_set(&init_deasserted, 1);
196 #endif
197 return 0;
198 }
199
200 static void uv_send_IPI_one(int cpu, int vector)
201 {
202 unsigned long apicid;
203 int pnode;
204
205 apicid = per_cpu(x86_cpu_to_apicid, cpu);
206 pnode = uv_apicid_to_pnode(apicid);
207 uv_hub_send_ipi(pnode, apicid, vector);
208 }
209
210 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
211 {
212 unsigned int cpu;
213
214 for_each_cpu(cpu, mask)
215 uv_send_IPI_one(cpu, vector);
216 }
217
218 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
219 {
220 unsigned int this_cpu = smp_processor_id();
221 unsigned int cpu;
222
223 for_each_cpu(cpu, mask) {
224 if (cpu != this_cpu)
225 uv_send_IPI_one(cpu, vector);
226 }
227 }
228
229 static void uv_send_IPI_allbutself(int vector)
230 {
231 unsigned int this_cpu = smp_processor_id();
232 unsigned int cpu;
233
234 for_each_online_cpu(cpu) {
235 if (cpu != this_cpu)
236 uv_send_IPI_one(cpu, vector);
237 }
238 }
239
240 static void uv_send_IPI_all(int vector)
241 {
242 uv_send_IPI_mask(cpu_online_mask, vector);
243 }
244
245 static int uv_apic_id_registered(void)
246 {
247 return 1;
248 }
249
250 static void uv_init_apic_ldr(void)
251 {
252 }
253
254 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
255 {
256 /*
257 * We're using fixed IRQ delivery, can only return one phys APIC ID.
258 * May as well be the first.
259 */
260 int cpu = cpumask_first(cpumask);
261
262 if ((unsigned)cpu < nr_cpu_ids)
263 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
264 else
265 return BAD_APICID;
266 }
267
268 static unsigned int
269 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
270 const struct cpumask *andmask)
271 {
272 int cpu;
273
274 /*
275 * We're using fixed IRQ delivery, can only return one phys APIC ID.
276 * May as well be the first.
277 */
278 for_each_cpu_and(cpu, cpumask, andmask) {
279 if (cpumask_test_cpu(cpu, cpu_online_mask))
280 break;
281 }
282 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
283 }
284
285 static unsigned int x2apic_get_apic_id(unsigned long x)
286 {
287 unsigned int id;
288
289 WARN_ON(preemptible() && num_online_cpus() > 1);
290 id = x | __this_cpu_read(x2apic_extra_bits);
291
292 return id;
293 }
294
295 static unsigned long set_apic_id(unsigned int id)
296 {
297 unsigned long x;
298
299 /* maskout x2apic_extra_bits ? */
300 x = id;
301 return x;
302 }
303
304 static unsigned int uv_read_apic_id(void)
305 {
306
307 return x2apic_get_apic_id(apic_read(APIC_ID));
308 }
309
310 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
311 {
312 return uv_read_apic_id() >> index_msb;
313 }
314
315 static void uv_send_IPI_self(int vector)
316 {
317 apic_write(APIC_SELF_IPI, vector);
318 }
319
320 struct apic __refdata apic_x2apic_uv_x = {
321
322 .name = "UV large system",
323 .probe = NULL,
324 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
325 .apic_id_registered = uv_apic_id_registered,
326
327 .irq_delivery_mode = dest_Fixed,
328 .irq_dest_mode = 0, /* physical */
329
330 .target_cpus = uv_target_cpus,
331 .disable_esr = 0,
332 .dest_logical = APIC_DEST_LOGICAL,
333 .check_apicid_used = NULL,
334 .check_apicid_present = NULL,
335
336 .vector_allocation_domain = uv_vector_allocation_domain,
337 .init_apic_ldr = uv_init_apic_ldr,
338
339 .ioapic_phys_id_map = NULL,
340 .setup_apic_routing = NULL,
341 .multi_timer_check = NULL,
342 .cpu_present_to_apicid = default_cpu_present_to_apicid,
343 .apicid_to_cpu_present = NULL,
344 .setup_portio_remap = NULL,
345 .check_phys_apicid_present = default_check_phys_apicid_present,
346 .enable_apic_mode = NULL,
347 .phys_pkg_id = uv_phys_pkg_id,
348 .mps_oem_check = NULL,
349
350 .get_apic_id = x2apic_get_apic_id,
351 .set_apic_id = set_apic_id,
352 .apic_id_mask = 0xFFFFFFFFu,
353
354 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
355 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
356
357 .send_IPI_mask = uv_send_IPI_mask,
358 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
359 .send_IPI_allbutself = uv_send_IPI_allbutself,
360 .send_IPI_all = uv_send_IPI_all,
361 .send_IPI_self = uv_send_IPI_self,
362
363 .wakeup_secondary_cpu = uv_wakeup_secondary,
364 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
365 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
366 .wait_for_init_deassert = NULL,
367 .smp_callin_clear_local_apic = NULL,
368 .inquire_remote_apic = NULL,
369
370 .read = native_apic_msr_read,
371 .write = native_apic_msr_write,
372 .icr_read = native_x2apic_icr_read,
373 .icr_write = native_x2apic_icr_write,
374 .wait_icr_idle = native_x2apic_wait_icr_idle,
375 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
376 };
377
378 static __cpuinit void set_x2apic_extra_bits(int pnode)
379 {
380 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
381 }
382
383 /*
384 * Called on boot cpu.
385 */
386 static __init int boot_pnode_to_blade(int pnode)
387 {
388 int blade;
389
390 for (blade = 0; blade < uv_num_possible_blades(); blade++)
391 if (pnode == uv_blade_info[blade].pnode)
392 return blade;
393 BUG();
394 }
395
396 struct redir_addr {
397 unsigned long redirect;
398 unsigned long alias;
399 };
400
401 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
402
403 static __initdata struct redir_addr redir_addrs[] = {
404 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
405 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
406 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
407 };
408
409 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
410 {
411 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
412 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
413 int i;
414
415 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
416 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
417 if (alias.s.enable && alias.s.base == 0) {
418 *size = (1UL << alias.s.m_alias);
419 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
420 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
421 return;
422 }
423 }
424 *base = *size = 0;
425 }
426
427 enum map_type {map_wb, map_uc};
428
429 static __init void map_high(char *id, unsigned long base, int pshift,
430 int bshift, int max_pnode, enum map_type map_type)
431 {
432 unsigned long bytes, paddr;
433
434 paddr = base << pshift;
435 bytes = (1UL << bshift) * (max_pnode + 1);
436 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
437 paddr + bytes);
438 if (map_type == map_uc)
439 init_extra_mapping_uc(paddr, bytes);
440 else
441 init_extra_mapping_wb(paddr, bytes);
442
443 }
444 static __init void map_gru_high(int max_pnode)
445 {
446 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
447 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
448
449 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
450 if (gru.s.enable) {
451 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
452 gru_start_paddr = ((u64)gru.s.base << shift);
453 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
454
455 }
456 }
457
458 static __init void map_mmr_high(int max_pnode)
459 {
460 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
461 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
462
463 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
464 if (mmr.s.enable)
465 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
466 }
467
468 static __init void map_mmioh_high(int max_pnode)
469 {
470 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
471 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
472
473 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
474 if (mmioh.s.enable)
475 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
476 max_pnode, map_uc);
477 }
478
479 static __init void map_low_mmrs(void)
480 {
481 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
482 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
483 }
484
485 static __init void uv_rtc_init(void)
486 {
487 long status;
488 u64 ticks_per_sec;
489
490 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
491 &ticks_per_sec);
492 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
493 printk(KERN_WARNING
494 "unable to determine platform RTC clock frequency, "
495 "guessing.\n");
496 /* BIOS gives wrong value for clock freq. so guess */
497 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
498 } else
499 sn_rtc_cycles_per_second = ticks_per_sec;
500 }
501
502 /*
503 * percpu heartbeat timer
504 */
505 static void uv_heartbeat(unsigned long ignored)
506 {
507 struct timer_list *timer = &uv_hub_info->scir.timer;
508 unsigned char bits = uv_hub_info->scir.state;
509
510 /* flip heartbeat bit */
511 bits ^= SCIR_CPU_HEARTBEAT;
512
513 /* is this cpu idle? */
514 if (idle_cpu(raw_smp_processor_id()))
515 bits &= ~SCIR_CPU_ACTIVITY;
516 else
517 bits |= SCIR_CPU_ACTIVITY;
518
519 /* update system controller interface reg */
520 uv_set_scir_bits(bits);
521
522 /* enable next timer period */
523 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
524 }
525
526 static void __cpuinit uv_heartbeat_enable(int cpu)
527 {
528 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
529 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
530
531 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
532 setup_timer(timer, uv_heartbeat, cpu);
533 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
534 add_timer_on(timer, cpu);
535 uv_cpu_hub_info(cpu)->scir.enabled = 1;
536
537 /* also ensure that boot cpu is enabled */
538 cpu = 0;
539 }
540 }
541
542 #ifdef CONFIG_HOTPLUG_CPU
543 static void __cpuinit uv_heartbeat_disable(int cpu)
544 {
545 if (uv_cpu_hub_info(cpu)->scir.enabled) {
546 uv_cpu_hub_info(cpu)->scir.enabled = 0;
547 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
548 }
549 uv_set_cpu_scir_bits(cpu, 0xff);
550 }
551
552 /*
553 * cpu hotplug notifier
554 */
555 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
556 unsigned long action, void *hcpu)
557 {
558 long cpu = (long)hcpu;
559
560 switch (action) {
561 case CPU_ONLINE:
562 uv_heartbeat_enable(cpu);
563 break;
564 case CPU_DOWN_PREPARE:
565 uv_heartbeat_disable(cpu);
566 break;
567 default:
568 break;
569 }
570 return NOTIFY_OK;
571 }
572
573 static __init void uv_scir_register_cpu_notifier(void)
574 {
575 hotcpu_notifier(uv_scir_cpu_notify, 0);
576 }
577
578 #else /* !CONFIG_HOTPLUG_CPU */
579
580 static __init void uv_scir_register_cpu_notifier(void)
581 {
582 }
583
584 static __init int uv_init_heartbeat(void)
585 {
586 int cpu;
587
588 if (is_uv_system())
589 for_each_online_cpu(cpu)
590 uv_heartbeat_enable(cpu);
591 return 0;
592 }
593
594 late_initcall(uv_init_heartbeat);
595
596 #endif /* !CONFIG_HOTPLUG_CPU */
597
598 /* Direct Legacy VGA I/O traffic to designated IOH */
599 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
600 unsigned int command_bits, bool change_bridge)
601 {
602 int domain, bus, rc;
603
604 PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
605 pdev->devfn, decode, command_bits, change_bridge);
606
607 if (!change_bridge)
608 return 0;
609
610 if ((command_bits & PCI_COMMAND_IO) == 0)
611 return 0;
612
613 domain = pci_domain_nr(pdev->bus);
614 bus = pdev->bus->number;
615
616 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
617 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
618
619 return rc;
620 }
621
622 /*
623 * Called on each cpu to initialize the per_cpu UV data area.
624 * FIXME: hotplug not supported yet
625 */
626 void __cpuinit uv_cpu_init(void)
627 {
628 /* CPU 0 initilization will be done via uv_system_init. */
629 if (!uv_blade_info)
630 return;
631
632 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
633
634 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
635 set_x2apic_extra_bits(uv_hub_info->pnode);
636 }
637
638 /*
639 * When NMI is received, print a stack trace.
640 */
641 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
642 {
643 if (reason != DIE_NMIUNKNOWN)
644 return NOTIFY_OK;
645
646 if (in_crash_kexec)
647 /* do nothing if entering the crash kernel */
648 return NOTIFY_OK;
649 /*
650 * Use a lock so only one cpu prints at a time
651 * to prevent intermixed output.
652 */
653 spin_lock(&uv_nmi_lock);
654 pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
655 dump_stack();
656 spin_unlock(&uv_nmi_lock);
657
658 return NOTIFY_STOP;
659 }
660
661 static struct notifier_block uv_dump_stack_nmi_nb = {
662 .notifier_call = uv_handle_nmi
663 };
664
665 void uv_register_nmi_notifier(void)
666 {
667 if (register_die_notifier(&uv_dump_stack_nmi_nb))
668 printk(KERN_WARNING "UV NMI handler failed to register\n");
669 }
670
671 void uv_nmi_init(void)
672 {
673 unsigned int value;
674
675 /*
676 * Unmask NMI on all cpus
677 */
678 value = apic_read(APIC_LVT1) | APIC_DM_NMI;
679 value &= ~APIC_LVT_MASKED;
680 apic_write(APIC_LVT1, value);
681 }
682
683 void __init uv_system_init(void)
684 {
685 union uvh_rh_gam_config_mmr_u m_n_config;
686 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
687 union uvh_node_id_u node_id;
688 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
689 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
690 int gnode_extra, max_pnode = 0;
691 unsigned long mmr_base, present, paddr;
692 unsigned short pnode_mask, pnode_io_mask;
693
694 map_low_mmrs();
695
696 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
697 m_val = m_n_config.s.m_skt;
698 n_val = m_n_config.s.n_skt;
699 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
700 n_io = mmioh.s.n_io;
701 mmr_base =
702 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
703 ~UV_MMR_ENABLE;
704 pnode_mask = (1 << n_val) - 1;
705 pnode_io_mask = (1 << n_io) - 1;
706
707 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
708 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
709 gnode_upper = ((unsigned long)gnode_extra << m_val);
710 printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
711 n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
712
713 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
714
715 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
716 uv_possible_blades +=
717 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
718 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
719
720 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
721 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
722 BUG_ON(!uv_blade_info);
723 for (blade = 0; blade < uv_num_possible_blades(); blade++)
724 uv_blade_info[blade].memory_nid = -1;
725
726 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
727
728 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
729 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
730 BUG_ON(!uv_node_to_blade);
731 memset(uv_node_to_blade, 255, bytes);
732
733 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
734 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
735 BUG_ON(!uv_cpu_to_blade);
736 memset(uv_cpu_to_blade, 255, bytes);
737
738 blade = 0;
739 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
740 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
741 for (j = 0; j < 64; j++) {
742 if (!test_bit(j, &present))
743 continue;
744 pnode = (i * 64 + j) & pnode_mask;
745 uv_blade_info[blade].pnode = pnode;
746 uv_blade_info[blade].nr_possible_cpus = 0;
747 uv_blade_info[blade].nr_online_cpus = 0;
748 max_pnode = max(pnode, max_pnode);
749 blade++;
750 }
751 }
752
753 uv_bios_init();
754 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
755 &sn_region_size, &system_serial_number);
756 uv_rtc_init();
757
758 for_each_present_cpu(cpu) {
759 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
760
761 nid = cpu_to_node(cpu);
762 /*
763 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
764 */
765 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
766 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
767 pnode = uv_apicid_to_pnode(apicid);
768 blade = boot_pnode_to_blade(pnode);
769 lcpu = uv_blade_info[blade].nr_possible_cpus;
770 uv_blade_info[blade].nr_possible_cpus++;
771
772 /* Any node on the blade, else will contain -1. */
773 uv_blade_info[blade].memory_nid = nid;
774
775 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
776 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
777 uv_cpu_hub_info(cpu)->m_val = m_val;
778 uv_cpu_hub_info(cpu)->n_val = n_val;
779 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
780 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
781 uv_cpu_hub_info(cpu)->pnode = pnode;
782 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
783 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
784 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
785 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
786 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
787 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
788 uv_node_to_blade[nid] = blade;
789 uv_cpu_to_blade[cpu] = blade;
790 }
791
792 /* Add blade/pnode info for nodes without cpus */
793 for_each_online_node(nid) {
794 if (uv_node_to_blade[nid] >= 0)
795 continue;
796 paddr = node_start_pfn(nid) << PAGE_SHIFT;
797 paddr = uv_soc_phys_ram_to_gpa(paddr);
798 pnode = (paddr >> m_val) & pnode_mask;
799 blade = boot_pnode_to_blade(pnode);
800 uv_node_to_blade[nid] = blade;
801 }
802
803 map_gru_high(max_pnode);
804 map_mmr_high(max_pnode);
805 map_mmioh_high(max_pnode & pnode_io_mask);
806
807 uv_cpu_init();
808 uv_scir_register_cpu_notifier();
809 uv_register_nmi_notifier();
810 proc_mkdir("sgi_uv", NULL);
811
812 /* register Legacy VGA I/O redirection handler */
813 pci_register_set_vga_state(uv_set_vga_state);
814 }
Linus' kernel tree