arch/sh/drivers/pci/pci-sh7751.c

   1 /*
   2  *      Low-Level PCI Support for the SH7751
   3  *
   4  *  Dustin McIntire (dustin@sensoria.com)
   5  *      Derived from arch/i386/kernel/pci-*.c which bore the message:
   6  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   7  *
   8  *  Ported to the new API by Paul Mundt <lethal@linux-sh.org>
   9  *  With cleanup by Paul van Gool <pvangool@mimotech.com>
  10  *
  11  *  May be copied or modified under the terms of the GNU General Public
  12  *  License.  See linux/COPYING for more information.
  13  *
  14  */
  15
  16 #undef DEBUG
  17
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include "pci-sh4.h"
  24 #include <asm/addrspace.h>
  25 #include <asm/io.h>
  26
  27 /*
  28  * Initialization. Try all known PCI access methods. Note that we support
  29  * using both PCI BIOS and direct access: in such cases, we use I/O ports
  30  * to access config space.
  31  *
  32  * Note that the platform specific initialization (BSC registers, and memory
  33  * space mapping) will be called via the platform defined function
  34  * pcibios_init_platform().
  35  */
  36 static int __init sh7751_pci_init(void)
  37 {
  38         unsigned int id;
  39         int ret;
  40
  41         pr_debug("PCI: Starting intialization.\n");
  42
  43         /* check for SH7751/SH7751R hardware */
  44         id = pci_read_reg(SH7751_PCICONF0);
  45         if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
  46             id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
  47                 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
  48                 return -ENODEV;
  49         }
  50
  51         if ((ret = sh4_pci_check_direct()) != 0)
  52                 return ret;
  53
  54         return pcibios_init_platform();
  55 }
  56 subsys_initcall(sh7751_pci_init);
  57
  58 static int __init __area_sdram_check(unsigned int area)
  59 {
  60         u32 word;
  61
  62         word = inl(SH7751_BCR1);
  63         /* check BCR for SDRAM in area */
  64         if (((word >> area) & 1) == 0) {
  65                 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
  66                        area, word);
  67                 return 0;
  68         }
  69         pci_write_reg(word, SH4_PCIBCR1);
  70
  71         word = (u16)inw(SH7751_BCR2);
  72         /* check BCR2 for 32bit SDRAM interface*/
  73         if (((word >> (area << 1)) & 0x3) != 0x3) {
  74                 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
  75                        area, word);
  76                 return 0;
  77         }
  78         pci_write_reg(word, SH4_PCIBCR2);
  79
  80         return 1;
  81 }
  82
  83 int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
  84 {
  85         u32 reg;
  86         u32 word;
  87
  88         /* Set the BCR's to enable PCI access */
  89         reg = inl(SH7751_BCR1);
  90         reg |= 0x80000;
  91         outl(reg, SH7751_BCR1);
  92
  93         /* Turn the clocks back on (not done in reset)*/
  94         pci_write_reg(0, SH4_PCICLKR);
  95         /* Clear Powerdown IRQ's (not done in reset) */
  96         word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
  97         pci_write_reg(word, SH4_PCIPINT);
  98
  99         /*
 100          * This code is unused for some boards as it is done in the
 101          * bootloader and doing it here means the MAC addresses loaded
 102          * by the bootloader get lost.
 103          */
 104         if (!(map->flags & SH4_PCIC_NO_RESET)) {
 105                 /* toggle PCI reset pin */
 106                 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
 107                 pci_write_reg(word, SH4_PCICR);
 108                 /* Wait for a long time... not 1 sec. but long enough */
 109                 mdelay(100);
 110                 word = SH4_PCICR_PREFIX;
 111                 pci_write_reg(word, SH4_PCICR);
 112         }
 113
 114         /* set the command/status bits to:
 115          * Wait Cycle Control + Parity Enable + Bus Master +
 116          * Mem space enable
 117          */
 118         word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
 119                SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
 120         pci_write_reg(word, SH7751_PCICONF1);
 121
 122         /* define this host as the host bridge */
 123         word = PCI_BASE_CLASS_BRIDGE << 24;
 124         pci_write_reg(word, SH7751_PCICONF2);
 125
 126         /* Set IO and Mem windows to local address
 127          * Make PCI and local address the same for easy 1 to 1 mapping
 128          * Window0 = map->window0.size @ non-cached area base = SDRAM
 129          * Window1 = map->window1.size @ cached area base = SDRAM
 130          */
 131         word = map->window0.size - 1;
 132         pci_write_reg(word, SH4_PCILSR0);
 133         word = map->window1.size - 1;
 134         pci_write_reg(word, SH4_PCILSR1);
 135         /* Set the values on window 0 PCI config registers */
 136         word = P2SEGADDR(map->window0.base);
 137         pci_write_reg(word, SH4_PCILAR0);
 138         pci_write_reg(word, SH7751_PCICONF5);
 139         /* Set the values on window 1 PCI config registers */
 140         word =  PHYSADDR(map->window1.base);
 141         pci_write_reg(word, SH4_PCILAR1);
 142         pci_write_reg(word, SH7751_PCICONF6);
 143
 144         /* Set the local 16MB PCI memory space window to
 145          * the lowest PCI mapped address
 146          */
 147         word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK;
 148         pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
 149         pci_write_reg(word , SH4_PCIMBR);
 150
 151         /* Map IO space into PCI IO window
 152          * The IO window is 64K-PCIBIOS_MIN_IO in size
 153          * IO addresses will be translated to the
 154          * PCI IO window base address
 155          */
 156         pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
 157                  PCIBIOS_MIN_IO, (64 << 10),
 158                  SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
 159
 160         /* Make sure the MSB's of IO window are set to access PCI space
 161          * correctly */
 162         word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK;
 163         pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
 164         pci_write_reg(word, SH4_PCIIOBR);
 165
 166         /* Set PCI WCRx, BCRx's, copy from BSC locations */
 167
 168         /* check BCR for SDRAM in specified area */
 169         switch (map->window0.base) {
 170         case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
 171         case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
 172         case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
 173         case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
 174         case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
 175         case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
 176         case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
 177         }
 178
 179         if (!word)
 180                 return 0;
 181
 182         /* configure the wait control registers */
 183         word = inl(SH7751_WCR1);
 184         pci_write_reg(word, SH4_PCIWCR1);
 185         word = inl(SH7751_WCR2);
 186         pci_write_reg(word, SH4_PCIWCR2);
 187         word = inl(SH7751_WCR3);
 188         pci_write_reg(word, SH4_PCIWCR3);
 189         word = inl(SH7751_MCR);
 190         pci_write_reg(word, SH4_PCIMCR);
 191
 192         /* NOTE: I'm ignoring the PCI error IRQs for now..
 193          * TODO: add support for the internal error interrupts and
 194          * DMA interrupts...
 195          */
 196
 197 #if defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_LBOX_RE2)
 198         pci_fixup_pcic();
 199 #endif
 200
 201         /* SH7751 init done, set central function init complete */
 202         /* use round robin mode to stop a device starving/overruning */
 203         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
 204         pci_write_reg(word, SH4_PCICR);
 205
 206         return 1;
 207 }