arch/arm/plat-mxc/ehci.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/mxc_ehci.h>
  25
  26 #define USBCTRL_OTGBASE_OFFSET  0x600
  27
  28 #define MX31_OTG_SIC_SHIFT      29
  29 #define MX31_OTG_SIC_MASK       (0x3 << MX31_OTG_SIC_SHIFT)
  30 #define MX31_OTG_PM_BIT         (1 << 24)
  31
  32 #define MX31_H2_SIC_SHIFT       21
  33 #define MX31_H2_SIC_MASK        (0x3 << MX31_H2_SIC_SHIFT)
  34 #define MX31_H2_PM_BIT          (1 << 16)
  35 #define MX31_H2_DT_BIT          (1 << 5)
  36
  37 #define MX31_H1_SIC_SHIFT       13
  38 #define MX31_H1_SIC_MASK        (0x3 << MX31_H1_SIC_SHIFT)
  39 #define MX31_H1_PM_BIT          (1 << 8)
  40 #define MX31_H1_DT_BIT          (1 << 4)
  41
  42 #define MX35_OTG_SIC_SHIFT      29
  43 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
  44 #define MX35_OTG_PM_BIT         (1 << 24)
  45
  46 #define MX35_H1_SIC_SHIFT       21
  47 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
  48 #define MX35_H1_PM_BIT          (1 << 8)
  49 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
  50 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
  51 #define MX35_H1_TLL_BIT         (1 << 5)
  52 #define MX35_H1_USBTE_BIT       (1 << 4)
  53
  54 #define MXC_OTG_OFFSET          0
  55 #define MXC_H1_OFFSET           0x200
  56
  57 /* USB_CTRL */
  58 #define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
  59 #define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
  60 #define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
  61 #define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
  62 #define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
  63
  64 /* USB_PHY_CTRL_FUNC */
  65 #define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
  66 #define MXC_H1_OC_DIS_BIT                       (1 << 5)        /* UH1 Disable Overcurrent Event */
  67
  68 #define MXC_USBCMD_OFFSET                       0x140
  69
  70 /* USBCMD */
  71 #define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
  72
  73 int mxc_initialize_usb_hw(int port, unsigned int flags)
  74 {
  75         unsigned int v;
  76 #ifdef CONFIG_ARCH_MX3
  77         if (cpu_is_mx31()) {
  78                 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
  79                                      USBCTRL_OTGBASE_OFFSET));
  80
  81                 switch (port) {
  82                 case 0: /* OTG port */
  83                         v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
  84                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
  85                                         << MX31_OTG_SIC_SHIFT;
  86                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  87                                 v |= MX31_OTG_PM_BIT;
  88
  89                         break;
  90                 case 1: /* H1 port */
  91                         v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
  92                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
  93                                                 << MX31_H1_SIC_SHIFT;
  94                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  95                                 v |= MX31_H1_PM_BIT;
  96
  97                         if (!(flags & MXC_EHCI_TTL_ENABLED))
  98                                 v |= MX31_H1_DT_BIT;
  99
 100                         break;
 101                 case 2: /* H2 port */
 102                         v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
 103                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 104                                                 << MX31_H2_SIC_SHIFT;
 105                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 106                                 v |= MX31_H2_PM_BIT;
 107
 108                         if (!(flags & MXC_EHCI_TTL_ENABLED))
 109                                 v |= MX31_H2_DT_BIT;
 110
 111                         break;
 112                 default:
 113                         return -EINVAL;
 114                 }
 115
 116                 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
 117                                      USBCTRL_OTGBASE_OFFSET));
 118                 return 0;
 119         }
 120
 121         if (cpu_is_mx35()) {
 122                 v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
 123                                      USBCTRL_OTGBASE_OFFSET));
 124
 125                 switch (port) {
 126                 case 0: /* OTG port */
 127                         v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
 128                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 129                                         << MX35_OTG_SIC_SHIFT;
 130                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 131                                 v |= MX35_OTG_PM_BIT;
 132
 133                         break;
 134                 case 1: /* H1 port */
 135                         v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
 136                                 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
 137                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 138                                                 << MX35_H1_SIC_SHIFT;
 139                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 140                                 v |= MX35_H1_PM_BIT;
 141
 142                         if (!(flags & MXC_EHCI_TTL_ENABLED))
 143                                 v |= MX35_H1_TLL_BIT;
 144
 145                         if (flags & MXC_EHCI_INTERNAL_PHY)
 146                                 v |= MX35_H1_USBTE_BIT;
 147
 148                         if (flags & MXC_EHCI_IPPUE_DOWN)
 149                                 v |= MX35_H1_IPPUE_DOWN_BIT;
 150
 151                         if (flags & MXC_EHCI_IPPUE_UP)
 152                                 v |= MX35_H1_IPPUE_UP_BIT;
 153
 154                         break;
 155                 default:
 156                         return -EINVAL;
 157                 }
 158
 159                 writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
 160                                      USBCTRL_OTGBASE_OFFSET));
 161                 return 0;
 162         }
 163 #endif /* CONFIG_ARCH_MX3 */
 164 #ifdef CONFIG_MACH_MX27
 165         if (cpu_is_mx27()) {
 166                 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
 167                  * are identical
 168                  */
 169                 v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
 170                                      USBCTRL_OTGBASE_OFFSET));
 171                 switch (port) {
 172                 case 0: /* OTG port */
 173                         v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
 174                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 175                                         << MX31_OTG_SIC_SHIFT;
 176                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 177                                 v |= MX31_OTG_PM_BIT;
 178                         break;
 179                 case 1: /* H1 port */
 180                         v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
 181                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 182                                                 << MX31_H1_SIC_SHIFT;
 183                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 184                                 v |= MX31_H1_PM_BIT;
 185
 186                         if (!(flags & MXC_EHCI_TTL_ENABLED))
 187                                 v |= MX31_H1_DT_BIT;
 188
 189                         break;
 190                 case 2: /* H2 port */
 191                         v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
 192                         v |= (flags & MXC_EHCI_INTERFACE_MASK)
 193                                                 << MX31_H2_SIC_SHIFT;
 194                         if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
 195                                 v |= MX31_H2_PM_BIT;
 196
 197                         if (!(flags & MXC_EHCI_TTL_ENABLED))
 198                                 v |= MX31_H2_DT_BIT;
 199
 200                         break;
 201                 default:
 202                         return -EINVAL;
 203                 }
 204                 writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
 205                                      USBCTRL_OTGBASE_OFFSET));
 206                 return 0;
 207         }
 208 #endif /* CONFIG_MACH_MX27 */
 209 #ifdef CONFIG_ARCH_MX51
 210         if (cpu_is_mx51()) {
 211                 void __iomem *usb_base;
 212                 u32 usbotg_base;
 213                 u32 usbother_base;
 214                 int ret = 0;
 215
 216                 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 217
 218                 switch (port) {
 219                 case 0: /* OTG port */
 220                         usbotg_base = usb_base + MXC_OTG_OFFSET;
 221                         break;
 222                 case 1: /* Host 1 port */
 223                         usbotg_base = usb_base + MXC_H1_OFFSET;
 224                         break;
 225                 default:
 226                         printk(KERN_ERR"%s no such port %d\n", __func__, port);
 227                         ret = -ENOENT;
 228                         goto error;
 229                 }
 230                 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 231
 232                 switch (port) {
 233                 case 0: /*OTG port */
 234                         if (flags & MXC_EHCI_INTERNAL_PHY) {
 235                                 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 236
 237                                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 238                                         v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
 239                                 else
 240                                         v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
 241                                 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 242
 243                                 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 244                                 if (flags & MXC_EHCI_WAKEUP_ENABLED)
 245                                         v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
 246                                 else
 247                                         v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
 248                                 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 249                         }
 250                         break;
 251                 case 1: /* Host 1 */
 252                         /*Host ULPI */
 253                         v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 254                         if (flags & MXC_EHCI_WAKEUP_ENABLED)
 255                                 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
 256                         else
 257                                 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
 258
 259                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 260                                 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
 261                         else
 262                                 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
 263                         __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 264
 265                         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 266                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 267                                 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 268                         else
 269                                 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
 270                         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 271
 272                         v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
 273                         if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
 274                                 /* Interrupt Threshold Control:Immediate (no threshold) */
 275                                 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
 276                         __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
 277                         break;
 278                 }
 279
 280 error:
 281                 iounmap(usb_base);
 282                 return ret;
 283         }
 284 #endif
 285         printk(KERN_WARNING
 286                 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
 287         return -EINVAL;
 288 }
 289 EXPORT_SYMBOL(mxc_initialize_usb_hw);
 290