2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <asm/mach/time.h>
41 #include <plat/dmtimer.h>
42 #include <asm/localtimer.h>
43 #include <asm/sched_clock.h>
44 #include <plat/common.h>
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap-pm.h>
49 #include "powerdomain.h"
51 /* Parent clocks, eventually these will come from the clock framework */
53 #define OMAP2_MPU_SOURCE "sys_ck"
54 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
55 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
56 #define OMAP2_32K_SOURCE "func_32k_ck"
57 #define OMAP3_32K_SOURCE "omap_32k_fck"
58 #define OMAP4_32K_SOURCE "sys_32k_ck"
60 #ifdef CONFIG_OMAP_32K_TIMER
61 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
62 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
63 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
64 #define OMAP3_SECURE_TIMER 12
66 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
67 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
68 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
69 #define OMAP3_SECURE_TIMER 1
72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
73 #define MAX_GPTIMER_ID 12
75 static u32 sys_timer_reserved
;
79 static struct omap_dm_timer clkev
;
80 static struct clock_event_device clockevent_gpt
;
82 static irqreturn_t
omap2_gp_timer_interrupt(int irq
, void *dev_id
)
84 struct clock_event_device
*evt
= &clockevent_gpt
;
86 __omap_dm_timer_write_status(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
88 evt
->event_handler(evt
);
92 static struct irqaction omap2_gp_timer_irq
= {
94 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
95 .handler
= omap2_gp_timer_interrupt
,
98 static int omap2_gp_timer_set_next_event(unsigned long cycles
,
99 struct clock_event_device
*evt
)
101 __omap_dm_timer_load_start(&clkev
, OMAP_TIMER_CTRL_ST
,
102 0xffffffff - cycles
, 1);
107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode
,
108 struct clock_event_device
*evt
)
112 __omap_dm_timer_stop(&clkev
, 1, clkev
.rate
);
115 case CLOCK_EVT_MODE_PERIODIC
:
116 period
= clkev
.rate
/ HZ
;
118 /* Looks like we need to first set the load value separately */
119 __omap_dm_timer_write(&clkev
, OMAP_TIMER_LOAD_REG
,
120 0xffffffff - period
, 1);
121 __omap_dm_timer_load_start(&clkev
,
122 OMAP_TIMER_CTRL_AR
| OMAP_TIMER_CTRL_ST
,
123 0xffffffff - period
, 1);
125 case CLOCK_EVT_MODE_ONESHOT
:
127 case CLOCK_EVT_MODE_UNUSED
:
128 case CLOCK_EVT_MODE_SHUTDOWN
:
129 case CLOCK_EVT_MODE_RESUME
:
134 static struct clock_event_device clockevent_gpt
= {
136 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
138 .set_next_event
= omap2_gp_timer_set_next_event
,
139 .set_mode
= omap2_gp_timer_set_mode
,
142 static int __init
omap_dm_timer_init_one(struct omap_dm_timer
*timer
,
144 const char *fck_source
)
146 char name
[10]; /* 10 = sizeof("gptXX_Xck0") */
147 struct omap_hwmod
*oh
;
151 sprintf(name
, "timer%d", gptimer_id
);
152 omap_hwmod_setup_one(name
);
153 oh
= omap_hwmod_lookup(name
);
157 timer
->irq
= oh
->mpu_irqs
[0].irq
;
158 timer
->phys_base
= oh
->slaves
[0]->addr
->pa_start
;
159 size
= oh
->slaves
[0]->addr
->pa_end
- timer
->phys_base
;
161 /* Static mapping, never released */
162 timer
->io_base
= ioremap(timer
->phys_base
, size
);
166 /* After the dmtimer is using hwmod these clocks won't be needed */
167 sprintf(name
, "gpt%d_fck", gptimer_id
);
168 timer
->fclk
= clk_get(NULL
, name
);
169 if (IS_ERR(timer
->fclk
))
172 sprintf(name
, "gpt%d_ick", gptimer_id
);
173 timer
->iclk
= clk_get(NULL
, name
);
174 if (IS_ERR(timer
->iclk
)) {
175 clk_put(timer
->fclk
);
179 omap_hwmod_enable(oh
);
181 sys_timer_reserved
|= (1 << (gptimer_id
- 1));
183 if (gptimer_id
!= 12) {
186 src
= clk_get(NULL
, fck_source
);
190 res
= __omap_dm_timer_set_source(timer
->fclk
, src
);
191 if (IS_ERR_VALUE(res
))
192 pr_warning("%s: timer%i cannot set source\n",
193 __func__
, gptimer_id
);
197 __omap_dm_timer_init_regs(timer
);
198 __omap_dm_timer_reset(timer
, 1, 1);
201 timer
->rate
= clk_get_rate(timer
->fclk
);
208 static void __init
omap2_gp_clockevent_init(int gptimer_id
,
209 const char *fck_source
)
213 res
= omap_dm_timer_init_one(&clkev
, gptimer_id
, fck_source
);
216 omap2_gp_timer_irq
.dev_id
= (void *)&clkev
;
217 setup_irq(clkev
.irq
, &omap2_gp_timer_irq
);
219 __omap_dm_timer_int_enable(&clkev
, OMAP_TIMER_INT_OVERFLOW
);
221 clockevent_gpt
.mult
= div_sc(clkev
.rate
, NSEC_PER_SEC
,
222 clockevent_gpt
.shift
);
223 clockevent_gpt
.max_delta_ns
=
224 clockevent_delta2ns(0xffffffff, &clockevent_gpt
);
225 clockevent_gpt
.min_delta_ns
=
226 clockevent_delta2ns(3, &clockevent_gpt
);
227 /* Timer internal resynch latency. */
229 clockevent_gpt
.cpumask
= cpumask_of(0);
230 clockevents_register_device(&clockevent_gpt
);
232 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
233 gptimer_id
, clkev
.rate
);
236 /* Clocksource code */
238 #ifdef CONFIG_OMAP_32K_TIMER
240 * When 32k-timer is enabled, don't use GPTimer for clocksource
241 * instead, just leave default clocksource which uses the 32k
242 * sync counter. See clocksource setup in plat-omap/counter_32k.c
245 static void __init
omap2_gp_clocksource_init(int unused
, const char *dummy
)
247 omap_init_clocksource_32k();
252 static struct omap_dm_timer clksrc
;
257 static DEFINE_CLOCK_DATA(cd
);
258 static cycle_t
clocksource_read_cycles(struct clocksource
*cs
)
260 return (cycle_t
)__omap_dm_timer_read_counter(&clksrc
, 1);
263 static struct clocksource clocksource_gpt
= {
266 .read
= clocksource_read_cycles
,
267 .mask
= CLOCKSOURCE_MASK(32),
268 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
271 static void notrace
dmtimer_update_sched_clock(void)
275 cyc
= __omap_dm_timer_read_counter(&clksrc
, 1);
277 update_sched_clock(&cd
, cyc
, (u32
)~0);
280 unsigned long long notrace
sched_clock(void)
285 cyc
= __omap_dm_timer_read_counter(&clksrc
, 1);
287 return cyc_to_sched_clock(&cd
, cyc
, (u32
)~0);
290 /* Setup free-running counter for clocksource */
291 static void __init
omap2_gp_clocksource_init(int gptimer_id
,
292 const char *fck_source
)
296 res
= omap_dm_timer_init_one(&clksrc
, gptimer_id
, fck_source
);
299 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
300 gptimer_id
, clksrc
.rate
);
302 __omap_dm_timer_load_start(&clksrc
,
303 OMAP_TIMER_CTRL_ST
| OMAP_TIMER_CTRL_AR
, 0, 1);
304 init_sched_clock(&cd
, dmtimer_update_sched_clock
, 32, clksrc
.rate
);
306 if (clocksource_register_hz(&clocksource_gpt
, clksrc
.rate
))
307 pr_err("Could not register clocksource %s\n",
308 clocksource_gpt
.name
);
312 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
313 clksrc_nr, clksrc_src) \
314 static void __init omap##name##_timer_init(void) \
316 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
317 omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
320 #define OMAP_SYS_TIMER(name) \
321 struct sys_timer omap##name##_timer = { \
322 .init = omap##name##_timer_init, \
325 #ifdef CONFIG_ARCH_OMAP2
326 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE
, 2, OMAP2_MPU_SOURCE
)
330 #ifdef CONFIG_ARCH_OMAP3
331 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE
, 2, OMAP3_MPU_SOURCE
)
333 OMAP_SYS_TIMER_INIT(3_secure
, OMAP3_SECURE_TIMER
, OMAP3_CLKEV_SOURCE
,
335 OMAP_SYS_TIMER(3_secure
)
338 #ifdef CONFIG_ARCH_OMAP4
339 static void __init
omap4_timer_init(void)
341 #ifdef CONFIG_LOCAL_TIMERS
342 twd_base
= ioremap(OMAP44XX_LOCAL_TWD_BASE
, SZ_256
);
345 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE
);
346 omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE
);
352 * omap2_dm_timer_set_src - change the timer input clock source
353 * @pdev: timer platform device pointer
354 * @source: array index of parent clock source
356 static int omap2_dm_timer_set_src(struct platform_device
*pdev
, int source
)
359 struct dmtimer_platform_data
*pdata
= pdev
->dev
.platform_data
;
360 struct clk
*fclk
, *parent
;
361 char *parent_name
= NULL
;
363 fclk
= clk_get(&pdev
->dev
, "fck");
364 if (IS_ERR_OR_NULL(fclk
)) {
365 dev_err(&pdev
->dev
, "%s: %d: clk_get() FAILED\n",
371 case OMAP_TIMER_SRC_SYS_CLK
:
372 parent_name
= "sys_ck";
375 case OMAP_TIMER_SRC_32_KHZ
:
376 parent_name
= "32k_ck";
379 case OMAP_TIMER_SRC_EXT_CLK
:
380 if (pdata
->timer_ip_version
== OMAP_TIMER_IP_VERSION_1
) {
381 parent_name
= "alt_ck";
384 dev_err(&pdev
->dev
, "%s: %d: invalid clk src.\n",
390 parent
= clk_get(&pdev
->dev
, parent_name
);
391 if (IS_ERR_OR_NULL(parent
)) {
392 dev_err(&pdev
->dev
, "%s: %d: clk_get() %s FAILED\n",
393 __func__
, __LINE__
, parent_name
);
398 ret
= clk_set_parent(fclk
, parent
);
399 if (IS_ERR_VALUE(ret
)) {
400 dev_err(&pdev
->dev
, "%s: clk_set_parent() to %s FAILED\n",
401 __func__
, parent_name
);
411 struct omap_device_pm_latency omap2_dmtimer_latency
[] = {
413 .deactivate_func
= omap_device_idle_hwmods
,
414 .activate_func
= omap_device_enable_hwmods
,
415 .flags
= OMAP_DEVICE_LATENCY_AUTO_ADJUST
,
420 * omap_timer_init - build and register timer device with an
421 * associated timer hwmod
422 * @oh: timer hwmod pointer to be used to build timer device
423 * @user: parameter that can be passed from calling hwmod API
425 * Called by omap_hwmod_for_each_by_class to register each of the timer
426 * devices present in the system. The number of timer devices is known
427 * by parsing through the hwmod database for a given class name. At the
428 * end of function call memory is allocated for timer device and it is
429 * registered to the framework ready to be proved by the driver.
431 static int __init
omap_timer_init(struct omap_hwmod
*oh
, void *unused
)
435 char *name
= "omap_timer";
436 struct dmtimer_platform_data
*pdata
;
437 struct platform_device
*pdev
;
438 struct omap_timer_capability_dev_attr
*timer_dev_attr
;
439 struct powerdomain
*pwrdm
;
441 pr_debug("%s: %s\n", __func__
, oh
->name
);
443 /* on secure device, do not register secure timer */
444 timer_dev_attr
= oh
->dev_attr
;
445 if (omap_type() != OMAP2_DEVICE_TYPE_GP
&& timer_dev_attr
)
446 if (timer_dev_attr
->timer_capability
== OMAP_TIMER_SECURE
)
449 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
451 pr_err("%s: No memory for [%s]\n", __func__
, oh
->name
);
456 * Extract the IDs from name field in hwmod database
457 * and use the same for constructing ids' for the
458 * timer devices. In a way, we are avoiding usage of
459 * static variable witin the function to do the same.
460 * CAUTION: We have to be careful and make sure the
461 * name in hwmod database does not change in which case
462 * we might either make corresponding change here or
463 * switch back static variable mechanism.
465 sscanf(oh
->name
, "timer%2d", &id
);
467 pdata
->set_timer_src
= omap2_dm_timer_set_src
;
468 pdata
->timer_ip_version
= oh
->class->rev
;
470 /* Mark clocksource and clockevent timers as reserved */
471 if ((sys_timer_reserved
>> (id
- 1)) & 0x1)
474 pwrdm
= omap_hwmod_get_pwrdm(oh
);
475 pdata
->loses_context
= pwrdm_can_ever_lose_context(pwrdm
);
477 pdata
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
479 pdev
= omap_device_build(name
, id
, oh
, pdata
, sizeof(*pdata
),
480 omap2_dmtimer_latency
,
481 ARRAY_SIZE(omap2_dmtimer_latency
),
485 pr_err("%s: Can't build omap_device for %s: %s.\n",
486 __func__
, name
, oh
->name
);
496 * omap2_dm_timer_init - top level regular device initialization
498 * Uses dedicated hwmod api to parse through hwmod database for
499 * given class name and then build and register the timer device.
501 static int __init
omap2_dm_timer_init(void)
505 ret
= omap_hwmod_for_each_by_class("timer", omap_timer_init
, NULL
);
507 pr_err("%s: device registration failed.\n", __func__
);
513 arch_initcall(omap2_dm_timer_init
);