arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Since the original Pentium M, most new Intel CPUs support Enhanced
   6  * SpeedStep.
   7  *
   8  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   9  * traditional SpeedStep.
  10  *
  11  * Modelled on speedstep.c
  12  *
  13  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/sched.h>        /* current */
  21 #include <linux/delay.h>
  22 #include <linux/compiler.h>
  23
  24 #include <asm/msr.h>
  25 #include <asm/processor.h>
  26 #include <asm/cpufeature.h>
  27
  28 #define PFX             "speedstep-centrino: "
  29 #define MAINTAINER      "cpufreq@lists.linux.org.uk"
  30
  31 #define dprintk(msg...) \
  32         cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  33
  34 #define INTEL_MSR_RANGE (0xffff)
  35
  36 struct cpu_id
  37 {
  38         __u8    x86;            /* CPU family */
  39         __u8    x86_model;      /* model */
  40         __u8    x86_mask;       /* stepping */
  41 };
  42
  43 enum {
  44         CPU_BANIAS,
  45         CPU_DOTHAN_A1,
  46         CPU_DOTHAN_A2,
  47         CPU_DOTHAN_B0,
  48         CPU_MP4HT_D0,
  49         CPU_MP4HT_E0,
  50 };
  51
  52 static const struct cpu_id cpu_ids[] = {
  53         [CPU_BANIAS]    = { 6,  9, 5 },
  54         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  55         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  56         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  57         [CPU_MP4HT_D0]  = {15,  3, 4 },
  58         [CPU_MP4HT_E0]  = {15,  4, 1 },
  59 };
  60 #define N_IDS   ARRAY_SIZE(cpu_ids)
  61
  62 struct cpu_model
  63 {
  64         const struct cpu_id *cpu_id;
  65         const char      *model_name;
  66         unsigned        max_freq; /* max clock in kHz */
  67
  68         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  69 };
  70 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
  71                                   const struct cpu_id *x);
  72
  73 /* Operating points for current CPU */
  74 static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
  75 static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
  76
  77 static struct cpufreq_driver centrino_driver;
  78
  79 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  80
  81 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  82    frequency/voltage operating point; frequency in MHz, volts in mV.
  83    This is stored as "index" in the structure. */
  84 #define OP(mhz, mv)                                                     \
  85         {                                                               \
  86                 .frequency = (mhz) * 1000,                              \
  87                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  88         }
  89
  90 /*
  91  * These voltage tables were derived from the Intel Pentium M
  92  * datasheet, document 25261202.pdf, Table 5.  I have verified they
  93  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
  94  * M.
  95  */
  96
  97 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
  98 static struct cpufreq_frequency_table banias_900[] =
  99 {
 100         OP(600,  844),
 101         OP(800,  988),
 102         OP(900, 1004),
 103         { .frequency = CPUFREQ_TABLE_END }
 104 };
 105
 106 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 107 static struct cpufreq_frequency_table banias_1000[] =
 108 {
 109         OP(600,   844),
 110         OP(800,   972),
 111         OP(900,   988),
 112         OP(1000, 1004),
 113         { .frequency = CPUFREQ_TABLE_END }
 114 };
 115
 116 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 117 static struct cpufreq_frequency_table banias_1100[] =
 118 {
 119         OP( 600,  956),
 120         OP( 800, 1020),
 121         OP( 900, 1100),
 122         OP(1000, 1164),
 123         OP(1100, 1180),
 124         { .frequency = CPUFREQ_TABLE_END }
 125 };
 126
 127
 128 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 129 static struct cpufreq_frequency_table banias_1200[] =
 130 {
 131         OP( 600,  956),
 132         OP( 800, 1004),
 133         OP( 900, 1020),
 134         OP(1000, 1100),
 135         OP(1100, 1164),
 136         OP(1200, 1180),
 137         { .frequency = CPUFREQ_TABLE_END }
 138 };
 139
 140 /* Intel Pentium M processor 1.30GHz (Banias) */
 141 static struct cpufreq_frequency_table banias_1300[] =
 142 {
 143         OP( 600,  956),
 144         OP( 800, 1260),
 145         OP(1000, 1292),
 146         OP(1200, 1356),
 147         OP(1300, 1388),
 148         { .frequency = CPUFREQ_TABLE_END }
 149 };
 150
 151 /* Intel Pentium M processor 1.40GHz (Banias) */
 152 static struct cpufreq_frequency_table banias_1400[] =
 153 {
 154         OP( 600,  956),
 155         OP( 800, 1180),
 156         OP(1000, 1308),
 157         OP(1200, 1436),
 158         OP(1400, 1484),
 159         { .frequency = CPUFREQ_TABLE_END }
 160 };
 161
 162 /* Intel Pentium M processor 1.50GHz (Banias) */
 163 static struct cpufreq_frequency_table banias_1500[] =
 164 {
 165         OP( 600,  956),
 166         OP( 800, 1116),
 167         OP(1000, 1228),
 168         OP(1200, 1356),
 169         OP(1400, 1452),
 170         OP(1500, 1484),
 171         { .frequency = CPUFREQ_TABLE_END }
 172 };
 173
 174 /* Intel Pentium M processor 1.60GHz (Banias) */
 175 static struct cpufreq_frequency_table banias_1600[] =
 176 {
 177         OP( 600,  956),
 178         OP( 800, 1036),
 179         OP(1000, 1164),
 180         OP(1200, 1276),
 181         OP(1400, 1420),
 182         OP(1600, 1484),
 183         { .frequency = CPUFREQ_TABLE_END }
 184 };
 185
 186 /* Intel Pentium M processor 1.70GHz (Banias) */
 187 static struct cpufreq_frequency_table banias_1700[] =
 188 {
 189         OP( 600,  956),
 190         OP( 800, 1004),
 191         OP(1000, 1116),
 192         OP(1200, 1228),
 193         OP(1400, 1308),
 194         OP(1700, 1484),
 195         { .frequency = CPUFREQ_TABLE_END }
 196 };
 197 #undef OP
 198
 199 #define _BANIAS(cpuid, max, name)       \
 200 {       .cpu_id         = cpuid,        \
 201         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 202         .max_freq       = (max)*1000,   \
 203         .op_points      = banias_##max, \
 204 }
 205 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 206
 207 /* CPU models, their operating frequency range, and freq/voltage
 208    operating points */
 209 static struct cpu_model models[] =
 210 {
 211         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 212         BANIAS(1000),
 213         BANIAS(1100),
 214         BANIAS(1200),
 215         BANIAS(1300),
 216         BANIAS(1400),
 217         BANIAS(1500),
 218         BANIAS(1600),
 219         BANIAS(1700),
 220
 221         /* NULL model_name is a wildcard */
 222         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 223         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 224         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 225         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 226         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 227
 228         { NULL, }
 229 };
 230 #undef _BANIAS
 231 #undef BANIAS
 232
 233 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 234 {
 235         struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
 236         struct cpu_model *model;
 237
 238         for(model = models; model->cpu_id != NULL; model++)
 239                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 240                     (model->model_name == NULL ||
 241                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 242                         break;
 243
 244         if (model->cpu_id == NULL) {
 245                 /* No match at all */
 246                 dprintk("no support for CPU model \"%s\": "
 247                        "send /proc/cpuinfo to " MAINTAINER "\n",
 248                        cpu->x86_model_id);
 249                 return -ENOENT;
 250         }
 251
 252         if (model->op_points == NULL) {
 253                 /* Matched a non-match */
 254                 dprintk("no table support for CPU model \"%s\"\n",
 255                        cpu->x86_model_id);
 256                 dprintk("try using the acpi-cpufreq driver\n");
 257                 return -ENOENT;
 258         }
 259
 260         per_cpu(centrino_model, policy->cpu) = model;
 261
 262         dprintk("found \"%s\": max frequency: %dkHz\n",
 263                model->model_name, model->max_freq);
 264
 265         return 0;
 266 }
 267
 268 #else
 269 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
 270 {
 271         return -ENODEV;
 272 }
 273 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 274
 275 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
 276                                   const struct cpu_id *x)
 277 {
 278         if ((c->x86 == x->x86) &&
 279             (c->x86_model == x->x86_model) &&
 280             (c->x86_mask == x->x86_mask))
 281                 return 1;
 282         return 0;
 283 }
 284
 285 /* To be called only after centrino_model is initialized */
 286 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 287 {
 288         int i;
 289
 290         /*
 291          * Extract clock in kHz from PERF_CTL value
 292          * for centrino, as some DSDTs are buggy.
 293          * Ideally, this can be done using the acpi_data structure.
 294          */
 295         if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
 296             (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
 297             (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
 298                 msr = (msr >> 8) & 0xff;
 299                 return msr * 100000;
 300         }
 301
 302         if ((!per_cpu(centrino_model, cpu)) ||
 303             (!per_cpu(centrino_model, cpu)->op_points))
 304                 return 0;
 305
 306         msr &= 0xffff;
 307         for (i = 0;
 308                 per_cpu(centrino_model, cpu)->op_points[i].frequency
 309                                                         != CPUFREQ_TABLE_END;
 310              i++) {
 311                 if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
 312                         return per_cpu(centrino_model, cpu)->
 313                                                         op_points[i].frequency;
 314         }
 315         if (failsafe)
 316                 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
 317         else
 318                 return 0;
 319 }
 320
 321 /* Return the current CPU frequency in kHz */
 322 static unsigned int get_cur_freq(unsigned int cpu)
 323 {
 324         unsigned l, h;
 325         unsigned clock_freq;
 326         cpumask_t saved_mask;
 327         cpumask_of_cpu_ptr(new_mask, cpu);
 328
 329         saved_mask = current->cpus_allowed;
 330         set_cpus_allowed_ptr(current, new_mask);
 331         if (smp_processor_id() != cpu)
 332                 return 0;
 333
 334         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 335         clock_freq = extract_clock(l, cpu, 0);
 336
 337         if (unlikely(clock_freq == 0)) {
 338                 /*
 339                  * On some CPUs, we can see transient MSR values (which are
 340                  * not present in _PSS), while CPU is doing some automatic
 341                  * P-state transition (like TM2). Get the last freq set
 342                  * in PERF_CTL.
 343                  */
 344                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 345                 clock_freq = extract_clock(l, cpu, 1);
 346         }
 347
 348         set_cpus_allowed_ptr(current, &saved_mask);
 349         return clock_freq;
 350 }
 351
 352
 353 static int centrino_cpu_init(struct cpufreq_policy *policy)
 354 {
 355         struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
 356         unsigned freq;
 357         unsigned l, h;
 358         int ret;
 359         int i;
 360
 361         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 362         if (cpu->x86_vendor != X86_VENDOR_INTEL ||
 363             !cpu_has(cpu, X86_FEATURE_EST))
 364                 return -ENODEV;
 365
 366         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
 367                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 368
 369         if (policy->cpu != 0)
 370                 return -ENODEV;
 371
 372         for (i = 0; i < N_IDS; i++)
 373                 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 374                         break;
 375
 376         if (i != N_IDS)
 377                 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
 378
 379         if (!per_cpu(centrino_cpu, policy->cpu)) {
 380                 dprintk("found unsupported CPU with "
 381                 "Enhanced SpeedStep: send /proc/cpuinfo to "
 382                 MAINTAINER "\n");
 383                 return -ENODEV;
 384         }
 385
 386         if (centrino_cpu_init_table(policy)) {
 387                 return -ENODEV;
 388         }
 389
 390         /* Check to see if Enhanced SpeedStep is enabled, and try to
 391            enable it if not. */
 392         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 393
 394         if (!(l & (1<<16))) {
 395                 l |= (1<<16);
 396                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 397                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 398
 399                 /* check to see if it stuck */
 400                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 401                 if (!(l & (1<<16))) {
 402                         printk(KERN_INFO PFX
 403                                 "couldn't enable Enhanced SpeedStep\n");
 404                         return -ENODEV;
 405                 }
 406         }
 407
 408         freq = get_cur_freq(policy->cpu);
 409         policy->cpuinfo.transition_latency = 10000;
 410                                                 /* 10uS transition latency */
 411         policy->cur = freq;
 412
 413         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 414
 415         ret = cpufreq_frequency_table_cpuinfo(policy,
 416                 per_cpu(centrino_model, policy->cpu)->op_points);
 417         if (ret)
 418                 return (ret);
 419
 420         cpufreq_frequency_table_get_attr(
 421                 per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
 422
 423         return 0;
 424 }
 425
 426 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 427 {
 428         unsigned int cpu = policy->cpu;
 429
 430         if (!per_cpu(centrino_model, cpu))
 431                 return -ENODEV;
 432
 433         cpufreq_frequency_table_put_attr(cpu);
 434
 435         per_cpu(centrino_model, cpu) = NULL;
 436
 437         return 0;
 438 }
 439
 440 /**
 441  * centrino_verify - verifies a new CPUFreq policy
 442  * @policy: new policy
 443  *
 444  * Limit must be within this model's frequency range at least one
 445  * border included.
 446  */
 447 static int centrino_verify (struct cpufreq_policy *policy)
 448 {
 449         return cpufreq_frequency_table_verify(policy,
 450                         per_cpu(centrino_model, policy->cpu)->op_points);
 451 }
 452
 453 /**
 454  * centrino_setpolicy - set a new CPUFreq policy
 455  * @policy: new policy
 456  * @target_freq: the target frequency
 457  * @relation: how that frequency relates to achieved frequency
 458  *      (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 459  *
 460  * Sets a new CPUFreq policy.
 461  */
 462 struct allmasks {
 463         cpumask_t               online_policy_cpus;
 464         cpumask_t               saved_mask;
 465         cpumask_t               set_mask;
 466         cpumask_t               covered_cpus;
 467 };
 468
 469 static int centrino_target (struct cpufreq_policy *policy,
 470                             unsigned int target_freq,
 471                             unsigned int relation)
 472 {
 473         unsigned int    newstate = 0;
 474         unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
 475         struct cpufreq_freqs    freqs;
 476         int                     retval = 0;
 477         unsigned int            j, k, first_cpu, tmp;
 478         CPUMASK_ALLOC(allmasks);
 479         CPUMASK_PTR(online_policy_cpus, allmasks);
 480         CPUMASK_PTR(saved_mask, allmasks);
 481         CPUMASK_PTR(set_mask, allmasks);
 482         CPUMASK_PTR(covered_cpus, allmasks);
 483
 484         if (unlikely(allmasks == NULL))
 485                 return -ENOMEM;
 486
 487         if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
 488                 retval = -ENODEV;
 489                 goto out;
 490         }
 491
 492         if (unlikely(cpufreq_frequency_table_target(policy,
 493                         per_cpu(centrino_model, cpu)->op_points,
 494                         target_freq,
 495                         relation,
 496                         &newstate))) {
 497                 retval = -EINVAL;
 498                 goto out;
 499         }
 500
 501 #ifdef CONFIG_HOTPLUG_CPU
 502         /* cpufreq holds the hotplug lock, so we are safe from here on */
 503         cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
 504 #else
 505         *online_policy_cpus = policy->cpus;
 506 #endif
 507
 508         *saved_mask = current->cpus_allowed;
 509         first_cpu = 1;
 510         cpus_clear(*covered_cpus);
 511         for_each_cpu_mask_nr(j, *online_policy_cpus) {
 512                 /*
 513                  * Support for SMP systems.
 514                  * Make sure we are running on CPU that wants to change freq
 515                  */
 516                 cpus_clear(*set_mask);
 517                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 518                         cpus_or(*set_mask, *set_mask, *online_policy_cpus);
 519                 else
 520                         cpu_set(j, *set_mask);
 521
 522                 set_cpus_allowed_ptr(current, set_mask);
 523                 preempt_disable();
 524                 if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
 525                         dprintk("couldn't limit to CPUs in this domain\n");
 526                         retval = -EAGAIN;
 527                         if (first_cpu) {
 528                                 /* We haven't started the transition yet. */
 529                                 goto migrate_end;
 530                         }
 531                         preempt_enable();
 532                         break;
 533                 }
 534
 535                 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
 536
 537                 if (first_cpu) {
 538                         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 539                         if (msr == (oldmsr & 0xffff)) {
 540                                 dprintk("no change needed - msr was and needs "
 541                                         "to be %x\n", oldmsr);
 542                                 retval = 0;
 543                                 goto migrate_end;
 544                         }
 545
 546                         freqs.old = extract_clock(oldmsr, cpu, 0);
 547                         freqs.new = extract_clock(msr, cpu, 0);
 548
 549                         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 550                                 target_freq, freqs.old, freqs.new, msr);
 551
 552                         for_each_cpu_mask_nr(k, *online_policy_cpus) {
 553                                 freqs.cpu = k;
 554                                 cpufreq_notify_transition(&freqs,
 555                                         CPUFREQ_PRECHANGE);
 556                         }
 557
 558                         first_cpu = 0;
 559                         /* all but 16 LSB are reserved, treat them with care */
 560                         oldmsr &= ~0xffff;
 561                         msr &= 0xffff;
 562                         oldmsr |= msr;
 563                 }
 564
 565                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 566                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
 567                         preempt_enable();
 568                         break;
 569                 }
 570
 571                 cpu_set(j, *covered_cpus);
 572                 preempt_enable();
 573         }
 574
 575         for_each_cpu_mask_nr(k, *online_policy_cpus) {
 576                 freqs.cpu = k;
 577                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 578         }
 579
 580         if (unlikely(retval)) {
 581                 /*
 582                  * We have failed halfway through the frequency change.
 583                  * We have sent callbacks to policy->cpus and
 584                  * MSRs have already been written on coverd_cpus.
 585                  * Best effort undo..
 586                  */
 587
 588                 if (!cpus_empty(*covered_cpus)) {
 589                         cpumask_of_cpu_ptr_declare(new_mask);
 590
 591                         for_each_cpu_mask_nr(j, *covered_cpus) {
 592                                 cpumask_of_cpu_ptr_next(new_mask, j);
 593                                 set_cpus_allowed_ptr(current, new_mask);
 594                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 595                         }
 596                 }
 597
 598                 tmp = freqs.new;
 599                 freqs.new = freqs.old;
 600                 freqs.old = tmp;
 601                 for_each_cpu_mask_nr(j, *online_policy_cpus) {
 602                         freqs.cpu = j;
 603                         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 604                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 605                 }
 606         }
 607         set_cpus_allowed_ptr(current, saved_mask);
 608         retval = 0;
 609         goto out;
 610
 611 migrate_end:
 612         preempt_enable();
 613         set_cpus_allowed_ptr(current, saved_mask);
 614 out:
 615         CPUMASK_FREE(allmasks);
 616         return retval;
 617 }
 618
 619 static struct freq_attr* centrino_attr[] = {
 620         &cpufreq_freq_attr_scaling_available_freqs,
 621         NULL,
 622 };
 623
 624 static struct cpufreq_driver centrino_driver = {
 625         .name           = "centrino", /* should be speedstep-centrino,
 626                                          but there's a 16 char limit */
 627         .init           = centrino_cpu_init,
 628         .exit           = centrino_cpu_exit,
 629         .verify         = centrino_verify,
 630         .target         = centrino_target,
 631         .get            = get_cur_freq,
 632         .attr           = centrino_attr,
 633         .owner          = THIS_MODULE,
 634 };
 635
 636
 637 /**
 638  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 639  *
 640  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 641  * unsupported devices, -ENOENT if there's no voltage table for this
 642  * particular CPU model, -EINVAL on problems during initiatization,
 643  * and zero on success.
 644  *
 645  * This is quite picky.  Not only does the CPU have to advertise the
 646  * "est" flag in the cpuid capability flags, we look for a specific
 647  * CPU model and stepping, and we need to have the exact model name in
 648  * our voltage tables.  That is, be paranoid about not releasing
 649  * someone's valuable magic smoke.
 650  */
 651 static int __init centrino_init(void)
 652 {
 653         struct cpuinfo_x86 *cpu = &cpu_data(0);
 654
 655         if (!cpu_has(cpu, X86_FEATURE_EST))
 656                 return -ENODEV;
 657
 658         return cpufreq_register_driver(&centrino_driver);
 659 }
 660
 661 static void __exit centrino_exit(void)
 662 {
 663         cpufreq_unregister_driver(&centrino_driver);
 664 }
 665
 666 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 667 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 668 MODULE_LICENSE ("GPL");
 669
 670 late_initcall(centrino_init);
 671 module_exit(centrino_exit);