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[SCSI] qla2xxx: Proper cleanup of pass through commands when firmware returns error.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_os.c
blobc9a74521b402f9f1b7b755e80be9ee24cf1cd95b
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16
17 #include <scsi/scsi_tcq.h>
18 #include <scsi/scsicam.h>
19 #include <scsi/scsi_transport.h>
20 #include <scsi/scsi_transport_fc.h>
21
22 /*
23 * Driver version
24 */
25 char qla2x00_version_str[40];
26
27 static int apidev_major;
28
29 /*
30 * SRB allocation cache
31 */
32 static struct kmem_cache *srb_cachep;
33
34 /*
35 * CT6 CTX allocation cache
36 */
37 static struct kmem_cache *ctx_cachep;
38 /*
39 * error level for logging
40 */
41 int ql_errlev = ql_log_all;
42
43 int ql2xlogintimeout = 20;
44 module_param(ql2xlogintimeout, int, S_IRUGO);
45 MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
48 int qlport_down_retry;
49 module_param(qlport_down_retry, int, S_IRUGO);
50 MODULE_PARM_DESC(qlport_down_retry,
51 "Maximum number of command retries to a port that returns "
52 "a PORT-DOWN status.");
53
54 int ql2xplogiabsentdevice;
55 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56 MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
58 "a Fabric scan. This is needed for several broken switches. "
59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
61 int ql2xloginretrycount = 0;
62 module_param(ql2xloginretrycount, int, S_IRUGO);
63 MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
66 int ql2xallocfwdump = 1;
67 module_param(ql2xallocfwdump, int, S_IRUGO);
68 MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
73 int ql2xextended_error_logging;
74 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
75 MODULE_PARM_DESC(ql2xextended_error_logging,
76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\t0x1e400000 - Preferred value for capturing essential "
87 "debug information (equivalent to old "
88 "ql2xextended_error_logging=1).\n"
89 "\t\tDo LOGICAL OR of the value to enable more than one level");
90
91 int ql2xshiftctondsd = 6;
92 module_param(ql2xshiftctondsd, int, S_IRUGO);
93 MODULE_PARM_DESC(ql2xshiftctondsd,
94 "Set to control shifting of command type processing "
95 "based on total number of SG elements.");
96
97 static void qla2x00_free_device(scsi_qla_host_t *);
98
99 int ql2xfdmienable=1;
100 module_param(ql2xfdmienable, int, S_IRUGO);
101 MODULE_PARM_DESC(ql2xfdmienable,
102 "Enables FDMI registrations. "
103 "0 - no FDMI. Default is 1 - perform FDMI.");
104
105 #define MAX_Q_DEPTH 32
106 static int ql2xmaxqdepth = MAX_Q_DEPTH;
107 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(ql2xmaxqdepth,
109 "Maximum queue depth to report for target devices.");
110
111 /* Do not change the value of this after module load */
112 int ql2xenabledif = 0;
113 module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
114 MODULE_PARM_DESC(ql2xenabledif,
115 " Enable T10-CRC-DIF "
116 " Default is 0 - No DIF Support. 1 - Enable it"
117 ", 2 - Enable DIF for all types, except Type 0.");
118
119 int ql2xenablehba_err_chk = 2;
120 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
121 MODULE_PARM_DESC(ql2xenablehba_err_chk,
122 " Enable T10-CRC-DIF Error isolation by HBA:\n"
123 " Default is 1.\n"
124 " 0 -- Error isolation disabled\n"
125 " 1 -- Error isolation enabled only for DIX Type 0\n"
126 " 2 -- Error isolation enabled for all Types\n");
127
128 int ql2xiidmaenable=1;
129 module_param(ql2xiidmaenable, int, S_IRUGO);
130 MODULE_PARM_DESC(ql2xiidmaenable,
131 "Enables iIDMA settings "
132 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
133
134 int ql2xmaxqueues = 1;
135 module_param(ql2xmaxqueues, int, S_IRUGO);
136 MODULE_PARM_DESC(ql2xmaxqueues,
137 "Enables MQ settings "
138 "Default is 1 for single queue. Set it to number "
139 "of queues in MQ mode.");
140
141 int ql2xmultique_tag;
142 module_param(ql2xmultique_tag, int, S_IRUGO);
143 MODULE_PARM_DESC(ql2xmultique_tag,
144 "Enables CPU affinity settings for the driver "
145 "Default is 0 for no affinity of request and response IO. "
146 "Set it to 1 to turn on the cpu affinity.");
147
148 int ql2xfwloadbin;
149 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
150 MODULE_PARM_DESC(ql2xfwloadbin,
151 "Option to specify location from which to load ISP firmware:.\n"
152 " 2 -- load firmware via the request_firmware() (hotplug).\n"
153 " interface.\n"
154 " 1 -- load firmware from flash.\n"
155 " 0 -- use default semantics.\n");
156
157 int ql2xetsenable;
158 module_param(ql2xetsenable, int, S_IRUGO);
159 MODULE_PARM_DESC(ql2xetsenable,
160 "Enables firmware ETS burst."
161 "Default is 0 - skip ETS enablement.");
162
163 int ql2xdbwr = 1;
164 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
165 MODULE_PARM_DESC(ql2xdbwr,
166 "Option to specify scheme for request queue posting.\n"
167 " 0 -- Regular doorbell.\n"
168 " 1 -- CAMRAM doorbell (faster).\n");
169
170 int ql2xtargetreset = 1;
171 module_param(ql2xtargetreset, int, S_IRUGO);
172 MODULE_PARM_DESC(ql2xtargetreset,
173 "Enable target reset."
174 "Default is 1 - use hw defaults.");
175
176 int ql2xgffidenable;
177 module_param(ql2xgffidenable, int, S_IRUGO);
178 MODULE_PARM_DESC(ql2xgffidenable,
179 "Enables GFF_ID checks of port type. "
180 "Default is 0 - Do not use GFF_ID information.");
181
182 int ql2xasynctmfenable;
183 module_param(ql2xasynctmfenable, int, S_IRUGO);
184 MODULE_PARM_DESC(ql2xasynctmfenable,
185 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
186 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
187
188 int ql2xdontresethba;
189 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
190 MODULE_PARM_DESC(ql2xdontresethba,
191 "Option to specify reset behaviour.\n"
192 " 0 (Default) -- Reset on failure.\n"
193 " 1 -- Do not reset on failure.\n");
194
195 uint ql2xmaxlun = MAX_LUNS;
196 module_param(ql2xmaxlun, uint, S_IRUGO);
197 MODULE_PARM_DESC(ql2xmaxlun,
198 "Defines the maximum LU number to register with the SCSI "
199 "midlayer. Default is 65535.");
200
201 int ql2xmdcapmask = 0x1F;
202 module_param(ql2xmdcapmask, int, S_IRUGO);
203 MODULE_PARM_DESC(ql2xmdcapmask,
204 "Set the Minidump driver capture mask level. "
205 "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
206
207 int ql2xmdenable = 1;
208 module_param(ql2xmdenable, int, S_IRUGO);
209 MODULE_PARM_DESC(ql2xmdenable,
210 "Enable/disable MiniDump. "
211 "0 - MiniDump disabled. "
212 "1 (Default) - MiniDump enabled.");
213
214 /*
215 * SCSI host template entry points
216 */
217 static int qla2xxx_slave_configure(struct scsi_device * device);
218 static int qla2xxx_slave_alloc(struct scsi_device *);
219 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
220 static void qla2xxx_scan_start(struct Scsi_Host *);
221 static void qla2xxx_slave_destroy(struct scsi_device *);
222 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
223 static int qla2xxx_eh_abort(struct scsi_cmnd *);
224 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
225 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
226 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
227 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
228
229 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
230 static int qla2x00_change_queue_type(struct scsi_device *, int);
231
232 struct scsi_host_template qla2xxx_driver_template = {
233 .module = THIS_MODULE,
234 .name = QLA2XXX_DRIVER_NAME,
235 .queuecommand = qla2xxx_queuecommand,
236
237 .eh_abort_handler = qla2xxx_eh_abort,
238 .eh_device_reset_handler = qla2xxx_eh_device_reset,
239 .eh_target_reset_handler = qla2xxx_eh_target_reset,
240 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
241 .eh_host_reset_handler = qla2xxx_eh_host_reset,
242
243 .slave_configure = qla2xxx_slave_configure,
244
245 .slave_alloc = qla2xxx_slave_alloc,
246 .slave_destroy = qla2xxx_slave_destroy,
247 .scan_finished = qla2xxx_scan_finished,
248 .scan_start = qla2xxx_scan_start,
249 .change_queue_depth = qla2x00_change_queue_depth,
250 .change_queue_type = qla2x00_change_queue_type,
251 .this_id = -1,
252 .cmd_per_lun = 3,
253 .use_clustering = ENABLE_CLUSTERING,
254 .sg_tablesize = SG_ALL,
255
256 .max_sectors = 0xFFFF,
257 .shost_attrs = qla2x00_host_attrs,
258 };
259
260 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
261 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
262
263 /* TODO Convert to inlines
264 *
265 * Timer routines
266 */
267
268 __inline__ void
269 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
270 {
271 init_timer(&vha->timer);
272 vha->timer.expires = jiffies + interval * HZ;
273 vha->timer.data = (unsigned long)vha;
274 vha->timer.function = (void (*)(unsigned long))func;
275 add_timer(&vha->timer);
276 vha->timer_active = 1;
277 }
278
279 static inline void
280 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
281 {
282 /* Currently used for 82XX only. */
283 if (vha->device_flags & DFLG_DEV_FAILED) {
284 ql_dbg(ql_dbg_timer, vha, 0x600d,
285 "Device in a failed state, returning.\n");
286 return;
287 }
288
289 mod_timer(&vha->timer, jiffies + interval * HZ);
290 }
291
292 static __inline__ void
293 qla2x00_stop_timer(scsi_qla_host_t *vha)
294 {
295 del_timer_sync(&vha->timer);
296 vha->timer_active = 0;
297 }
298
299 static int qla2x00_do_dpc(void *data);
300
301 static void qla2x00_rst_aen(scsi_qla_host_t *);
302
303 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
304 struct req_que **, struct rsp_que **);
305 static void qla2x00_free_fw_dump(struct qla_hw_data *);
306 static void qla2x00_mem_free(struct qla_hw_data *);
307 static void qla2x00_sp_free_dma(srb_t *);
308
309 /* -------------------------------------------------------------------------- */
310 static int qla2x00_alloc_queues(struct qla_hw_data *ha)
311 {
312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
314 GFP_KERNEL);
315 if (!ha->req_q_map) {
316 ql_log(ql_log_fatal, vha, 0x003b,
317 "Unable to allocate memory for request queue ptrs.\n");
318 goto fail_req_map;
319 }
320
321 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
322 GFP_KERNEL);
323 if (!ha->rsp_q_map) {
324 ql_log(ql_log_fatal, vha, 0x003c,
325 "Unable to allocate memory for response queue ptrs.\n");
326 goto fail_rsp_map;
327 }
328 set_bit(0, ha->rsp_qid_map);
329 set_bit(0, ha->req_qid_map);
330 return 1;
331
332 fail_rsp_map:
333 kfree(ha->req_q_map);
334 ha->req_q_map = NULL;
335 fail_req_map:
336 return -ENOMEM;
337 }
338
339 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
340 {
341 if (req && req->ring)
342 dma_free_coherent(&ha->pdev->dev,
343 (req->length + 1) * sizeof(request_t),
344 req->ring, req->dma);
345
346 kfree(req);
347 req = NULL;
348 }
349
350 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
351 {
352 if (rsp && rsp->ring)
353 dma_free_coherent(&ha->pdev->dev,
354 (rsp->length + 1) * sizeof(response_t),
355 rsp->ring, rsp->dma);
356
357 kfree(rsp);
358 rsp = NULL;
359 }
360
361 static void qla2x00_free_queues(struct qla_hw_data *ha)
362 {
363 struct req_que *req;
364 struct rsp_que *rsp;
365 int cnt;
366
367 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
368 req = ha->req_q_map[cnt];
369 qla2x00_free_req_que(ha, req);
370 }
371 kfree(ha->req_q_map);
372 ha->req_q_map = NULL;
373
374 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
375 rsp = ha->rsp_q_map[cnt];
376 qla2x00_free_rsp_que(ha, rsp);
377 }
378 kfree(ha->rsp_q_map);
379 ha->rsp_q_map = NULL;
380 }
381
382 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
383 {
384 uint16_t options = 0;
385 int ques, req, ret;
386 struct qla_hw_data *ha = vha->hw;
387
388 if (!(ha->fw_attributes & BIT_6)) {
389 ql_log(ql_log_warn, vha, 0x00d8,
390 "Firmware is not multi-queue capable.\n");
391 goto fail;
392 }
393 if (ql2xmultique_tag) {
394 /* create a request queue for IO */
395 options |= BIT_7;
396 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
397 QLA_DEFAULT_QUE_QOS);
398 if (!req) {
399 ql_log(ql_log_warn, vha, 0x00e0,
400 "Failed to create request queue.\n");
401 goto fail;
402 }
403 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
404 vha->req = ha->req_q_map[req];
405 options |= BIT_1;
406 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
407 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
408 if (!ret) {
409 ql_log(ql_log_warn, vha, 0x00e8,
410 "Failed to create response queue.\n");
411 goto fail2;
412 }
413 }
414 ha->flags.cpu_affinity_enabled = 1;
415 ql_dbg(ql_dbg_multiq, vha, 0xc007,
416 "CPU affinity mode enalbed, "
417 "no. of response queues:%d no. of request queues:%d.\n",
418 ha->max_rsp_queues, ha->max_req_queues);
419 ql_dbg(ql_dbg_init, vha, 0x00e9,
420 "CPU affinity mode enalbed, "
421 "no. of response queues:%d no. of request queues:%d.\n",
422 ha->max_rsp_queues, ha->max_req_queues);
423 }
424 return 0;
425 fail2:
426 qla25xx_delete_queues(vha);
427 destroy_workqueue(ha->wq);
428 ha->wq = NULL;
429 vha->req = ha->req_q_map[0];
430 fail:
431 ha->mqenable = 0;
432 kfree(ha->req_q_map);
433 kfree(ha->rsp_q_map);
434 ha->max_req_queues = ha->max_rsp_queues = 1;
435 return 1;
436 }
437
438 static char *
439 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
440 {
441 struct qla_hw_data *ha = vha->hw;
442 static char *pci_bus_modes[] = {
443 "33", "66", "100", "133",
444 };
445 uint16_t pci_bus;
446
447 strcpy(str, "PCI");
448 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
449 if (pci_bus) {
450 strcat(str, "-X (");
451 strcat(str, pci_bus_modes[pci_bus]);
452 } else {
453 pci_bus = (ha->pci_attr & BIT_8) >> 8;
454 strcat(str, " (");
455 strcat(str, pci_bus_modes[pci_bus]);
456 }
457 strcat(str, " MHz)");
458
459 return (str);
460 }
461
462 static char *
463 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
464 {
465 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
466 struct qla_hw_data *ha = vha->hw;
467 uint32_t pci_bus;
468 int pcie_reg;
469
470 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
471 if (pcie_reg) {
472 char lwstr[6];
473 uint16_t pcie_lstat, lspeed, lwidth;
474
475 pcie_reg += 0x12;
476 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
477 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
478 lwidth = (pcie_lstat &
479 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
480
481 strcpy(str, "PCIe (");
482 if (lspeed == 1)
483 strcat(str, "2.5GT/s ");
484 else if (lspeed == 2)
485 strcat(str, "5.0GT/s ");
486 else
487 strcat(str, "<unknown> ");
488 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
489 strcat(str, lwstr);
490
491 return str;
492 }
493
494 strcpy(str, "PCI");
495 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
496 if (pci_bus == 0 || pci_bus == 8) {
497 strcat(str, " (");
498 strcat(str, pci_bus_modes[pci_bus >> 3]);
499 } else {
500 strcat(str, "-X ");
501 if (pci_bus & BIT_2)
502 strcat(str, "Mode 2");
503 else
504 strcat(str, "Mode 1");
505 strcat(str, " (");
506 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
507 }
508 strcat(str, " MHz)");
509
510 return str;
511 }
512
513 static char *
514 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
515 {
516 char un_str[10];
517 struct qla_hw_data *ha = vha->hw;
518
519 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
520 ha->fw_minor_version,
521 ha->fw_subminor_version);
522
523 if (ha->fw_attributes & BIT_9) {
524 strcat(str, "FLX");
525 return (str);
526 }
527
528 switch (ha->fw_attributes & 0xFF) {
529 case 0x7:
530 strcat(str, "EF");
531 break;
532 case 0x17:
533 strcat(str, "TP");
534 break;
535 case 0x37:
536 strcat(str, "IP");
537 break;
538 case 0x77:
539 strcat(str, "VI");
540 break;
541 default:
542 sprintf(un_str, "(%x)", ha->fw_attributes);
543 strcat(str, un_str);
544 break;
545 }
546 if (ha->fw_attributes & 0x100)
547 strcat(str, "X");
548
549 return (str);
550 }
551
552 static char *
553 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
554 {
555 struct qla_hw_data *ha = vha->hw;
556
557 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
558 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
559 return str;
560 }
561
562 static inline srb_t *
563 qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
564 struct scsi_cmnd *cmd)
565 {
566 srb_t *sp;
567 struct qla_hw_data *ha = vha->hw;
568
569 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
570 if (!sp) {
571 ql_log(ql_log_warn, vha, 0x3006,
572 "Memory allocation failed for sp.\n");
573 return sp;
574 }
575
576 atomic_set(&sp->ref_count, 1);
577 sp->fcport = fcport;
578 sp->cmd = cmd;
579 sp->flags = 0;
580 CMD_SP(cmd) = (void *)sp;
581 sp->ctx = NULL;
582
583 return sp;
584 }
585
586 static int
587 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
588 {
589 scsi_qla_host_t *vha = shost_priv(host);
590 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
591 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
592 struct qla_hw_data *ha = vha->hw;
593 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
594 srb_t *sp;
595 int rval;
596
597 if (ha->flags.eeh_busy) {
598 if (ha->flags.pci_channel_io_perm_failure) {
599 ql_dbg(ql_dbg_io, vha, 0x3001,
600 "PCI Channel IO permanent failure, exiting "
601 "cmd=%p.\n", cmd);
602 cmd->result = DID_NO_CONNECT << 16;
603 } else {
604 ql_dbg(ql_dbg_io, vha, 0x3002,
605 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
606 cmd->result = DID_REQUEUE << 16;
607 }
608 goto qc24_fail_command;
609 }
610
611 rval = fc_remote_port_chkready(rport);
612 if (rval) {
613 cmd->result = rval;
614 ql_dbg(ql_dbg_io, vha, 0x3003,
615 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
616 cmd, rval);
617 goto qc24_fail_command;
618 }
619
620 if (!vha->flags.difdix_supported &&
621 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
622 ql_dbg(ql_dbg_io, vha, 0x3004,
623 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
624 cmd);
625 cmd->result = DID_NO_CONNECT << 16;
626 goto qc24_fail_command;
627 }
628 if (atomic_read(&fcport->state) != FCS_ONLINE) {
629 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
630 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
631 ql_dbg(ql_dbg_io, vha, 0x3005,
632 "Returning DNC, fcport_state=%d loop_state=%d.\n",
633 atomic_read(&fcport->state),
634 atomic_read(&base_vha->loop_state));
635 cmd->result = DID_NO_CONNECT << 16;
636 goto qc24_fail_command;
637 }
638 goto qc24_target_busy;
639 }
640
641 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
642 if (!sp)
643 goto qc24_host_busy;
644
645 rval = ha->isp_ops->start_scsi(sp);
646 if (rval != QLA_SUCCESS) {
647 ql_dbg(ql_dbg_io, vha, 0x3013,
648 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
649 goto qc24_host_busy_free_sp;
650 }
651
652 return 0;
653
654 qc24_host_busy_free_sp:
655 qla2x00_sp_free_dma(sp);
656 mempool_free(sp, ha->srb_mempool);
657
658 qc24_host_busy:
659 return SCSI_MLQUEUE_HOST_BUSY;
660
661 qc24_target_busy:
662 return SCSI_MLQUEUE_TARGET_BUSY;
663
664 qc24_fail_command:
665 cmd->scsi_done(cmd);
666
667 return 0;
668 }
669
670 /*
671 * qla2x00_eh_wait_on_command
672 * Waits for the command to be returned by the Firmware for some
673 * max time.
674 *
675 * Input:
676 * cmd = Scsi Command to wait on.
677 *
678 * Return:
679 * Not Found : 0
680 * Found : 1
681 */
682 static int
683 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
684 {
685 #define ABORT_POLLING_PERIOD 1000
686 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
687 unsigned long wait_iter = ABORT_WAIT_ITER;
688 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
689 struct qla_hw_data *ha = vha->hw;
690 int ret = QLA_SUCCESS;
691
692 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
693 ql_dbg(ql_dbg_taskm, vha, 0x8005,
694 "Return:eh_wait.\n");
695 return ret;
696 }
697
698 while (CMD_SP(cmd) && wait_iter--) {
699 msleep(ABORT_POLLING_PERIOD);
700 }
701 if (CMD_SP(cmd))
702 ret = QLA_FUNCTION_FAILED;
703
704 return ret;
705 }
706
707 /*
708 * qla2x00_wait_for_hba_online
709 * Wait till the HBA is online after going through
710 * <= MAX_RETRIES_OF_ISP_ABORT or
711 * finally HBA is disabled ie marked offline
712 *
713 * Input:
714 * ha - pointer to host adapter structure
715 *
716 * Note:
717 * Does context switching-Release SPIN_LOCK
718 * (if any) before calling this routine.
719 *
720 * Return:
721 * Success (Adapter is online) : 0
722 * Failed (Adapter is offline/disabled) : 1
723 */
724 int
725 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
726 {
727 int return_status;
728 unsigned long wait_online;
729 struct qla_hw_data *ha = vha->hw;
730 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
731
732 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
733 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
734 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
735 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
736 ha->dpc_active) && time_before(jiffies, wait_online)) {
737
738 msleep(1000);
739 }
740 if (base_vha->flags.online)
741 return_status = QLA_SUCCESS;
742 else
743 return_status = QLA_FUNCTION_FAILED;
744
745 return (return_status);
746 }
747
748 /*
749 * qla2x00_wait_for_reset_ready
750 * Wait till the HBA is online after going through
751 * <= MAX_RETRIES_OF_ISP_ABORT or
752 * finally HBA is disabled ie marked offline or flash
753 * operations are in progress.
754 *
755 * Input:
756 * ha - pointer to host adapter structure
757 *
758 * Note:
759 * Does context switching-Release SPIN_LOCK
760 * (if any) before calling this routine.
761 *
762 * Return:
763 * Success (Adapter is online/no flash ops) : 0
764 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
765 */
766 static int
767 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
768 {
769 int return_status;
770 unsigned long wait_online;
771 struct qla_hw_data *ha = vha->hw;
772 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
773
774 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
775 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
776 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
777 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
778 ha->optrom_state != QLA_SWAITING ||
779 ha->dpc_active) && time_before(jiffies, wait_online))
780 msleep(1000);
781
782 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
783 return_status = QLA_SUCCESS;
784 else
785 return_status = QLA_FUNCTION_FAILED;
786
787 ql_dbg(ql_dbg_taskm, vha, 0x8019,
788 "%s return status=%d.\n", __func__, return_status);
789
790 return return_status;
791 }
792
793 int
794 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
795 {
796 int return_status;
797 unsigned long wait_reset;
798 struct qla_hw_data *ha = vha->hw;
799 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
800
801 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
802 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
803 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
804 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
805 ha->dpc_active) && time_before(jiffies, wait_reset)) {
806
807 msleep(1000);
808
809 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
810 ha->flags.chip_reset_done)
811 break;
812 }
813 if (ha->flags.chip_reset_done)
814 return_status = QLA_SUCCESS;
815 else
816 return_status = QLA_FUNCTION_FAILED;
817
818 return return_status;
819 }
820
821 static void
822 sp_get(struct srb *sp)
823 {
824 atomic_inc(&sp->ref_count);
825 }
826
827 /**************************************************************************
828 * qla2xxx_eh_abort
829 *
830 * Description:
831 * The abort function will abort the specified command.
832 *
833 * Input:
834 * cmd = Linux SCSI command packet to be aborted.
835 *
836 * Returns:
837 * Either SUCCESS or FAILED.
838 *
839 * Note:
840 * Only return FAILED if command not returned by firmware.
841 **************************************************************************/
842 static int
843 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
844 {
845 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
846 srb_t *sp;
847 int ret;
848 unsigned int id, lun;
849 unsigned long flags;
850 int wait = 0;
851 struct qla_hw_data *ha = vha->hw;
852
853 if (!CMD_SP(cmd))
854 return SUCCESS;
855
856 ret = fc_block_scsi_eh(cmd);
857 if (ret != 0)
858 return ret;
859 ret = SUCCESS;
860
861 id = cmd->device->id;
862 lun = cmd->device->lun;
863
864 spin_lock_irqsave(&ha->hardware_lock, flags);
865 sp = (srb_t *) CMD_SP(cmd);
866 if (!sp) {
867 spin_unlock_irqrestore(&ha->hardware_lock, flags);
868 return SUCCESS;
869 }
870
871 ql_dbg(ql_dbg_taskm, vha, 0x8002,
872 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
873 vha->host_no, id, lun, sp, cmd);
874
875 /* Get a reference to the sp and drop the lock.*/
876 sp_get(sp);
877
878 spin_unlock_irqrestore(&ha->hardware_lock, flags);
879 if (ha->isp_ops->abort_command(sp)) {
880 ql_dbg(ql_dbg_taskm, vha, 0x8003,
881 "Abort command mbx failed cmd=%p.\n", cmd);
882 } else {
883 ql_dbg(ql_dbg_taskm, vha, 0x8004,
884 "Abort command mbx success cmd=%p.\n", cmd);
885 wait = 1;
886 }
887
888 spin_lock_irqsave(&ha->hardware_lock, flags);
889 qla2x00_sp_compl(ha, sp);
890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
891
892 /* Did the command return during mailbox execution? */
893 if (ret == FAILED && !CMD_SP(cmd))
894 ret = SUCCESS;
895
896 /* Wait for the command to be returned. */
897 if (wait) {
898 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
899 ql_log(ql_log_warn, vha, 0x8006,
900 "Abort handler timed out cmd=%p.\n", cmd);
901 ret = FAILED;
902 }
903 }
904
905 ql_log(ql_log_info, vha, 0x801c,
906 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
907 vha->host_no, id, lun, wait, ret);
908
909 return ret;
910 }
911
912 int
913 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
914 unsigned int l, enum nexus_wait_type type)
915 {
916 int cnt, match, status;
917 unsigned long flags;
918 struct qla_hw_data *ha = vha->hw;
919 struct req_que *req;
920 srb_t *sp;
921
922 status = QLA_SUCCESS;
923
924 spin_lock_irqsave(&ha->hardware_lock, flags);
925 req = vha->req;
926 for (cnt = 1; status == QLA_SUCCESS &&
927 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
928 sp = req->outstanding_cmds[cnt];
929 if (!sp)
930 continue;
931 if ((sp->ctx) && !IS_PROT_IO(sp))
932 continue;
933 if (vha->vp_idx != sp->fcport->vha->vp_idx)
934 continue;
935 match = 0;
936 switch (type) {
937 case WAIT_HOST:
938 match = 1;
939 break;
940 case WAIT_TARGET:
941 match = sp->cmd->device->id == t;
942 break;
943 case WAIT_LUN:
944 match = (sp->cmd->device->id == t &&
945 sp->cmd->device->lun == l);
946 break;
947 }
948 if (!match)
949 continue;
950
951 spin_unlock_irqrestore(&ha->hardware_lock, flags);
952 status = qla2x00_eh_wait_on_command(sp->cmd);
953 spin_lock_irqsave(&ha->hardware_lock, flags);
954 }
955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
956
957 return status;
958 }
959
960 static char *reset_errors[] = {
961 "HBA not online",
962 "HBA not ready",
963 "Task management failed",
964 "Waiting for command completions",
965 };
966
967 static int
968 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
969 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
970 {
971 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
972 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
973 int err;
974
975 if (!fcport) {
976 return FAILED;
977 }
978
979 err = fc_block_scsi_eh(cmd);
980 if (err != 0)
981 return err;
982
983 ql_log(ql_log_info, vha, 0x8009,
984 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
985 cmd->device->id, cmd->device->lun, cmd);
986
987 err = 0;
988 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
989 ql_log(ql_log_warn, vha, 0x800a,
990 "Wait for hba online failed for cmd=%p.\n", cmd);
991 goto eh_reset_failed;
992 }
993 err = 2;
994 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
995 != QLA_SUCCESS) {
996 ql_log(ql_log_warn, vha, 0x800c,
997 "do_reset failed for cmd=%p.\n", cmd);
998 goto eh_reset_failed;
999 }
1000 err = 3;
1001 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1002 cmd->device->lun, type) != QLA_SUCCESS) {
1003 ql_log(ql_log_warn, vha, 0x800d,
1004 "wait for peding cmds failed for cmd=%p.\n", cmd);
1005 goto eh_reset_failed;
1006 }
1007
1008 ql_log(ql_log_info, vha, 0x800e,
1009 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1010 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1011
1012 return SUCCESS;
1013
1014 eh_reset_failed:
1015 ql_log(ql_log_info, vha, 0x800f,
1016 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1017 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1018 cmd);
1019 return FAILED;
1020 }
1021
1022 static int
1023 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1024 {
1025 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1026 struct qla_hw_data *ha = vha->hw;
1027
1028 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1029 ha->isp_ops->lun_reset);
1030 }
1031
1032 static int
1033 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1034 {
1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1036 struct qla_hw_data *ha = vha->hw;
1037
1038 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1039 ha->isp_ops->target_reset);
1040 }
1041
1042 /**************************************************************************
1043 * qla2xxx_eh_bus_reset
1044 *
1045 * Description:
1046 * The bus reset function will reset the bus and abort any executing
1047 * commands.
1048 *
1049 * Input:
1050 * cmd = Linux SCSI command packet of the command that cause the
1051 * bus reset.
1052 *
1053 * Returns:
1054 * SUCCESS/FAILURE (defined as macro in scsi.h).
1055 *
1056 **************************************************************************/
1057 static int
1058 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1059 {
1060 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1061 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1062 int ret = FAILED;
1063 unsigned int id, lun;
1064
1065 id = cmd->device->id;
1066 lun = cmd->device->lun;
1067
1068 if (!fcport) {
1069 return ret;
1070 }
1071
1072 ret = fc_block_scsi_eh(cmd);
1073 if (ret != 0)
1074 return ret;
1075 ret = FAILED;
1076
1077 ql_log(ql_log_info, vha, 0x8012,
1078 "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun);
1079
1080 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1081 ql_log(ql_log_fatal, vha, 0x8013,
1082 "Wait for hba online failed board disabled.\n");
1083 goto eh_bus_reset_done;
1084 }
1085
1086 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1087 ret = SUCCESS;
1088
1089 if (ret == FAILED)
1090 goto eh_bus_reset_done;
1091
1092 /* Flush outstanding commands. */
1093 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1094 QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x8014,
1096 "Wait for pending commands failed.\n");
1097 ret = FAILED;
1098 }
1099
1100 eh_bus_reset_done:
1101 ql_log(ql_log_warn, vha, 0x802b,
1102 "BUS RESET %s nexus=%ld:%d:%d.\n",
1103 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun);
1104
1105 return ret;
1106 }
1107
1108 /**************************************************************************
1109 * qla2xxx_eh_host_reset
1110 *
1111 * Description:
1112 * The reset function will reset the Adapter.
1113 *
1114 * Input:
1115 * cmd = Linux SCSI command packet of the command that cause the
1116 * adapter reset.
1117 *
1118 * Returns:
1119 * Either SUCCESS or FAILED.
1120 *
1121 * Note:
1122 **************************************************************************/
1123 static int
1124 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1125 {
1126 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1127 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1128 struct qla_hw_data *ha = vha->hw;
1129 int ret = FAILED;
1130 unsigned int id, lun;
1131 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1132
1133 id = cmd->device->id;
1134 lun = cmd->device->lun;
1135
1136 if (!fcport) {
1137 return ret;
1138 }
1139
1140 ret = fc_block_scsi_eh(cmd);
1141 if (ret != 0)
1142 return ret;
1143 ret = FAILED;
1144
1145 ql_log(ql_log_info, vha, 0x8018,
1146 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1147
1148 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
1149 goto eh_host_reset_lock;
1150
1151 if (vha != base_vha) {
1152 if (qla2x00_vp_abort_isp(vha))
1153 goto eh_host_reset_lock;
1154 } else {
1155 if (IS_QLA82XX(vha->hw)) {
1156 if (!qla82xx_fcoe_ctx_reset(vha)) {
1157 /* Ctx reset success */
1158 ret = SUCCESS;
1159 goto eh_host_reset_lock;
1160 }
1161 /* fall thru if ctx reset failed */
1162 }
1163 if (ha->wq)
1164 flush_workqueue(ha->wq);
1165
1166 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1167 if (ha->isp_ops->abort_isp(base_vha)) {
1168 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1169 /* failed. schedule dpc to try */
1170 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1171
1172 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1173 ql_log(ql_log_warn, vha, 0x802a,
1174 "wait for hba online failed.\n");
1175 goto eh_host_reset_lock;
1176 }
1177 }
1178 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1179 }
1180
1181 /* Waiting for command to be returned to OS.*/
1182 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1183 QLA_SUCCESS)
1184 ret = SUCCESS;
1185
1186 eh_host_reset_lock:
1187 ql_log(ql_log_info, vha, 0x8017,
1188 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1189 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1190
1191 return ret;
1192 }
1193
1194 /*
1195 * qla2x00_loop_reset
1196 * Issue loop reset.
1197 *
1198 * Input:
1199 * ha = adapter block pointer.
1200 *
1201 * Returns:
1202 * 0 = success
1203 */
1204 int
1205 qla2x00_loop_reset(scsi_qla_host_t *vha)
1206 {
1207 int ret;
1208 struct fc_port *fcport;
1209 struct qla_hw_data *ha = vha->hw;
1210
1211 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1212 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1213 if (fcport->port_type != FCT_TARGET)
1214 continue;
1215
1216 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1217 if (ret != QLA_SUCCESS) {
1218 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1219 "Bus Reset failed: Target Reset=%d "
1220 "d_id=%x.\n", ret, fcport->d_id.b24);
1221 }
1222 }
1223 }
1224
1225 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
1226 ret = qla2x00_full_login_lip(vha);
1227 if (ret != QLA_SUCCESS) {
1228 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1229 "full_login_lip=%d.\n", ret);
1230 }
1231 atomic_set(&vha->loop_state, LOOP_DOWN);
1232 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1233 qla2x00_mark_all_devices_lost(vha, 0);
1234 }
1235
1236 if (ha->flags.enable_lip_reset) {
1237 ret = qla2x00_lip_reset(vha);
1238 if (ret != QLA_SUCCESS)
1239 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1240 "lip_reset failed (%d).\n", ret);
1241 }
1242
1243 /* Issue marker command only when we are going to start the I/O */
1244 vha->marker_needed = 1;
1245
1246 return QLA_SUCCESS;
1247 }
1248
1249 void
1250 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1251 {
1252 int que, cnt;
1253 unsigned long flags;
1254 srb_t *sp;
1255 struct srb_ctx *ctx;
1256 struct qla_hw_data *ha = vha->hw;
1257 struct req_que *req;
1258
1259 spin_lock_irqsave(&ha->hardware_lock, flags);
1260 for (que = 0; que < ha->max_req_queues; que++) {
1261 req = ha->req_q_map[que];
1262 if (!req)
1263 continue;
1264 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1265 sp = req->outstanding_cmds[cnt];
1266 if (sp) {
1267 req->outstanding_cmds[cnt] = NULL;
1268 if (!sp->ctx ||
1269 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1270 IS_PROT_IO(sp)) {
1271 sp->cmd->result = res;
1272 qla2x00_sp_compl(ha, sp);
1273 } else {
1274 ctx = sp->ctx;
1275 if (ctx->type == SRB_ELS_CMD_RPT ||
1276 ctx->type == SRB_ELS_CMD_HST ||
1277 ctx->type == SRB_CT_CMD) {
1278 struct fc_bsg_job *bsg_job =
1279 ctx->u.bsg_job;
1280 if (bsg_job->request->msgcode
1281 == FC_BSG_HST_CT)
1282 kfree(sp->fcport);
1283 bsg_job->req->errors = 0;
1284 bsg_job->reply->result = res;
1285 bsg_job->job_done(bsg_job);
1286 kfree(sp->ctx);
1287 mempool_free(sp,
1288 ha->srb_mempool);
1289 } else {
1290 ctx->u.iocb_cmd->free(sp);
1291 }
1292 }
1293 }
1294 }
1295 }
1296 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1297 }
1298
1299 static int
1300 qla2xxx_slave_alloc(struct scsi_device *sdev)
1301 {
1302 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1303
1304 if (!rport || fc_remote_port_chkready(rport))
1305 return -ENXIO;
1306
1307 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1308
1309 return 0;
1310 }
1311
1312 static int
1313 qla2xxx_slave_configure(struct scsi_device *sdev)
1314 {
1315 scsi_qla_host_t *vha = shost_priv(sdev->host);
1316 struct req_que *req = vha->req;
1317
1318 if (sdev->tagged_supported)
1319 scsi_activate_tcq(sdev, req->max_q_depth);
1320 else
1321 scsi_deactivate_tcq(sdev, req->max_q_depth);
1322 return 0;
1323 }
1324
1325 static void
1326 qla2xxx_slave_destroy(struct scsi_device *sdev)
1327 {
1328 sdev->hostdata = NULL;
1329 }
1330
1331 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1332 {
1333 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1334
1335 if (!scsi_track_queue_full(sdev, qdepth))
1336 return;
1337
1338 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1339 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1340 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1341 }
1342
1343 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1344 {
1345 fc_port_t *fcport = sdev->hostdata;
1346 struct scsi_qla_host *vha = fcport->vha;
1347 struct req_que *req = NULL;
1348
1349 req = vha->req;
1350 if (!req)
1351 return;
1352
1353 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1354 return;
1355
1356 if (sdev->ordered_tags)
1357 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1358 else
1359 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1360
1361 ql_dbg(ql_dbg_io, vha, 0x302a,
1362 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1363 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1364 }
1365
1366 static int
1367 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1368 {
1369 switch (reason) {
1370 case SCSI_QDEPTH_DEFAULT:
1371 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1372 break;
1373 case SCSI_QDEPTH_QFULL:
1374 qla2x00_handle_queue_full(sdev, qdepth);
1375 break;
1376 case SCSI_QDEPTH_RAMP_UP:
1377 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1378 break;
1379 default:
1380 return -EOPNOTSUPP;
1381 }
1382
1383 return sdev->queue_depth;
1384 }
1385
1386 static int
1387 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1388 {
1389 if (sdev->tagged_supported) {
1390 scsi_set_tag_type(sdev, tag_type);
1391 if (tag_type)
1392 scsi_activate_tcq(sdev, sdev->queue_depth);
1393 else
1394 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1395 } else
1396 tag_type = 0;
1397
1398 return tag_type;
1399 }
1400
1401 /**
1402 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1403 * @ha: HA context
1404 *
1405 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1406 * supported addressing method.
1407 */
1408 static void
1409 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1410 {
1411 /* Assume a 32bit DMA mask. */
1412 ha->flags.enable_64bit_addressing = 0;
1413
1414 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1415 /* Any upper-dword bits set? */
1416 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1417 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1418 /* Ok, a 64bit DMA mask is applicable. */
1419 ha->flags.enable_64bit_addressing = 1;
1420 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1421 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1422 return;
1423 }
1424 }
1425
1426 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1427 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1428 }
1429
1430 static void
1431 qla2x00_enable_intrs(struct qla_hw_data *ha)
1432 {
1433 unsigned long flags = 0;
1434 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1435
1436 spin_lock_irqsave(&ha->hardware_lock, flags);
1437 ha->interrupts_on = 1;
1438 /* enable risc and host interrupts */
1439 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1440 RD_REG_WORD(&reg->ictrl);
1441 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1442
1443 }
1444
1445 static void
1446 qla2x00_disable_intrs(struct qla_hw_data *ha)
1447 {
1448 unsigned long flags = 0;
1449 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1450
1451 spin_lock_irqsave(&ha->hardware_lock, flags);
1452 ha->interrupts_on = 0;
1453 /* disable risc and host interrupts */
1454 WRT_REG_WORD(&reg->ictrl, 0);
1455 RD_REG_WORD(&reg->ictrl);
1456 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1457 }
1458
1459 static void
1460 qla24xx_enable_intrs(struct qla_hw_data *ha)
1461 {
1462 unsigned long flags = 0;
1463 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1464
1465 spin_lock_irqsave(&ha->hardware_lock, flags);
1466 ha->interrupts_on = 1;
1467 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1468 RD_REG_DWORD(&reg->ictrl);
1469 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1470 }
1471
1472 static void
1473 qla24xx_disable_intrs(struct qla_hw_data *ha)
1474 {
1475 unsigned long flags = 0;
1476 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1477
1478 if (IS_NOPOLLING_TYPE(ha))
1479 return;
1480 spin_lock_irqsave(&ha->hardware_lock, flags);
1481 ha->interrupts_on = 0;
1482 WRT_REG_DWORD(&reg->ictrl, 0);
1483 RD_REG_DWORD(&reg->ictrl);
1484 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1485 }
1486
1487 static struct isp_operations qla2100_isp_ops = {
1488 .pci_config = qla2100_pci_config,
1489 .reset_chip = qla2x00_reset_chip,
1490 .chip_diag = qla2x00_chip_diag,
1491 .config_rings = qla2x00_config_rings,
1492 .reset_adapter = qla2x00_reset_adapter,
1493 .nvram_config = qla2x00_nvram_config,
1494 .update_fw_options = qla2x00_update_fw_options,
1495 .load_risc = qla2x00_load_risc,
1496 .pci_info_str = qla2x00_pci_info_str,
1497 .fw_version_str = qla2x00_fw_version_str,
1498 .intr_handler = qla2100_intr_handler,
1499 .enable_intrs = qla2x00_enable_intrs,
1500 .disable_intrs = qla2x00_disable_intrs,
1501 .abort_command = qla2x00_abort_command,
1502 .target_reset = qla2x00_abort_target,
1503 .lun_reset = qla2x00_lun_reset,
1504 .fabric_login = qla2x00_login_fabric,
1505 .fabric_logout = qla2x00_fabric_logout,
1506 .calc_req_entries = qla2x00_calc_iocbs_32,
1507 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1508 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1509 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1510 .read_nvram = qla2x00_read_nvram_data,
1511 .write_nvram = qla2x00_write_nvram_data,
1512 .fw_dump = qla2100_fw_dump,
1513 .beacon_on = NULL,
1514 .beacon_off = NULL,
1515 .beacon_blink = NULL,
1516 .read_optrom = qla2x00_read_optrom_data,
1517 .write_optrom = qla2x00_write_optrom_data,
1518 .get_flash_version = qla2x00_get_flash_version,
1519 .start_scsi = qla2x00_start_scsi,
1520 .abort_isp = qla2x00_abort_isp,
1521 };
1522
1523 static struct isp_operations qla2300_isp_ops = {
1524 .pci_config = qla2300_pci_config,
1525 .reset_chip = qla2x00_reset_chip,
1526 .chip_diag = qla2x00_chip_diag,
1527 .config_rings = qla2x00_config_rings,
1528 .reset_adapter = qla2x00_reset_adapter,
1529 .nvram_config = qla2x00_nvram_config,
1530 .update_fw_options = qla2x00_update_fw_options,
1531 .load_risc = qla2x00_load_risc,
1532 .pci_info_str = qla2x00_pci_info_str,
1533 .fw_version_str = qla2x00_fw_version_str,
1534 .intr_handler = qla2300_intr_handler,
1535 .enable_intrs = qla2x00_enable_intrs,
1536 .disable_intrs = qla2x00_disable_intrs,
1537 .abort_command = qla2x00_abort_command,
1538 .target_reset = qla2x00_abort_target,
1539 .lun_reset = qla2x00_lun_reset,
1540 .fabric_login = qla2x00_login_fabric,
1541 .fabric_logout = qla2x00_fabric_logout,
1542 .calc_req_entries = qla2x00_calc_iocbs_32,
1543 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1544 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1545 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1546 .read_nvram = qla2x00_read_nvram_data,
1547 .write_nvram = qla2x00_write_nvram_data,
1548 .fw_dump = qla2300_fw_dump,
1549 .beacon_on = qla2x00_beacon_on,
1550 .beacon_off = qla2x00_beacon_off,
1551 .beacon_blink = qla2x00_beacon_blink,
1552 .read_optrom = qla2x00_read_optrom_data,
1553 .write_optrom = qla2x00_write_optrom_data,
1554 .get_flash_version = qla2x00_get_flash_version,
1555 .start_scsi = qla2x00_start_scsi,
1556 .abort_isp = qla2x00_abort_isp,
1557 };
1558
1559 static struct isp_operations qla24xx_isp_ops = {
1560 .pci_config = qla24xx_pci_config,
1561 .reset_chip = qla24xx_reset_chip,
1562 .chip_diag = qla24xx_chip_diag,
1563 .config_rings = qla24xx_config_rings,
1564 .reset_adapter = qla24xx_reset_adapter,
1565 .nvram_config = qla24xx_nvram_config,
1566 .update_fw_options = qla24xx_update_fw_options,
1567 .load_risc = qla24xx_load_risc,
1568 .pci_info_str = qla24xx_pci_info_str,
1569 .fw_version_str = qla24xx_fw_version_str,
1570 .intr_handler = qla24xx_intr_handler,
1571 .enable_intrs = qla24xx_enable_intrs,
1572 .disable_intrs = qla24xx_disable_intrs,
1573 .abort_command = qla24xx_abort_command,
1574 .target_reset = qla24xx_abort_target,
1575 .lun_reset = qla24xx_lun_reset,
1576 .fabric_login = qla24xx_login_fabric,
1577 .fabric_logout = qla24xx_fabric_logout,
1578 .calc_req_entries = NULL,
1579 .build_iocbs = NULL,
1580 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1581 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1582 .read_nvram = qla24xx_read_nvram_data,
1583 .write_nvram = qla24xx_write_nvram_data,
1584 .fw_dump = qla24xx_fw_dump,
1585 .beacon_on = qla24xx_beacon_on,
1586 .beacon_off = qla24xx_beacon_off,
1587 .beacon_blink = qla24xx_beacon_blink,
1588 .read_optrom = qla24xx_read_optrom_data,
1589 .write_optrom = qla24xx_write_optrom_data,
1590 .get_flash_version = qla24xx_get_flash_version,
1591 .start_scsi = qla24xx_start_scsi,
1592 .abort_isp = qla2x00_abort_isp,
1593 };
1594
1595 static struct isp_operations qla25xx_isp_ops = {
1596 .pci_config = qla25xx_pci_config,
1597 .reset_chip = qla24xx_reset_chip,
1598 .chip_diag = qla24xx_chip_diag,
1599 .config_rings = qla24xx_config_rings,
1600 .reset_adapter = qla24xx_reset_adapter,
1601 .nvram_config = qla24xx_nvram_config,
1602 .update_fw_options = qla24xx_update_fw_options,
1603 .load_risc = qla24xx_load_risc,
1604 .pci_info_str = qla24xx_pci_info_str,
1605 .fw_version_str = qla24xx_fw_version_str,
1606 .intr_handler = qla24xx_intr_handler,
1607 .enable_intrs = qla24xx_enable_intrs,
1608 .disable_intrs = qla24xx_disable_intrs,
1609 .abort_command = qla24xx_abort_command,
1610 .target_reset = qla24xx_abort_target,
1611 .lun_reset = qla24xx_lun_reset,
1612 .fabric_login = qla24xx_login_fabric,
1613 .fabric_logout = qla24xx_fabric_logout,
1614 .calc_req_entries = NULL,
1615 .build_iocbs = NULL,
1616 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1617 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1618 .read_nvram = qla25xx_read_nvram_data,
1619 .write_nvram = qla25xx_write_nvram_data,
1620 .fw_dump = qla25xx_fw_dump,
1621 .beacon_on = qla24xx_beacon_on,
1622 .beacon_off = qla24xx_beacon_off,
1623 .beacon_blink = qla24xx_beacon_blink,
1624 .read_optrom = qla25xx_read_optrom_data,
1625 .write_optrom = qla24xx_write_optrom_data,
1626 .get_flash_version = qla24xx_get_flash_version,
1627 .start_scsi = qla24xx_dif_start_scsi,
1628 .abort_isp = qla2x00_abort_isp,
1629 };
1630
1631 static struct isp_operations qla81xx_isp_ops = {
1632 .pci_config = qla25xx_pci_config,
1633 .reset_chip = qla24xx_reset_chip,
1634 .chip_diag = qla24xx_chip_diag,
1635 .config_rings = qla24xx_config_rings,
1636 .reset_adapter = qla24xx_reset_adapter,
1637 .nvram_config = qla81xx_nvram_config,
1638 .update_fw_options = qla81xx_update_fw_options,
1639 .load_risc = qla81xx_load_risc,
1640 .pci_info_str = qla24xx_pci_info_str,
1641 .fw_version_str = qla24xx_fw_version_str,
1642 .intr_handler = qla24xx_intr_handler,
1643 .enable_intrs = qla24xx_enable_intrs,
1644 .disable_intrs = qla24xx_disable_intrs,
1645 .abort_command = qla24xx_abort_command,
1646 .target_reset = qla24xx_abort_target,
1647 .lun_reset = qla24xx_lun_reset,
1648 .fabric_login = qla24xx_login_fabric,
1649 .fabric_logout = qla24xx_fabric_logout,
1650 .calc_req_entries = NULL,
1651 .build_iocbs = NULL,
1652 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1653 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1654 .read_nvram = NULL,
1655 .write_nvram = NULL,
1656 .fw_dump = qla81xx_fw_dump,
1657 .beacon_on = qla24xx_beacon_on,
1658 .beacon_off = qla24xx_beacon_off,
1659 .beacon_blink = qla24xx_beacon_blink,
1660 .read_optrom = qla25xx_read_optrom_data,
1661 .write_optrom = qla24xx_write_optrom_data,
1662 .get_flash_version = qla24xx_get_flash_version,
1663 .start_scsi = qla24xx_dif_start_scsi,
1664 .abort_isp = qla2x00_abort_isp,
1665 };
1666
1667 static struct isp_operations qla82xx_isp_ops = {
1668 .pci_config = qla82xx_pci_config,
1669 .reset_chip = qla82xx_reset_chip,
1670 .chip_diag = qla24xx_chip_diag,
1671 .config_rings = qla82xx_config_rings,
1672 .reset_adapter = qla24xx_reset_adapter,
1673 .nvram_config = qla81xx_nvram_config,
1674 .update_fw_options = qla24xx_update_fw_options,
1675 .load_risc = qla82xx_load_risc,
1676 .pci_info_str = qla82xx_pci_info_str,
1677 .fw_version_str = qla24xx_fw_version_str,
1678 .intr_handler = qla82xx_intr_handler,
1679 .enable_intrs = qla82xx_enable_intrs,
1680 .disable_intrs = qla82xx_disable_intrs,
1681 .abort_command = qla24xx_abort_command,
1682 .target_reset = qla24xx_abort_target,
1683 .lun_reset = qla24xx_lun_reset,
1684 .fabric_login = qla24xx_login_fabric,
1685 .fabric_logout = qla24xx_fabric_logout,
1686 .calc_req_entries = NULL,
1687 .build_iocbs = NULL,
1688 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1689 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1690 .read_nvram = qla24xx_read_nvram_data,
1691 .write_nvram = qla24xx_write_nvram_data,
1692 .fw_dump = qla24xx_fw_dump,
1693 .beacon_on = qla82xx_beacon_on,
1694 .beacon_off = qla82xx_beacon_off,
1695 .beacon_blink = NULL,
1696 .read_optrom = qla82xx_read_optrom_data,
1697 .write_optrom = qla82xx_write_optrom_data,
1698 .get_flash_version = qla24xx_get_flash_version,
1699 .start_scsi = qla82xx_start_scsi,
1700 .abort_isp = qla82xx_abort_isp,
1701 };
1702
1703 static inline void
1704 qla2x00_set_isp_flags(struct qla_hw_data *ha)
1705 {
1706 ha->device_type = DT_EXTENDED_IDS;
1707 switch (ha->pdev->device) {
1708 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1709 ha->device_type |= DT_ISP2100;
1710 ha->device_type &= ~DT_EXTENDED_IDS;
1711 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
1712 break;
1713 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1714 ha->device_type |= DT_ISP2200;
1715 ha->device_type &= ~DT_EXTENDED_IDS;
1716 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
1717 break;
1718 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1719 ha->device_type |= DT_ISP2300;
1720 ha->device_type |= DT_ZIO_SUPPORTED;
1721 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1722 break;
1723 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1724 ha->device_type |= DT_ISP2312;
1725 ha->device_type |= DT_ZIO_SUPPORTED;
1726 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1727 break;
1728 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1729 ha->device_type |= DT_ISP2322;
1730 ha->device_type |= DT_ZIO_SUPPORTED;
1731 if (ha->pdev->subsystem_vendor == 0x1028 &&
1732 ha->pdev->subsystem_device == 0x0170)
1733 ha->device_type |= DT_OEM_001;
1734 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1735 break;
1736 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1737 ha->device_type |= DT_ISP6312;
1738 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1739 break;
1740 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1741 ha->device_type |= DT_ISP6322;
1742 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
1743 break;
1744 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1745 ha->device_type |= DT_ISP2422;
1746 ha->device_type |= DT_ZIO_SUPPORTED;
1747 ha->device_type |= DT_FWI2;
1748 ha->device_type |= DT_IIDMA;
1749 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1750 break;
1751 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1752 ha->device_type |= DT_ISP2432;
1753 ha->device_type |= DT_ZIO_SUPPORTED;
1754 ha->device_type |= DT_FWI2;
1755 ha->device_type |= DT_IIDMA;
1756 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1757 break;
1758 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1759 ha->device_type |= DT_ISP8432;
1760 ha->device_type |= DT_ZIO_SUPPORTED;
1761 ha->device_type |= DT_FWI2;
1762 ha->device_type |= DT_IIDMA;
1763 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1764 break;
1765 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1766 ha->device_type |= DT_ISP5422;
1767 ha->device_type |= DT_FWI2;
1768 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1769 break;
1770 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1771 ha->device_type |= DT_ISP5432;
1772 ha->device_type |= DT_FWI2;
1773 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1774 break;
1775 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1776 ha->device_type |= DT_ISP2532;
1777 ha->device_type |= DT_ZIO_SUPPORTED;
1778 ha->device_type |= DT_FWI2;
1779 ha->device_type |= DT_IIDMA;
1780 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1781 break;
1782 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1783 ha->device_type |= DT_ISP8001;
1784 ha->device_type |= DT_ZIO_SUPPORTED;
1785 ha->device_type |= DT_FWI2;
1786 ha->device_type |= DT_IIDMA;
1787 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1788 break;
1789 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1790 ha->device_type |= DT_ISP8021;
1791 ha->device_type |= DT_ZIO_SUPPORTED;
1792 ha->device_type |= DT_FWI2;
1793 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1794 /* Initialize 82XX ISP flags */
1795 qla82xx_init_flags(ha);
1796 break;
1797 }
1798
1799 if (IS_QLA82XX(ha))
1800 ha->port_no = !(ha->portnum & 1);
1801 else
1802 /* Get adapter physical port no from interrupt pin register. */
1803 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1804
1805 if (ha->port_no & 1)
1806 ha->flags.port0 = 1;
1807 else
1808 ha->flags.port0 = 0;
1809 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1810 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
1811 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
1812 }
1813
1814 static int
1815 qla2x00_iospace_config(struct qla_hw_data *ha)
1816 {
1817 resource_size_t pio;
1818 uint16_t msix;
1819 int cpus;
1820
1821 if (IS_QLA82XX(ha))
1822 return qla82xx_iospace_config(ha);
1823
1824 if (pci_request_selected_regions(ha->pdev, ha->bars,
1825 QLA2XXX_DRIVER_NAME)) {
1826 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1827 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1828 pci_name(ha->pdev));
1829 goto iospace_error_exit;
1830 }
1831 if (!(ha->bars & 1))
1832 goto skip_pio;
1833
1834 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1835 pio = pci_resource_start(ha->pdev, 0);
1836 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1837 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1838 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1839 "Invalid pci I/O region size (%s).\n",
1840 pci_name(ha->pdev));
1841 pio = 0;
1842 }
1843 } else {
1844 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1845 "Region #0 no a PIO resource (%s).\n",
1846 pci_name(ha->pdev));
1847 pio = 0;
1848 }
1849 ha->pio_address = pio;
1850 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1851 "PIO address=%llu.\n",
1852 (unsigned long long)ha->pio_address);
1853
1854 skip_pio:
1855 /* Use MMIO operations for all accesses. */
1856 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1857 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1858 "Region #1 not an MMIO resource (%s), aborting.\n",
1859 pci_name(ha->pdev));
1860 goto iospace_error_exit;
1861 }
1862 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1863 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1864 "Invalid PCI mem region size (%s), aborting.\n",
1865 pci_name(ha->pdev));
1866 goto iospace_error_exit;
1867 }
1868
1869 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1870 if (!ha->iobase) {
1871 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1872 "Cannot remap MMIO (%s), aborting.\n",
1873 pci_name(ha->pdev));
1874 goto iospace_error_exit;
1875 }
1876
1877 /* Determine queue resources */
1878 ha->max_req_queues = ha->max_rsp_queues = 1;
1879 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1880 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1881 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1882 goto mqiobase_exit;
1883
1884 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1885 pci_resource_len(ha->pdev, 3));
1886 if (ha->mqiobase) {
1887 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1888 "MQIO Base=%p.\n", ha->mqiobase);
1889 /* Read MSIX vector size of the board */
1890 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1891 ha->msix_count = msix;
1892 /* Max queues are bounded by available msix vectors */
1893 /* queue 0 uses two msix vectors */
1894 if (ql2xmultique_tag) {
1895 cpus = num_online_cpus();
1896 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1897 (cpus + 1) : (ha->msix_count - 1);
1898 ha->max_req_queues = 2;
1899 } else if (ql2xmaxqueues > 1) {
1900 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1901 QLA_MQ_SIZE : ql2xmaxqueues;
1902 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1903 "QoS mode set, max no of request queues:%d.\n",
1904 ha->max_req_queues);
1905 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1906 "QoS mode set, max no of request queues:%d.\n",
1907 ha->max_req_queues);
1908 }
1909 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1910 "MSI-X vector count: %d.\n", msix);
1911 } else
1912 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1913 "BAR 3 not enabled.\n");
1914
1915 mqiobase_exit:
1916 ha->msix_count = ha->max_rsp_queues + 1;
1917 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1918 "MSIX Count:%d.\n", ha->msix_count);
1919 return (0);
1920
1921 iospace_error_exit:
1922 return (-ENOMEM);
1923 }
1924
1925 static void
1926 qla2xxx_scan_start(struct Scsi_Host *shost)
1927 {
1928 scsi_qla_host_t *vha = shost_priv(shost);
1929
1930 if (vha->hw->flags.running_gold_fw)
1931 return;
1932
1933 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1934 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1935 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1936 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1937 }
1938
1939 static int
1940 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
1941 {
1942 scsi_qla_host_t *vha = shost_priv(shost);
1943
1944 if (!vha->host)
1945 return 1;
1946 if (time > vha->hw->loop_reset_delay * HZ)
1947 return 1;
1948
1949 return atomic_read(&vha->loop_state) == LOOP_READY;
1950 }
1951
1952 /*
1953 * PCI driver interface
1954 */
1955 static int __devinit
1956 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1957 {
1958 int ret = -ENODEV;
1959 struct Scsi_Host *host;
1960 scsi_qla_host_t *base_vha = NULL;
1961 struct qla_hw_data *ha;
1962 char pci_info[30];
1963 char fw_str[30];
1964 struct scsi_host_template *sht;
1965 int bars, max_id, mem_only = 0;
1966 uint16_t req_length = 0, rsp_length = 0;
1967 struct req_que *req = NULL;
1968 struct rsp_que *rsp = NULL;
1969
1970 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1971 sht = &qla2xxx_driver_template;
1972 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
1973 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
1974 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
1975 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
1976 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
1977 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
1978 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
1979 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
1980 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1981 mem_only = 1;
1982 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
1983 "Mem only adapter.\n");
1984 }
1985 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
1986 "Bars=%d.\n", bars);
1987
1988 if (mem_only) {
1989 if (pci_enable_device_mem(pdev))
1990 goto probe_out;
1991 } else {
1992 if (pci_enable_device(pdev))
1993 goto probe_out;
1994 }
1995
1996 /* This may fail but that's ok */
1997 pci_enable_pcie_error_reporting(pdev);
1998
1999 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2000 if (!ha) {
2001 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2002 "Unable to allocate memory for ha.\n");
2003 goto probe_out;
2004 }
2005 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2006 "Memory allocated for ha=%p.\n", ha);
2007 ha->pdev = pdev;
2008
2009 /* Clear our data area */
2010 ha->bars = bars;
2011 ha->mem_only = mem_only;
2012 spin_lock_init(&ha->hardware_lock);
2013 spin_lock_init(&ha->vport_slock);
2014
2015 /* Set ISP-type information. */
2016 qla2x00_set_isp_flags(ha);
2017
2018 /* Set EEH reset type to fundamental if required by hba */
2019 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2020 pdev->needs_freset = 1;
2021 }
2022
2023 /* Configure PCI I/O space */
2024 ret = qla2x00_iospace_config(ha);
2025 if (ret)
2026 goto probe_hw_failed;
2027
2028 ql_log_pci(ql_log_info, pdev, 0x001d,
2029 "Found an ISP%04X irq %d iobase 0x%p.\n",
2030 pdev->device, pdev->irq, ha->iobase);
2031 ha->prev_topology = 0;
2032 ha->init_cb_size = sizeof(init_cb_t);
2033 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2034 ha->optrom_size = OPTROM_SIZE_2300;
2035
2036 /* Assign ISP specific operations. */
2037 max_id = MAX_TARGETS_2200;
2038 if (IS_QLA2100(ha)) {
2039 max_id = MAX_TARGETS_2100;
2040 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2041 req_length = REQUEST_ENTRY_CNT_2100;
2042 rsp_length = RESPONSE_ENTRY_CNT_2100;
2043 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2044 ha->gid_list_info_size = 4;
2045 ha->flash_conf_off = ~0;
2046 ha->flash_data_off = ~0;
2047 ha->nvram_conf_off = ~0;
2048 ha->nvram_data_off = ~0;
2049 ha->isp_ops = &qla2100_isp_ops;
2050 } else if (IS_QLA2200(ha)) {
2051 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2052 req_length = REQUEST_ENTRY_CNT_2200;
2053 rsp_length = RESPONSE_ENTRY_CNT_2100;
2054 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2055 ha->gid_list_info_size = 4;
2056 ha->flash_conf_off = ~0;
2057 ha->flash_data_off = ~0;
2058 ha->nvram_conf_off = ~0;
2059 ha->nvram_data_off = ~0;
2060 ha->isp_ops = &qla2100_isp_ops;
2061 } else if (IS_QLA23XX(ha)) {
2062 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2063 req_length = REQUEST_ENTRY_CNT_2200;
2064 rsp_length = RESPONSE_ENTRY_CNT_2300;
2065 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2066 ha->gid_list_info_size = 6;
2067 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2068 ha->optrom_size = OPTROM_SIZE_2322;
2069 ha->flash_conf_off = ~0;
2070 ha->flash_data_off = ~0;
2071 ha->nvram_conf_off = ~0;
2072 ha->nvram_data_off = ~0;
2073 ha->isp_ops = &qla2300_isp_ops;
2074 } else if (IS_QLA24XX_TYPE(ha)) {
2075 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2076 req_length = REQUEST_ENTRY_CNT_24XX;
2077 rsp_length = RESPONSE_ENTRY_CNT_2300;
2078 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2079 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2080 ha->gid_list_info_size = 8;
2081 ha->optrom_size = OPTROM_SIZE_24XX;
2082 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2083 ha->isp_ops = &qla24xx_isp_ops;
2084 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2085 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2086 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2087 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2088 } else if (IS_QLA25XX(ha)) {
2089 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2090 req_length = REQUEST_ENTRY_CNT_24XX;
2091 rsp_length = RESPONSE_ENTRY_CNT_2300;
2092 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2093 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2094 ha->gid_list_info_size = 8;
2095 ha->optrom_size = OPTROM_SIZE_25XX;
2096 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2097 ha->isp_ops = &qla25xx_isp_ops;
2098 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2099 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2100 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2101 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2102 } else if (IS_QLA81XX(ha)) {
2103 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2104 req_length = REQUEST_ENTRY_CNT_24XX;
2105 rsp_length = RESPONSE_ENTRY_CNT_2300;
2106 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2107 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2108 ha->gid_list_info_size = 8;
2109 ha->optrom_size = OPTROM_SIZE_81XX;
2110 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2111 ha->isp_ops = &qla81xx_isp_ops;
2112 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2113 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2114 ha->nvram_conf_off = ~0;
2115 ha->nvram_data_off = ~0;
2116 } else if (IS_QLA82XX(ha)) {
2117 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2118 req_length = REQUEST_ENTRY_CNT_82XX;
2119 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2120 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2121 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2122 ha->gid_list_info_size = 8;
2123 ha->optrom_size = OPTROM_SIZE_82XX;
2124 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2125 ha->isp_ops = &qla82xx_isp_ops;
2126 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2127 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2128 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2129 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2130 }
2131 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2132 "mbx_count=%d, req_length=%d, "
2133 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2134 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2135 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2136 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2137 ha->nvram_npiv_size);
2138 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2139 "isp_ops=%p, flash_conf_off=%d, "
2140 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2141 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2142 ha->nvram_conf_off, ha->nvram_data_off);
2143 mutex_init(&ha->vport_lock);
2144 init_completion(&ha->mbx_cmd_comp);
2145 complete(&ha->mbx_cmd_comp);
2146 init_completion(&ha->mbx_intr_comp);
2147 init_completion(&ha->dcbx_comp);
2148
2149 set_bit(0, (unsigned long *) ha->vp_idx_map);
2150
2151 qla2x00_config_dma_addressing(ha);
2152 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2153 "64 Bit addressing is %s.\n",
2154 ha->flags.enable_64bit_addressing ? "enable" :
2155 "disable");
2156 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2157 if (!ret) {
2158 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2159 "Failed to allocate memory for adapter, aborting.\n");
2160
2161 goto probe_hw_failed;
2162 }
2163
2164 req->max_q_depth = MAX_Q_DEPTH;
2165 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2166 req->max_q_depth = ql2xmaxqdepth;
2167
2168
2169 base_vha = qla2x00_create_host(sht, ha);
2170 if (!base_vha) {
2171 ret = -ENOMEM;
2172 qla2x00_mem_free(ha);
2173 qla2x00_free_req_que(ha, req);
2174 qla2x00_free_rsp_que(ha, rsp);
2175 goto probe_hw_failed;
2176 }
2177
2178 pci_set_drvdata(pdev, base_vha);
2179
2180 host = base_vha->host;
2181 base_vha->req = req;
2182 host->can_queue = req->length + 128;
2183 if (IS_QLA2XXX_MIDTYPE(ha))
2184 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2185 else
2186 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2187 base_vha->vp_idx;
2188
2189 /* Set the SG table size based on ISP type */
2190 if (!IS_FWI2_CAPABLE(ha)) {
2191 if (IS_QLA2100(ha))
2192 host->sg_tablesize = 32;
2193 } else {
2194 if (!IS_QLA82XX(ha))
2195 host->sg_tablesize = QLA_SG_ALL;
2196 }
2197 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2198 "can_queue=%d, req=%p, "
2199 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2200 host->can_queue, base_vha->req,
2201 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2202 host->max_id = max_id;
2203 host->this_id = 255;
2204 host->cmd_per_lun = 3;
2205 host->unique_id = host->host_no;
2206 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2207 host->max_cmd_len = 32;
2208 else
2209 host->max_cmd_len = MAX_CMDSZ;
2210 host->max_channel = MAX_BUSES - 1;
2211 host->max_lun = ql2xmaxlun;
2212 host->transportt = qla2xxx_transport_template;
2213 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2214
2215 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2216 "max_id=%d this_id=%d "
2217 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2218 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
2219 host->this_id, host->cmd_per_lun, host->unique_id,
2220 host->max_cmd_len, host->max_channel, host->max_lun,
2221 host->transportt, sht->vendor_id);
2222
2223 /* Set up the irqs */
2224 ret = qla2x00_request_irqs(ha, rsp);
2225 if (ret)
2226 goto probe_init_failed;
2227
2228 pci_save_state(pdev);
2229
2230 /* Alloc arrays of request and response ring ptrs */
2231 que_init:
2232 if (!qla2x00_alloc_queues(ha)) {
2233 ql_log(ql_log_fatal, base_vha, 0x003d,
2234 "Failed to allocate memory for queue pointers.. aborting.\n");
2235 goto probe_init_failed;
2236 }
2237
2238 ha->rsp_q_map[0] = rsp;
2239 ha->req_q_map[0] = req;
2240 rsp->req = req;
2241 req->rsp = rsp;
2242 set_bit(0, ha->req_qid_map);
2243 set_bit(0, ha->rsp_qid_map);
2244 /* FWI2-capable only. */
2245 req->req_q_in = &ha->iobase->isp24.req_q_in;
2246 req->req_q_out = &ha->iobase->isp24.req_q_out;
2247 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2248 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2249 if (ha->mqenable) {
2250 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2251 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2252 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2253 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2254 }
2255
2256 if (IS_QLA82XX(ha)) {
2257 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2258 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2259 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2260 }
2261
2262 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2263 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2264 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2265 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2266 "req->req_q_in=%p req->req_q_out=%p "
2267 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2268 req->req_q_in, req->req_q_out,
2269 rsp->rsp_q_in, rsp->rsp_q_out);
2270 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2271 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2272 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2273 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2274 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2275 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2276
2277 if (qla2x00_initialize_adapter(base_vha)) {
2278 ql_log(ql_log_fatal, base_vha, 0x00d6,
2279 "Failed to initialize adapter - Adapter flags %x.\n",
2280 base_vha->device_flags);
2281
2282 if (IS_QLA82XX(ha)) {
2283 qla82xx_idc_lock(ha);
2284 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2285 QLA82XX_DEV_FAILED);
2286 qla82xx_idc_unlock(ha);
2287 ql_log(ql_log_fatal, base_vha, 0x00d7,
2288 "HW State: FAILED.\n");
2289 }
2290
2291 ret = -ENODEV;
2292 goto probe_failed;
2293 }
2294
2295 if (ha->mqenable) {
2296 if (qla25xx_setup_mode(base_vha)) {
2297 ql_log(ql_log_warn, base_vha, 0x00ec,
2298 "Failed to create queues, falling back to single queue mode.\n");
2299 goto que_init;
2300 }
2301 }
2302
2303 if (ha->flags.running_gold_fw)
2304 goto skip_dpc;
2305
2306 /*
2307 * Startup the kernel thread for this host adapter
2308 */
2309 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2310 "%s_dpc", base_vha->host_str);
2311 if (IS_ERR(ha->dpc_thread)) {
2312 ql_log(ql_log_fatal, base_vha, 0x00ed,
2313 "Failed to start DPC thread.\n");
2314 ret = PTR_ERR(ha->dpc_thread);
2315 goto probe_failed;
2316 }
2317 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2318 "DPC thread started successfully.\n");
2319
2320 skip_dpc:
2321 list_add_tail(&base_vha->list, &ha->vp_list);
2322 base_vha->host->irq = ha->pdev->irq;
2323
2324 /* Initialized the timer */
2325 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2326 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2327 "Started qla2x00_timer with "
2328 "interval=%d.\n", WATCH_INTERVAL);
2329 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2330 "Detected hba at address=%p.\n",
2331 ha);
2332
2333 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2334 if (ha->fw_attributes & BIT_4) {
2335 int prot = 0;
2336 base_vha->flags.difdix_supported = 1;
2337 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2338 "Registering for DIF/DIX type 1 and 3 protection.\n");
2339 if (ql2xenabledif == 1)
2340 prot = SHOST_DIX_TYPE0_PROTECTION;
2341 scsi_host_set_prot(host,
2342 prot | SHOST_DIF_TYPE1_PROTECTION
2343 | SHOST_DIF_TYPE2_PROTECTION
2344 | SHOST_DIF_TYPE3_PROTECTION
2345 | SHOST_DIX_TYPE1_PROTECTION
2346 | SHOST_DIX_TYPE2_PROTECTION
2347 | SHOST_DIX_TYPE3_PROTECTION);
2348 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2349 } else
2350 base_vha->flags.difdix_supported = 0;
2351 }
2352
2353 ha->isp_ops->enable_intrs(ha);
2354
2355 ret = scsi_add_host(host, &pdev->dev);
2356 if (ret)
2357 goto probe_failed;
2358
2359 base_vha->flags.init_done = 1;
2360 base_vha->flags.online = 1;
2361
2362 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2363 "Init done and hba is online.\n");
2364
2365 scsi_scan_host(host);
2366
2367 qla2x00_alloc_sysfs_attr(base_vha);
2368
2369 qla2x00_init_host_attr(base_vha);
2370
2371 qla2x00_dfs_setup(base_vha);
2372
2373 ql_log(ql_log_info, base_vha, 0x00fb,
2374 "QLogic %s - %s.\n",
2375 ha->model_number, ha->model_desc ? ha->model_desc : "");
2376 ql_log(ql_log_info, base_vha, 0x00fc,
2377 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2378 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2379 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2380 base_vha->host_no,
2381 ha->isp_ops->fw_version_str(base_vha, fw_str));
2382
2383 return 0;
2384
2385 probe_init_failed:
2386 qla2x00_free_req_que(ha, req);
2387 qla2x00_free_rsp_que(ha, rsp);
2388 ha->max_req_queues = ha->max_rsp_queues = 0;
2389
2390 probe_failed:
2391 if (base_vha->timer_active)
2392 qla2x00_stop_timer(base_vha);
2393 base_vha->flags.online = 0;
2394 if (ha->dpc_thread) {
2395 struct task_struct *t = ha->dpc_thread;
2396
2397 ha->dpc_thread = NULL;
2398 kthread_stop(t);
2399 }
2400
2401 qla2x00_free_device(base_vha);
2402
2403 scsi_host_put(base_vha->host);
2404
2405 probe_hw_failed:
2406 if (IS_QLA82XX(ha)) {
2407 qla82xx_idc_lock(ha);
2408 qla82xx_clear_drv_active(ha);
2409 qla82xx_idc_unlock(ha);
2410 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2411 if (!ql2xdbwr)
2412 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2413 } else {
2414 if (ha->iobase)
2415 iounmap(ha->iobase);
2416 }
2417 pci_release_selected_regions(ha->pdev, ha->bars);
2418 kfree(ha);
2419 ha = NULL;
2420
2421 probe_out:
2422 pci_disable_device(pdev);
2423 return ret;
2424 }
2425
2426 static void
2427 qla2x00_shutdown(struct pci_dev *pdev)
2428 {
2429 scsi_qla_host_t *vha;
2430 struct qla_hw_data *ha;
2431
2432 vha = pci_get_drvdata(pdev);
2433 ha = vha->hw;
2434
2435 /* Turn-off FCE trace */
2436 if (ha->flags.fce_enabled) {
2437 qla2x00_disable_fce_trace(vha, NULL, NULL);
2438 ha->flags.fce_enabled = 0;
2439 }
2440
2441 /* Turn-off EFT trace */
2442 if (ha->eft)
2443 qla2x00_disable_eft_trace(vha);
2444
2445 /* Stop currently executing firmware. */
2446 qla2x00_try_to_stop_firmware(vha);
2447
2448 /* Turn adapter off line */
2449 vha->flags.online = 0;
2450
2451 /* turn-off interrupts on the card */
2452 if (ha->interrupts_on) {
2453 vha->flags.init_done = 0;
2454 ha->isp_ops->disable_intrs(ha);
2455 }
2456
2457 qla2x00_free_irqs(vha);
2458
2459 qla2x00_free_fw_dump(ha);
2460 }
2461
2462 static void
2463 qla2x00_remove_one(struct pci_dev *pdev)
2464 {
2465 scsi_qla_host_t *base_vha, *vha;
2466 struct qla_hw_data *ha;
2467 unsigned long flags;
2468
2469 base_vha = pci_get_drvdata(pdev);
2470 ha = base_vha->hw;
2471
2472 mutex_lock(&ha->vport_lock);
2473 while (ha->cur_vport_count) {
2474 struct Scsi_Host *scsi_host;
2475
2476 spin_lock_irqsave(&ha->vport_slock, flags);
2477
2478 BUG_ON(base_vha->list.next == &ha->vp_list);
2479 /* This assumes first entry in ha->vp_list is always base vha */
2480 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2481 scsi_host = scsi_host_get(vha->host);
2482
2483 spin_unlock_irqrestore(&ha->vport_slock, flags);
2484 mutex_unlock(&ha->vport_lock);
2485
2486 fc_vport_terminate(vha->fc_vport);
2487 scsi_host_put(vha->host);
2488
2489 mutex_lock(&ha->vport_lock);
2490 }
2491 mutex_unlock(&ha->vport_lock);
2492
2493 set_bit(UNLOADING, &base_vha->dpc_flags);
2494
2495 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2496
2497 qla2x00_dfs_remove(base_vha);
2498
2499 qla84xx_put_chip(base_vha);
2500
2501 /* Disable timer */
2502 if (base_vha->timer_active)
2503 qla2x00_stop_timer(base_vha);
2504
2505 base_vha->flags.online = 0;
2506
2507 /* Flush the work queue and remove it */
2508 if (ha->wq) {
2509 flush_workqueue(ha->wq);
2510 destroy_workqueue(ha->wq);
2511 ha->wq = NULL;
2512 }
2513
2514 /* Kill the kernel thread for this host */
2515 if (ha->dpc_thread) {
2516 struct task_struct *t = ha->dpc_thread;
2517
2518 /*
2519 * qla2xxx_wake_dpc checks for ->dpc_thread
2520 * so we need to zero it out.
2521 */
2522 ha->dpc_thread = NULL;
2523 kthread_stop(t);
2524 }
2525
2526 qla2x00_free_sysfs_attr(base_vha);
2527
2528 fc_remove_host(base_vha->host);
2529
2530 scsi_remove_host(base_vha->host);
2531
2532 qla2x00_free_device(base_vha);
2533
2534 scsi_host_put(base_vha->host);
2535
2536 if (IS_QLA82XX(ha)) {
2537 qla82xx_idc_lock(ha);
2538 qla82xx_clear_drv_active(ha);
2539 qla82xx_idc_unlock(ha);
2540
2541 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2542 if (!ql2xdbwr)
2543 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2544 } else {
2545 if (ha->iobase)
2546 iounmap(ha->iobase);
2547
2548 if (ha->mqiobase)
2549 iounmap(ha->mqiobase);
2550 }
2551
2552 pci_release_selected_regions(ha->pdev, ha->bars);
2553 kfree(ha);
2554 ha = NULL;
2555
2556 pci_disable_pcie_error_reporting(pdev);
2557
2558 pci_disable_device(pdev);
2559 pci_set_drvdata(pdev, NULL);
2560 }
2561
2562 static void
2563 qla2x00_free_device(scsi_qla_host_t *vha)
2564 {
2565 struct qla_hw_data *ha = vha->hw;
2566
2567 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2568
2569 /* Disable timer */
2570 if (vha->timer_active)
2571 qla2x00_stop_timer(vha);
2572
2573 /* Kill the kernel thread for this host */
2574 if (ha->dpc_thread) {
2575 struct task_struct *t = ha->dpc_thread;
2576
2577 /*
2578 * qla2xxx_wake_dpc checks for ->dpc_thread
2579 * so we need to zero it out.
2580 */
2581 ha->dpc_thread = NULL;
2582 kthread_stop(t);
2583 }
2584
2585 qla25xx_delete_queues(vha);
2586
2587 if (ha->flags.fce_enabled)
2588 qla2x00_disable_fce_trace(vha, NULL, NULL);
2589
2590 if (ha->eft)
2591 qla2x00_disable_eft_trace(vha);
2592
2593 /* Stop currently executing firmware. */
2594 qla2x00_try_to_stop_firmware(vha);
2595
2596 vha->flags.online = 0;
2597
2598 /* turn-off interrupts on the card */
2599 if (ha->interrupts_on) {
2600 vha->flags.init_done = 0;
2601 ha->isp_ops->disable_intrs(ha);
2602 }
2603
2604 qla2x00_free_irqs(vha);
2605
2606 qla2x00_free_fcports(vha);
2607
2608 qla2x00_mem_free(ha);
2609
2610 qla82xx_md_free(vha);
2611
2612 qla2x00_free_queues(ha);
2613 }
2614
2615 void qla2x00_free_fcports(struct scsi_qla_host *vha)
2616 {
2617 fc_port_t *fcport, *tfcport;
2618
2619 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2620 list_del(&fcport->list);
2621 kfree(fcport);
2622 fcport = NULL;
2623 }
2624 }
2625
2626 static inline void
2627 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
2628 int defer)
2629 {
2630 struct fc_rport *rport;
2631 scsi_qla_host_t *base_vha;
2632 unsigned long flags;
2633
2634 if (!fcport->rport)
2635 return;
2636
2637 rport = fcport->rport;
2638 if (defer) {
2639 base_vha = pci_get_drvdata(vha->hw->pdev);
2640 spin_lock_irqsave(vha->host->host_lock, flags);
2641 fcport->drport = rport;
2642 spin_unlock_irqrestore(vha->host->host_lock, flags);
2643 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2644 qla2xxx_wake_dpc(base_vha);
2645 } else
2646 fc_remote_port_delete(rport);
2647 }
2648
2649 /*
2650 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2651 *
2652 * Input: ha = adapter block pointer. fcport = port structure pointer.
2653 *
2654 * Return: None.
2655 *
2656 * Context:
2657 */
2658 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
2659 int do_login, int defer)
2660 {
2661 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2662 vha->vp_idx == fcport->vp_idx) {
2663 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2664 qla2x00_schedule_rport_del(vha, fcport, defer);
2665 }
2666 /*
2667 * We may need to retry the login, so don't change the state of the
2668 * port but do the retries.
2669 */
2670 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
2671 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2672
2673 if (!do_login)
2674 return;
2675
2676 if (fcport->login_retry == 0) {
2677 fcport->login_retry = vha->hw->login_retry_count;
2678 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2679
2680 ql_dbg(ql_dbg_disc, vha, 0x2067,
2681 "Port login retry "
2682 "%02x%02x%02x%02x%02x%02x%02x%02x, "
2683 "id = 0x%04x retry cnt=%d.\n",
2684 fcport->port_name[0], fcport->port_name[1],
2685 fcport->port_name[2], fcport->port_name[3],
2686 fcport->port_name[4], fcport->port_name[5],
2687 fcport->port_name[6], fcport->port_name[7],
2688 fcport->loop_id, fcport->login_retry);
2689 }
2690 }
2691
2692 /*
2693 * qla2x00_mark_all_devices_lost
2694 * Updates fcport state when device goes offline.
2695 *
2696 * Input:
2697 * ha = adapter block pointer.
2698 * fcport = port structure pointer.
2699 *
2700 * Return:
2701 * None.
2702 *
2703 * Context:
2704 */
2705 void
2706 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
2707 {
2708 fc_port_t *fcport;
2709
2710 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2711 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
2712 continue;
2713
2714 /*
2715 * No point in marking the device as lost, if the device is
2716 * already DEAD.
2717 */
2718 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2719 continue;
2720 if (atomic_read(&fcport->state) == FCS_ONLINE) {
2721 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2722 if (defer)
2723 qla2x00_schedule_rport_del(vha, fcport, defer);
2724 else if (vha->vp_idx == fcport->vp_idx)
2725 qla2x00_schedule_rport_del(vha, fcport, defer);
2726 }
2727 }
2728 }
2729
2730 /*
2731 * qla2x00_mem_alloc
2732 * Allocates adapter memory.
2733 *
2734 * Returns:
2735 * 0 = success.
2736 * !0 = failure.
2737 */
2738 static int
2739 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2740 struct req_que **req, struct rsp_que **rsp)
2741 {
2742 char name[16];
2743
2744 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
2745 &ha->init_cb_dma, GFP_KERNEL);
2746 if (!ha->init_cb)
2747 goto fail;
2748
2749 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2750 &ha->gid_list_dma, GFP_KERNEL);
2751 if (!ha->gid_list)
2752 goto fail_free_init_cb;
2753
2754 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2755 if (!ha->srb_mempool)
2756 goto fail_free_gid_list;
2757
2758 if (IS_QLA82XX(ha)) {
2759 /* Allocate cache for CT6 Ctx. */
2760 if (!ctx_cachep) {
2761 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2762 sizeof(struct ct6_dsd), 0,
2763 SLAB_HWCACHE_ALIGN, NULL);
2764 if (!ctx_cachep)
2765 goto fail_free_gid_list;
2766 }
2767 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2768 ctx_cachep);
2769 if (!ha->ctx_mempool)
2770 goto fail_free_srb_mempool;
2771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2772 "ctx_cachep=%p ctx_mempool=%p.\n",
2773 ctx_cachep, ha->ctx_mempool);
2774 }
2775
2776 /* Get memory for cached NVRAM */
2777 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2778 if (!ha->nvram)
2779 goto fail_free_ctx_mempool;
2780
2781 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2782 ha->pdev->device);
2783 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2784 DMA_POOL_SIZE, 8, 0);
2785 if (!ha->s_dma_pool)
2786 goto fail_free_nvram;
2787
2788 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2789 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2790 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2791
2792 if (IS_QLA82XX(ha) || ql2xenabledif) {
2793 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2794 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2795 if (!ha->dl_dma_pool) {
2796 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2797 "Failed to allocate memory for dl_dma_pool.\n");
2798 goto fail_s_dma_pool;
2799 }
2800
2801 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2802 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2803 if (!ha->fcp_cmnd_dma_pool) {
2804 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2805 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
2806 goto fail_dl_dma_pool;
2807 }
2808 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2809 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2810 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
2811 }
2812
2813 /* Allocate memory for SNS commands */
2814 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2815 /* Get consistent memory allocated for SNS commands */
2816 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
2817 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
2818 if (!ha->sns_cmd)
2819 goto fail_dma_pool;
2820 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2821 "sns_cmd: %p.\n", ha->sns_cmd);
2822 } else {
2823 /* Get consistent memory allocated for MS IOCB */
2824 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2825 &ha->ms_iocb_dma);
2826 if (!ha->ms_iocb)
2827 goto fail_dma_pool;
2828 /* Get consistent memory allocated for CT SNS commands */
2829 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
2830 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
2831 if (!ha->ct_sns)
2832 goto fail_free_ms_iocb;
2833 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2834 "ms_iocb=%p ct_sns=%p.\n",
2835 ha->ms_iocb, ha->ct_sns);
2836 }
2837
2838 /* Allocate memory for request ring */
2839 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2840 if (!*req) {
2841 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2842 "Failed to allocate memory for req.\n");
2843 goto fail_req;
2844 }
2845 (*req)->length = req_len;
2846 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2847 ((*req)->length + 1) * sizeof(request_t),
2848 &(*req)->dma, GFP_KERNEL);
2849 if (!(*req)->ring) {
2850 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2851 "Failed to allocate memory for req_ring.\n");
2852 goto fail_req_ring;
2853 }
2854 /* Allocate memory for response ring */
2855 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2856 if (!*rsp) {
2857 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2858 "Failed to allocate memory for rsp.\n");
2859 goto fail_rsp;
2860 }
2861 (*rsp)->hw = ha;
2862 (*rsp)->length = rsp_len;
2863 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2864 ((*rsp)->length + 1) * sizeof(response_t),
2865 &(*rsp)->dma, GFP_KERNEL);
2866 if (!(*rsp)->ring) {
2867 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2868 "Failed to allocate memory for rsp_ring.\n");
2869 goto fail_rsp_ring;
2870 }
2871 (*req)->rsp = *rsp;
2872 (*rsp)->req = *req;
2873 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2874 "req=%p req->length=%d req->ring=%p rsp=%p "
2875 "rsp->length=%d rsp->ring=%p.\n",
2876 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2877 (*rsp)->ring);
2878 /* Allocate memory for NVRAM data for vports */
2879 if (ha->nvram_npiv_size) {
2880 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
2881 ha->nvram_npiv_size, GFP_KERNEL);
2882 if (!ha->npiv_info) {
2883 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2884 "Failed to allocate memory for npiv_info.\n");
2885 goto fail_npiv_info;
2886 }
2887 } else
2888 ha->npiv_info = NULL;
2889
2890 /* Get consistent memory allocated for EX-INIT-CB. */
2891 if (IS_QLA8XXX_TYPE(ha)) {
2892 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2893 &ha->ex_init_cb_dma);
2894 if (!ha->ex_init_cb)
2895 goto fail_ex_init_cb;
2896 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2897 "ex_init_cb=%p.\n", ha->ex_init_cb);
2898 }
2899
2900 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2901
2902 /* Get consistent memory allocated for Async Port-Database. */
2903 if (!IS_FWI2_CAPABLE(ha)) {
2904 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2905 &ha->async_pd_dma);
2906 if (!ha->async_pd)
2907 goto fail_async_pd;
2908 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2909 "async_pd=%p.\n", ha->async_pd);
2910 }
2911
2912 INIT_LIST_HEAD(&ha->vp_list);
2913 return 1;
2914
2915 fail_async_pd:
2916 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
2917 fail_ex_init_cb:
2918 kfree(ha->npiv_info);
2919 fail_npiv_info:
2920 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2921 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2922 (*rsp)->ring = NULL;
2923 (*rsp)->dma = 0;
2924 fail_rsp_ring:
2925 kfree(*rsp);
2926 fail_rsp:
2927 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2928 sizeof(request_t), (*req)->ring, (*req)->dma);
2929 (*req)->ring = NULL;
2930 (*req)->dma = 0;
2931 fail_req_ring:
2932 kfree(*req);
2933 fail_req:
2934 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2935 ha->ct_sns, ha->ct_sns_dma);
2936 ha->ct_sns = NULL;
2937 ha->ct_sns_dma = 0;
2938 fail_free_ms_iocb:
2939 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
2940 ha->ms_iocb = NULL;
2941 ha->ms_iocb_dma = 0;
2942 fail_dma_pool:
2943 if (IS_QLA82XX(ha) || ql2xenabledif) {
2944 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
2945 ha->fcp_cmnd_dma_pool = NULL;
2946 }
2947 fail_dl_dma_pool:
2948 if (IS_QLA82XX(ha) || ql2xenabledif) {
2949 dma_pool_destroy(ha->dl_dma_pool);
2950 ha->dl_dma_pool = NULL;
2951 }
2952 fail_s_dma_pool:
2953 dma_pool_destroy(ha->s_dma_pool);
2954 ha->s_dma_pool = NULL;
2955 fail_free_nvram:
2956 kfree(ha->nvram);
2957 ha->nvram = NULL;
2958 fail_free_ctx_mempool:
2959 mempool_destroy(ha->ctx_mempool);
2960 ha->ctx_mempool = NULL;
2961 fail_free_srb_mempool:
2962 mempool_destroy(ha->srb_mempool);
2963 ha->srb_mempool = NULL;
2964 fail_free_gid_list:
2965 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
2966 ha->gid_list_dma);
2967 ha->gid_list = NULL;
2968 ha->gid_list_dma = 0;
2969 fail_free_init_cb:
2970 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
2971 ha->init_cb_dma);
2972 ha->init_cb = NULL;
2973 ha->init_cb_dma = 0;
2974 fail:
2975 ql_log(ql_log_fatal, NULL, 0x0030,
2976 "Memory allocation failure.\n");
2977 return -ENOMEM;
2978 }
2979
2980 /*
2981 * qla2x00_free_fw_dump
2982 * Frees fw dump stuff.
2983 *
2984 * Input:
2985 * ha = adapter block pointer.
2986 */
2987 static void
2988 qla2x00_free_fw_dump(struct qla_hw_data *ha)
2989 {
2990 if (ha->fce)
2991 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2992 ha->fce_dma);
2993
2994 if (ha->fw_dump) {
2995 if (ha->eft)
2996 dma_free_coherent(&ha->pdev->dev,
2997 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
2998 vfree(ha->fw_dump);
2999 }
3000 ha->fce = NULL;
3001 ha->fce_dma = 0;
3002 ha->eft = NULL;
3003 ha->eft_dma = 0;
3004 ha->fw_dump = NULL;
3005 ha->fw_dumped = 0;
3006 ha->fw_dump_reading = 0;
3007 }
3008
3009 /*
3010 * qla2x00_mem_free
3011 * Frees all adapter allocated memory.
3012 *
3013 * Input:
3014 * ha = adapter block pointer.
3015 */
3016 static void
3017 qla2x00_mem_free(struct qla_hw_data *ha)
3018 {
3019 qla2x00_free_fw_dump(ha);
3020
3021 if (ha->srb_mempool)
3022 mempool_destroy(ha->srb_mempool);
3023
3024 if (ha->dcbx_tlv)
3025 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3026 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3027
3028 if (ha->xgmac_data)
3029 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3030 ha->xgmac_data, ha->xgmac_data_dma);
3031
3032 if (ha->sns_cmd)
3033 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3034 ha->sns_cmd, ha->sns_cmd_dma);
3035
3036 if (ha->ct_sns)
3037 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3038 ha->ct_sns, ha->ct_sns_dma);
3039
3040 if (ha->sfp_data)
3041 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3042
3043 if (ha->edc_data)
3044 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3045
3046 if (ha->ms_iocb)
3047 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3048
3049 if (ha->ex_init_cb)
3050 dma_pool_free(ha->s_dma_pool,
3051 ha->ex_init_cb, ha->ex_init_cb_dma);
3052
3053 if (ha->async_pd)
3054 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3055
3056 if (ha->s_dma_pool)
3057 dma_pool_destroy(ha->s_dma_pool);
3058
3059 if (ha->gid_list)
3060 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
3061 ha->gid_list_dma);
3062
3063 if (IS_QLA82XX(ha)) {
3064 if (!list_empty(&ha->gbl_dsd_list)) {
3065 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3066
3067 /* clean up allocated prev pool */
3068 list_for_each_entry_safe(dsd_ptr,
3069 tdsd_ptr, &ha->gbl_dsd_list, list) {
3070 dma_pool_free(ha->dl_dma_pool,
3071 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3072 list_del(&dsd_ptr->list);
3073 kfree(dsd_ptr);
3074 }
3075 }
3076 }
3077
3078 if (ha->dl_dma_pool)
3079 dma_pool_destroy(ha->dl_dma_pool);
3080
3081 if (ha->fcp_cmnd_dma_pool)
3082 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3083
3084 if (ha->ctx_mempool)
3085 mempool_destroy(ha->ctx_mempool);
3086
3087 if (ha->init_cb)
3088 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3089 ha->init_cb, ha->init_cb_dma);
3090 vfree(ha->optrom_buffer);
3091 kfree(ha->nvram);
3092 kfree(ha->npiv_info);
3093
3094 ha->srb_mempool = NULL;
3095 ha->ctx_mempool = NULL;
3096 ha->sns_cmd = NULL;
3097 ha->sns_cmd_dma = 0;
3098 ha->ct_sns = NULL;
3099 ha->ct_sns_dma = 0;
3100 ha->ms_iocb = NULL;
3101 ha->ms_iocb_dma = 0;
3102 ha->init_cb = NULL;
3103 ha->init_cb_dma = 0;
3104 ha->ex_init_cb = NULL;
3105 ha->ex_init_cb_dma = 0;
3106 ha->async_pd = NULL;
3107 ha->async_pd_dma = 0;
3108
3109 ha->s_dma_pool = NULL;
3110 ha->dl_dma_pool = NULL;
3111 ha->fcp_cmnd_dma_pool = NULL;
3112
3113 ha->gid_list = NULL;
3114 ha->gid_list_dma = 0;
3115 }
3116
3117 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3118 struct qla_hw_data *ha)
3119 {
3120 struct Scsi_Host *host;
3121 struct scsi_qla_host *vha = NULL;
3122
3123 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3124 if (host == NULL) {
3125 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3126 "Failed to allocate host from the scsi layer, aborting.\n");
3127 goto fail;
3128 }
3129
3130 /* Clear our data area */
3131 vha = shost_priv(host);
3132 memset(vha, 0, sizeof(scsi_qla_host_t));
3133
3134 vha->host = host;
3135 vha->host_no = host->host_no;
3136 vha->hw = ha;
3137
3138 INIT_LIST_HEAD(&vha->vp_fcports);
3139 INIT_LIST_HEAD(&vha->work_list);
3140 INIT_LIST_HEAD(&vha->list);
3141
3142 spin_lock_init(&vha->work_lock);
3143
3144 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3145 ql_dbg(ql_dbg_init, vha, 0x0041,
3146 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3147 vha->host, vha->hw, vha,
3148 dev_name(&(ha->pdev->dev)));
3149
3150 return vha;
3151
3152 fail:
3153 return vha;
3154 }
3155
3156 static struct qla_work_evt *
3157 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3158 {
3159 struct qla_work_evt *e;
3160 uint8_t bail;
3161
3162 QLA_VHA_MARK_BUSY(vha, bail);
3163 if (bail)
3164 return NULL;
3165
3166 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3167 if (!e) {
3168 QLA_VHA_MARK_NOT_BUSY(vha);
3169 return NULL;
3170 }
3171
3172 INIT_LIST_HEAD(&e->list);
3173 e->type = type;
3174 e->flags = QLA_EVT_FLAG_FREE;
3175 return e;
3176 }
3177
3178 static int
3179 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3180 {
3181 unsigned long flags;
3182
3183 spin_lock_irqsave(&vha->work_lock, flags);
3184 list_add_tail(&e->list, &vha->work_list);
3185 spin_unlock_irqrestore(&vha->work_lock, flags);
3186 qla2xxx_wake_dpc(vha);
3187
3188 return QLA_SUCCESS;
3189 }
3190
3191 int
3192 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3193 u32 data)
3194 {
3195 struct qla_work_evt *e;
3196
3197 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3198 if (!e)
3199 return QLA_FUNCTION_FAILED;
3200
3201 e->u.aen.code = code;
3202 e->u.aen.data = data;
3203 return qla2x00_post_work(vha, e);
3204 }
3205
3206 int
3207 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3208 {
3209 struct qla_work_evt *e;
3210
3211 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3212 if (!e)
3213 return QLA_FUNCTION_FAILED;
3214
3215 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3216 return qla2x00_post_work(vha, e);
3217 }
3218
3219 #define qla2x00_post_async_work(name, type) \
3220 int qla2x00_post_async_##name##_work( \
3221 struct scsi_qla_host *vha, \
3222 fc_port_t *fcport, uint16_t *data) \
3223 { \
3224 struct qla_work_evt *e; \
3225 \
3226 e = qla2x00_alloc_work(vha, type); \
3227 if (!e) \
3228 return QLA_FUNCTION_FAILED; \
3229 \
3230 e->u.logio.fcport = fcport; \
3231 if (data) { \
3232 e->u.logio.data[0] = data[0]; \
3233 e->u.logio.data[1] = data[1]; \
3234 } \
3235 return qla2x00_post_work(vha, e); \
3236 }
3237
3238 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3239 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3240 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3241 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3242 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3243 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3244
3245 int
3246 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3247 {
3248 struct qla_work_evt *e;
3249
3250 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3251 if (!e)
3252 return QLA_FUNCTION_FAILED;
3253
3254 e->u.uevent.code = code;
3255 return qla2x00_post_work(vha, e);
3256 }
3257
3258 static void
3259 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3260 {
3261 char event_string[40];
3262 char *envp[] = { event_string, NULL };
3263
3264 switch (code) {
3265 case QLA_UEVENT_CODE_FW_DUMP:
3266 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3267 vha->host_no);
3268 break;
3269 default:
3270 /* do nothing */
3271 break;
3272 }
3273 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3274 }
3275
3276 void
3277 qla2x00_do_work(struct scsi_qla_host *vha)
3278 {
3279 struct qla_work_evt *e, *tmp;
3280 unsigned long flags;
3281 LIST_HEAD(work);
3282
3283 spin_lock_irqsave(&vha->work_lock, flags);
3284 list_splice_init(&vha->work_list, &work);
3285 spin_unlock_irqrestore(&vha->work_lock, flags);
3286
3287 list_for_each_entry_safe(e, tmp, &work, list) {
3288 list_del_init(&e->list);
3289
3290 switch (e->type) {
3291 case QLA_EVT_AEN:
3292 fc_host_post_event(vha->host, fc_get_event_number(),
3293 e->u.aen.code, e->u.aen.data);
3294 break;
3295 case QLA_EVT_IDC_ACK:
3296 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3297 break;
3298 case QLA_EVT_ASYNC_LOGIN:
3299 qla2x00_async_login(vha, e->u.logio.fcport,
3300 e->u.logio.data);
3301 break;
3302 case QLA_EVT_ASYNC_LOGIN_DONE:
3303 qla2x00_async_login_done(vha, e->u.logio.fcport,
3304 e->u.logio.data);
3305 break;
3306 case QLA_EVT_ASYNC_LOGOUT:
3307 qla2x00_async_logout(vha, e->u.logio.fcport);
3308 break;
3309 case QLA_EVT_ASYNC_LOGOUT_DONE:
3310 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3311 e->u.logio.data);
3312 break;
3313 case QLA_EVT_ASYNC_ADISC:
3314 qla2x00_async_adisc(vha, e->u.logio.fcport,
3315 e->u.logio.data);
3316 break;
3317 case QLA_EVT_ASYNC_ADISC_DONE:
3318 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3319 e->u.logio.data);
3320 break;
3321 case QLA_EVT_UEVENT:
3322 qla2x00_uevent_emit(vha, e->u.uevent.code);
3323 break;
3324 }
3325 if (e->flags & QLA_EVT_FLAG_FREE)
3326 kfree(e);
3327
3328 /* For each work completed decrement vha ref count */
3329 QLA_VHA_MARK_NOT_BUSY(vha);
3330 }
3331 }
3332
3333 /* Relogins all the fcports of a vport
3334 * Context: dpc thread
3335 */
3336 void qla2x00_relogin(struct scsi_qla_host *vha)
3337 {
3338 fc_port_t *fcport;
3339 int status;
3340 uint16_t next_loopid = 0;
3341 struct qla_hw_data *ha = vha->hw;
3342 uint16_t data[2];
3343
3344 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3345 /*
3346 * If the port is not ONLINE then try to login
3347 * to it if we haven't run out of retries.
3348 */
3349 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3350 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
3351 fcport->login_retry--;
3352 if (fcport->flags & FCF_FABRIC_DEVICE) {
3353 if (fcport->flags & FCF_FCP2_DEVICE)
3354 ha->isp_ops->fabric_logout(vha,
3355 fcport->loop_id,
3356 fcport->d_id.b.domain,
3357 fcport->d_id.b.area,
3358 fcport->d_id.b.al_pa);
3359
3360 if (fcport->loop_id == FC_NO_LOOP_ID) {
3361 fcport->loop_id = next_loopid =
3362 ha->min_external_loopid;
3363 status = qla2x00_find_new_loop_id(
3364 vha, fcport);
3365 if (status != QLA_SUCCESS) {
3366 /* Ran out of IDs to use */
3367 break;
3368 }
3369 }
3370
3371 if (IS_ALOGIO_CAPABLE(ha)) {
3372 fcport->flags |= FCF_ASYNC_SENT;
3373 data[0] = 0;
3374 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3375 status = qla2x00_post_async_login_work(
3376 vha, fcport, data);
3377 if (status == QLA_SUCCESS)
3378 continue;
3379 /* Attempt a retry. */
3380 status = 1;
3381 } else
3382 status = qla2x00_fabric_login(vha,
3383 fcport, &next_loopid);
3384 } else
3385 status = qla2x00_local_device_login(vha,
3386 fcport);
3387
3388 if (status == QLA_SUCCESS) {
3389 fcport->old_loop_id = fcport->loop_id;
3390
3391 ql_dbg(ql_dbg_disc, vha, 0x2003,
3392 "Port login OK: logged in ID 0x%x.\n",
3393 fcport->loop_id);
3394
3395 qla2x00_update_fcport(vha, fcport);
3396
3397 } else if (status == 1) {
3398 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3399 /* retry the login again */
3400 ql_dbg(ql_dbg_disc, vha, 0x2007,
3401 "Retrying %d login again loop_id 0x%x.\n",
3402 fcport->login_retry, fcport->loop_id);
3403 } else {
3404 fcport->login_retry = 0;
3405 }
3406
3407 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3408 fcport->loop_id = FC_NO_LOOP_ID;
3409 }
3410 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3411 break;
3412 }
3413 }
3414
3415 /**************************************************************************
3416 * qla2x00_do_dpc
3417 * This kernel thread is a task that is schedule by the interrupt handler
3418 * to perform the background processing for interrupts.
3419 *
3420 * Notes:
3421 * This task always run in the context of a kernel thread. It
3422 * is kick-off by the driver's detect code and starts up
3423 * up one per adapter. It immediately goes to sleep and waits for
3424 * some fibre event. When either the interrupt handler or
3425 * the timer routine detects a event it will one of the task
3426 * bits then wake us up.
3427 **************************************************************************/
3428 static int
3429 qla2x00_do_dpc(void *data)
3430 {
3431 int rval;
3432 scsi_qla_host_t *base_vha;
3433 struct qla_hw_data *ha;
3434
3435 ha = (struct qla_hw_data *)data;
3436 base_vha = pci_get_drvdata(ha->pdev);
3437
3438 set_user_nice(current, -20);
3439
3440 set_current_state(TASK_INTERRUPTIBLE);
3441 while (!kthread_should_stop()) {
3442 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3443 "DPC handler sleeping.\n");
3444
3445 schedule();
3446 __set_current_state(TASK_RUNNING);
3447
3448 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3449 "DPC handler waking up.\n");
3450 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3451 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
3452
3453 /* Initialization not yet finished. Don't do anything yet. */
3454 if (!base_vha->flags.init_done)
3455 continue;
3456
3457 if (ha->flags.eeh_busy) {
3458 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3459 "eeh_busy=%d.\n", ha->flags.eeh_busy);
3460 continue;
3461 }
3462
3463 ha->dpc_active = 1;
3464
3465 if (ha->flags.mbox_busy) {
3466 ha->dpc_active = 0;
3467 continue;
3468 }
3469
3470 qla2x00_do_work(base_vha);
3471
3472 if (IS_QLA82XX(ha)) {
3473 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3474 &base_vha->dpc_flags)) {
3475 qla82xx_idc_lock(ha);
3476 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3477 QLA82XX_DEV_FAILED);
3478 qla82xx_idc_unlock(ha);
3479 ql_log(ql_log_info, base_vha, 0x4004,
3480 "HW State: FAILED.\n");
3481 qla82xx_device_state_handler(base_vha);
3482 continue;
3483 }
3484
3485 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3486 &base_vha->dpc_flags)) {
3487
3488 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3489 "FCoE context reset scheduled.\n");
3490 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3491 &base_vha->dpc_flags))) {
3492 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3493 /* FCoE-ctx reset failed.
3494 * Escalate to chip-reset
3495 */
3496 set_bit(ISP_ABORT_NEEDED,
3497 &base_vha->dpc_flags);
3498 }
3499 clear_bit(ABORT_ISP_ACTIVE,
3500 &base_vha->dpc_flags);
3501 }
3502
3503 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3504 "FCoE context reset end.\n");
3505 }
3506 }
3507
3508 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3509 &base_vha->dpc_flags)) {
3510
3511 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3512 "ISP abort scheduled.\n");
3513 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3514 &base_vha->dpc_flags))) {
3515
3516 if (ha->isp_ops->abort_isp(base_vha)) {
3517 /* failed. retry later */
3518 set_bit(ISP_ABORT_NEEDED,
3519 &base_vha->dpc_flags);
3520 }
3521 clear_bit(ABORT_ISP_ACTIVE,
3522 &base_vha->dpc_flags);
3523 }
3524
3525 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3526 "ISP abort end.\n");
3527 }
3528
3529 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3530 qla2x00_update_fcports(base_vha);
3531 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3532 }
3533
3534 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
3535 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3536 "Quiescence mode scheduled.\n");
3537 qla82xx_device_state_handler(base_vha);
3538 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3539 if (!ha->flags.quiesce_owner) {
3540 qla2x00_perform_loop_resync(base_vha);
3541
3542 qla82xx_idc_lock(ha);
3543 qla82xx_clear_qsnt_ready(base_vha);
3544 qla82xx_idc_unlock(ha);
3545 }
3546 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3547 "Quiescence mode end.\n");
3548 }
3549
3550 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3551 &base_vha->dpc_flags) &&
3552 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
3553
3554 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3555 "Reset marker scheduled.\n");
3556 qla2x00_rst_aen(base_vha);
3557 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
3558 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3559 "Reset marker end.\n");
3560 }
3561
3562 /* Retry each device up to login retry count */
3563 if ((test_and_clear_bit(RELOGIN_NEEDED,
3564 &base_vha->dpc_flags)) &&
3565 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3566 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
3567
3568 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3569 "Relogin scheduled.\n");
3570 qla2x00_relogin(base_vha);
3571 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3572 "Relogin end.\n");
3573 }
3574
3575 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3576 &base_vha->dpc_flags)) {
3577
3578 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3579 "Loop resync scheduled.\n");
3580
3581 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
3582 &base_vha->dpc_flags))) {
3583
3584 rval = qla2x00_loop_resync(base_vha);
3585
3586 clear_bit(LOOP_RESYNC_ACTIVE,
3587 &base_vha->dpc_flags);
3588 }
3589
3590 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3591 "Loop resync end.\n");
3592 }
3593
3594 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3595 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3596 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3597 qla2xxx_flash_npiv_conf(base_vha);
3598 }
3599
3600 if (!ha->interrupts_on)
3601 ha->isp_ops->enable_intrs(ha);
3602
3603 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3604 &base_vha->dpc_flags))
3605 ha->isp_ops->beacon_blink(base_vha);
3606
3607 qla2x00_do_dpc_all_vps(base_vha);
3608
3609 ha->dpc_active = 0;
3610 set_current_state(TASK_INTERRUPTIBLE);
3611 } /* End of while(1) */
3612 __set_current_state(TASK_RUNNING);
3613
3614 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3615 "DPC handler exiting.\n");
3616
3617 /*
3618 * Make sure that nobody tries to wake us up again.
3619 */
3620 ha->dpc_active = 0;
3621
3622 /* Cleanup any residual CTX SRBs. */
3623 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3624
3625 return 0;
3626 }
3627
3628 void
3629 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
3630 {
3631 struct qla_hw_data *ha = vha->hw;
3632 struct task_struct *t = ha->dpc_thread;
3633
3634 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
3635 wake_up_process(t);
3636 }
3637
3638 /*
3639 * qla2x00_rst_aen
3640 * Processes asynchronous reset.
3641 *
3642 * Input:
3643 * ha = adapter block pointer.
3644 */
3645 static void
3646 qla2x00_rst_aen(scsi_qla_host_t *vha)
3647 {
3648 if (vha->flags.online && !vha->flags.reset_active &&
3649 !atomic_read(&vha->loop_down_timer) &&
3650 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
3651 do {
3652 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
3653
3654 /*
3655 * Issue marker command only when we are going to start
3656 * the I/O.
3657 */
3658 vha->marker_needed = 1;
3659 } while (!atomic_read(&vha->loop_down_timer) &&
3660 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
3661 }
3662 }
3663
3664 static void
3665 qla2x00_sp_free_dma(srb_t *sp)
3666 {
3667 struct scsi_cmnd *cmd = sp->cmd;
3668 struct qla_hw_data *ha = sp->fcport->vha->hw;
3669
3670 if (sp->flags & SRB_DMA_VALID) {
3671 scsi_dma_unmap(cmd);
3672 sp->flags &= ~SRB_DMA_VALID;
3673 }
3674
3675 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3676 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3677 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3678 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3679 }
3680
3681 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3682 /* List assured to be having elements */
3683 qla2x00_clean_dsd_pool(ha, sp);
3684 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3685 }
3686
3687 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3688 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3689 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3690 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3691 }
3692
3693 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3694 struct ct6_dsd *ctx = sp->ctx;
3695 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3696 ctx->fcp_cmnd_dma);
3697 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3698 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3699 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3700 mempool_free(sp->ctx, ha->ctx_mempool);
3701 sp->ctx = NULL;
3702 }
3703
3704 CMD_SP(cmd) = NULL;
3705 }
3706
3707 static void
3708 qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
3709 {
3710 struct scsi_cmnd *cmd = sp->cmd;
3711
3712 qla2x00_sp_free_dma(sp);
3713 mempool_free(sp, ha->srb_mempool);
3714 cmd->scsi_done(cmd);
3715 }
3716
3717 void
3718 qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3719 {
3720 if (atomic_read(&sp->ref_count) == 0) {
3721 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3722 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3723 sp, sp->cmd);
3724 if (ql2xextended_error_logging & ql_dbg_io)
3725 BUG();
3726 return;
3727 }
3728 if (!atomic_dec_and_test(&sp->ref_count))
3729 return;
3730 qla2x00_sp_final_compl(ha, sp);
3731 }
3732
3733 /**************************************************************************
3734 * qla2x00_timer
3735 *
3736 * Description:
3737 * One second timer
3738 *
3739 * Context: Interrupt
3740 ***************************************************************************/
3741 void
3742 qla2x00_timer(scsi_qla_host_t *vha)
3743 {
3744 unsigned long cpu_flags = 0;
3745 int start_dpc = 0;
3746 int index;
3747 srb_t *sp;
3748 uint16_t w;
3749 struct qla_hw_data *ha = vha->hw;
3750 struct req_que *req;
3751
3752 if (ha->flags.eeh_busy) {
3753 ql_dbg(ql_dbg_timer, vha, 0x6000,
3754 "EEH = %d, restarting timer.\n",
3755 ha->flags.eeh_busy);
3756 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3757 return;
3758 }
3759
3760 /* Hardware read to raise pending EEH errors during mailbox waits. */
3761 if (!pci_channel_offline(ha->pdev))
3762 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
3763
3764 /* Make sure qla82xx_watchdog is run only for physical port */
3765 if (!vha->vp_idx && IS_QLA82XX(ha)) {
3766 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3767 start_dpc++;
3768 qla82xx_watchdog(vha);
3769 }
3770
3771 /* Loop down handler. */
3772 if (atomic_read(&vha->loop_down_timer) > 0 &&
3773 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3774 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
3775 && vha->flags.online) {
3776
3777 if (atomic_read(&vha->loop_down_timer) ==
3778 vha->loop_down_abort_time) {
3779
3780 ql_log(ql_log_info, vha, 0x6008,
3781 "Loop down - aborting the queues before time expires.\n");
3782
3783 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3784 atomic_set(&vha->loop_state, LOOP_DEAD);
3785
3786 /*
3787 * Schedule an ISP abort to return any FCP2-device
3788 * commands.
3789 */
3790 /* NPIV - scan physical port only */
3791 if (!vha->vp_idx) {
3792 spin_lock_irqsave(&ha->hardware_lock,
3793 cpu_flags);
3794 req = ha->req_q_map[0];
3795 for (index = 1;
3796 index < MAX_OUTSTANDING_COMMANDS;
3797 index++) {
3798 fc_port_t *sfcp;
3799
3800 sp = req->outstanding_cmds[index];
3801 if (!sp)
3802 continue;
3803 if (sp->ctx && !IS_PROT_IO(sp))
3804 continue;
3805 sfcp = sp->fcport;
3806 if (!(sfcp->flags & FCF_FCP2_DEVICE))
3807 continue;
3808
3809 if (IS_QLA82XX(ha))
3810 set_bit(FCOE_CTX_RESET_NEEDED,
3811 &vha->dpc_flags);
3812 else
3813 set_bit(ISP_ABORT_NEEDED,
3814 &vha->dpc_flags);
3815 break;
3816 }
3817 spin_unlock_irqrestore(&ha->hardware_lock,
3818 cpu_flags);
3819 }
3820 start_dpc++;
3821 }
3822
3823 /* if the loop has been down for 4 minutes, reinit adapter */
3824 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
3825 if (!(vha->device_flags & DFLG_NO_CABLE)) {
3826 ql_log(ql_log_warn, vha, 0x6009,
3827 "Loop down - aborting ISP.\n");
3828
3829 if (IS_QLA82XX(ha))
3830 set_bit(FCOE_CTX_RESET_NEEDED,
3831 &vha->dpc_flags);
3832 else
3833 set_bit(ISP_ABORT_NEEDED,
3834 &vha->dpc_flags);
3835 }
3836 }
3837 ql_dbg(ql_dbg_timer, vha, 0x600a,
3838 "Loop down - seconds remaining %d.\n",
3839 atomic_read(&vha->loop_down_timer));
3840 }
3841
3842 /* Check if beacon LED needs to be blinked for physical host only */
3843 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
3844 /* There is no beacon_blink function for ISP82xx */
3845 if (!IS_QLA82XX(ha)) {
3846 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3847 start_dpc++;
3848 }
3849 }
3850
3851 /* Process any deferred work. */
3852 if (!list_empty(&vha->work_list))
3853 start_dpc++;
3854
3855 /* Schedule the DPC routine if needed */
3856 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3857 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3858 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
3859 start_dpc ||
3860 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3861 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
3862 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3863 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3864 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3865 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3866 ql_dbg(ql_dbg_timer, vha, 0x600b,
3867 "isp_abort_needed=%d loop_resync_needed=%d "
3868 "fcport_update_needed=%d start_dpc=%d "
3869 "reset_marker_needed=%d",
3870 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3871 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3872 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3873 start_dpc,
3874 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3875 ql_dbg(ql_dbg_timer, vha, 0x600c,
3876 "beacon_blink_needed=%d isp_unrecoverable=%d "
3877 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3878 "relogin_needed=%d.\n",
3879 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3880 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3881 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3882 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3883 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
3884 qla2xxx_wake_dpc(vha);
3885 }
3886
3887 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3888 }
3889
3890 /* Firmware interface routines. */
3891
3892 #define FW_BLOBS 8
3893 #define FW_ISP21XX 0
3894 #define FW_ISP22XX 1
3895 #define FW_ISP2300 2
3896 #define FW_ISP2322 3
3897 #define FW_ISP24XX 4
3898 #define FW_ISP25XX 5
3899 #define FW_ISP81XX 6
3900 #define FW_ISP82XX 7
3901
3902 #define FW_FILE_ISP21XX "ql2100_fw.bin"
3903 #define FW_FILE_ISP22XX "ql2200_fw.bin"
3904 #define FW_FILE_ISP2300 "ql2300_fw.bin"
3905 #define FW_FILE_ISP2322 "ql2322_fw.bin"
3906 #define FW_FILE_ISP24XX "ql2400_fw.bin"
3907 #define FW_FILE_ISP25XX "ql2500_fw.bin"
3908 #define FW_FILE_ISP81XX "ql8100_fw.bin"
3909 #define FW_FILE_ISP82XX "ql8200_fw.bin"
3910
3911 static DEFINE_MUTEX(qla_fw_lock);
3912
3913 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
3914 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3915 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3916 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3917 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3918 { .name = FW_FILE_ISP24XX, },
3919 { .name = FW_FILE_ISP25XX, },
3920 { .name = FW_FILE_ISP81XX, },
3921 { .name = FW_FILE_ISP82XX, },
3922 };
3923
3924 struct fw_blob *
3925 qla2x00_request_firmware(scsi_qla_host_t *vha)
3926 {
3927 struct qla_hw_data *ha = vha->hw;
3928 struct fw_blob *blob;
3929
3930 blob = NULL;
3931 if (IS_QLA2100(ha)) {
3932 blob = &qla_fw_blobs[FW_ISP21XX];
3933 } else if (IS_QLA2200(ha)) {
3934 blob = &qla_fw_blobs[FW_ISP22XX];
3935 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3936 blob = &qla_fw_blobs[FW_ISP2300];
3937 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
3938 blob = &qla_fw_blobs[FW_ISP2322];
3939 } else if (IS_QLA24XX_TYPE(ha)) {
3940 blob = &qla_fw_blobs[FW_ISP24XX];
3941 } else if (IS_QLA25XX(ha)) {
3942 blob = &qla_fw_blobs[FW_ISP25XX];
3943 } else if (IS_QLA81XX(ha)) {
3944 blob = &qla_fw_blobs[FW_ISP81XX];
3945 } else if (IS_QLA82XX(ha)) {
3946 blob = &qla_fw_blobs[FW_ISP82XX];
3947 }
3948
3949 mutex_lock(&qla_fw_lock);
3950 if (blob->fw)
3951 goto out;
3952
3953 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
3954 ql_log(ql_log_warn, vha, 0x0063,
3955 "Failed to load firmware image (%s).\n", blob->name);
3956 blob->fw = NULL;
3957 blob = NULL;
3958 goto out;
3959 }
3960
3961 out:
3962 mutex_unlock(&qla_fw_lock);
3963 return blob;
3964 }
3965
3966 static void
3967 qla2x00_release_firmware(void)
3968 {
3969 int idx;
3970
3971 mutex_lock(&qla_fw_lock);
3972 for (idx = 0; idx < FW_BLOBS; idx++)
3973 if (qla_fw_blobs[idx].fw)
3974 release_firmware(qla_fw_blobs[idx].fw);
3975 mutex_unlock(&qla_fw_lock);
3976 }
3977
3978 static pci_ers_result_t
3979 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3980 {
3981 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
3982 struct qla_hw_data *ha = vha->hw;
3983
3984 ql_dbg(ql_dbg_aer, vha, 0x9000,
3985 "PCI error detected, state %x.\n", state);
3986
3987 switch (state) {
3988 case pci_channel_io_normal:
3989 ha->flags.eeh_busy = 0;
3990 return PCI_ERS_RESULT_CAN_RECOVER;
3991 case pci_channel_io_frozen:
3992 ha->flags.eeh_busy = 1;
3993 /* For ISP82XX complete any pending mailbox cmd */
3994 if (IS_QLA82XX(ha)) {
3995 ha->flags.isp82xx_fw_hung = 1;
3996 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
3997 qla82xx_clear_pending_mbx(vha);
3998 }
3999 qla2x00_free_irqs(vha);
4000 pci_disable_device(pdev);
4001 /* Return back all IOs */
4002 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4003 return PCI_ERS_RESULT_NEED_RESET;
4004 case pci_channel_io_perm_failure:
4005 ha->flags.pci_channel_io_perm_failure = 1;
4006 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4007 return PCI_ERS_RESULT_DISCONNECT;
4008 }
4009 return PCI_ERS_RESULT_NEED_RESET;
4010 }
4011
4012 static pci_ers_result_t
4013 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4014 {
4015 int risc_paused = 0;
4016 uint32_t stat;
4017 unsigned long flags;
4018 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4019 struct qla_hw_data *ha = base_vha->hw;
4020 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4021 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4022
4023 if (IS_QLA82XX(ha))
4024 return PCI_ERS_RESULT_RECOVERED;
4025
4026 spin_lock_irqsave(&ha->hardware_lock, flags);
4027 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4028 stat = RD_REG_DWORD(&reg->hccr);
4029 if (stat & HCCR_RISC_PAUSE)
4030 risc_paused = 1;
4031 } else if (IS_QLA23XX(ha)) {
4032 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4033 if (stat & HSR_RISC_PAUSED)
4034 risc_paused = 1;
4035 } else if (IS_FWI2_CAPABLE(ha)) {
4036 stat = RD_REG_DWORD(&reg24->host_status);
4037 if (stat & HSRX_RISC_PAUSED)
4038 risc_paused = 1;
4039 }
4040 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4041
4042 if (risc_paused) {
4043 ql_log(ql_log_info, base_vha, 0x9003,
4044 "RISC paused -- mmio_enabled, Dumping firmware.\n");
4045 ha->isp_ops->fw_dump(base_vha, 0);
4046
4047 return PCI_ERS_RESULT_NEED_RESET;
4048 } else
4049 return PCI_ERS_RESULT_RECOVERED;
4050 }
4051
4052 uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4053 {
4054 uint32_t rval = QLA_FUNCTION_FAILED;
4055 uint32_t drv_active = 0;
4056 struct qla_hw_data *ha = base_vha->hw;
4057 int fn;
4058 struct pci_dev *other_pdev = NULL;
4059
4060 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4061 "Entered %s.\n", __func__);
4062
4063 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4064
4065 if (base_vha->flags.online) {
4066 /* Abort all outstanding commands,
4067 * so as to be requeued later */
4068 qla2x00_abort_isp_cleanup(base_vha);
4069 }
4070
4071
4072 fn = PCI_FUNC(ha->pdev->devfn);
4073 while (fn > 0) {
4074 fn--;
4075 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4076 "Finding pci device at function = 0x%x.\n", fn);
4077 other_pdev =
4078 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4079 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4080 fn));
4081
4082 if (!other_pdev)
4083 continue;
4084 if (atomic_read(&other_pdev->enable_cnt)) {
4085 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4086 "Found PCI func available and enable at 0x%x.\n",
4087 fn);
4088 pci_dev_put(other_pdev);
4089 break;
4090 }
4091 pci_dev_put(other_pdev);
4092 }
4093
4094 if (!fn) {
4095 /* Reset owner */
4096 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4097 "This devfn is reset owner = 0x%x.\n",
4098 ha->pdev->devfn);
4099 qla82xx_idc_lock(ha);
4100
4101 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4102 QLA82XX_DEV_INITIALIZING);
4103
4104 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4105 QLA82XX_IDC_VERSION);
4106
4107 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
4108 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4109 "drv_active = 0x%x.\n", drv_active);
4110
4111 qla82xx_idc_unlock(ha);
4112 /* Reset if device is not already reset
4113 * drv_active would be 0 if a reset has already been done
4114 */
4115 if (drv_active)
4116 rval = qla82xx_start_firmware(base_vha);
4117 else
4118 rval = QLA_SUCCESS;
4119 qla82xx_idc_lock(ha);
4120
4121 if (rval != QLA_SUCCESS) {
4122 ql_log(ql_log_info, base_vha, 0x900b,
4123 "HW State: FAILED.\n");
4124 qla82xx_clear_drv_active(ha);
4125 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4126 QLA82XX_DEV_FAILED);
4127 } else {
4128 ql_log(ql_log_info, base_vha, 0x900c,
4129 "HW State: READY.\n");
4130 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4131 QLA82XX_DEV_READY);
4132 qla82xx_idc_unlock(ha);
4133 ha->flags.isp82xx_fw_hung = 0;
4134 rval = qla82xx_restart_isp(base_vha);
4135 qla82xx_idc_lock(ha);
4136 /* Clear driver state register */
4137 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4138 qla82xx_set_drv_active(base_vha);
4139 }
4140 qla82xx_idc_unlock(ha);
4141 } else {
4142 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4143 "This devfn is not reset owner = 0x%x.\n",
4144 ha->pdev->devfn);
4145 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4146 QLA82XX_DEV_READY)) {
4147 ha->flags.isp82xx_fw_hung = 0;
4148 rval = qla82xx_restart_isp(base_vha);
4149 qla82xx_idc_lock(ha);
4150 qla82xx_set_drv_active(base_vha);
4151 qla82xx_idc_unlock(ha);
4152 }
4153 }
4154 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4155
4156 return rval;
4157 }
4158
4159 static pci_ers_result_t
4160 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4161 {
4162 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
4163 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4164 struct qla_hw_data *ha = base_vha->hw;
4165 struct rsp_que *rsp;
4166 int rc, retries = 10;
4167
4168 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4169 "Slot Reset.\n");
4170
4171 /* Workaround: qla2xxx driver which access hardware earlier
4172 * needs error state to be pci_channel_io_online.
4173 * Otherwise mailbox command timesout.
4174 */
4175 pdev->error_state = pci_channel_io_normal;
4176
4177 pci_restore_state(pdev);
4178
4179 /* pci_restore_state() clears the saved_state flag of the device
4180 * save restored state which resets saved_state flag
4181 */
4182 pci_save_state(pdev);
4183
4184 if (ha->mem_only)
4185 rc = pci_enable_device_mem(pdev);
4186 else
4187 rc = pci_enable_device(pdev);
4188
4189 if (rc) {
4190 ql_log(ql_log_warn, base_vha, 0x9005,
4191 "Can't re-enable PCI device after reset.\n");
4192 goto exit_slot_reset;
4193 }
4194
4195 rsp = ha->rsp_q_map[0];
4196 if (qla2x00_request_irqs(ha, rsp))
4197 goto exit_slot_reset;
4198
4199 if (ha->isp_ops->pci_config(base_vha))
4200 goto exit_slot_reset;
4201
4202 if (IS_QLA82XX(ha)) {
4203 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4204 ret = PCI_ERS_RESULT_RECOVERED;
4205 goto exit_slot_reset;
4206 } else
4207 goto exit_slot_reset;
4208 }
4209
4210 while (ha->flags.mbox_busy && retries--)
4211 msleep(1000);
4212
4213 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4214 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
4215 ret = PCI_ERS_RESULT_RECOVERED;
4216 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4217
4218
4219 exit_slot_reset:
4220 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4221 "slot_reset return %x.\n", ret);
4222
4223 return ret;
4224 }
4225
4226 static void
4227 qla2xxx_pci_resume(struct pci_dev *pdev)
4228 {
4229 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4230 struct qla_hw_data *ha = base_vha->hw;
4231 int ret;
4232
4233 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4234 "pci_resume.\n");
4235
4236 ret = qla2x00_wait_for_hba_online(base_vha);
4237 if (ret != QLA_SUCCESS) {
4238 ql_log(ql_log_fatal, base_vha, 0x9002,
4239 "The device failed to resume I/O from slot/link_reset.\n");
4240 }
4241
4242 pci_cleanup_aer_uncorrect_error_status(pdev);
4243
4244 ha->flags.eeh_busy = 0;
4245 }
4246
4247 static struct pci_error_handlers qla2xxx_err_handler = {
4248 .error_detected = qla2xxx_pci_error_detected,
4249 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4250 .slot_reset = qla2xxx_pci_slot_reset,
4251 .resume = qla2xxx_pci_resume,
4252 };
4253
4254 static struct pci_device_id qla2xxx_pci_tbl[] = {
4255 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4256 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4257 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4258 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4259 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4260 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4261 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4262 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4263 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4264 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
4265 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4266 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
4267 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
4268 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
4269 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
4270 { 0 },
4271 };
4272 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4273
4274 static struct pci_driver qla2xxx_pci_driver = {
4275 .name = QLA2XXX_DRIVER_NAME,
4276 .driver = {
4277 .owner = THIS_MODULE,
4278 },
4279 .id_table = qla2xxx_pci_tbl,
4280 .probe = qla2x00_probe_one,
4281 .remove = qla2x00_remove_one,
4282 .shutdown = qla2x00_shutdown,
4283 .err_handler = &qla2xxx_err_handler,
4284 };
4285
4286 static struct file_operations apidev_fops = {
4287 .owner = THIS_MODULE,
4288 .llseek = noop_llseek,
4289 };
4290
4291 /**
4292 * qla2x00_module_init - Module initialization.
4293 **/
4294 static int __init
4295 qla2x00_module_init(void)
4296 {
4297 int ret = 0;
4298
4299 /* Allocate cache for SRBs. */
4300 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
4301 SLAB_HWCACHE_ALIGN, NULL);
4302 if (srb_cachep == NULL) {
4303 ql_log(ql_log_fatal, NULL, 0x0001,
4304 "Unable to allocate SRB cache...Failing load!.\n");
4305 return -ENOMEM;
4306 }
4307
4308 /* Derive version string. */
4309 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
4310 if (ql2xextended_error_logging)
4311 strcat(qla2x00_version_str, "-debug");
4312
4313 qla2xxx_transport_template =
4314 fc_attach_transport(&qla2xxx_transport_functions);
4315 if (!qla2xxx_transport_template) {
4316 kmem_cache_destroy(srb_cachep);
4317 ql_log(ql_log_fatal, NULL, 0x0002,
4318 "fc_attach_transport failed...Failing load!.\n");
4319 return -ENODEV;
4320 }
4321
4322 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4323 if (apidev_major < 0) {
4324 ql_log(ql_log_fatal, NULL, 0x0003,
4325 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
4326 }
4327
4328 qla2xxx_transport_vport_template =
4329 fc_attach_transport(&qla2xxx_transport_vport_functions);
4330 if (!qla2xxx_transport_vport_template) {
4331 kmem_cache_destroy(srb_cachep);
4332 fc_release_transport(qla2xxx_transport_template);
4333 ql_log(ql_log_fatal, NULL, 0x0004,
4334 "fc_attach_transport vport failed...Failing load!.\n");
4335 return -ENODEV;
4336 }
4337 ql_log(ql_log_info, NULL, 0x0005,
4338 "QLogic Fibre Channel HBA Driver: %s.\n",
4339 qla2x00_version_str);
4340 ret = pci_register_driver(&qla2xxx_pci_driver);
4341 if (ret) {
4342 kmem_cache_destroy(srb_cachep);
4343 fc_release_transport(qla2xxx_transport_template);
4344 fc_release_transport(qla2xxx_transport_vport_template);
4345 ql_log(ql_log_fatal, NULL, 0x0006,
4346 "pci_register_driver failed...ret=%d Failing load!.\n",
4347 ret);
4348 }
4349 return ret;
4350 }
4351
4352 /**
4353 * qla2x00_module_exit - Module cleanup.
4354 **/
4355 static void __exit
4356 qla2x00_module_exit(void)
4357 {
4358 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
4359 pci_unregister_driver(&qla2xxx_pci_driver);
4360 qla2x00_release_firmware();
4361 kmem_cache_destroy(srb_cachep);
4362 if (ctx_cachep)
4363 kmem_cache_destroy(ctx_cachep);
4364 fc_release_transport(qla2xxx_transport_template);
4365 fc_release_transport(qla2xxx_transport_vport_template);
4366 }
4367
4368 module_init(qla2x00_module_init);
4369 module_exit(qla2x00_module_exit);
4370
4371 MODULE_AUTHOR("QLogic Corporation");
4372 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4373 MODULE_LICENSE("GPL");
4374 MODULE_VERSION(QLA2XXX_VERSION);
4375 MODULE_FIRMWARE(FW_FILE_ISP21XX);
4376 MODULE_FIRMWARE(FW_FILE_ISP22XX);
4377 MODULE_FIRMWARE(FW_FILE_ISP2300);
4378 MODULE_FIRMWARE(FW_FILE_ISP2322);
4379 MODULE_FIRMWARE(FW_FILE_ISP24XX);
4380 MODULE_FIRMWARE(FW_FILE_ISP25XX);
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