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bnx2x: Add new 57840 device IDs
[linux-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blob9aaf863b4237679d36ec933dd93a5fdb9655ab13
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
78
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
81
82 static char version[] __devinitdata =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
96
97
98 int num_queues;
99 module_param(num_queues, int, 0);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
102
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
109 int int_mode;
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 "(1 INT#x; 2 MSI)");
113
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121
122 static int debug;
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125
126
127
128 struct workqueue_struct *bnx2x_wq;
129
130 enum bnx2x_board_type {
131 BCM57710 = 0,
132 BCM57711,
133 BCM57711E,
134 BCM57712,
135 BCM57712_MF,
136 BCM57800,
137 BCM57800_MF,
138 BCM57810,
139 BCM57810_MF,
140 BCM57840_O,
141 BCM57840_4_10,
142 BCM57840_2_20,
143 BCM57840_MFO,
144 BCM57840_MF,
145 BCM57811,
146 BCM57811_MF
147 };
148
149 /* indexed by board_type, above */
150 static struct {
151 char *name;
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
169 };
170
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
218 #endif
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
220 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
221 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
222 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
223 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
224 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
225 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
226 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
227 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
228 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
229 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
230 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
231 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
236 { 0 }
237 };
238
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
240
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
248
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
250 u32 addr, dma_addr_t mapping)
251 {
252 REG_WR(bp, addr, U64_LO(mapping));
253 REG_WR(bp, addr + 4, U64_HI(mapping));
254 }
255
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257 dma_addr_t mapping, u16 abs_fid)
258 {
259 u32 addr = XSEM_REG_FAST_MEMORY +
260 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
261
262 __storm_memset_dma_mapping(bp, addr, mapping);
263 }
264
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
266 u16 pf_id)
267 {
268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
269 pf_id);
270 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
271 pf_id);
272 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
273 pf_id);
274 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
275 pf_id);
276 }
277
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
279 u8 enable)
280 {
281 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
282 enable);
283 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
284 enable);
285 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
286 enable);
287 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
288 enable);
289 }
290
291 static void storm_memset_eq_data(struct bnx2x *bp,
292 struct event_ring_data *eq_data,
293 u16 pfid)
294 {
295 size_t size = sizeof(struct event_ring_data);
296
297 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
298
299 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
300 }
301
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
303 u16 pfid)
304 {
305 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
306 REG_WR16(bp, addr, eq_prod);
307 }
308
309 /* used only at init
310 * locking is done by mcp
311 */
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
313 {
314 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
317 PCICFG_VENDOR_ID_OFFSET);
318 }
319
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
321 {
322 u32 val;
323
324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
327 PCICFG_VENDOR_ID_OFFSET);
328
329 return val;
330 }
331
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
337
338
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
341 {
342 u32 cmd_offset;
343 int i;
344
345 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
348 }
349 REG_WR(bp, dmae_reg_go_c[idx], 1);
350 }
351
352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
353 {
354 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
355 DMAE_CMD_C_ENABLE);
356 }
357
358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
359 {
360 return opcode & ~DMAE_CMD_SRC_RESET;
361 }
362
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364 bool with_comp, u8 comp_type)
365 {
366 u32 opcode = 0;
367
368 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369 (dst_type << DMAE_COMMAND_DST_SHIFT));
370
371 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
372
373 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
375 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
376 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
377
378 #ifdef __BIG_ENDIAN
379 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
380 #else
381 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
382 #endif
383 if (with_comp)
384 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
385 return opcode;
386 }
387
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389 struct dmae_command *dmae,
390 u8 src_type, u8 dst_type)
391 {
392 memset(dmae, 0, sizeof(struct dmae_command));
393
394 /* set the opcode */
395 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396 true, DMAE_COMP_PCI);
397
398 /* fill in the completion parameters */
399 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401 dmae->comp_val = DMAE_COMP_VAL;
402 }
403
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406 struct dmae_command *dmae)
407 {
408 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
410 int rc = 0;
411
412 /*
413 * Lock the dmae channel. Disable BHs to prevent a dead-lock
414 * as long as this code is called both from syscall context and
415 * from ndo_set_rx_mode() flow that may be called from BH.
416 */
417 spin_lock_bh(&bp->dmae_lock);
418
419 /* reset completion */
420 *wb_comp = 0;
421
422 /* post the command on the channel used for initializations */
423 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
424
425 /* wait for completion */
426 udelay(5);
427 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
428
429 if (!cnt ||
430 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
431 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
432 BNX2X_ERR("DMAE timeout!\n");
433 rc = DMAE_TIMEOUT;
434 goto unlock;
435 }
436 cnt--;
437 udelay(50);
438 }
439 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440 BNX2X_ERR("DMAE PCI error!\n");
441 rc = DMAE_PCI_ERROR;
442 }
443
444 unlock:
445 spin_unlock_bh(&bp->dmae_lock);
446 return rc;
447 }
448
449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
450 u32 len32)
451 {
452 struct dmae_command dmae;
453
454 if (!bp->dmae_ready) {
455 u32 *data = bnx2x_sp(bp, wb_data[0]);
456
457 if (CHIP_IS_E1(bp))
458 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
459 else
460 bnx2x_init_str_wr(bp, dst_addr, data, len32);
461 return;
462 }
463
464 /* set opcode and fixed command fields */
465 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
466
467 /* fill in addresses and len */
468 dmae.src_addr_lo = U64_LO(dma_addr);
469 dmae.src_addr_hi = U64_HI(dma_addr);
470 dmae.dst_addr_lo = dst_addr >> 2;
471 dmae.dst_addr_hi = 0;
472 dmae.len = len32;
473
474 /* issue the command and wait for completion */
475 bnx2x_issue_dmae_with_comp(bp, &dmae);
476 }
477
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
479 {
480 struct dmae_command dmae;
481
482 if (!bp->dmae_ready) {
483 u32 *data = bnx2x_sp(bp, wb_data[0]);
484 int i;
485
486 if (CHIP_IS_E1(bp))
487 for (i = 0; i < len32; i++)
488 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
489 else
490 for (i = 0; i < len32; i++)
491 data[i] = REG_RD(bp, src_addr + i*4);
492
493 return;
494 }
495
496 /* set opcode and fixed command fields */
497 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
498
499 /* fill in addresses and len */
500 dmae.src_addr_lo = src_addr >> 2;
501 dmae.src_addr_hi = 0;
502 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
504 dmae.len = len32;
505
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
508 }
509
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
511 u32 addr, u32 len)
512 {
513 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
514 int offset = 0;
515
516 while (len > dmae_wr_max) {
517 bnx2x_write_dmae(bp, phys_addr + offset,
518 addr + offset, dmae_wr_max);
519 offset += dmae_wr_max * 4;
520 len -= dmae_wr_max;
521 }
522
523 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
524 }
525
526 static int bnx2x_mc_assert(struct bnx2x *bp)
527 {
528 char last_idx;
529 int i, rc = 0;
530 u32 row0, row1, row2, row3;
531
532 /* XSTORM */
533 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
534 XSTORM_ASSERT_LIST_INDEX_OFFSET);
535 if (last_idx)
536 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
537
538 /* print the asserts */
539 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
540
541 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
542 XSTORM_ASSERT_LIST_OFFSET(i));
543 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
544 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
545 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
547 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
549
550 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552 i, row3, row2, row1, row0);
553 rc++;
554 } else {
555 break;
556 }
557 }
558
559 /* TSTORM */
560 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
561 TSTORM_ASSERT_LIST_INDEX_OFFSET);
562 if (last_idx)
563 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
564
565 /* print the asserts */
566 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
567
568 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
569 TSTORM_ASSERT_LIST_OFFSET(i));
570 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
571 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
572 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
574 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
576
577 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i, row3, row2, row1, row0);
580 rc++;
581 } else {
582 break;
583 }
584 }
585
586 /* CSTORM */
587 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
588 CSTORM_ASSERT_LIST_INDEX_OFFSET);
589 if (last_idx)
590 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
591
592 /* print the asserts */
593 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
594
595 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
596 CSTORM_ASSERT_LIST_OFFSET(i));
597 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
598 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
599 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
601 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
603
604 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606 i, row3, row2, row1, row0);
607 rc++;
608 } else {
609 break;
610 }
611 }
612
613 /* USTORM */
614 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
615 USTORM_ASSERT_LIST_INDEX_OFFSET);
616 if (last_idx)
617 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
618
619 /* print the asserts */
620 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
621
622 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
623 USTORM_ASSERT_LIST_OFFSET(i));
624 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
625 USTORM_ASSERT_LIST_OFFSET(i) + 4);
626 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_OFFSET(i) + 8);
628 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629 USTORM_ASSERT_LIST_OFFSET(i) + 12);
630
631 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633 i, row3, row2, row1, row0);
634 rc++;
635 } else {
636 break;
637 }
638 }
639
640 return rc;
641 }
642
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
644 {
645 u32 addr, val;
646 u32 mark, offset;
647 __be32 data[9];
648 int word;
649 u32 trace_shmem_base;
650 if (BP_NOMCP(bp)) {
651 BNX2X_ERR("NO MCP - can not dump\n");
652 return;
653 }
654 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655 (bp->common.bc_ver & 0xff0000) >> 16,
656 (bp->common.bc_ver & 0xff00) >> 8,
657 (bp->common.bc_ver & 0xff));
658
659 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
660 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
661 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
662
663 if (BP_PATH(bp) == 0)
664 trace_shmem_base = bp->common.shmem_base;
665 else
666 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667 addr = trace_shmem_base - 0x800;
668
669 /* validate TRCB signature */
670 mark = REG_RD(bp, addr);
671 if (mark != MFW_TRACE_SIGNATURE) {
672 BNX2X_ERR("Trace buffer signature is missing.");
673 return ;
674 }
675
676 /* read cyclic buffer pointer */
677 addr += 4;
678 mark = REG_RD(bp, addr);
679 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
680 + ((mark + 0x3) & ~0x3) - 0x08000000;
681 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
682
683 printk("%s", lvl);
684 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685 for (word = 0; word < 8; word++)
686 data[word] = htonl(REG_RD(bp, offset + 4*word));
687 data[8] = 0x0;
688 pr_cont("%s", (char *)data);
689 }
690 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691 for (word = 0; word < 8; word++)
692 data[word] = htonl(REG_RD(bp, offset + 4*word));
693 data[8] = 0x0;
694 pr_cont("%s", (char *)data);
695 }
696 printk("%s" "end of fw dump\n", lvl);
697 }
698
699 static void bnx2x_fw_dump(struct bnx2x *bp)
700 {
701 bnx2x_fw_dump_lvl(bp, KERN_ERR);
702 }
703
704 void bnx2x_panic_dump(struct bnx2x *bp)
705 {
706 int i;
707 u16 j;
708 struct hc_sp_status_block_data sp_sb_data;
709 int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711 u16 start = 0, end = 0;
712 u8 cos;
713 #endif
714
715 bp->stats_state = STATS_STATE_DISABLED;
716 bp->eth_stats.unrecoverable_error++;
717 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
718
719 BNX2X_ERR("begin crash dump -----------------\n");
720
721 /* Indices */
722 /* Common */
723 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724 bp->def_idx, bp->def_att_idx, bp->attn_state,
725 bp->spq_prod_idx, bp->stats_counter);
726 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727 bp->def_status_blk->atten_status_block.attn_bits,
728 bp->def_status_blk->atten_status_block.attn_bits_ack,
729 bp->def_status_blk->atten_status_block.status_block_id,
730 bp->def_status_blk->atten_status_block.attn_bits_index);
731 BNX2X_ERR(" def (");
732 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
733 pr_cont("0x%x%s",
734 bp->def_status_blk->sp_sb.index_values[i],
735 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
736
737 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
739 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
740 i*sizeof(u32));
741
742 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743 sp_sb_data.igu_sb_id,
744 sp_sb_data.igu_seg_id,
745 sp_sb_data.p_func.pf_id,
746 sp_sb_data.p_func.vnic_id,
747 sp_sb_data.p_func.vf_id,
748 sp_sb_data.p_func.vf_valid,
749 sp_sb_data.state);
750
751
752 for_each_eth_queue(bp, i) {
753 struct bnx2x_fastpath *fp = &bp->fp[i];
754 int loop;
755 struct hc_status_block_data_e2 sb_data_e2;
756 struct hc_status_block_data_e1x sb_data_e1x;
757 struct hc_status_block_sm *hc_sm_p =
758 CHIP_IS_E1x(bp) ?
759 sb_data_e1x.common.state_machine :
760 sb_data_e2.common.state_machine;
761 struct hc_index_data *hc_index_p =
762 CHIP_IS_E1x(bp) ?
763 sb_data_e1x.index_data :
764 sb_data_e2.index_data;
765 u8 data_size, cos;
766 u32 *sb_data_p;
767 struct bnx2x_fp_txdata txdata;
768
769 /* Rx */
770 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771 i, fp->rx_bd_prod, fp->rx_bd_cons,
772 fp->rx_comp_prod,
773 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775 fp->rx_sge_prod, fp->last_max_sge,
776 le16_to_cpu(fp->fp_hc_idx));
777
778 /* Tx */
779 for_each_cos_in_tx_queue(fp, cos)
780 {
781 txdata = *fp->txdata_ptr[cos];
782 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783 i, txdata.tx_pkt_prod,
784 txdata.tx_pkt_cons, txdata.tx_bd_prod,
785 txdata.tx_bd_cons,
786 le16_to_cpu(*txdata.tx_cons_sb));
787 }
788
789 loop = CHIP_IS_E1x(bp) ?
790 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
791
792 /* host sb data */
793
794 #ifdef BCM_CNIC
795 if (IS_FCOE_FP(fp))
796 continue;
797 #endif
798 BNX2X_ERR(" run indexes (");
799 for (j = 0; j < HC_SB_MAX_SM; j++)
800 pr_cont("0x%x%s",
801 fp->sb_running_index[j],
802 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
803
804 BNX2X_ERR(" indexes (");
805 for (j = 0; j < loop; j++)
806 pr_cont("0x%x%s",
807 fp->sb_index_values[j],
808 (j == loop - 1) ? ")" : " ");
809 /* fw sb data */
810 data_size = CHIP_IS_E1x(bp) ?
811 sizeof(struct hc_status_block_data_e1x) :
812 sizeof(struct hc_status_block_data_e2);
813 data_size /= sizeof(u32);
814 sb_data_p = CHIP_IS_E1x(bp) ?
815 (u32 *)&sb_data_e1x :
816 (u32 *)&sb_data_e2;
817 /* copy sb data in here */
818 for (j = 0; j < data_size; j++)
819 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
820 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
821 j * sizeof(u32));
822
823 if (!CHIP_IS_E1x(bp)) {
824 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
825 sb_data_e2.common.p_func.pf_id,
826 sb_data_e2.common.p_func.vf_id,
827 sb_data_e2.common.p_func.vf_valid,
828 sb_data_e2.common.p_func.vnic_id,
829 sb_data_e2.common.same_igu_sb_1b,
830 sb_data_e2.common.state);
831 } else {
832 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
833 sb_data_e1x.common.p_func.pf_id,
834 sb_data_e1x.common.p_func.vf_id,
835 sb_data_e1x.common.p_func.vf_valid,
836 sb_data_e1x.common.p_func.vnic_id,
837 sb_data_e1x.common.same_igu_sb_1b,
838 sb_data_e1x.common.state);
839 }
840
841 /* SB_SMs data */
842 for (j = 0; j < HC_SB_MAX_SM; j++) {
843 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
844 j, hc_sm_p[j].__flags,
845 hc_sm_p[j].igu_sb_id,
846 hc_sm_p[j].igu_seg_id,
847 hc_sm_p[j].time_to_expire,
848 hc_sm_p[j].timer_value);
849 }
850
851 /* Indecies data */
852 for (j = 0; j < loop; j++) {
853 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
854 hc_index_p[j].flags,
855 hc_index_p[j].timeout);
856 }
857 }
858
859 #ifdef BNX2X_STOP_ON_ERROR
860 /* Rings */
861 /* Rx */
862 for_each_rx_queue(bp, i) {
863 struct bnx2x_fastpath *fp = &bp->fp[i];
864
865 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
866 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
867 for (j = start; j != end; j = RX_BD(j + 1)) {
868 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
869 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
870
871 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
872 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
873 }
874
875 start = RX_SGE(fp->rx_sge_prod);
876 end = RX_SGE(fp->last_max_sge);
877 for (j = start; j != end; j = RX_SGE(j + 1)) {
878 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
879 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
880
881 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
882 i, j, rx_sge[1], rx_sge[0], sw_page->page);
883 }
884
885 start = RCQ_BD(fp->rx_comp_cons - 10);
886 end = RCQ_BD(fp->rx_comp_cons + 503);
887 for (j = start; j != end; j = RCQ_BD(j + 1)) {
888 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
889
890 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
891 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
892 }
893 }
894
895 /* Tx */
896 for_each_tx_queue(bp, i) {
897 struct bnx2x_fastpath *fp = &bp->fp[i];
898 for_each_cos_in_tx_queue(fp, cos) {
899 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
900
901 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
902 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
903 for (j = start; j != end; j = TX_BD(j + 1)) {
904 struct sw_tx_bd *sw_bd =
905 &txdata->tx_buf_ring[j];
906
907 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
908 i, cos, j, sw_bd->skb,
909 sw_bd->first_bd);
910 }
911
912 start = TX_BD(txdata->tx_bd_cons - 10);
913 end = TX_BD(txdata->tx_bd_cons + 254);
914 for (j = start; j != end; j = TX_BD(j + 1)) {
915 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
916
917 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
918 i, cos, j, tx_bd[0], tx_bd[1],
919 tx_bd[2], tx_bd[3]);
920 }
921 }
922 }
923 #endif
924 bnx2x_fw_dump(bp);
925 bnx2x_mc_assert(bp);
926 BNX2X_ERR("end crash dump -----------------\n");
927 }
928
929 /*
930 * FLR Support for E2
931 *
932 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
933 * initialization.
934 */
935 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
936 #define FLR_WAIT_INTERVAL 50 /* usec */
937 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
938
939 struct pbf_pN_buf_regs {
940 int pN;
941 u32 init_crd;
942 u32 crd;
943 u32 crd_freed;
944 };
945
946 struct pbf_pN_cmd_regs {
947 int pN;
948 u32 lines_occup;
949 u32 lines_freed;
950 };
951
952 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
953 struct pbf_pN_buf_regs *regs,
954 u32 poll_count)
955 {
956 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
957 u32 cur_cnt = poll_count;
958
959 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
960 crd = crd_start = REG_RD(bp, regs->crd);
961 init_crd = REG_RD(bp, regs->init_crd);
962
963 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
964 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
965 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
966
967 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
968 (init_crd - crd_start))) {
969 if (cur_cnt--) {
970 udelay(FLR_WAIT_INTERVAL);
971 crd = REG_RD(bp, regs->crd);
972 crd_freed = REG_RD(bp, regs->crd_freed);
973 } else {
974 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
975 regs->pN);
976 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
977 regs->pN, crd);
978 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
979 regs->pN, crd_freed);
980 break;
981 }
982 }
983 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
984 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
985 }
986
987 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
988 struct pbf_pN_cmd_regs *regs,
989 u32 poll_count)
990 {
991 u32 occup, to_free, freed, freed_start;
992 u32 cur_cnt = poll_count;
993
994 occup = to_free = REG_RD(bp, regs->lines_occup);
995 freed = freed_start = REG_RD(bp, regs->lines_freed);
996
997 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
998 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
999
1000 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1001 if (cur_cnt--) {
1002 udelay(FLR_WAIT_INTERVAL);
1003 occup = REG_RD(bp, regs->lines_occup);
1004 freed = REG_RD(bp, regs->lines_freed);
1005 } else {
1006 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1007 regs->pN);
1008 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1009 regs->pN, occup);
1010 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1011 regs->pN, freed);
1012 break;
1013 }
1014 }
1015 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1016 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1017 }
1018
1019 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1020 u32 expected, u32 poll_count)
1021 {
1022 u32 cur_cnt = poll_count;
1023 u32 val;
1024
1025 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1026 udelay(FLR_WAIT_INTERVAL);
1027
1028 return val;
1029 }
1030
1031 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1032 char *msg, u32 poll_cnt)
1033 {
1034 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1035 if (val != 0) {
1036 BNX2X_ERR("%s usage count=%d\n", msg, val);
1037 return 1;
1038 }
1039 return 0;
1040 }
1041
1042 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1043 {
1044 /* adjust polling timeout */
1045 if (CHIP_REV_IS_EMUL(bp))
1046 return FLR_POLL_CNT * 2000;
1047
1048 if (CHIP_REV_IS_FPGA(bp))
1049 return FLR_POLL_CNT * 120;
1050
1051 return FLR_POLL_CNT;
1052 }
1053
1054 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1055 {
1056 struct pbf_pN_cmd_regs cmd_regs[] = {
1057 {0, (CHIP_IS_E3B0(bp)) ?
1058 PBF_REG_TQ_OCCUPANCY_Q0 :
1059 PBF_REG_P0_TQ_OCCUPANCY,
1060 (CHIP_IS_E3B0(bp)) ?
1061 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1062 PBF_REG_P0_TQ_LINES_FREED_CNT},
1063 {1, (CHIP_IS_E3B0(bp)) ?
1064 PBF_REG_TQ_OCCUPANCY_Q1 :
1065 PBF_REG_P1_TQ_OCCUPANCY,
1066 (CHIP_IS_E3B0(bp)) ?
1067 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1068 PBF_REG_P1_TQ_LINES_FREED_CNT},
1069 {4, (CHIP_IS_E3B0(bp)) ?
1070 PBF_REG_TQ_OCCUPANCY_LB_Q :
1071 PBF_REG_P4_TQ_OCCUPANCY,
1072 (CHIP_IS_E3B0(bp)) ?
1073 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1074 PBF_REG_P4_TQ_LINES_FREED_CNT}
1075 };
1076
1077 struct pbf_pN_buf_regs buf_regs[] = {
1078 {0, (CHIP_IS_E3B0(bp)) ?
1079 PBF_REG_INIT_CRD_Q0 :
1080 PBF_REG_P0_INIT_CRD ,
1081 (CHIP_IS_E3B0(bp)) ?
1082 PBF_REG_CREDIT_Q0 :
1083 PBF_REG_P0_CREDIT,
1084 (CHIP_IS_E3B0(bp)) ?
1085 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1086 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1087 {1, (CHIP_IS_E3B0(bp)) ?
1088 PBF_REG_INIT_CRD_Q1 :
1089 PBF_REG_P1_INIT_CRD,
1090 (CHIP_IS_E3B0(bp)) ?
1091 PBF_REG_CREDIT_Q1 :
1092 PBF_REG_P1_CREDIT,
1093 (CHIP_IS_E3B0(bp)) ?
1094 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1095 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1096 {4, (CHIP_IS_E3B0(bp)) ?
1097 PBF_REG_INIT_CRD_LB_Q :
1098 PBF_REG_P4_INIT_CRD,
1099 (CHIP_IS_E3B0(bp)) ?
1100 PBF_REG_CREDIT_LB_Q :
1101 PBF_REG_P4_CREDIT,
1102 (CHIP_IS_E3B0(bp)) ?
1103 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1104 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1105 };
1106
1107 int i;
1108
1109 /* Verify the command queues are flushed P0, P1, P4 */
1110 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1111 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1112
1113
1114 /* Verify the transmission buffers are flushed P0, P1, P4 */
1115 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1116 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1117 }
1118
1119 #define OP_GEN_PARAM(param) \
1120 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1121
1122 #define OP_GEN_TYPE(type) \
1123 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1124
1125 #define OP_GEN_AGG_VECT(index) \
1126 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1127
1128
1129 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1130 u32 poll_cnt)
1131 {
1132 struct sdm_op_gen op_gen = {0};
1133
1134 u32 comp_addr = BAR_CSTRORM_INTMEM +
1135 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1136 int ret = 0;
1137
1138 if (REG_RD(bp, comp_addr)) {
1139 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1140 return 1;
1141 }
1142
1143 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1144 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1145 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1146 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1147
1148 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1149 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1150
1151 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1152 BNX2X_ERR("FW final cleanup did not succeed\n");
1153 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1154 (REG_RD(bp, comp_addr)));
1155 ret = 1;
1156 }
1157 /* Zero completion for nxt FLR */
1158 REG_WR(bp, comp_addr, 0);
1159
1160 return ret;
1161 }
1162
1163 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1164 {
1165 int pos;
1166 u16 status;
1167
1168 pos = pci_pcie_cap(dev);
1169 if (!pos)
1170 return false;
1171
1172 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1173 return status & PCI_EXP_DEVSTA_TRPND;
1174 }
1175
1176 /* PF FLR specific routines
1177 */
1178 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1179 {
1180
1181 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1182 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1183 CFC_REG_NUM_LCIDS_INSIDE_PF,
1184 "CFC PF usage counter timed out",
1185 poll_cnt))
1186 return 1;
1187
1188
1189 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1190 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1191 DORQ_REG_PF_USAGE_CNT,
1192 "DQ PF usage counter timed out",
1193 poll_cnt))
1194 return 1;
1195
1196 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1197 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1198 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1199 "QM PF usage counter timed out",
1200 poll_cnt))
1201 return 1;
1202
1203 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1204 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1205 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1206 "Timers VNIC usage counter timed out",
1207 poll_cnt))
1208 return 1;
1209 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1210 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1211 "Timers NUM_SCANS usage counter timed out",
1212 poll_cnt))
1213 return 1;
1214
1215 /* Wait DMAE PF usage counter to zero */
1216 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1217 dmae_reg_go_c[INIT_DMAE_C(bp)],
1218 "DMAE dommand register timed out",
1219 poll_cnt))
1220 return 1;
1221
1222 return 0;
1223 }
1224
1225 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1226 {
1227 u32 val;
1228
1229 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1230 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1231
1232 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1233 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1234
1235 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1236 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1237
1238 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1239 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1240
1241 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1242 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1243
1244 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1245 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1246
1247 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1248 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1249
1250 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1251 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1252 val);
1253 }
1254
1255 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1256 {
1257 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1258
1259 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1260
1261 /* Re-enable PF target read access */
1262 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1263
1264 /* Poll HW usage counters */
1265 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1266 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1267 return -EBUSY;
1268
1269 /* Zero the igu 'trailing edge' and 'leading edge' */
1270
1271 /* Send the FW cleanup command */
1272 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1273 return -EBUSY;
1274
1275 /* ATC cleanup */
1276
1277 /* Verify TX hw is flushed */
1278 bnx2x_tx_hw_flushed(bp, poll_cnt);
1279
1280 /* Wait 100ms (not adjusted according to platform) */
1281 msleep(100);
1282
1283 /* Verify no pending pci transactions */
1284 if (bnx2x_is_pcie_pending(bp->pdev))
1285 BNX2X_ERR("PCIE Transactions still pending\n");
1286
1287 /* Debug */
1288 bnx2x_hw_enable_status(bp);
1289
1290 /*
1291 * Master enable - Due to WB DMAE writes performed before this
1292 * register is re-initialized as part of the regular function init
1293 */
1294 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1295
1296 return 0;
1297 }
1298
1299 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1300 {
1301 int port = BP_PORT(bp);
1302 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1303 u32 val = REG_RD(bp, addr);
1304 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1305 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1306 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1307
1308 if (msix) {
1309 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1310 HC_CONFIG_0_REG_INT_LINE_EN_0);
1311 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1312 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1313 if (single_msix)
1314 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1315 } else if (msi) {
1316 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1317 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1318 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1319 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1320 } else {
1321 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1322 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1323 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1324 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1325
1326 if (!CHIP_IS_E1(bp)) {
1327 DP(NETIF_MSG_IFUP,
1328 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1329
1330 REG_WR(bp, addr, val);
1331
1332 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1333 }
1334 }
1335
1336 if (CHIP_IS_E1(bp))
1337 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1338
1339 DP(NETIF_MSG_IFUP,
1340 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1341 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1342
1343 REG_WR(bp, addr, val);
1344 /*
1345 * Ensure that HC_CONFIG is written before leading/trailing edge config
1346 */
1347 mmiowb();
1348 barrier();
1349
1350 if (!CHIP_IS_E1(bp)) {
1351 /* init leading/trailing edge */
1352 if (IS_MF(bp)) {
1353 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1354 if (bp->port.pmf)
1355 /* enable nig and gpio3 attention */
1356 val |= 0x1100;
1357 } else
1358 val = 0xffff;
1359
1360 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1361 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1362 }
1363
1364 /* Make sure that interrupts are indeed enabled from here on */
1365 mmiowb();
1366 }
1367
1368 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1369 {
1370 u32 val;
1371 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1372 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1373 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1374
1375 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1376
1377 if (msix) {
1378 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1379 IGU_PF_CONF_SINGLE_ISR_EN);
1380 val |= (IGU_PF_CONF_FUNC_EN |
1381 IGU_PF_CONF_MSI_MSIX_EN |
1382 IGU_PF_CONF_ATTN_BIT_EN);
1383
1384 if (single_msix)
1385 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1386 } else if (msi) {
1387 val &= ~IGU_PF_CONF_INT_LINE_EN;
1388 val |= (IGU_PF_CONF_FUNC_EN |
1389 IGU_PF_CONF_MSI_MSIX_EN |
1390 IGU_PF_CONF_ATTN_BIT_EN |
1391 IGU_PF_CONF_SINGLE_ISR_EN);
1392 } else {
1393 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1394 val |= (IGU_PF_CONF_FUNC_EN |
1395 IGU_PF_CONF_INT_LINE_EN |
1396 IGU_PF_CONF_ATTN_BIT_EN |
1397 IGU_PF_CONF_SINGLE_ISR_EN);
1398 }
1399
1400 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1401 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1402
1403 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1404
1405 if (val & IGU_PF_CONF_INT_LINE_EN)
1406 pci_intx(bp->pdev, true);
1407
1408 barrier();
1409
1410 /* init leading/trailing edge */
1411 if (IS_MF(bp)) {
1412 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1413 if (bp->port.pmf)
1414 /* enable nig and gpio3 attention */
1415 val |= 0x1100;
1416 } else
1417 val = 0xffff;
1418
1419 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1420 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1421
1422 /* Make sure that interrupts are indeed enabled from here on */
1423 mmiowb();
1424 }
1425
1426 void bnx2x_int_enable(struct bnx2x *bp)
1427 {
1428 if (bp->common.int_block == INT_BLOCK_HC)
1429 bnx2x_hc_int_enable(bp);
1430 else
1431 bnx2x_igu_int_enable(bp);
1432 }
1433
1434 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1435 {
1436 int port = BP_PORT(bp);
1437 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1438 u32 val = REG_RD(bp, addr);
1439
1440 /*
1441 * in E1 we must use only PCI configuration space to disable
1442 * MSI/MSIX capablility
1443 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1444 */
1445 if (CHIP_IS_E1(bp)) {
1446 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1447 * Use mask register to prevent from HC sending interrupts
1448 * after we exit the function
1449 */
1450 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1451
1452 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1453 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1454 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1455 } else
1456 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1457 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1458 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1459 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1460
1461 DP(NETIF_MSG_IFDOWN,
1462 "write %x to HC %d (addr 0x%x)\n",
1463 val, port, addr);
1464
1465 /* flush all outstanding writes */
1466 mmiowb();
1467
1468 REG_WR(bp, addr, val);
1469 if (REG_RD(bp, addr) != val)
1470 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1471 }
1472
1473 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1474 {
1475 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1476
1477 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1478 IGU_PF_CONF_INT_LINE_EN |
1479 IGU_PF_CONF_ATTN_BIT_EN);
1480
1481 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1482
1483 /* flush all outstanding writes */
1484 mmiowb();
1485
1486 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1487 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1488 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1489 }
1490
1491 void bnx2x_int_disable(struct bnx2x *bp)
1492 {
1493 if (bp->common.int_block == INT_BLOCK_HC)
1494 bnx2x_hc_int_disable(bp);
1495 else
1496 bnx2x_igu_int_disable(bp);
1497 }
1498
1499 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1500 {
1501 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1502 int i, offset;
1503
1504 if (disable_hw)
1505 /* prevent the HW from sending interrupts */
1506 bnx2x_int_disable(bp);
1507
1508 /* make sure all ISRs are done */
1509 if (msix) {
1510 synchronize_irq(bp->msix_table[0].vector);
1511 offset = 1;
1512 #ifdef BCM_CNIC
1513 offset++;
1514 #endif
1515 for_each_eth_queue(bp, i)
1516 synchronize_irq(bp->msix_table[offset++].vector);
1517 } else
1518 synchronize_irq(bp->pdev->irq);
1519
1520 /* make sure sp_task is not running */
1521 cancel_delayed_work(&bp->sp_task);
1522 cancel_delayed_work(&bp->period_task);
1523 flush_workqueue(bnx2x_wq);
1524 }
1525
1526 /* fast path */
1527
1528 /*
1529 * General service functions
1530 */
1531
1532 /* Return true if succeeded to acquire the lock */
1533 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1534 {
1535 u32 lock_status;
1536 u32 resource_bit = (1 << resource);
1537 int func = BP_FUNC(bp);
1538 u32 hw_lock_control_reg;
1539
1540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1541 "Trying to take a lock on resource %d\n", resource);
1542
1543 /* Validating that the resource is within range */
1544 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1547 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1548 return false;
1549 }
1550
1551 if (func <= 5)
1552 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1553 else
1554 hw_lock_control_reg =
1555 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1556
1557 /* Try to acquire the lock */
1558 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1559 lock_status = REG_RD(bp, hw_lock_control_reg);
1560 if (lock_status & resource_bit)
1561 return true;
1562
1563 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1564 "Failed to get a lock on resource %d\n", resource);
1565 return false;
1566 }
1567
1568 /**
1569 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1570 *
1571 * @bp: driver handle
1572 *
1573 * Returns the recovery leader resource id according to the engine this function
1574 * belongs to. Currently only only 2 engines is supported.
1575 */
1576 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1577 {
1578 if (BP_PATH(bp))
1579 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1580 else
1581 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1582 }
1583
1584 /**
1585 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1586 *
1587 * @bp: driver handle
1588 *
1589 * Tries to aquire a leader lock for current engine.
1590 */
1591 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1592 {
1593 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1594 }
1595
1596 #ifdef BCM_CNIC
1597 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1598 #endif
1599
1600 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1601 {
1602 struct bnx2x *bp = fp->bp;
1603 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1604 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1605 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1606 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1607
1608 DP(BNX2X_MSG_SP,
1609 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1610 fp->index, cid, command, bp->state,
1611 rr_cqe->ramrod_cqe.ramrod_type);
1612
1613 switch (command) {
1614 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1615 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1616 drv_cmd = BNX2X_Q_CMD_UPDATE;
1617 break;
1618
1619 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1620 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1621 drv_cmd = BNX2X_Q_CMD_SETUP;
1622 break;
1623
1624 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1625 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1626 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1627 break;
1628
1629 case (RAMROD_CMD_ID_ETH_HALT):
1630 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1631 drv_cmd = BNX2X_Q_CMD_HALT;
1632 break;
1633
1634 case (RAMROD_CMD_ID_ETH_TERMINATE):
1635 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1636 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1637 break;
1638
1639 case (RAMROD_CMD_ID_ETH_EMPTY):
1640 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1641 drv_cmd = BNX2X_Q_CMD_EMPTY;
1642 break;
1643
1644 default:
1645 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1646 command, fp->index);
1647 return;
1648 }
1649
1650 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1651 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1652 /* q_obj->complete_cmd() failure means that this was
1653 * an unexpected completion.
1654 *
1655 * In this case we don't want to increase the bp->spq_left
1656 * because apparently we haven't sent this command the first
1657 * place.
1658 */
1659 #ifdef BNX2X_STOP_ON_ERROR
1660 bnx2x_panic();
1661 #else
1662 return;
1663 #endif
1664
1665 smp_mb__before_atomic_inc();
1666 atomic_inc(&bp->cq_spq_left);
1667 /* push the change in bp->spq_left and towards the memory */
1668 smp_mb__after_atomic_inc();
1669
1670 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1671
1672 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1673 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1674 /* if Q update ramrod is completed for last Q in AFEX vif set
1675 * flow, then ACK MCP at the end
1676 *
1677 * mark pending ACK to MCP bit.
1678 * prevent case that both bits are cleared.
1679 * At the end of load/unload driver checks that
1680 * sp_state is cleaerd, and this order prevents
1681 * races
1682 */
1683 smp_mb__before_clear_bit();
1684 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1685 wmb();
1686 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1687 smp_mb__after_clear_bit();
1688
1689 /* schedule workqueue to send ack to MCP */
1690 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1691 }
1692
1693 return;
1694 }
1695
1696 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1697 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1698 {
1699 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1700
1701 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1702 start);
1703 }
1704
1705 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1706 {
1707 struct bnx2x *bp = netdev_priv(dev_instance);
1708 u16 status = bnx2x_ack_int(bp);
1709 u16 mask;
1710 int i;
1711 u8 cos;
1712
1713 /* Return here if interrupt is shared and it's not for us */
1714 if (unlikely(status == 0)) {
1715 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1716 return IRQ_NONE;
1717 }
1718 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1719
1720 #ifdef BNX2X_STOP_ON_ERROR
1721 if (unlikely(bp->panic))
1722 return IRQ_HANDLED;
1723 #endif
1724
1725 for_each_eth_queue(bp, i) {
1726 struct bnx2x_fastpath *fp = &bp->fp[i];
1727
1728 mask = 0x2 << (fp->index + CNIC_PRESENT);
1729 if (status & mask) {
1730 /* Handle Rx or Tx according to SB id */
1731 prefetch(fp->rx_cons_sb);
1732 for_each_cos_in_tx_queue(fp, cos)
1733 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1734 prefetch(&fp->sb_running_index[SM_RX_ID]);
1735 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1736 status &= ~mask;
1737 }
1738 }
1739
1740 #ifdef BCM_CNIC
1741 mask = 0x2;
1742 if (status & (mask | 0x1)) {
1743 struct cnic_ops *c_ops = NULL;
1744
1745 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1746 rcu_read_lock();
1747 c_ops = rcu_dereference(bp->cnic_ops);
1748 if (c_ops)
1749 c_ops->cnic_handler(bp->cnic_data, NULL);
1750 rcu_read_unlock();
1751 }
1752
1753 status &= ~mask;
1754 }
1755 #endif
1756
1757 if (unlikely(status & 0x1)) {
1758 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1759
1760 status &= ~0x1;
1761 if (!status)
1762 return IRQ_HANDLED;
1763 }
1764
1765 if (unlikely(status))
1766 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1767 status);
1768
1769 return IRQ_HANDLED;
1770 }
1771
1772 /* Link */
1773
1774 /*
1775 * General service functions
1776 */
1777
1778 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1779 {
1780 u32 lock_status;
1781 u32 resource_bit = (1 << resource);
1782 int func = BP_FUNC(bp);
1783 u32 hw_lock_control_reg;
1784 int cnt;
1785
1786 /* Validating that the resource is within range */
1787 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1788 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1789 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1790 return -EINVAL;
1791 }
1792
1793 if (func <= 5) {
1794 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1795 } else {
1796 hw_lock_control_reg =
1797 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1798 }
1799
1800 /* Validating that the resource is not already taken */
1801 lock_status = REG_RD(bp, hw_lock_control_reg);
1802 if (lock_status & resource_bit) {
1803 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1804 lock_status, resource_bit);
1805 return -EEXIST;
1806 }
1807
1808 /* Try for 5 second every 5ms */
1809 for (cnt = 0; cnt < 1000; cnt++) {
1810 /* Try to acquire the lock */
1811 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit)
1814 return 0;
1815
1816 msleep(5);
1817 }
1818 BNX2X_ERR("Timeout\n");
1819 return -EAGAIN;
1820 }
1821
1822 int bnx2x_release_leader_lock(struct bnx2x *bp)
1823 {
1824 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1825 }
1826
1827 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1828 {
1829 u32 lock_status;
1830 u32 resource_bit = (1 << resource);
1831 int func = BP_FUNC(bp);
1832 u32 hw_lock_control_reg;
1833
1834 /* Validating that the resource is within range */
1835 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1836 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1837 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1838 return -EINVAL;
1839 }
1840
1841 if (func <= 5) {
1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1843 } else {
1844 hw_lock_control_reg =
1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1846 }
1847
1848 /* Validating that the resource is currently taken */
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (!(lock_status & resource_bit)) {
1851 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1852 lock_status, resource_bit);
1853 return -EFAULT;
1854 }
1855
1856 REG_WR(bp, hw_lock_control_reg, resource_bit);
1857 return 0;
1858 }
1859
1860
1861 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1862 {
1863 /* The GPIO should be swapped if swap register is set and active */
1864 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1865 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1866 int gpio_shift = gpio_num +
1867 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1868 u32 gpio_mask = (1 << gpio_shift);
1869 u32 gpio_reg;
1870 int value;
1871
1872 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1873 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1874 return -EINVAL;
1875 }
1876
1877 /* read GPIO value */
1878 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1879
1880 /* get the requested pin value */
1881 if ((gpio_reg & gpio_mask) == gpio_mask)
1882 value = 1;
1883 else
1884 value = 0;
1885
1886 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1887
1888 return value;
1889 }
1890
1891 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1892 {
1893 /* The GPIO should be swapped if swap register is set and active */
1894 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1895 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1896 int gpio_shift = gpio_num +
1897 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1898 u32 gpio_mask = (1 << gpio_shift);
1899 u32 gpio_reg;
1900
1901 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1902 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1903 return -EINVAL;
1904 }
1905
1906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1907 /* read GPIO and mask except the float bits */
1908 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1909
1910 switch (mode) {
1911 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1912 DP(NETIF_MSG_LINK,
1913 "Set GPIO %d (shift %d) -> output low\n",
1914 gpio_num, gpio_shift);
1915 /* clear FLOAT and set CLR */
1916 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1917 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1918 break;
1919
1920 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1921 DP(NETIF_MSG_LINK,
1922 "Set GPIO %d (shift %d) -> output high\n",
1923 gpio_num, gpio_shift);
1924 /* clear FLOAT and set SET */
1925 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1926 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1927 break;
1928
1929 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1930 DP(NETIF_MSG_LINK,
1931 "Set GPIO %d (shift %d) -> input\n",
1932 gpio_num, gpio_shift);
1933 /* set FLOAT */
1934 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1935 break;
1936
1937 default:
1938 break;
1939 }
1940
1941 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1942 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1943
1944 return 0;
1945 }
1946
1947 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1948 {
1949 u32 gpio_reg = 0;
1950 int rc = 0;
1951
1952 /* Any port swapping should be handled by caller. */
1953
1954 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1955 /* read GPIO and mask except the float bits */
1956 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1957 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1959 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1960
1961 switch (mode) {
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1963 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1964 /* set CLR */
1965 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1966 break;
1967
1968 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1969 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1970 /* set SET */
1971 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1972 break;
1973
1974 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1975 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1976 /* set FLOAT */
1977 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1978 break;
1979
1980 default:
1981 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1982 rc = -EINVAL;
1983 break;
1984 }
1985
1986 if (rc == 0)
1987 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1988
1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1990
1991 return rc;
1992 }
1993
1994 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1995 {
1996 /* The GPIO should be swapped if swap register is set and active */
1997 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1998 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1999 int gpio_shift = gpio_num +
2000 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2001 u32 gpio_mask = (1 << gpio_shift);
2002 u32 gpio_reg;
2003
2004 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2005 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2006 return -EINVAL;
2007 }
2008
2009 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2010 /* read GPIO int */
2011 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2012
2013 switch (mode) {
2014 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2015 DP(NETIF_MSG_LINK,
2016 "Clear GPIO INT %d (shift %d) -> output low\n",
2017 gpio_num, gpio_shift);
2018 /* clear SET and set CLR */
2019 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2020 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2021 break;
2022
2023 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2024 DP(NETIF_MSG_LINK,
2025 "Set GPIO INT %d (shift %d) -> output high\n",
2026 gpio_num, gpio_shift);
2027 /* clear CLR and set SET */
2028 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2029 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2030 break;
2031
2032 default:
2033 break;
2034 }
2035
2036 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2038
2039 return 0;
2040 }
2041
2042 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2043 {
2044 u32 spio_mask = (1 << spio_num);
2045 u32 spio_reg;
2046
2047 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2048 (spio_num > MISC_REGISTERS_SPIO_7)) {
2049 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2050 return -EINVAL;
2051 }
2052
2053 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2054 /* read SPIO and mask except the float bits */
2055 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2056
2057 switch (mode) {
2058 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2060 /* clear FLOAT and set CLR */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2063 break;
2064
2065 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2067 /* clear FLOAT and set SET */
2068 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2069 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2070 break;
2071
2072 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2073 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2074 /* set FLOAT */
2075 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2076 break;
2077
2078 default:
2079 break;
2080 }
2081
2082 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2084
2085 return 0;
2086 }
2087
2088 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2089 {
2090 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2091 switch (bp->link_vars.ieee_fc &
2092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2093 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2094 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2095 ADVERTISED_Pause);
2096 break;
2097
2098 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2099 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2100 ADVERTISED_Pause);
2101 break;
2102
2103 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2104 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2105 break;
2106
2107 default:
2108 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2109 ADVERTISED_Pause);
2110 break;
2111 }
2112 }
2113
2114 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2115 {
2116 if (!BP_NOMCP(bp)) {
2117 u8 rc;
2118 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2119 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2120 /*
2121 * Initialize link parameters structure variables
2122 * It is recommended to turn off RX FC for jumbo frames
2123 * for better performance
2124 */
2125 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2126 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2127 else
2128 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2129
2130 bnx2x_acquire_phy_lock(bp);
2131
2132 if (load_mode == LOAD_DIAG) {
2133 struct link_params *lp = &bp->link_params;
2134 lp->loopback_mode = LOOPBACK_XGXS;
2135 /* do PHY loopback at 10G speed, if possible */
2136 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2137 if (lp->speed_cap_mask[cfx_idx] &
2138 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2139 lp->req_line_speed[cfx_idx] =
2140 SPEED_10000;
2141 else
2142 lp->req_line_speed[cfx_idx] =
2143 SPEED_1000;
2144 }
2145 }
2146
2147 if (load_mode == LOAD_LOOPBACK_EXT) {
2148 struct link_params *lp = &bp->link_params;
2149 lp->loopback_mode = LOOPBACK_EXT;
2150 }
2151
2152 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2153
2154 bnx2x_release_phy_lock(bp);
2155
2156 bnx2x_calc_fc_adv(bp);
2157
2158 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2159 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2160 bnx2x_link_report(bp);
2161 } else
2162 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2163 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2164 return rc;
2165 }
2166 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2167 return -EINVAL;
2168 }
2169
2170 void bnx2x_link_set(struct bnx2x *bp)
2171 {
2172 if (!BP_NOMCP(bp)) {
2173 bnx2x_acquire_phy_lock(bp);
2174 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2175 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2176 bnx2x_release_phy_lock(bp);
2177
2178 bnx2x_calc_fc_adv(bp);
2179 } else
2180 BNX2X_ERR("Bootcode is missing - can not set link\n");
2181 }
2182
2183 static void bnx2x__link_reset(struct bnx2x *bp)
2184 {
2185 if (!BP_NOMCP(bp)) {
2186 bnx2x_acquire_phy_lock(bp);
2187 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2188 bnx2x_release_phy_lock(bp);
2189 } else
2190 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2191 }
2192
2193 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2194 {
2195 u8 rc = 0;
2196
2197 if (!BP_NOMCP(bp)) {
2198 bnx2x_acquire_phy_lock(bp);
2199 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2200 is_serdes);
2201 bnx2x_release_phy_lock(bp);
2202 } else
2203 BNX2X_ERR("Bootcode is missing - can not test link\n");
2204
2205 return rc;
2206 }
2207
2208
2209 /* Calculates the sum of vn_min_rates.
2210 It's needed for further normalizing of the min_rates.
2211 Returns:
2212 sum of vn_min_rates.
2213 or
2214 0 - if all the min_rates are 0.
2215 In the later case fainess algorithm should be deactivated.
2216 If not all min_rates are zero then those that are zeroes will be set to 1.
2217 */
2218 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2219 struct cmng_init_input *input)
2220 {
2221 int all_zero = 1;
2222 int vn;
2223
2224 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2225 u32 vn_cfg = bp->mf_config[vn];
2226 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2227 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2228
2229 /* Skip hidden vns */
2230 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2231 vn_min_rate = 0;
2232 /* If min rate is zero - set it to 1 */
2233 else if (!vn_min_rate)
2234 vn_min_rate = DEF_MIN_RATE;
2235 else
2236 all_zero = 0;
2237
2238 input->vnic_min_rate[vn] = vn_min_rate;
2239 }
2240
2241 /* if ETS or all min rates are zeros - disable fairness */
2242 if (BNX2X_IS_ETS_ENABLED(bp)) {
2243 input->flags.cmng_enables &=
2244 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2245 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2246 } else if (all_zero) {
2247 input->flags.cmng_enables &=
2248 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2249 DP(NETIF_MSG_IFUP,
2250 "All MIN values are zeroes fairness will be disabled\n");
2251 } else
2252 input->flags.cmng_enables |=
2253 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2254 }
2255
2256 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2257 struct cmng_init_input *input)
2258 {
2259 u16 vn_max_rate;
2260 u32 vn_cfg = bp->mf_config[vn];
2261
2262 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2263 vn_max_rate = 0;
2264 else {
2265 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2266
2267 if (IS_MF_SI(bp)) {
2268 /* maxCfg in percents of linkspeed */
2269 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2270 } else /* SD modes */
2271 /* maxCfg is absolute in 100Mb units */
2272 vn_max_rate = maxCfg * 100;
2273 }
2274
2275 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2276
2277 input->vnic_max_rate[vn] = vn_max_rate;
2278 }
2279
2280
2281 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2282 {
2283 if (CHIP_REV_IS_SLOW(bp))
2284 return CMNG_FNS_NONE;
2285 if (IS_MF(bp))
2286 return CMNG_FNS_MINMAX;
2287
2288 return CMNG_FNS_NONE;
2289 }
2290
2291 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2292 {
2293 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2294
2295 if (BP_NOMCP(bp))
2296 return; /* what should be the default bvalue in this case */
2297
2298 /* For 2 port configuration the absolute function number formula
2299 * is:
2300 * abs_func = 2 * vn + BP_PORT + BP_PATH
2301 *
2302 * and there are 4 functions per port
2303 *
2304 * For 4 port configuration it is
2305 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2306 *
2307 * and there are 2 functions per port
2308 */
2309 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2310 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2311
2312 if (func >= E1H_FUNC_MAX)
2313 break;
2314
2315 bp->mf_config[vn] =
2316 MF_CFG_RD(bp, func_mf_config[func].config);
2317 }
2318 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2319 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2320 bp->flags |= MF_FUNC_DIS;
2321 } else {
2322 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2323 bp->flags &= ~MF_FUNC_DIS;
2324 }
2325 }
2326
2327 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2328 {
2329 struct cmng_init_input input;
2330 memset(&input, 0, sizeof(struct cmng_init_input));
2331
2332 input.port_rate = bp->link_vars.line_speed;
2333
2334 if (cmng_type == CMNG_FNS_MINMAX) {
2335 int vn;
2336
2337 /* read mf conf from shmem */
2338 if (read_cfg)
2339 bnx2x_read_mf_cfg(bp);
2340
2341 /* vn_weight_sum and enable fairness if not 0 */
2342 bnx2x_calc_vn_min(bp, &input);
2343
2344 /* calculate and set min-max rate for each vn */
2345 if (bp->port.pmf)
2346 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2347 bnx2x_calc_vn_max(bp, vn, &input);
2348
2349 /* always enable rate shaping and fairness */
2350 input.flags.cmng_enables |=
2351 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2352
2353 bnx2x_init_cmng(&input, &bp->cmng);
2354 return;
2355 }
2356
2357 /* rate shaping and fairness are disabled */
2358 DP(NETIF_MSG_IFUP,
2359 "rate shaping and fairness are disabled\n");
2360 }
2361
2362 static void storm_memset_cmng(struct bnx2x *bp,
2363 struct cmng_init *cmng,
2364 u8 port)
2365 {
2366 int vn;
2367 size_t size = sizeof(struct cmng_struct_per_port);
2368
2369 u32 addr = BAR_XSTRORM_INTMEM +
2370 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2371
2372 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2373
2374 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2375 int func = func_by_vn(bp, vn);
2376
2377 addr = BAR_XSTRORM_INTMEM +
2378 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2379 size = sizeof(struct rate_shaping_vars_per_vn);
2380 __storm_memset_struct(bp, addr, size,
2381 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2382
2383 addr = BAR_XSTRORM_INTMEM +
2384 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2385 size = sizeof(struct fairness_vars_per_vn);
2386 __storm_memset_struct(bp, addr, size,
2387 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2388 }
2389 }
2390
2391 /* This function is called upon link interrupt */
2392 static void bnx2x_link_attn(struct bnx2x *bp)
2393 {
2394 /* Make sure that we are synced with the current statistics */
2395 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2396
2397 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2398
2399 if (bp->link_vars.link_up) {
2400
2401 /* dropless flow control */
2402 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2403 int port = BP_PORT(bp);
2404 u32 pause_enabled = 0;
2405
2406 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2407 pause_enabled = 1;
2408
2409 REG_WR(bp, BAR_USTRORM_INTMEM +
2410 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2411 pause_enabled);
2412 }
2413
2414 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2415 struct host_port_stats *pstats;
2416
2417 pstats = bnx2x_sp(bp, port_stats);
2418 /* reset old mac stats */
2419 memset(&(pstats->mac_stx[0]), 0,
2420 sizeof(struct mac_stx));
2421 }
2422 if (bp->state == BNX2X_STATE_OPEN)
2423 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2424 }
2425
2426 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2427 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2428
2429 if (cmng_fns != CMNG_FNS_NONE) {
2430 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2431 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2432 } else
2433 /* rate shaping and fairness are disabled */
2434 DP(NETIF_MSG_IFUP,
2435 "single function mode without fairness\n");
2436 }
2437
2438 __bnx2x_link_report(bp);
2439
2440 if (IS_MF(bp))
2441 bnx2x_link_sync_notify(bp);
2442 }
2443
2444 void bnx2x__link_status_update(struct bnx2x *bp)
2445 {
2446 if (bp->state != BNX2X_STATE_OPEN)
2447 return;
2448
2449 /* read updated dcb configuration */
2450 bnx2x_dcbx_pmf_update(bp);
2451
2452 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2453
2454 if (bp->link_vars.link_up)
2455 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2456 else
2457 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2458
2459 /* indicate link status */
2460 bnx2x_link_report(bp);
2461 }
2462
2463 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2464 u16 vlan_val, u8 allowed_prio)
2465 {
2466 struct bnx2x_func_state_params func_params = {0};
2467 struct bnx2x_func_afex_update_params *f_update_params =
2468 &func_params.params.afex_update;
2469
2470 func_params.f_obj = &bp->func_obj;
2471 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2472
2473 /* no need to wait for RAMROD completion, so don't
2474 * set RAMROD_COMP_WAIT flag
2475 */
2476
2477 f_update_params->vif_id = vifid;
2478 f_update_params->afex_default_vlan = vlan_val;
2479 f_update_params->allowed_priorities = allowed_prio;
2480
2481 /* if ramrod can not be sent, response to MCP immediately */
2482 if (bnx2x_func_state_change(bp, &func_params) < 0)
2483 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2484
2485 return 0;
2486 }
2487
2488 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2489 u16 vif_index, u8 func_bit_map)
2490 {
2491 struct bnx2x_func_state_params func_params = {0};
2492 struct bnx2x_func_afex_viflists_params *update_params =
2493 &func_params.params.afex_viflists;
2494 int rc;
2495 u32 drv_msg_code;
2496
2497 /* validate only LIST_SET and LIST_GET are received from switch */
2498 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2499 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2500 cmd_type);
2501
2502 func_params.f_obj = &bp->func_obj;
2503 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2504
2505 /* set parameters according to cmd_type */
2506 update_params->afex_vif_list_command = cmd_type;
2507 update_params->vif_list_index = cpu_to_le16(vif_index);
2508 update_params->func_bit_map =
2509 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2510 update_params->func_to_clear = 0;
2511 drv_msg_code =
2512 (cmd_type == VIF_LIST_RULE_GET) ?
2513 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2514 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2515
2516 /* if ramrod can not be sent, respond to MCP immediately for
2517 * SET and GET requests (other are not triggered from MCP)
2518 */
2519 rc = bnx2x_func_state_change(bp, &func_params);
2520 if (rc < 0)
2521 bnx2x_fw_command(bp, drv_msg_code, 0);
2522
2523 return 0;
2524 }
2525
2526 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2527 {
2528 struct afex_stats afex_stats;
2529 u32 func = BP_ABS_FUNC(bp);
2530 u32 mf_config;
2531 u16 vlan_val;
2532 u32 vlan_prio;
2533 u16 vif_id;
2534 u8 allowed_prio;
2535 u8 vlan_mode;
2536 u32 addr_to_write, vifid, addrs, stats_type, i;
2537
2538 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2539 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2540 DP(BNX2X_MSG_MCP,
2541 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2542 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2543 }
2544
2545 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2546 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2547 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2548 DP(BNX2X_MSG_MCP,
2549 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2550 vifid, addrs);
2551 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2552 addrs);
2553 }
2554
2555 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2556 addr_to_write = SHMEM2_RD(bp,
2557 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2558 stats_type = SHMEM2_RD(bp,
2559 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2560
2561 DP(BNX2X_MSG_MCP,
2562 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2563 addr_to_write);
2564
2565 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2566
2567 /* write response to scratchpad, for MCP */
2568 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2569 REG_WR(bp, addr_to_write + i*sizeof(u32),
2570 *(((u32 *)(&afex_stats))+i));
2571
2572 /* send ack message to MCP */
2573 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2574 }
2575
2576 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2577 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2578 bp->mf_config[BP_VN(bp)] = mf_config;
2579 DP(BNX2X_MSG_MCP,
2580 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2581 mf_config);
2582
2583 /* if VIF_SET is "enabled" */
2584 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2585 /* set rate limit directly to internal RAM */
2586 struct cmng_init_input cmng_input;
2587 struct rate_shaping_vars_per_vn m_rs_vn;
2588 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2589 u32 addr = BAR_XSTRORM_INTMEM +
2590 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2591
2592 bp->mf_config[BP_VN(bp)] = mf_config;
2593
2594 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2595 m_rs_vn.vn_counter.rate =
2596 cmng_input.vnic_max_rate[BP_VN(bp)];
2597 m_rs_vn.vn_counter.quota =
2598 (m_rs_vn.vn_counter.rate *
2599 RS_PERIODIC_TIMEOUT_USEC) / 8;
2600
2601 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2602
2603 /* read relevant values from mf_cfg struct in shmem */
2604 vif_id =
2605 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2606 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2607 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2608 vlan_val =
2609 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2610 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2611 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2612 vlan_prio = (mf_config &
2613 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2614 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2615 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2616 vlan_mode =
2617 (MF_CFG_RD(bp,
2618 func_mf_config[func].afex_config) &
2619 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2620 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2621 allowed_prio =
2622 (MF_CFG_RD(bp,
2623 func_mf_config[func].afex_config) &
2624 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2625 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2626
2627 /* send ramrod to FW, return in case of failure */
2628 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2629 allowed_prio))
2630 return;
2631
2632 bp->afex_def_vlan_tag = vlan_val;
2633 bp->afex_vlan_mode = vlan_mode;
2634 } else {
2635 /* notify link down because BP->flags is disabled */
2636 bnx2x_link_report(bp);
2637
2638 /* send INVALID VIF ramrod to FW */
2639 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2640
2641 /* Reset the default afex VLAN */
2642 bp->afex_def_vlan_tag = -1;
2643 }
2644 }
2645 }
2646
2647 static void bnx2x_pmf_update(struct bnx2x *bp)
2648 {
2649 int port = BP_PORT(bp);
2650 u32 val;
2651
2652 bp->port.pmf = 1;
2653 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2654
2655 /*
2656 * We need the mb() to ensure the ordering between the writing to
2657 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2658 */
2659 smp_mb();
2660
2661 /* queue a periodic task */
2662 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2663
2664 bnx2x_dcbx_pmf_update(bp);
2665
2666 /* enable nig attention */
2667 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2668 if (bp->common.int_block == INT_BLOCK_HC) {
2669 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2670 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2671 } else if (!CHIP_IS_E1x(bp)) {
2672 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2673 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2674 }
2675
2676 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2677 }
2678
2679 /* end of Link */
2680
2681 /* slow path */
2682
2683 /*
2684 * General service functions
2685 */
2686
2687 /* send the MCP a request, block until there is a reply */
2688 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2689 {
2690 int mb_idx = BP_FW_MB_IDX(bp);
2691 u32 seq;
2692 u32 rc = 0;
2693 u32 cnt = 1;
2694 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2695
2696 mutex_lock(&bp->fw_mb_mutex);
2697 seq = ++bp->fw_seq;
2698 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2699 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2700
2701 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2702 (command | seq), param);
2703
2704 do {
2705 /* let the FW do it's magic ... */
2706 msleep(delay);
2707
2708 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2709
2710 /* Give the FW up to 5 second (500*10ms) */
2711 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2712
2713 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2714 cnt*delay, rc, seq);
2715
2716 /* is this a reply to our command? */
2717 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2718 rc &= FW_MSG_CODE_MASK;
2719 else {
2720 /* FW BUG! */
2721 BNX2X_ERR("FW failed to respond!\n");
2722 bnx2x_fw_dump(bp);
2723 rc = 0;
2724 }
2725 mutex_unlock(&bp->fw_mb_mutex);
2726
2727 return rc;
2728 }
2729
2730
2731 static void storm_memset_func_cfg(struct bnx2x *bp,
2732 struct tstorm_eth_function_common_config *tcfg,
2733 u16 abs_fid)
2734 {
2735 size_t size = sizeof(struct tstorm_eth_function_common_config);
2736
2737 u32 addr = BAR_TSTRORM_INTMEM +
2738 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2739
2740 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2741 }
2742
2743 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2744 {
2745 if (CHIP_IS_E1x(bp)) {
2746 struct tstorm_eth_function_common_config tcfg = {0};
2747
2748 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2749 }
2750
2751 /* Enable the function in the FW */
2752 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2753 storm_memset_func_en(bp, p->func_id, 1);
2754
2755 /* spq */
2756 if (p->func_flgs & FUNC_FLG_SPQ) {
2757 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2758 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2759 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2760 }
2761 }
2762
2763 /**
2764 * bnx2x_get_tx_only_flags - Return common flags
2765 *
2766 * @bp device handle
2767 * @fp queue handle
2768 * @zero_stats TRUE if statistics zeroing is needed
2769 *
2770 * Return the flags that are common for the Tx-only and not normal connections.
2771 */
2772 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2773 struct bnx2x_fastpath *fp,
2774 bool zero_stats)
2775 {
2776 unsigned long flags = 0;
2777
2778 /* PF driver will always initialize the Queue to an ACTIVE state */
2779 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2780
2781 /* tx only connections collect statistics (on the same index as the
2782 * parent connection). The statistics are zeroed when the parent
2783 * connection is initialized.
2784 */
2785
2786 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2787 if (zero_stats)
2788 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2789
2790
2791 return flags;
2792 }
2793
2794 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2795 struct bnx2x_fastpath *fp,
2796 bool leading)
2797 {
2798 unsigned long flags = 0;
2799
2800 /* calculate other queue flags */
2801 if (IS_MF_SD(bp))
2802 __set_bit(BNX2X_Q_FLG_OV, &flags);
2803
2804 if (IS_FCOE_FP(fp)) {
2805 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2806 /* For FCoE - force usage of default priority (for afex) */
2807 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2808 }
2809
2810 if (!fp->disable_tpa) {
2811 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2812 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2813 if (fp->mode == TPA_MODE_GRO)
2814 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2815 }
2816
2817 if (leading) {
2818 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2819 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2820 }
2821
2822 /* Always set HW VLAN stripping */
2823 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2824
2825 /* configure silent vlan removal */
2826 if (IS_MF_AFEX(bp))
2827 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2828
2829
2830 return flags | bnx2x_get_common_flags(bp, fp, true);
2831 }
2832
2833 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2834 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2835 u8 cos)
2836 {
2837 gen_init->stat_id = bnx2x_stats_id(fp);
2838 gen_init->spcl_id = fp->cl_id;
2839
2840 /* Always use mini-jumbo MTU for FCoE L2 ring */
2841 if (IS_FCOE_FP(fp))
2842 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2843 else
2844 gen_init->mtu = bp->dev->mtu;
2845
2846 gen_init->cos = cos;
2847 }
2848
2849 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2850 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2851 struct bnx2x_rxq_setup_params *rxq_init)
2852 {
2853 u8 max_sge = 0;
2854 u16 sge_sz = 0;
2855 u16 tpa_agg_size = 0;
2856
2857 if (!fp->disable_tpa) {
2858 pause->sge_th_lo = SGE_TH_LO(bp);
2859 pause->sge_th_hi = SGE_TH_HI(bp);
2860
2861 /* validate SGE ring has enough to cross high threshold */
2862 WARN_ON(bp->dropless_fc &&
2863 pause->sge_th_hi + FW_PREFETCH_CNT >
2864 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2865
2866 tpa_agg_size = min_t(u32,
2867 (min_t(u32, 8, MAX_SKB_FRAGS) *
2868 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2869 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2870 SGE_PAGE_SHIFT;
2871 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2872 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2873 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2874 0xffff);
2875 }
2876
2877 /* pause - not for e1 */
2878 if (!CHIP_IS_E1(bp)) {
2879 pause->bd_th_lo = BD_TH_LO(bp);
2880 pause->bd_th_hi = BD_TH_HI(bp);
2881
2882 pause->rcq_th_lo = RCQ_TH_LO(bp);
2883 pause->rcq_th_hi = RCQ_TH_HI(bp);
2884 /*
2885 * validate that rings have enough entries to cross
2886 * high thresholds
2887 */
2888 WARN_ON(bp->dropless_fc &&
2889 pause->bd_th_hi + FW_PREFETCH_CNT >
2890 bp->rx_ring_size);
2891 WARN_ON(bp->dropless_fc &&
2892 pause->rcq_th_hi + FW_PREFETCH_CNT >
2893 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2894
2895 pause->pri_map = 1;
2896 }
2897
2898 /* rxq setup */
2899 rxq_init->dscr_map = fp->rx_desc_mapping;
2900 rxq_init->sge_map = fp->rx_sge_mapping;
2901 rxq_init->rcq_map = fp->rx_comp_mapping;
2902 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2903
2904 /* This should be a maximum number of data bytes that may be
2905 * placed on the BD (not including paddings).
2906 */
2907 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2908 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2909
2910 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2911 rxq_init->tpa_agg_sz = tpa_agg_size;
2912 rxq_init->sge_buf_sz = sge_sz;
2913 rxq_init->max_sges_pkt = max_sge;
2914 rxq_init->rss_engine_id = BP_FUNC(bp);
2915 rxq_init->mcast_engine_id = BP_FUNC(bp);
2916
2917 /* Maximum number or simultaneous TPA aggregation for this Queue.
2918 *
2919 * For PF Clients it should be the maximum avaliable number.
2920 * VF driver(s) may want to define it to a smaller value.
2921 */
2922 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2923
2924 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2925 rxq_init->fw_sb_id = fp->fw_sb_id;
2926
2927 if (IS_FCOE_FP(fp))
2928 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2929 else
2930 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2931 /* configure silent vlan removal
2932 * if multi function mode is afex, then mask default vlan
2933 */
2934 if (IS_MF_AFEX(bp)) {
2935 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2936 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2937 }
2938 }
2939
2940 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2941 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2942 u8 cos)
2943 {
2944 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2945 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2946 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2947 txq_init->fw_sb_id = fp->fw_sb_id;
2948
2949 /*
2950 * set the tss leading client id for TX classfication ==
2951 * leading RSS client id
2952 */
2953 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2954
2955 if (IS_FCOE_FP(fp)) {
2956 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2957 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2958 }
2959 }
2960
2961 static void bnx2x_pf_init(struct bnx2x *bp)
2962 {
2963 struct bnx2x_func_init_params func_init = {0};
2964 struct event_ring_data eq_data = { {0} };
2965 u16 flags;
2966
2967 if (!CHIP_IS_E1x(bp)) {
2968 /* reset IGU PF statistics: MSIX + ATTN */
2969 /* PF */
2970 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2971 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2972 (CHIP_MODE_IS_4_PORT(bp) ?
2973 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2974 /* ATTN */
2975 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2976 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2977 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2978 (CHIP_MODE_IS_4_PORT(bp) ?
2979 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2980 }
2981
2982 /* function setup flags */
2983 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2984
2985 /* This flag is relevant for E1x only.
2986 * E2 doesn't have a TPA configuration in a function level.
2987 */
2988 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2989
2990 func_init.func_flgs = flags;
2991 func_init.pf_id = BP_FUNC(bp);
2992 func_init.func_id = BP_FUNC(bp);
2993 func_init.spq_map = bp->spq_mapping;
2994 func_init.spq_prod = bp->spq_prod_idx;
2995
2996 bnx2x_func_init(bp, &func_init);
2997
2998 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2999
3000 /*
3001 * Congestion management values depend on the link rate
3002 * There is no active link so initial link rate is set to 10 Gbps.
3003 * When the link comes up The congestion management values are
3004 * re-calculated according to the actual link rate.
3005 */
3006 bp->link_vars.line_speed = SPEED_10000;
3007 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3008
3009 /* Only the PMF sets the HW */
3010 if (bp->port.pmf)
3011 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3012
3013 /* init Event Queue */
3014 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3015 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3016 eq_data.producer = bp->eq_prod;
3017 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3018 eq_data.sb_id = DEF_SB_ID;
3019 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3020 }
3021
3022
3023 static void bnx2x_e1h_disable(struct bnx2x *bp)
3024 {
3025 int port = BP_PORT(bp);
3026
3027 bnx2x_tx_disable(bp);
3028
3029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3030 }
3031
3032 static void bnx2x_e1h_enable(struct bnx2x *bp)
3033 {
3034 int port = BP_PORT(bp);
3035
3036 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3037
3038 /* Tx queue should be only reenabled */
3039 netif_tx_wake_all_queues(bp->dev);
3040
3041 /*
3042 * Should not call netif_carrier_on since it will be called if the link
3043 * is up when checking for link state
3044 */
3045 }
3046
3047 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3048
3049 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3050 {
3051 struct eth_stats_info *ether_stat =
3052 &bp->slowpath->drv_info_to_mcp.ether_stat;
3053
3054 /* leave last char as NULL */
3055 memcpy(ether_stat->version, DRV_MODULE_VERSION,
3056 ETH_STAT_INFO_VERSION_LEN - 1);
3057
3058 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3059 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3060 ether_stat->mac_local);
3061
3062 ether_stat->mtu_size = bp->dev->mtu;
3063
3064 if (bp->dev->features & NETIF_F_RXCSUM)
3065 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3066 if (bp->dev->features & NETIF_F_TSO)
3067 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3068 ether_stat->feature_flags |= bp->common.boot_mode;
3069
3070 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3071
3072 ether_stat->txq_size = bp->tx_ring_size;
3073 ether_stat->rxq_size = bp->rx_ring_size;
3074 }
3075
3076 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3077 {
3078 #ifdef BCM_CNIC
3079 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3080 struct fcoe_stats_info *fcoe_stat =
3081 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3082
3083 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3084 bp->fip_mac, ETH_ALEN);
3085
3086 fcoe_stat->qos_priority =
3087 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3088
3089 /* insert FCoE stats from ramrod response */
3090 if (!NO_FCOE(bp)) {
3091 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3092 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3093 tstorm_queue_statistics;
3094
3095 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3096 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3097 xstorm_queue_statistics;
3098
3099 struct fcoe_statistics_params *fw_fcoe_stat =
3100 &bp->fw_stats_data->fcoe;
3101
3102 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3103 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3104
3105 ADD_64(fcoe_stat->rx_bytes_hi,
3106 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3107 fcoe_stat->rx_bytes_lo,
3108 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3109
3110 ADD_64(fcoe_stat->rx_bytes_hi,
3111 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3112 fcoe_stat->rx_bytes_lo,
3113 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3114
3115 ADD_64(fcoe_stat->rx_bytes_hi,
3116 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3117 fcoe_stat->rx_bytes_lo,
3118 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3119
3120 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3121 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3122
3123 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3124 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3125
3126 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3128
3129 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3131
3132 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3133 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3134
3135 ADD_64(fcoe_stat->tx_bytes_hi,
3136 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3137 fcoe_stat->tx_bytes_lo,
3138 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3139
3140 ADD_64(fcoe_stat->tx_bytes_hi,
3141 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3142 fcoe_stat->tx_bytes_lo,
3143 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3144
3145 ADD_64(fcoe_stat->tx_bytes_hi,
3146 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3147 fcoe_stat->tx_bytes_lo,
3148 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3149
3150 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3151 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3152
3153 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3154 fcoe_q_xstorm_stats->ucast_pkts_sent);
3155
3156 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157 fcoe_q_xstorm_stats->bcast_pkts_sent);
3158
3159 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160 fcoe_q_xstorm_stats->mcast_pkts_sent);
3161 }
3162
3163 /* ask L5 driver to add data to the struct */
3164 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3165 #endif
3166 }
3167
3168 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3169 {
3170 #ifdef BCM_CNIC
3171 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3172 struct iscsi_stats_info *iscsi_stat =
3173 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3174
3175 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3176 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3177
3178 iscsi_stat->qos_priority =
3179 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3180
3181 /* ask L5 driver to add data to the struct */
3182 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3183 #endif
3184 }
3185
3186 /* called due to MCP event (on pmf):
3187 * reread new bandwidth configuration
3188 * configure FW
3189 * notify others function about the change
3190 */
3191 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3192 {
3193 if (bp->link_vars.link_up) {
3194 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3195 bnx2x_link_sync_notify(bp);
3196 }
3197 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3198 }
3199
3200 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3201 {
3202 bnx2x_config_mf_bw(bp);
3203 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3204 }
3205
3206 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3207 {
3208 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3209 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3210 }
3211
3212 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3213 {
3214 enum drv_info_opcode op_code;
3215 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3216
3217 /* if drv_info version supported by MFW doesn't match - send NACK */
3218 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3219 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3220 return;
3221 }
3222
3223 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3224 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3225
3226 memset(&bp->slowpath->drv_info_to_mcp, 0,
3227 sizeof(union drv_info_to_mcp));
3228
3229 switch (op_code) {
3230 case ETH_STATS_OPCODE:
3231 bnx2x_drv_info_ether_stat(bp);
3232 break;
3233 case FCOE_STATS_OPCODE:
3234 bnx2x_drv_info_fcoe_stat(bp);
3235 break;
3236 case ISCSI_STATS_OPCODE:
3237 bnx2x_drv_info_iscsi_stat(bp);
3238 break;
3239 default:
3240 /* if op code isn't supported - send NACK */
3241 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3242 return;
3243 }
3244
3245 /* if we got drv_info attn from MFW then these fields are defined in
3246 * shmem2 for sure
3247 */
3248 SHMEM2_WR(bp, drv_info_host_addr_lo,
3249 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3250 SHMEM2_WR(bp, drv_info_host_addr_hi,
3251 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3252
3253 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3254 }
3255
3256 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3257 {
3258 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3259
3260 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3261
3262 /*
3263 * This is the only place besides the function initialization
3264 * where the bp->flags can change so it is done without any
3265 * locks
3266 */
3267 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3268 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3269 bp->flags |= MF_FUNC_DIS;
3270
3271 bnx2x_e1h_disable(bp);
3272 } else {
3273 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3274 bp->flags &= ~MF_FUNC_DIS;
3275
3276 bnx2x_e1h_enable(bp);
3277 }
3278 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3279 }
3280 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3281 bnx2x_config_mf_bw(bp);
3282 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3283 }
3284
3285 /* Report results to MCP */
3286 if (dcc_event)
3287 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3288 else
3289 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3290 }
3291
3292 /* must be called under the spq lock */
3293 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3294 {
3295 struct eth_spe *next_spe = bp->spq_prod_bd;
3296
3297 if (bp->spq_prod_bd == bp->spq_last_bd) {
3298 bp->spq_prod_bd = bp->spq;
3299 bp->spq_prod_idx = 0;
3300 DP(BNX2X_MSG_SP, "end of spq\n");
3301 } else {
3302 bp->spq_prod_bd++;
3303 bp->spq_prod_idx++;
3304 }
3305 return next_spe;
3306 }
3307
3308 /* must be called under the spq lock */
3309 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3310 {
3311 int func = BP_FUNC(bp);
3312
3313 /*
3314 * Make sure that BD data is updated before writing the producer:
3315 * BD data is written to the memory, the producer is read from the
3316 * memory, thus we need a full memory barrier to ensure the ordering.
3317 */
3318 mb();
3319
3320 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3321 bp->spq_prod_idx);
3322 mmiowb();
3323 }
3324
3325 /**
3326 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3327 *
3328 * @cmd: command to check
3329 * @cmd_type: command type
3330 */
3331 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3332 {
3333 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3334 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3335 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3336 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3337 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3338 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3339 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3340 return true;
3341 else
3342 return false;
3343
3344 }
3345
3346
3347 /**
3348 * bnx2x_sp_post - place a single command on an SP ring
3349 *
3350 * @bp: driver handle
3351 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3352 * @cid: SW CID the command is related to
3353 * @data_hi: command private data address (high 32 bits)
3354 * @data_lo: command private data address (low 32 bits)
3355 * @cmd_type: command type (e.g. NONE, ETH)
3356 *
3357 * SP data is handled as if it's always an address pair, thus data fields are
3358 * not swapped to little endian in upper functions. Instead this function swaps
3359 * data as if it's two u32 fields.
3360 */
3361 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3362 u32 data_hi, u32 data_lo, int cmd_type)
3363 {
3364 struct eth_spe *spe;
3365 u16 type;
3366 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3367
3368 #ifdef BNX2X_STOP_ON_ERROR
3369 if (unlikely(bp->panic)) {
3370 BNX2X_ERR("Can't post SP when there is panic\n");
3371 return -EIO;
3372 }
3373 #endif
3374
3375 spin_lock_bh(&bp->spq_lock);
3376
3377 if (common) {
3378 if (!atomic_read(&bp->eq_spq_left)) {
3379 BNX2X_ERR("BUG! EQ ring full!\n");
3380 spin_unlock_bh(&bp->spq_lock);
3381 bnx2x_panic();
3382 return -EBUSY;
3383 }
3384 } else if (!atomic_read(&bp->cq_spq_left)) {
3385 BNX2X_ERR("BUG! SPQ ring full!\n");
3386 spin_unlock_bh(&bp->spq_lock);
3387 bnx2x_panic();
3388 return -EBUSY;
3389 }
3390
3391 spe = bnx2x_sp_get_next(bp);
3392
3393 /* CID needs port number to be encoded int it */
3394 spe->hdr.conn_and_cmd_data =
3395 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3396 HW_CID(bp, cid));
3397
3398 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3399
3400 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3401 SPE_HDR_FUNCTION_ID);
3402
3403 spe->hdr.type = cpu_to_le16(type);
3404
3405 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3406 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3407
3408 /*
3409 * It's ok if the actual decrement is issued towards the memory
3410 * somewhere between the spin_lock and spin_unlock. Thus no
3411 * more explict memory barrier is needed.
3412 */
3413 if (common)
3414 atomic_dec(&bp->eq_spq_left);
3415 else
3416 atomic_dec(&bp->cq_spq_left);
3417
3418
3419 DP(BNX2X_MSG_SP,
3420 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3421 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3422 (u32)(U64_LO(bp->spq_mapping) +
3423 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3424 HW_CID(bp, cid), data_hi, data_lo, type,
3425 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3426
3427 bnx2x_sp_prod_update(bp);
3428 spin_unlock_bh(&bp->spq_lock);
3429 return 0;
3430 }
3431
3432 /* acquire split MCP access lock register */
3433 static int bnx2x_acquire_alr(struct bnx2x *bp)
3434 {
3435 u32 j, val;
3436 int rc = 0;
3437
3438 might_sleep();
3439 for (j = 0; j < 1000; j++) {
3440 val = (1UL << 31);
3441 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3442 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3443 if (val & (1L << 31))
3444 break;
3445
3446 msleep(5);
3447 }
3448 if (!(val & (1L << 31))) {
3449 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3450 rc = -EBUSY;
3451 }
3452
3453 return rc;
3454 }
3455
3456 /* release split MCP access lock register */
3457 static void bnx2x_release_alr(struct bnx2x *bp)
3458 {
3459 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3460 }
3461
3462 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3463 #define BNX2X_DEF_SB_IDX 0x0002
3464
3465 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3466 {
3467 struct host_sp_status_block *def_sb = bp->def_status_blk;
3468 u16 rc = 0;
3469
3470 barrier(); /* status block is written to by the chip */
3471 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3472 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3473 rc |= BNX2X_DEF_SB_ATT_IDX;
3474 }
3475
3476 if (bp->def_idx != def_sb->sp_sb.running_index) {
3477 bp->def_idx = def_sb->sp_sb.running_index;
3478 rc |= BNX2X_DEF_SB_IDX;
3479 }
3480
3481 /* Do not reorder: indecies reading should complete before handling */
3482 barrier();
3483 return rc;
3484 }
3485
3486 /*
3487 * slow path service functions
3488 */
3489
3490 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3491 {
3492 int port = BP_PORT(bp);
3493 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3494 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3495 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3496 NIG_REG_MASK_INTERRUPT_PORT0;
3497 u32 aeu_mask;
3498 u32 nig_mask = 0;
3499 u32 reg_addr;
3500
3501 if (bp->attn_state & asserted)
3502 BNX2X_ERR("IGU ERROR\n");
3503
3504 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3505 aeu_mask = REG_RD(bp, aeu_addr);
3506
3507 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3508 aeu_mask, asserted);
3509 aeu_mask &= ~(asserted & 0x3ff);
3510 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3511
3512 REG_WR(bp, aeu_addr, aeu_mask);
3513 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3514
3515 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3516 bp->attn_state |= asserted;
3517 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3518
3519 if (asserted & ATTN_HARD_WIRED_MASK) {
3520 if (asserted & ATTN_NIG_FOR_FUNC) {
3521
3522 bnx2x_acquire_phy_lock(bp);
3523
3524 /* save nig interrupt mask */
3525 nig_mask = REG_RD(bp, nig_int_mask_addr);
3526
3527 /* If nig_mask is not set, no need to call the update
3528 * function.
3529 */
3530 if (nig_mask) {
3531 REG_WR(bp, nig_int_mask_addr, 0);
3532
3533 bnx2x_link_attn(bp);
3534 }
3535
3536 /* handle unicore attn? */
3537 }
3538 if (asserted & ATTN_SW_TIMER_4_FUNC)
3539 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3540
3541 if (asserted & GPIO_2_FUNC)
3542 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3543
3544 if (asserted & GPIO_3_FUNC)
3545 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3546
3547 if (asserted & GPIO_4_FUNC)
3548 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3549
3550 if (port == 0) {
3551 if (asserted & ATTN_GENERAL_ATTN_1) {
3552 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3553 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3554 }
3555 if (asserted & ATTN_GENERAL_ATTN_2) {
3556 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3557 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3558 }
3559 if (asserted & ATTN_GENERAL_ATTN_3) {
3560 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3561 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3562 }
3563 } else {
3564 if (asserted & ATTN_GENERAL_ATTN_4) {
3565 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3566 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3567 }
3568 if (asserted & ATTN_GENERAL_ATTN_5) {
3569 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3570 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3571 }
3572 if (asserted & ATTN_GENERAL_ATTN_6) {
3573 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3574 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3575 }
3576 }
3577
3578 } /* if hardwired */
3579
3580 if (bp->common.int_block == INT_BLOCK_HC)
3581 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3582 COMMAND_REG_ATTN_BITS_SET);
3583 else
3584 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3585
3586 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3587 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3588 REG_WR(bp, reg_addr, asserted);
3589
3590 /* now set back the mask */
3591 if (asserted & ATTN_NIG_FOR_FUNC) {
3592 REG_WR(bp, nig_int_mask_addr, nig_mask);
3593 bnx2x_release_phy_lock(bp);
3594 }
3595 }
3596
3597 static void bnx2x_fan_failure(struct bnx2x *bp)
3598 {
3599 int port = BP_PORT(bp);
3600 u32 ext_phy_config;
3601 /* mark the failure */
3602 ext_phy_config =
3603 SHMEM_RD(bp,
3604 dev_info.port_hw_config[port].external_phy_config);
3605
3606 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3607 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3608 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3609 ext_phy_config);
3610
3611 /* log the failure */
3612 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3613 "Please contact OEM Support for assistance\n");
3614
3615 /*
3616 * Scheudle device reset (unload)
3617 * This is due to some boards consuming sufficient power when driver is
3618 * up to overheat if fan fails.
3619 */
3620 smp_mb__before_clear_bit();
3621 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3622 smp_mb__after_clear_bit();
3623 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3624
3625 }
3626
3627 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3628 {
3629 int port = BP_PORT(bp);
3630 int reg_offset;
3631 u32 val;
3632
3633 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3634 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3635
3636 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3637
3638 val = REG_RD(bp, reg_offset);
3639 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3640 REG_WR(bp, reg_offset, val);
3641
3642 BNX2X_ERR("SPIO5 hw attention\n");
3643
3644 /* Fan failure attention */
3645 bnx2x_hw_reset_phy(&bp->link_params);
3646 bnx2x_fan_failure(bp);
3647 }
3648
3649 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3650 bnx2x_acquire_phy_lock(bp);
3651 bnx2x_handle_module_detect_int(&bp->link_params);
3652 bnx2x_release_phy_lock(bp);
3653 }
3654
3655 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3656
3657 val = REG_RD(bp, reg_offset);
3658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3659 REG_WR(bp, reg_offset, val);
3660
3661 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3662 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3663 bnx2x_panic();
3664 }
3665 }
3666
3667 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3668 {
3669 u32 val;
3670
3671 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3672
3673 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3674 BNX2X_ERR("DB hw attention 0x%x\n", val);
3675 /* DORQ discard attention */
3676 if (val & 0x2)
3677 BNX2X_ERR("FATAL error from DORQ\n");
3678 }
3679
3680 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3681
3682 int port = BP_PORT(bp);
3683 int reg_offset;
3684
3685 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3686 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3687
3688 val = REG_RD(bp, reg_offset);
3689 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3690 REG_WR(bp, reg_offset, val);
3691
3692 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3693 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3694 bnx2x_panic();
3695 }
3696 }
3697
3698 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3699 {
3700 u32 val;
3701
3702 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3703
3704 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3705 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3706 /* CFC error attention */
3707 if (val & 0x2)
3708 BNX2X_ERR("FATAL error from CFC\n");
3709 }
3710
3711 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3712 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3713 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3714 /* RQ_USDMDP_FIFO_OVERFLOW */
3715 if (val & 0x18000)
3716 BNX2X_ERR("FATAL error from PXP\n");
3717
3718 if (!CHIP_IS_E1x(bp)) {
3719 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3720 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3721 }
3722 }
3723
3724 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3725
3726 int port = BP_PORT(bp);
3727 int reg_offset;
3728
3729 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3730 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3731
3732 val = REG_RD(bp, reg_offset);
3733 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3734 REG_WR(bp, reg_offset, val);
3735
3736 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3737 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3738 bnx2x_panic();
3739 }
3740 }
3741
3742 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3743 {
3744 u32 val;
3745
3746 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3747
3748 if (attn & BNX2X_PMF_LINK_ASSERT) {
3749 int func = BP_FUNC(bp);
3750
3751 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3752 bnx2x_read_mf_cfg(bp);
3753 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3754 func_mf_config[BP_ABS_FUNC(bp)].config);
3755 val = SHMEM_RD(bp,
3756 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3757 if (val & DRV_STATUS_DCC_EVENT_MASK)
3758 bnx2x_dcc_event(bp,
3759 (val & DRV_STATUS_DCC_EVENT_MASK));
3760
3761 if (val & DRV_STATUS_SET_MF_BW)
3762 bnx2x_set_mf_bw(bp);
3763
3764 if (val & DRV_STATUS_DRV_INFO_REQ)
3765 bnx2x_handle_drv_info_req(bp);
3766 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3767 bnx2x_pmf_update(bp);
3768
3769 if (bp->port.pmf &&
3770 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3771 bp->dcbx_enabled > 0)
3772 /* start dcbx state machine */
3773 bnx2x_dcbx_set_params(bp,
3774 BNX2X_DCBX_STATE_NEG_RECEIVED);
3775 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3776 bnx2x_handle_afex_cmd(bp,
3777 val & DRV_STATUS_AFEX_EVENT_MASK);
3778 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3779 bnx2x_handle_eee_event(bp);
3780 if (bp->link_vars.periodic_flags &
3781 PERIODIC_FLAGS_LINK_EVENT) {
3782 /* sync with link */
3783 bnx2x_acquire_phy_lock(bp);
3784 bp->link_vars.periodic_flags &=
3785 ~PERIODIC_FLAGS_LINK_EVENT;
3786 bnx2x_release_phy_lock(bp);
3787 if (IS_MF(bp))
3788 bnx2x_link_sync_notify(bp);
3789 bnx2x_link_report(bp);
3790 }
3791 /* Always call it here: bnx2x_link_report() will
3792 * prevent the link indication duplication.
3793 */
3794 bnx2x__link_status_update(bp);
3795 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3796
3797 BNX2X_ERR("MC assert!\n");
3798 bnx2x_mc_assert(bp);
3799 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3800 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3801 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3802 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3803 bnx2x_panic();
3804
3805 } else if (attn & BNX2X_MCP_ASSERT) {
3806
3807 BNX2X_ERR("MCP assert!\n");
3808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3809 bnx2x_fw_dump(bp);
3810
3811 } else
3812 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3813 }
3814
3815 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3816 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3817 if (attn & BNX2X_GRC_TIMEOUT) {
3818 val = CHIP_IS_E1(bp) ? 0 :
3819 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3820 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3821 }
3822 if (attn & BNX2X_GRC_RSV) {
3823 val = CHIP_IS_E1(bp) ? 0 :
3824 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3825 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3826 }
3827 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3828 }
3829 }
3830
3831 /*
3832 * Bits map:
3833 * 0-7 - Engine0 load counter.
3834 * 8-15 - Engine1 load counter.
3835 * 16 - Engine0 RESET_IN_PROGRESS bit.
3836 * 17 - Engine1 RESET_IN_PROGRESS bit.
3837 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3838 * on the engine
3839 * 19 - Engine1 ONE_IS_LOADED.
3840 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3841 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3842 * just the one belonging to its engine).
3843 *
3844 */
3845 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3846
3847 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3848 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3849 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3850 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3851 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3852 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3853 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3854
3855 /*
3856 * Set the GLOBAL_RESET bit.
3857 *
3858 * Should be run under rtnl lock
3859 */
3860 void bnx2x_set_reset_global(struct bnx2x *bp)
3861 {
3862 u32 val;
3863 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3864 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3865 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3866 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3867 }
3868
3869 /*
3870 * Clear the GLOBAL_RESET bit.
3871 *
3872 * Should be run under rtnl lock
3873 */
3874 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3875 {
3876 u32 val;
3877 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3878 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3879 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3880 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3881 }
3882
3883 /*
3884 * Checks the GLOBAL_RESET bit.
3885 *
3886 * should be run under rtnl lock
3887 */
3888 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3889 {
3890 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3891
3892 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3893 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3894 }
3895
3896 /*
3897 * Clear RESET_IN_PROGRESS bit for the current engine.
3898 *
3899 * Should be run under rtnl lock
3900 */
3901 static void bnx2x_set_reset_done(struct bnx2x *bp)
3902 {
3903 u32 val;
3904 u32 bit = BP_PATH(bp) ?
3905 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3907 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908
3909 /* Clear the bit */
3910 val &= ~bit;
3911 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3912
3913 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3914 }
3915
3916 /*
3917 * Set RESET_IN_PROGRESS for the current engine.
3918 *
3919 * should be run under rtnl lock
3920 */
3921 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3922 {
3923 u32 val;
3924 u32 bit = BP_PATH(bp) ?
3925 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3926 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3927 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3928
3929 /* Set the bit */
3930 val |= bit;
3931 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3932 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3933 }
3934
3935 /*
3936 * Checks the RESET_IN_PROGRESS bit for the given engine.
3937 * should be run under rtnl lock
3938 */
3939 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3940 {
3941 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3942 u32 bit = engine ?
3943 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3944
3945 /* return false if bit is set */
3946 return (val & bit) ? false : true;
3947 }
3948
3949 /*
3950 * set pf load for the current pf.
3951 *
3952 * should be run under rtnl lock
3953 */
3954 void bnx2x_set_pf_load(struct bnx2x *bp)
3955 {
3956 u32 val1, val;
3957 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3958 BNX2X_PATH0_LOAD_CNT_MASK;
3959 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3960 BNX2X_PATH0_LOAD_CNT_SHIFT;
3961
3962 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3963 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3964
3965 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3966
3967 /* get the current counter value */
3968 val1 = (val & mask) >> shift;
3969
3970 /* set bit of that PF */
3971 val1 |= (1 << bp->pf_num);
3972
3973 /* clear the old value */
3974 val &= ~mask;
3975
3976 /* set the new one */
3977 val |= ((val1 << shift) & mask);
3978
3979 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3980 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3981 }
3982
3983 /**
3984 * bnx2x_clear_pf_load - clear pf load mark
3985 *
3986 * @bp: driver handle
3987 *
3988 * Should be run under rtnl lock.
3989 * Decrements the load counter for the current engine. Returns
3990 * whether other functions are still loaded
3991 */
3992 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3993 {
3994 u32 val1, val;
3995 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3996 BNX2X_PATH0_LOAD_CNT_MASK;
3997 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3998 BNX2X_PATH0_LOAD_CNT_SHIFT;
3999
4000 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4001 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4002 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4003
4004 /* get the current counter value */
4005 val1 = (val & mask) >> shift;
4006
4007 /* clear bit of that PF */
4008 val1 &= ~(1 << bp->pf_num);
4009
4010 /* clear the old value */
4011 val &= ~mask;
4012
4013 /* set the new one */
4014 val |= ((val1 << shift) & mask);
4015
4016 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4018 return val1 != 0;
4019 }
4020
4021 /*
4022 * Read the load status for the current engine.
4023 *
4024 * should be run under rtnl lock
4025 */
4026 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4027 {
4028 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4029 BNX2X_PATH0_LOAD_CNT_MASK);
4030 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4031 BNX2X_PATH0_LOAD_CNT_SHIFT);
4032 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4033
4034 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4035
4036 val = (val & mask) >> shift;
4037
4038 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4039 engine, val);
4040
4041 return val != 0;
4042 }
4043
4044 /*
4045 * Reset the load status for the current engine.
4046 */
4047 static void bnx2x_clear_load_status(struct bnx2x *bp)
4048 {
4049 u32 val;
4050 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4051 BNX2X_PATH0_LOAD_CNT_MASK);
4052 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4053 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4054 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
4055 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4056 }
4057
4058 static void _print_next_block(int idx, const char *blk)
4059 {
4060 pr_cont("%s%s", idx ? ", " : "", blk);
4061 }
4062
4063 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4064 bool print)
4065 {
4066 int i = 0;
4067 u32 cur_bit = 0;
4068 for (i = 0; sig; i++) {
4069 cur_bit = ((u32)0x1 << i);
4070 if (sig & cur_bit) {
4071 switch (cur_bit) {
4072 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4073 if (print)
4074 _print_next_block(par_num++, "BRB");
4075 break;
4076 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4077 if (print)
4078 _print_next_block(par_num++, "PARSER");
4079 break;
4080 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4081 if (print)
4082 _print_next_block(par_num++, "TSDM");
4083 break;
4084 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4085 if (print)
4086 _print_next_block(par_num++,
4087 "SEARCHER");
4088 break;
4089 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4090 if (print)
4091 _print_next_block(par_num++, "TCM");
4092 break;
4093 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4094 if (print)
4095 _print_next_block(par_num++, "TSEMI");
4096 break;
4097 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4098 if (print)
4099 _print_next_block(par_num++, "XPB");
4100 break;
4101 }
4102
4103 /* Clear the bit */
4104 sig &= ~cur_bit;
4105 }
4106 }
4107
4108 return par_num;
4109 }
4110
4111 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4112 bool *global, bool print)
4113 {
4114 int i = 0;
4115 u32 cur_bit = 0;
4116 for (i = 0; sig; i++) {
4117 cur_bit = ((u32)0x1 << i);
4118 if (sig & cur_bit) {
4119 switch (cur_bit) {
4120 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4121 if (print)
4122 _print_next_block(par_num++, "PBF");
4123 break;
4124 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4125 if (print)
4126 _print_next_block(par_num++, "QM");
4127 break;
4128 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4129 if (print)
4130 _print_next_block(par_num++, "TM");
4131 break;
4132 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4133 if (print)
4134 _print_next_block(par_num++, "XSDM");
4135 break;
4136 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4137 if (print)
4138 _print_next_block(par_num++, "XCM");
4139 break;
4140 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4141 if (print)
4142 _print_next_block(par_num++, "XSEMI");
4143 break;
4144 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4145 if (print)
4146 _print_next_block(par_num++,
4147 "DOORBELLQ");
4148 break;
4149 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4150 if (print)
4151 _print_next_block(par_num++, "NIG");
4152 break;
4153 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4154 if (print)
4155 _print_next_block(par_num++,
4156 "VAUX PCI CORE");
4157 *global = true;
4158 break;
4159 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4160 if (print)
4161 _print_next_block(par_num++, "DEBUG");
4162 break;
4163 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4164 if (print)
4165 _print_next_block(par_num++, "USDM");
4166 break;
4167 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4168 if (print)
4169 _print_next_block(par_num++, "UCM");
4170 break;
4171 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4172 if (print)
4173 _print_next_block(par_num++, "USEMI");
4174 break;
4175 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4176 if (print)
4177 _print_next_block(par_num++, "UPB");
4178 break;
4179 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4180 if (print)
4181 _print_next_block(par_num++, "CSDM");
4182 break;
4183 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4184 if (print)
4185 _print_next_block(par_num++, "CCM");
4186 break;
4187 }
4188
4189 /* Clear the bit */
4190 sig &= ~cur_bit;
4191 }
4192 }
4193
4194 return par_num;
4195 }
4196
4197 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4198 bool print)
4199 {
4200 int i = 0;
4201 u32 cur_bit = 0;
4202 for (i = 0; sig; i++) {
4203 cur_bit = ((u32)0x1 << i);
4204 if (sig & cur_bit) {
4205 switch (cur_bit) {
4206 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4207 if (print)
4208 _print_next_block(par_num++, "CSEMI");
4209 break;
4210 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4211 if (print)
4212 _print_next_block(par_num++, "PXP");
4213 break;
4214 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4215 if (print)
4216 _print_next_block(par_num++,
4217 "PXPPCICLOCKCLIENT");
4218 break;
4219 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4220 if (print)
4221 _print_next_block(par_num++, "CFC");
4222 break;
4223 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4224 if (print)
4225 _print_next_block(par_num++, "CDU");
4226 break;
4227 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4228 if (print)
4229 _print_next_block(par_num++, "DMAE");
4230 break;
4231 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4232 if (print)
4233 _print_next_block(par_num++, "IGU");
4234 break;
4235 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4236 if (print)
4237 _print_next_block(par_num++, "MISC");
4238 break;
4239 }
4240
4241 /* Clear the bit */
4242 sig &= ~cur_bit;
4243 }
4244 }
4245
4246 return par_num;
4247 }
4248
4249 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4250 bool *global, bool print)
4251 {
4252 int i = 0;
4253 u32 cur_bit = 0;
4254 for (i = 0; sig; i++) {
4255 cur_bit = ((u32)0x1 << i);
4256 if (sig & cur_bit) {
4257 switch (cur_bit) {
4258 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4259 if (print)
4260 _print_next_block(par_num++, "MCP ROM");
4261 *global = true;
4262 break;
4263 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4264 if (print)
4265 _print_next_block(par_num++,
4266 "MCP UMP RX");
4267 *global = true;
4268 break;
4269 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4270 if (print)
4271 _print_next_block(par_num++,
4272 "MCP UMP TX");
4273 *global = true;
4274 break;
4275 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4276 if (print)
4277 _print_next_block(par_num++,
4278 "MCP SCPAD");
4279 *global = true;
4280 break;
4281 }
4282
4283 /* Clear the bit */
4284 sig &= ~cur_bit;
4285 }
4286 }
4287
4288 return par_num;
4289 }
4290
4291 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4292 bool print)
4293 {
4294 int i = 0;
4295 u32 cur_bit = 0;
4296 for (i = 0; sig; i++) {
4297 cur_bit = ((u32)0x1 << i);
4298 if (sig & cur_bit) {
4299 switch (cur_bit) {
4300 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4301 if (print)
4302 _print_next_block(par_num++, "PGLUE_B");
4303 break;
4304 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4305 if (print)
4306 _print_next_block(par_num++, "ATC");
4307 break;
4308 }
4309
4310 /* Clear the bit */
4311 sig &= ~cur_bit;
4312 }
4313 }
4314
4315 return par_num;
4316 }
4317
4318 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4319 u32 *sig)
4320 {
4321 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4322 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4323 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4324 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4325 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4326 int par_num = 0;
4327 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4328 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4329 sig[0] & HW_PRTY_ASSERT_SET_0,
4330 sig[1] & HW_PRTY_ASSERT_SET_1,
4331 sig[2] & HW_PRTY_ASSERT_SET_2,
4332 sig[3] & HW_PRTY_ASSERT_SET_3,
4333 sig[4] & HW_PRTY_ASSERT_SET_4);
4334 if (print)
4335 netdev_err(bp->dev,
4336 "Parity errors detected in blocks: ");
4337 par_num = bnx2x_check_blocks_with_parity0(
4338 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4339 par_num = bnx2x_check_blocks_with_parity1(
4340 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4341 par_num = bnx2x_check_blocks_with_parity2(
4342 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4343 par_num = bnx2x_check_blocks_with_parity3(
4344 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4345 par_num = bnx2x_check_blocks_with_parity4(
4346 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4347
4348 if (print)
4349 pr_cont("\n");
4350
4351 return true;
4352 } else
4353 return false;
4354 }
4355
4356 /**
4357 * bnx2x_chk_parity_attn - checks for parity attentions.
4358 *
4359 * @bp: driver handle
4360 * @global: true if there was a global attention
4361 * @print: show parity attention in syslog
4362 */
4363 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4364 {
4365 struct attn_route attn = { {0} };
4366 int port = BP_PORT(bp);
4367
4368 attn.sig[0] = REG_RD(bp,
4369 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4370 port*4);
4371 attn.sig[1] = REG_RD(bp,
4372 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4373 port*4);
4374 attn.sig[2] = REG_RD(bp,
4375 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4376 port*4);
4377 attn.sig[3] = REG_RD(bp,
4378 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4379 port*4);
4380
4381 if (!CHIP_IS_E1x(bp))
4382 attn.sig[4] = REG_RD(bp,
4383 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4384 port*4);
4385
4386 return bnx2x_parity_attn(bp, global, print, attn.sig);
4387 }
4388
4389
4390 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4391 {
4392 u32 val;
4393 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4394
4395 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4396 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4397 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4398 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4399 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4400 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4401 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4402 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4403 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4404 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4405 if (val &
4406 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4407 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4408 if (val &
4409 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4410 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4411 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4412 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4413 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4414 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4415 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4416 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4417 }
4418 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4419 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4420 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4421 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4422 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4423 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4424 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4425 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4426 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4427 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4428 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4429 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4430 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4431 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4432 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4433 }
4434
4435 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4436 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4437 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4438 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4439 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4440 }
4441
4442 }
4443
4444 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4445 {
4446 struct attn_route attn, *group_mask;
4447 int port = BP_PORT(bp);
4448 int index;
4449 u32 reg_addr;
4450 u32 val;
4451 u32 aeu_mask;
4452 bool global = false;
4453
4454 /* need to take HW lock because MCP or other port might also
4455 try to handle this event */
4456 bnx2x_acquire_alr(bp);
4457
4458 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4459 #ifndef BNX2X_STOP_ON_ERROR
4460 bp->recovery_state = BNX2X_RECOVERY_INIT;
4461 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4462 /* Disable HW interrupts */
4463 bnx2x_int_disable(bp);
4464 /* In case of parity errors don't handle attentions so that
4465 * other function would "see" parity errors.
4466 */
4467 #else
4468 bnx2x_panic();
4469 #endif
4470 bnx2x_release_alr(bp);
4471 return;
4472 }
4473
4474 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4475 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4476 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4477 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4478 if (!CHIP_IS_E1x(bp))
4479 attn.sig[4] =
4480 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4481 else
4482 attn.sig[4] = 0;
4483
4484 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4485 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4486
4487 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4488 if (deasserted & (1 << index)) {
4489 group_mask = &bp->attn_group[index];
4490
4491 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4492 index,
4493 group_mask->sig[0], group_mask->sig[1],
4494 group_mask->sig[2], group_mask->sig[3],
4495 group_mask->sig[4]);
4496
4497 bnx2x_attn_int_deasserted4(bp,
4498 attn.sig[4] & group_mask->sig[4]);
4499 bnx2x_attn_int_deasserted3(bp,
4500 attn.sig[3] & group_mask->sig[3]);
4501 bnx2x_attn_int_deasserted1(bp,
4502 attn.sig[1] & group_mask->sig[1]);
4503 bnx2x_attn_int_deasserted2(bp,
4504 attn.sig[2] & group_mask->sig[2]);
4505 bnx2x_attn_int_deasserted0(bp,
4506 attn.sig[0] & group_mask->sig[0]);
4507 }
4508 }
4509
4510 bnx2x_release_alr(bp);
4511
4512 if (bp->common.int_block == INT_BLOCK_HC)
4513 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4514 COMMAND_REG_ATTN_BITS_CLR);
4515 else
4516 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4517
4518 val = ~deasserted;
4519 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4520 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4521 REG_WR(bp, reg_addr, val);
4522
4523 if (~bp->attn_state & deasserted)
4524 BNX2X_ERR("IGU ERROR\n");
4525
4526 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4527 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4528
4529 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4530 aeu_mask = REG_RD(bp, reg_addr);
4531
4532 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4533 aeu_mask, deasserted);
4534 aeu_mask |= (deasserted & 0x3ff);
4535 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4536
4537 REG_WR(bp, reg_addr, aeu_mask);
4538 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4539
4540 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4541 bp->attn_state &= ~deasserted;
4542 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4543 }
4544
4545 static void bnx2x_attn_int(struct bnx2x *bp)
4546 {
4547 /* read local copy of bits */
4548 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4549 attn_bits);
4550 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4551 attn_bits_ack);
4552 u32 attn_state = bp->attn_state;
4553
4554 /* look for changed bits */
4555 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4556 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4557
4558 DP(NETIF_MSG_HW,
4559 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4560 attn_bits, attn_ack, asserted, deasserted);
4561
4562 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4563 BNX2X_ERR("BAD attention state\n");
4564
4565 /* handle bits that were raised */
4566 if (asserted)
4567 bnx2x_attn_int_asserted(bp, asserted);
4568
4569 if (deasserted)
4570 bnx2x_attn_int_deasserted(bp, deasserted);
4571 }
4572
4573 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4574 u16 index, u8 op, u8 update)
4575 {
4576 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4577
4578 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4579 igu_addr);
4580 }
4581
4582 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4583 {
4584 /* No memory barriers */
4585 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4586 mmiowb(); /* keep prod updates ordered */
4587 }
4588
4589 #ifdef BCM_CNIC
4590 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4591 union event_ring_elem *elem)
4592 {
4593 u8 err = elem->message.error;
4594
4595 if (!bp->cnic_eth_dev.starting_cid ||
4596 (cid < bp->cnic_eth_dev.starting_cid &&
4597 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4598 return 1;
4599
4600 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4601
4602 if (unlikely(err)) {
4603
4604 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4605 cid);
4606 bnx2x_panic_dump(bp);
4607 }
4608 bnx2x_cnic_cfc_comp(bp, cid, err);
4609 return 0;
4610 }
4611 #endif
4612
4613 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4614 {
4615 struct bnx2x_mcast_ramrod_params rparam;
4616 int rc;
4617
4618 memset(&rparam, 0, sizeof(rparam));
4619
4620 rparam.mcast_obj = &bp->mcast_obj;
4621
4622 netif_addr_lock_bh(bp->dev);
4623
4624 /* Clear pending state for the last command */
4625 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4626
4627 /* If there are pending mcast commands - send them */
4628 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4629 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4630 if (rc < 0)
4631 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4632 rc);
4633 }
4634
4635 netif_addr_unlock_bh(bp->dev);
4636 }
4637
4638 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4639 union event_ring_elem *elem)
4640 {
4641 unsigned long ramrod_flags = 0;
4642 int rc = 0;
4643 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4644 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4645
4646 /* Always push next commands out, don't wait here */
4647 __set_bit(RAMROD_CONT, &ramrod_flags);
4648
4649 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4650 case BNX2X_FILTER_MAC_PENDING:
4651 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4652 #ifdef BCM_CNIC
4653 if (cid == BNX2X_ISCSI_ETH_CID(bp))
4654 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4655 else
4656 #endif
4657 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4658
4659 break;
4660 case BNX2X_FILTER_MCAST_PENDING:
4661 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4662 /* This is only relevant for 57710 where multicast MACs are
4663 * configured as unicast MACs using the same ramrod.
4664 */
4665 bnx2x_handle_mcast_eqe(bp);
4666 return;
4667 default:
4668 BNX2X_ERR("Unsupported classification command: %d\n",
4669 elem->message.data.eth_event.echo);
4670 return;
4671 }
4672
4673 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4674
4675 if (rc < 0)
4676 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4677 else if (rc > 0)
4678 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4679
4680 }
4681
4682 #ifdef BCM_CNIC
4683 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4684 #endif
4685
4686 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4687 {
4688 netif_addr_lock_bh(bp->dev);
4689
4690 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4691
4692 /* Send rx_mode command again if was requested */
4693 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4694 bnx2x_set_storm_rx_mode(bp);
4695 #ifdef BCM_CNIC
4696 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4697 &bp->sp_state))
4698 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4699 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4700 &bp->sp_state))
4701 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4702 #endif
4703
4704 netif_addr_unlock_bh(bp->dev);
4705 }
4706
4707 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4708 union event_ring_elem *elem)
4709 {
4710 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4711 DP(BNX2X_MSG_SP,
4712 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4713 elem->message.data.vif_list_event.func_bit_map);
4714 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4715 elem->message.data.vif_list_event.func_bit_map);
4716 } else if (elem->message.data.vif_list_event.echo ==
4717 VIF_LIST_RULE_SET) {
4718 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4719 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4720 }
4721 }
4722
4723 /* called with rtnl_lock */
4724 static void bnx2x_after_function_update(struct bnx2x *bp)
4725 {
4726 int q, rc;
4727 struct bnx2x_fastpath *fp;
4728 struct bnx2x_queue_state_params queue_params = {NULL};
4729 struct bnx2x_queue_update_params *q_update_params =
4730 &queue_params.params.update;
4731
4732 /* Send Q update command with afex vlan removal values for all Qs */
4733 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4734
4735 /* set silent vlan removal values according to vlan mode */
4736 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4737 &q_update_params->update_flags);
4738 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4739 &q_update_params->update_flags);
4740 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4741
4742 /* in access mode mark mask and value are 0 to strip all vlans */
4743 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4744 q_update_params->silent_removal_value = 0;
4745 q_update_params->silent_removal_mask = 0;
4746 } else {
4747 q_update_params->silent_removal_value =
4748 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4749 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4750 }
4751
4752 for_each_eth_queue(bp, q) {
4753 /* Set the appropriate Queue object */
4754 fp = &bp->fp[q];
4755 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4756
4757 /* send the ramrod */
4758 rc = bnx2x_queue_state_change(bp, &queue_params);
4759 if (rc < 0)
4760 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4761 q);
4762 }
4763
4764 #ifdef BCM_CNIC
4765 if (!NO_FCOE(bp)) {
4766 fp = &bp->fp[FCOE_IDX(bp)];
4767 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4768
4769 /* clear pending completion bit */
4770 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4771
4772 /* mark latest Q bit */
4773 smp_mb__before_clear_bit();
4774 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4775 smp_mb__after_clear_bit();
4776
4777 /* send Q update ramrod for FCoE Q */
4778 rc = bnx2x_queue_state_change(bp, &queue_params);
4779 if (rc < 0)
4780 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4781 q);
4782 } else {
4783 /* If no FCoE ring - ACK MCP now */
4784 bnx2x_link_report(bp);
4785 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4786 }
4787 #else
4788 /* If no FCoE ring - ACK MCP now */
4789 bnx2x_link_report(bp);
4790 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4791 #endif /* BCM_CNIC */
4792 }
4793
4794 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4795 struct bnx2x *bp, u32 cid)
4796 {
4797 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4798 #ifdef BCM_CNIC
4799 if (cid == BNX2X_FCOE_ETH_CID(bp))
4800 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4801 else
4802 #endif
4803 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4804 }
4805
4806 static void bnx2x_eq_int(struct bnx2x *bp)
4807 {
4808 u16 hw_cons, sw_cons, sw_prod;
4809 union event_ring_elem *elem;
4810 u32 cid;
4811 u8 opcode;
4812 int spqe_cnt = 0;
4813 struct bnx2x_queue_sp_obj *q_obj;
4814 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4815 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4816
4817 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4818
4819 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4820 * when we get the the next-page we nned to adjust so the loop
4821 * condition below will be met. The next element is the size of a
4822 * regular element and hence incrementing by 1
4823 */
4824 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4825 hw_cons++;
4826
4827 /* This function may never run in parallel with itself for a
4828 * specific bp, thus there is no need in "paired" read memory
4829 * barrier here.
4830 */
4831 sw_cons = bp->eq_cons;
4832 sw_prod = bp->eq_prod;
4833
4834 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4835 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4836
4837 for (; sw_cons != hw_cons;
4838 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4839
4840
4841 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4842
4843 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4844 opcode = elem->message.opcode;
4845
4846
4847 /* handle eq element */
4848 switch (opcode) {
4849 case EVENT_RING_OPCODE_STAT_QUERY:
4850 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4851 "got statistics comp event %d\n",
4852 bp->stats_comp++);
4853 /* nothing to do with stats comp */
4854 goto next_spqe;
4855
4856 case EVENT_RING_OPCODE_CFC_DEL:
4857 /* handle according to cid range */
4858 /*
4859 * we may want to verify here that the bp state is
4860 * HALTING
4861 */
4862 DP(BNX2X_MSG_SP,
4863 "got delete ramrod for MULTI[%d]\n", cid);
4864 #ifdef BCM_CNIC
4865 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4866 goto next_spqe;
4867 #endif
4868 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4869
4870 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4871 break;
4872
4873
4874
4875 goto next_spqe;
4876
4877 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4878 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4879 if (f_obj->complete_cmd(bp, f_obj,
4880 BNX2X_F_CMD_TX_STOP))
4881 break;
4882 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4883 goto next_spqe;
4884
4885 case EVENT_RING_OPCODE_START_TRAFFIC:
4886 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4887 if (f_obj->complete_cmd(bp, f_obj,
4888 BNX2X_F_CMD_TX_START))
4889 break;
4890 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4891 goto next_spqe;
4892 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4893 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4894 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4895 f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4896
4897 /* We will perform the Queues update from sp_rtnl task
4898 * as all Queue SP operations should run under
4899 * rtnl_lock.
4900 */
4901 smp_mb__before_clear_bit();
4902 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4903 &bp->sp_rtnl_state);
4904 smp_mb__after_clear_bit();
4905
4906 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4907 goto next_spqe;
4908
4909 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4910 f_obj->complete_cmd(bp, f_obj,
4911 BNX2X_F_CMD_AFEX_VIFLISTS);
4912 bnx2x_after_afex_vif_lists(bp, elem);
4913 goto next_spqe;
4914 case EVENT_RING_OPCODE_FUNCTION_START:
4915 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4916 "got FUNC_START ramrod\n");
4917 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4918 break;
4919
4920 goto next_spqe;
4921
4922 case EVENT_RING_OPCODE_FUNCTION_STOP:
4923 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4924 "got FUNC_STOP ramrod\n");
4925 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4926 break;
4927
4928 goto next_spqe;
4929 }
4930
4931 switch (opcode | bp->state) {
4932 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4933 BNX2X_STATE_OPEN):
4934 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4935 BNX2X_STATE_OPENING_WAIT4_PORT):
4936 cid = elem->message.data.eth_event.echo &
4937 BNX2X_SWCID_MASK;
4938 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4939 cid);
4940 rss_raw->clear_pending(rss_raw);
4941 break;
4942
4943 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4944 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4945 case (EVENT_RING_OPCODE_SET_MAC |
4946 BNX2X_STATE_CLOSING_WAIT4_HALT):
4947 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4948 BNX2X_STATE_OPEN):
4949 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4950 BNX2X_STATE_DIAG):
4951 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4952 BNX2X_STATE_CLOSING_WAIT4_HALT):
4953 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4954 bnx2x_handle_classification_eqe(bp, elem);
4955 break;
4956
4957 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4958 BNX2X_STATE_OPEN):
4959 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4960 BNX2X_STATE_DIAG):
4961 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4962 BNX2X_STATE_CLOSING_WAIT4_HALT):
4963 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4964 bnx2x_handle_mcast_eqe(bp);
4965 break;
4966
4967 case (EVENT_RING_OPCODE_FILTERS_RULES |
4968 BNX2X_STATE_OPEN):
4969 case (EVENT_RING_OPCODE_FILTERS_RULES |
4970 BNX2X_STATE_DIAG):
4971 case (EVENT_RING_OPCODE_FILTERS_RULES |
4972 BNX2X_STATE_CLOSING_WAIT4_HALT):
4973 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4974 bnx2x_handle_rx_mode_eqe(bp);
4975 break;
4976 default:
4977 /* unknown event log error and continue */
4978 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4979 elem->message.opcode, bp->state);
4980 }
4981 next_spqe:
4982 spqe_cnt++;
4983 } /* for */
4984
4985 smp_mb__before_atomic_inc();
4986 atomic_add(spqe_cnt, &bp->eq_spq_left);
4987
4988 bp->eq_cons = sw_cons;
4989 bp->eq_prod = sw_prod;
4990 /* Make sure that above mem writes were issued towards the memory */
4991 smp_wmb();
4992
4993 /* update producer */
4994 bnx2x_update_eq_prod(bp, bp->eq_prod);
4995 }
4996
4997 static void bnx2x_sp_task(struct work_struct *work)
4998 {
4999 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5000 u16 status;
5001
5002 status = bnx2x_update_dsb_idx(bp);
5003 /* if (status == 0) */
5004 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
5005
5006 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
5007
5008 /* HW attentions */
5009 if (status & BNX2X_DEF_SB_ATT_IDX) {
5010 bnx2x_attn_int(bp);
5011 status &= ~BNX2X_DEF_SB_ATT_IDX;
5012 }
5013
5014 /* SP events: STAT_QUERY and others */
5015 if (status & BNX2X_DEF_SB_IDX) {
5016 #ifdef BCM_CNIC
5017 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5018
5019 if ((!NO_FCOE(bp)) &&
5020 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5021 /*
5022 * Prevent local bottom-halves from running as
5023 * we are going to change the local NAPI list.
5024 */
5025 local_bh_disable();
5026 napi_schedule(&bnx2x_fcoe(bp, napi));
5027 local_bh_enable();
5028 }
5029 #endif
5030 /* Handle EQ completions */
5031 bnx2x_eq_int(bp);
5032
5033 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5034 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5035
5036 status &= ~BNX2X_DEF_SB_IDX;
5037 }
5038
5039 if (unlikely(status))
5040 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5041 status);
5042
5043 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5044 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5045
5046 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5047 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5048 &bp->sp_state)) {
5049 bnx2x_link_report(bp);
5050 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5051 }
5052 }
5053
5054 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5055 {
5056 struct net_device *dev = dev_instance;
5057 struct bnx2x *bp = netdev_priv(dev);
5058
5059 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5060 IGU_INT_DISABLE, 0);
5061
5062 #ifdef BNX2X_STOP_ON_ERROR
5063 if (unlikely(bp->panic))
5064 return IRQ_HANDLED;
5065 #endif
5066
5067 #ifdef BCM_CNIC
5068 {
5069 struct cnic_ops *c_ops;
5070
5071 rcu_read_lock();
5072 c_ops = rcu_dereference(bp->cnic_ops);
5073 if (c_ops)
5074 c_ops->cnic_handler(bp->cnic_data, NULL);
5075 rcu_read_unlock();
5076 }
5077 #endif
5078 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5079
5080 return IRQ_HANDLED;
5081 }
5082
5083 /* end of slow path */
5084
5085
5086 void bnx2x_drv_pulse(struct bnx2x *bp)
5087 {
5088 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5089 bp->fw_drv_pulse_wr_seq);
5090 }
5091
5092
5093 static void bnx2x_timer(unsigned long data)
5094 {
5095 struct bnx2x *bp = (struct bnx2x *) data;
5096
5097 if (!netif_running(bp->dev))
5098 return;
5099
5100 if (!BP_NOMCP(bp)) {
5101 int mb_idx = BP_FW_MB_IDX(bp);
5102 u32 drv_pulse;
5103 u32 mcp_pulse;
5104
5105 ++bp->fw_drv_pulse_wr_seq;
5106 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5107 /* TBD - add SYSTEM_TIME */
5108 drv_pulse = bp->fw_drv_pulse_wr_seq;
5109 bnx2x_drv_pulse(bp);
5110
5111 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5112 MCP_PULSE_SEQ_MASK);
5113 /* The delta between driver pulse and mcp response
5114 * should be 1 (before mcp response) or 0 (after mcp response)
5115 */
5116 if ((drv_pulse != mcp_pulse) &&
5117 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5118 /* someone lost a heartbeat... */
5119 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5120 drv_pulse, mcp_pulse);
5121 }
5122 }
5123
5124 if (bp->state == BNX2X_STATE_OPEN)
5125 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5126
5127 mod_timer(&bp->timer, jiffies + bp->current_interval);
5128 }
5129
5130 /* end of Statistics */
5131
5132 /* nic init */
5133
5134 /*
5135 * nic init service functions
5136 */
5137
5138 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5139 {
5140 u32 i;
5141 if (!(len%4) && !(addr%4))
5142 for (i = 0; i < len; i += 4)
5143 REG_WR(bp, addr + i, fill);
5144 else
5145 for (i = 0; i < len; i++)
5146 REG_WR8(bp, addr + i, fill);
5147
5148 }
5149
5150 /* helper: writes FP SP data to FW - data_size in dwords */
5151 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5152 int fw_sb_id,
5153 u32 *sb_data_p,
5154 u32 data_size)
5155 {
5156 int index;
5157 for (index = 0; index < data_size; index++)
5158 REG_WR(bp, BAR_CSTRORM_INTMEM +
5159 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5160 sizeof(u32)*index,
5161 *(sb_data_p + index));
5162 }
5163
5164 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5165 {
5166 u32 *sb_data_p;
5167 u32 data_size = 0;
5168 struct hc_status_block_data_e2 sb_data_e2;
5169 struct hc_status_block_data_e1x sb_data_e1x;
5170
5171 /* disable the function first */
5172 if (!CHIP_IS_E1x(bp)) {
5173 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5174 sb_data_e2.common.state = SB_DISABLED;
5175 sb_data_e2.common.p_func.vf_valid = false;
5176 sb_data_p = (u32 *)&sb_data_e2;
5177 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5178 } else {
5179 memset(&sb_data_e1x, 0,
5180 sizeof(struct hc_status_block_data_e1x));
5181 sb_data_e1x.common.state = SB_DISABLED;
5182 sb_data_e1x.common.p_func.vf_valid = false;
5183 sb_data_p = (u32 *)&sb_data_e1x;
5184 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5185 }
5186 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5187
5188 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5189 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5190 CSTORM_STATUS_BLOCK_SIZE);
5191 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5192 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5193 CSTORM_SYNC_BLOCK_SIZE);
5194 }
5195
5196 /* helper: writes SP SB data to FW */
5197 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5198 struct hc_sp_status_block_data *sp_sb_data)
5199 {
5200 int func = BP_FUNC(bp);
5201 int i;
5202 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5203 REG_WR(bp, BAR_CSTRORM_INTMEM +
5204 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5205 i*sizeof(u32),
5206 *((u32 *)sp_sb_data + i));
5207 }
5208
5209 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5210 {
5211 int func = BP_FUNC(bp);
5212 struct hc_sp_status_block_data sp_sb_data;
5213 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5214
5215 sp_sb_data.state = SB_DISABLED;
5216 sp_sb_data.p_func.vf_valid = false;
5217
5218 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5219
5220 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5221 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5222 CSTORM_SP_STATUS_BLOCK_SIZE);
5223 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5224 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5225 CSTORM_SP_SYNC_BLOCK_SIZE);
5226
5227 }
5228
5229
5230 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5231 int igu_sb_id, int igu_seg_id)
5232 {
5233 hc_sm->igu_sb_id = igu_sb_id;
5234 hc_sm->igu_seg_id = igu_seg_id;
5235 hc_sm->timer_value = 0xFF;
5236 hc_sm->time_to_expire = 0xFFFFFFFF;
5237 }
5238
5239
5240 /* allocates state machine ids. */
5241 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5242 {
5243 /* zero out state machine indices */
5244 /* rx indices */
5245 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5246
5247 /* tx indices */
5248 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5249 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5250 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5251 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5252
5253 /* map indices */
5254 /* rx indices */
5255 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5256 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5257
5258 /* tx indices */
5259 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5260 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5261 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5262 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5263 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5264 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5265 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5266 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5267 }
5268
5269 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5270 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5271 {
5272 int igu_seg_id;
5273
5274 struct hc_status_block_data_e2 sb_data_e2;
5275 struct hc_status_block_data_e1x sb_data_e1x;
5276 struct hc_status_block_sm *hc_sm_p;
5277 int data_size;
5278 u32 *sb_data_p;
5279
5280 if (CHIP_INT_MODE_IS_BC(bp))
5281 igu_seg_id = HC_SEG_ACCESS_NORM;
5282 else
5283 igu_seg_id = IGU_SEG_ACCESS_NORM;
5284
5285 bnx2x_zero_fp_sb(bp, fw_sb_id);
5286
5287 if (!CHIP_IS_E1x(bp)) {
5288 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5289 sb_data_e2.common.state = SB_ENABLED;
5290 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5291 sb_data_e2.common.p_func.vf_id = vfid;
5292 sb_data_e2.common.p_func.vf_valid = vf_valid;
5293 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5294 sb_data_e2.common.same_igu_sb_1b = true;
5295 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5296 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5297 hc_sm_p = sb_data_e2.common.state_machine;
5298 sb_data_p = (u32 *)&sb_data_e2;
5299 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5300 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5301 } else {
5302 memset(&sb_data_e1x, 0,
5303 sizeof(struct hc_status_block_data_e1x));
5304 sb_data_e1x.common.state = SB_ENABLED;
5305 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5306 sb_data_e1x.common.p_func.vf_id = 0xff;
5307 sb_data_e1x.common.p_func.vf_valid = false;
5308 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5309 sb_data_e1x.common.same_igu_sb_1b = true;
5310 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5311 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5312 hc_sm_p = sb_data_e1x.common.state_machine;
5313 sb_data_p = (u32 *)&sb_data_e1x;
5314 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5315 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5316 }
5317
5318 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5319 igu_sb_id, igu_seg_id);
5320 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5321 igu_sb_id, igu_seg_id);
5322
5323 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5324
5325 /* write indecies to HW */
5326 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5327 }
5328
5329 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5330 u16 tx_usec, u16 rx_usec)
5331 {
5332 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5333 false, rx_usec);
5334 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5335 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5336 tx_usec);
5337 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5338 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5339 tx_usec);
5340 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5341 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5342 tx_usec);
5343 }
5344
5345 static void bnx2x_init_def_sb(struct bnx2x *bp)
5346 {
5347 struct host_sp_status_block *def_sb = bp->def_status_blk;
5348 dma_addr_t mapping = bp->def_status_blk_mapping;
5349 int igu_sp_sb_index;
5350 int igu_seg_id;
5351 int port = BP_PORT(bp);
5352 int func = BP_FUNC(bp);
5353 int reg_offset, reg_offset_en5;
5354 u64 section;
5355 int index;
5356 struct hc_sp_status_block_data sp_sb_data;
5357 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5358
5359 if (CHIP_INT_MODE_IS_BC(bp)) {
5360 igu_sp_sb_index = DEF_SB_IGU_ID;
5361 igu_seg_id = HC_SEG_ACCESS_DEF;
5362 } else {
5363 igu_sp_sb_index = bp->igu_dsb_id;
5364 igu_seg_id = IGU_SEG_ACCESS_DEF;
5365 }
5366
5367 /* ATTN */
5368 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5369 atten_status_block);
5370 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5371
5372 bp->attn_state = 0;
5373
5374 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5375 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5376 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5377 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5378 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5379 int sindex;
5380 /* take care of sig[0]..sig[4] */
5381 for (sindex = 0; sindex < 4; sindex++)
5382 bp->attn_group[index].sig[sindex] =
5383 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5384
5385 if (!CHIP_IS_E1x(bp))
5386 /*
5387 * enable5 is separate from the rest of the registers,
5388 * and therefore the address skip is 4
5389 * and not 16 between the different groups
5390 */
5391 bp->attn_group[index].sig[4] = REG_RD(bp,
5392 reg_offset_en5 + 0x4*index);
5393 else
5394 bp->attn_group[index].sig[4] = 0;
5395 }
5396
5397 if (bp->common.int_block == INT_BLOCK_HC) {
5398 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5399 HC_REG_ATTN_MSG0_ADDR_L);
5400
5401 REG_WR(bp, reg_offset, U64_LO(section));
5402 REG_WR(bp, reg_offset + 4, U64_HI(section));
5403 } else if (!CHIP_IS_E1x(bp)) {
5404 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5405 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5406 }
5407
5408 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5409 sp_sb);
5410
5411 bnx2x_zero_sp_sb(bp);
5412
5413 sp_sb_data.state = SB_ENABLED;
5414 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5415 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5416 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5417 sp_sb_data.igu_seg_id = igu_seg_id;
5418 sp_sb_data.p_func.pf_id = func;
5419 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5420 sp_sb_data.p_func.vf_id = 0xff;
5421
5422 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5423
5424 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5425 }
5426
5427 void bnx2x_update_coalesce(struct bnx2x *bp)
5428 {
5429 int i;
5430
5431 for_each_eth_queue(bp, i)
5432 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5433 bp->tx_ticks, bp->rx_ticks);
5434 }
5435
5436 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5437 {
5438 spin_lock_init(&bp->spq_lock);
5439 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5440
5441 bp->spq_prod_idx = 0;
5442 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5443 bp->spq_prod_bd = bp->spq;
5444 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5445 }
5446
5447 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5448 {
5449 int i;
5450 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5451 union event_ring_elem *elem =
5452 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5453
5454 elem->next_page.addr.hi =
5455 cpu_to_le32(U64_HI(bp->eq_mapping +
5456 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5457 elem->next_page.addr.lo =
5458 cpu_to_le32(U64_LO(bp->eq_mapping +
5459 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5460 }
5461 bp->eq_cons = 0;
5462 bp->eq_prod = NUM_EQ_DESC;
5463 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5464 /* we want a warning message before it gets rought... */
5465 atomic_set(&bp->eq_spq_left,
5466 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5467 }
5468
5469
5470 /* called with netif_addr_lock_bh() */
5471 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5472 unsigned long rx_mode_flags,
5473 unsigned long rx_accept_flags,
5474 unsigned long tx_accept_flags,
5475 unsigned long ramrod_flags)
5476 {
5477 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5478 int rc;
5479
5480 memset(&ramrod_param, 0, sizeof(ramrod_param));
5481
5482 /* Prepare ramrod parameters */
5483 ramrod_param.cid = 0;
5484 ramrod_param.cl_id = cl_id;
5485 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5486 ramrod_param.func_id = BP_FUNC(bp);
5487
5488 ramrod_param.pstate = &bp->sp_state;
5489 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5490
5491 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5492 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5493
5494 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5495
5496 ramrod_param.ramrod_flags = ramrod_flags;
5497 ramrod_param.rx_mode_flags = rx_mode_flags;
5498
5499 ramrod_param.rx_accept_flags = rx_accept_flags;
5500 ramrod_param.tx_accept_flags = tx_accept_flags;
5501
5502 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5503 if (rc < 0) {
5504 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5505 return;
5506 }
5507 }
5508
5509 /* called with netif_addr_lock_bh() */
5510 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5511 {
5512 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5513 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5514
5515 #ifdef BCM_CNIC
5516 if (!NO_FCOE(bp))
5517
5518 /* Configure rx_mode of FCoE Queue */
5519 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5520 #endif
5521
5522 switch (bp->rx_mode) {
5523 case BNX2X_RX_MODE_NONE:
5524 /*
5525 * 'drop all' supersedes any accept flags that may have been
5526 * passed to the function.
5527 */
5528 break;
5529 case BNX2X_RX_MODE_NORMAL:
5530 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5531 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5532 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5533
5534 /* internal switching mode */
5535 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5536 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5537 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5538
5539 break;
5540 case BNX2X_RX_MODE_ALLMULTI:
5541 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5542 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5543 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5544
5545 /* internal switching mode */
5546 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5547 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5548 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5549
5550 break;
5551 case BNX2X_RX_MODE_PROMISC:
5552 /* According to deffinition of SI mode, iface in promisc mode
5553 * should receive matched and unmatched (in resolution of port)
5554 * unicast packets.
5555 */
5556 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5557 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5558 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5559 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5560
5561 /* internal switching mode */
5562 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5563 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5564
5565 if (IS_MF_SI(bp))
5566 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5567 else
5568 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5569
5570 break;
5571 default:
5572 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5573 return;
5574 }
5575
5576 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5577 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5578 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5579 }
5580
5581 __set_bit(RAMROD_RX, &ramrod_flags);
5582 __set_bit(RAMROD_TX, &ramrod_flags);
5583
5584 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5585 tx_accept_flags, ramrod_flags);
5586 }
5587
5588 static void bnx2x_init_internal_common(struct bnx2x *bp)
5589 {
5590 int i;
5591
5592 if (IS_MF_SI(bp))
5593 /*
5594 * In switch independent mode, the TSTORM needs to accept
5595 * packets that failed classification, since approximate match
5596 * mac addresses aren't written to NIG LLH
5597 */
5598 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5599 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5600 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5601 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5602 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5603
5604 /* Zero this manually as its initialization is
5605 currently missing in the initTool */
5606 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5607 REG_WR(bp, BAR_USTRORM_INTMEM +
5608 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5609 if (!CHIP_IS_E1x(bp)) {
5610 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5611 CHIP_INT_MODE_IS_BC(bp) ?
5612 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5613 }
5614 }
5615
5616 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5617 {
5618 switch (load_code) {
5619 case FW_MSG_CODE_DRV_LOAD_COMMON:
5620 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5621 bnx2x_init_internal_common(bp);
5622 /* no break */
5623
5624 case FW_MSG_CODE_DRV_LOAD_PORT:
5625 /* nothing to do */
5626 /* no break */
5627
5628 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5629 /* internal memory per function is
5630 initialized inside bnx2x_pf_init */
5631 break;
5632
5633 default:
5634 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5635 break;
5636 }
5637 }
5638
5639 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5640 {
5641 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5642 }
5643
5644 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5645 {
5646 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5647 }
5648
5649 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5650 {
5651 if (CHIP_IS_E1x(fp->bp))
5652 return BP_L_ID(fp->bp) + fp->index;
5653 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5654 return bnx2x_fp_igu_sb_id(fp);
5655 }
5656
5657 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5658 {
5659 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5660 u8 cos;
5661 unsigned long q_type = 0;
5662 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5663 fp->rx_queue = fp_idx;
5664 fp->cid = fp_idx;
5665 fp->cl_id = bnx2x_fp_cl_id(fp);
5666 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5667 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5668 /* qZone id equals to FW (per path) client id */
5669 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5670
5671 /* init shortcut */
5672 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5673
5674 /* Setup SB indicies */
5675 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5676
5677 /* Configure Queue State object */
5678 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5679 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5680
5681 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5682
5683 /* init tx data */
5684 for_each_cos_in_tx_queue(fp, cos) {
5685 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5686 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5687 FP_COS_TO_TXQ(fp, cos, bp),
5688 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5689 cids[cos] = fp->txdata_ptr[cos]->cid;
5690 }
5691
5692 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5693 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5694 bnx2x_sp_mapping(bp, q_rdata), q_type);
5695
5696 /**
5697 * Configure classification DBs: Always enable Tx switching
5698 */
5699 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5700
5701 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5702 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5703 fp->igu_sb_id);
5704 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5705 fp->fw_sb_id, fp->igu_sb_id);
5706
5707 bnx2x_update_fpsb_idx(fp);
5708 }
5709
5710 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5711 {
5712 int i;
5713
5714 for (i = 1; i <= NUM_TX_RINGS; i++) {
5715 struct eth_tx_next_bd *tx_next_bd =
5716 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5717
5718 tx_next_bd->addr_hi =
5719 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5720 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5721 tx_next_bd->addr_lo =
5722 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5723 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5724 }
5725
5726 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5727 txdata->tx_db.data.zero_fill1 = 0;
5728 txdata->tx_db.data.prod = 0;
5729
5730 txdata->tx_pkt_prod = 0;
5731 txdata->tx_pkt_cons = 0;
5732 txdata->tx_bd_prod = 0;
5733 txdata->tx_bd_cons = 0;
5734 txdata->tx_pkt = 0;
5735 }
5736
5737 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5738 {
5739 int i;
5740 u8 cos;
5741
5742 for_each_tx_queue(bp, i)
5743 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5744 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5745 }
5746
5747 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5748 {
5749 int i;
5750
5751 for_each_eth_queue(bp, i)
5752 bnx2x_init_eth_fp(bp, i);
5753 #ifdef BCM_CNIC
5754 if (!NO_FCOE(bp))
5755 bnx2x_init_fcoe_fp(bp);
5756
5757 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5758 BNX2X_VF_ID_INVALID, false,
5759 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5760
5761 #endif
5762
5763 /* Initialize MOD_ABS interrupts */
5764 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5765 bp->common.shmem_base, bp->common.shmem2_base,
5766 BP_PORT(bp));
5767 /* ensure status block indices were read */
5768 rmb();
5769
5770 bnx2x_init_def_sb(bp);
5771 bnx2x_update_dsb_idx(bp);
5772 bnx2x_init_rx_rings(bp);
5773 bnx2x_init_tx_rings(bp);
5774 bnx2x_init_sp_ring(bp);
5775 bnx2x_init_eq_ring(bp);
5776 bnx2x_init_internal(bp, load_code);
5777 bnx2x_pf_init(bp);
5778 bnx2x_stats_init(bp);
5779
5780 /* flush all before enabling interrupts */
5781 mb();
5782 mmiowb();
5783
5784 bnx2x_int_enable(bp);
5785
5786 /* Check for SPIO5 */
5787 bnx2x_attn_int_deasserted0(bp,
5788 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5789 AEU_INPUTS_ATTN_BITS_SPIO5);
5790 }
5791
5792 /* end of nic init */
5793
5794 /*
5795 * gzip service functions
5796 */
5797
5798 static int bnx2x_gunzip_init(struct bnx2x *bp)
5799 {
5800 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5801 &bp->gunzip_mapping, GFP_KERNEL);
5802 if (bp->gunzip_buf == NULL)
5803 goto gunzip_nomem1;
5804
5805 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5806 if (bp->strm == NULL)
5807 goto gunzip_nomem2;
5808
5809 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5810 if (bp->strm->workspace == NULL)
5811 goto gunzip_nomem3;
5812
5813 return 0;
5814
5815 gunzip_nomem3:
5816 kfree(bp->strm);
5817 bp->strm = NULL;
5818
5819 gunzip_nomem2:
5820 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5821 bp->gunzip_mapping);
5822 bp->gunzip_buf = NULL;
5823
5824 gunzip_nomem1:
5825 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5826 return -ENOMEM;
5827 }
5828
5829 static void bnx2x_gunzip_end(struct bnx2x *bp)
5830 {
5831 if (bp->strm) {
5832 vfree(bp->strm->workspace);
5833 kfree(bp->strm);
5834 bp->strm = NULL;
5835 }
5836
5837 if (bp->gunzip_buf) {
5838 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5839 bp->gunzip_mapping);
5840 bp->gunzip_buf = NULL;
5841 }
5842 }
5843
5844 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5845 {
5846 int n, rc;
5847
5848 /* check gzip header */
5849 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5850 BNX2X_ERR("Bad gzip header\n");
5851 return -EINVAL;
5852 }
5853
5854 n = 10;
5855
5856 #define FNAME 0x8
5857
5858 if (zbuf[3] & FNAME)
5859 while ((zbuf[n++] != 0) && (n < len));
5860
5861 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5862 bp->strm->avail_in = len - n;
5863 bp->strm->next_out = bp->gunzip_buf;
5864 bp->strm->avail_out = FW_BUF_SIZE;
5865
5866 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5867 if (rc != Z_OK)
5868 return rc;
5869
5870 rc = zlib_inflate(bp->strm, Z_FINISH);
5871 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5872 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5873 bp->strm->msg);
5874
5875 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5876 if (bp->gunzip_outlen & 0x3)
5877 netdev_err(bp->dev,
5878 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5879 bp->gunzip_outlen);
5880 bp->gunzip_outlen >>= 2;
5881
5882 zlib_inflateEnd(bp->strm);
5883
5884 if (rc == Z_STREAM_END)
5885 return 0;
5886
5887 return rc;
5888 }
5889
5890 /* nic load/unload */
5891
5892 /*
5893 * General service functions
5894 */
5895
5896 /* send a NIG loopback debug packet */
5897 static void bnx2x_lb_pckt(struct bnx2x *bp)
5898 {
5899 u32 wb_write[3];
5900
5901 /* Ethernet source and destination addresses */
5902 wb_write[0] = 0x55555555;
5903 wb_write[1] = 0x55555555;
5904 wb_write[2] = 0x20; /* SOP */
5905 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5906
5907 /* NON-IP protocol */
5908 wb_write[0] = 0x09000000;
5909 wb_write[1] = 0x55555555;
5910 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5911 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5912 }
5913
5914 /* some of the internal memories
5915 * are not directly readable from the driver
5916 * to test them we send debug packets
5917 */
5918 static int bnx2x_int_mem_test(struct bnx2x *bp)
5919 {
5920 int factor;
5921 int count, i;
5922 u32 val = 0;
5923
5924 if (CHIP_REV_IS_FPGA(bp))
5925 factor = 120;
5926 else if (CHIP_REV_IS_EMUL(bp))
5927 factor = 200;
5928 else
5929 factor = 1;
5930
5931 /* Disable inputs of parser neighbor blocks */
5932 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5933 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5934 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5935 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5936
5937 /* Write 0 to parser credits for CFC search request */
5938 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5939
5940 /* send Ethernet packet */
5941 bnx2x_lb_pckt(bp);
5942
5943 /* TODO do i reset NIG statistic? */
5944 /* Wait until NIG register shows 1 packet of size 0x10 */
5945 count = 1000 * factor;
5946 while (count) {
5947
5948 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5949 val = *bnx2x_sp(bp, wb_data[0]);
5950 if (val == 0x10)
5951 break;
5952
5953 msleep(10);
5954 count--;
5955 }
5956 if (val != 0x10) {
5957 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5958 return -1;
5959 }
5960
5961 /* Wait until PRS register shows 1 packet */
5962 count = 1000 * factor;
5963 while (count) {
5964 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5965 if (val == 1)
5966 break;
5967
5968 msleep(10);
5969 count--;
5970 }
5971 if (val != 0x1) {
5972 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5973 return -2;
5974 }
5975
5976 /* Reset and init BRB, PRS */
5977 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5978 msleep(50);
5979 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5980 msleep(50);
5981 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5982 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5983
5984 DP(NETIF_MSG_HW, "part2\n");
5985
5986 /* Disable inputs of parser neighbor blocks */
5987 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5988 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5989 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5990 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5991
5992 /* Write 0 to parser credits for CFC search request */
5993 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5994
5995 /* send 10 Ethernet packets */
5996 for (i = 0; i < 10; i++)
5997 bnx2x_lb_pckt(bp);
5998
5999 /* Wait until NIG register shows 10 + 1
6000 packets of size 11*0x10 = 0xb0 */
6001 count = 1000 * factor;
6002 while (count) {
6003
6004 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6005 val = *bnx2x_sp(bp, wb_data[0]);
6006 if (val == 0xb0)
6007 break;
6008
6009 msleep(10);
6010 count--;
6011 }
6012 if (val != 0xb0) {
6013 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6014 return -3;
6015 }
6016
6017 /* Wait until PRS register shows 2 packets */
6018 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6019 if (val != 2)
6020 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6021
6022 /* Write 1 to parser credits for CFC search request */
6023 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6024
6025 /* Wait until PRS register shows 3 packets */
6026 msleep(10 * factor);
6027 /* Wait until NIG register shows 1 packet of size 0x10 */
6028 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6029 if (val != 3)
6030 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6031
6032 /* clear NIG EOP FIFO */
6033 for (i = 0; i < 11; i++)
6034 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6035 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6036 if (val != 1) {
6037 BNX2X_ERR("clear of NIG failed\n");
6038 return -4;
6039 }
6040
6041 /* Reset and init BRB, PRS, NIG */
6042 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6043 msleep(50);
6044 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6045 msleep(50);
6046 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6047 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6048 #ifndef BCM_CNIC
6049 /* set NIC mode */
6050 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6051 #endif
6052
6053 /* Enable inputs of parser neighbor blocks */
6054 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6055 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6056 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6057 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6058
6059 DP(NETIF_MSG_HW, "done\n");
6060
6061 return 0; /* OK */
6062 }
6063
6064 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6065 {
6066 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6067 if (!CHIP_IS_E1x(bp))
6068 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6069 else
6070 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6071 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6072 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6073 /*
6074 * mask read length error interrupts in brb for parser
6075 * (parsing unit and 'checksum and crc' unit)
6076 * these errors are legal (PU reads fixed length and CAC can cause
6077 * read length error on truncated packets)
6078 */
6079 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6080 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6081 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6082 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6083 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6084 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6085 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6086 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6087 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6088 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6089 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6090 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6091 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6092 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6093 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6094 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6095 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6096 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6097 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6098
6099 if (CHIP_REV_IS_FPGA(bp))
6100 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6101 else if (!CHIP_IS_E1x(bp))
6102 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6103 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6104 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6105 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6106 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6107 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6108 else
6109 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6110 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6111 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6112 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6113 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6114
6115 if (!CHIP_IS_E1x(bp))
6116 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6117 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6118
6119 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6120 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6121 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6122 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6123 }
6124
6125 static void bnx2x_reset_common(struct bnx2x *bp)
6126 {
6127 u32 val = 0x1400;
6128
6129 /* reset_common */
6130 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6131 0xd3ffff7f);
6132
6133 if (CHIP_IS_E3(bp)) {
6134 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6135 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6136 }
6137
6138 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6139 }
6140
6141 static void bnx2x_setup_dmae(struct bnx2x *bp)
6142 {
6143 bp->dmae_ready = 0;
6144 spin_lock_init(&bp->dmae_lock);
6145 }
6146
6147 static void bnx2x_init_pxp(struct bnx2x *bp)
6148 {
6149 u16 devctl;
6150 int r_order, w_order;
6151
6152 pci_read_config_word(bp->pdev,
6153 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
6154 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6155 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6156 if (bp->mrrs == -1)
6157 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6158 else {
6159 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6160 r_order = bp->mrrs;
6161 }
6162
6163 bnx2x_init_pxp_arb(bp, r_order, w_order);
6164 }
6165
6166 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6167 {
6168 int is_required;
6169 u32 val;
6170 int port;
6171
6172 if (BP_NOMCP(bp))
6173 return;
6174
6175 is_required = 0;
6176 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6177 SHARED_HW_CFG_FAN_FAILURE_MASK;
6178
6179 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6180 is_required = 1;
6181
6182 /*
6183 * The fan failure mechanism is usually related to the PHY type since
6184 * the power consumption of the board is affected by the PHY. Currently,
6185 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6186 */
6187 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6188 for (port = PORT_0; port < PORT_MAX; port++) {
6189 is_required |=
6190 bnx2x_fan_failure_det_req(
6191 bp,
6192 bp->common.shmem_base,
6193 bp->common.shmem2_base,
6194 port);
6195 }
6196
6197 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6198
6199 if (is_required == 0)
6200 return;
6201
6202 /* Fan failure is indicated by SPIO 5 */
6203 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6204 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6205
6206 /* set to active low mode */
6207 val = REG_RD(bp, MISC_REG_SPIO_INT);
6208 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6209 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6210 REG_WR(bp, MISC_REG_SPIO_INT, val);
6211
6212 /* enable interrupt to signal the IGU */
6213 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6214 val |= (1 << MISC_REGISTERS_SPIO_5);
6215 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6216 }
6217
6218 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6219 {
6220 u32 offset = 0;
6221
6222 if (CHIP_IS_E1(bp))
6223 return;
6224 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6225 return;
6226
6227 switch (BP_ABS_FUNC(bp)) {
6228 case 0:
6229 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6230 break;
6231 case 1:
6232 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6233 break;
6234 case 2:
6235 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6236 break;
6237 case 3:
6238 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6239 break;
6240 case 4:
6241 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6242 break;
6243 case 5:
6244 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6245 break;
6246 case 6:
6247 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6248 break;
6249 case 7:
6250 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6251 break;
6252 default:
6253 return;
6254 }
6255
6256 REG_WR(bp, offset, pretend_func_num);
6257 REG_RD(bp, offset);
6258 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6259 }
6260
6261 void bnx2x_pf_disable(struct bnx2x *bp)
6262 {
6263 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6264 val &= ~IGU_PF_CONF_FUNC_EN;
6265
6266 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6267 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6268 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6269 }
6270
6271 static void bnx2x__common_init_phy(struct bnx2x *bp)
6272 {
6273 u32 shmem_base[2], shmem2_base[2];
6274 shmem_base[0] = bp->common.shmem_base;
6275 shmem2_base[0] = bp->common.shmem2_base;
6276 if (!CHIP_IS_E1x(bp)) {
6277 shmem_base[1] =
6278 SHMEM2_RD(bp, other_shmem_base_addr);
6279 shmem2_base[1] =
6280 SHMEM2_RD(bp, other_shmem2_base_addr);
6281 }
6282 bnx2x_acquire_phy_lock(bp);
6283 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6284 bp->common.chip_id);
6285 bnx2x_release_phy_lock(bp);
6286 }
6287
6288 /**
6289 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6290 *
6291 * @bp: driver handle
6292 */
6293 static int bnx2x_init_hw_common(struct bnx2x *bp)
6294 {
6295 u32 val;
6296
6297 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6298
6299 /*
6300 * take the UNDI lock to protect undi_unload flow from accessing
6301 * registers while we're resetting the chip
6302 */
6303 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6304
6305 bnx2x_reset_common(bp);
6306 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6307
6308 val = 0xfffc;
6309 if (CHIP_IS_E3(bp)) {
6310 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6311 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6312 }
6313 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6314
6315 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6316
6317 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6318
6319 if (!CHIP_IS_E1x(bp)) {
6320 u8 abs_func_id;
6321
6322 /**
6323 * 4-port mode or 2-port mode we need to turn of master-enable
6324 * for everyone, after that, turn it back on for self.
6325 * so, we disregard multi-function or not, and always disable
6326 * for all functions on the given path, this means 0,2,4,6 for
6327 * path 0 and 1,3,5,7 for path 1
6328 */
6329 for (abs_func_id = BP_PATH(bp);
6330 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6331 if (abs_func_id == BP_ABS_FUNC(bp)) {
6332 REG_WR(bp,
6333 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6334 1);
6335 continue;
6336 }
6337
6338 bnx2x_pretend_func(bp, abs_func_id);
6339 /* clear pf enable */
6340 bnx2x_pf_disable(bp);
6341 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6342 }
6343 }
6344
6345 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6346 if (CHIP_IS_E1(bp)) {
6347 /* enable HW interrupt from PXP on USDM overflow
6348 bit 16 on INT_MASK_0 */
6349 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6350 }
6351
6352 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6353 bnx2x_init_pxp(bp);
6354
6355 #ifdef __BIG_ENDIAN
6356 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6357 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6358 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6359 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6360 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6361 /* make sure this value is 0 */
6362 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6363
6364 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6365 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6366 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6367 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6368 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6369 #endif
6370
6371 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6372
6373 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6374 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6375
6376 /* let the HW do it's magic ... */
6377 msleep(100);
6378 /* finish PXP init */
6379 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6380 if (val != 1) {
6381 BNX2X_ERR("PXP2 CFG failed\n");
6382 return -EBUSY;
6383 }
6384 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6385 if (val != 1) {
6386 BNX2X_ERR("PXP2 RD_INIT failed\n");
6387 return -EBUSY;
6388 }
6389
6390 /* Timers bug workaround E2 only. We need to set the entire ILT to
6391 * have entries with value "0" and valid bit on.
6392 * This needs to be done by the first PF that is loaded in a path
6393 * (i.e. common phase)
6394 */
6395 if (!CHIP_IS_E1x(bp)) {
6396 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6397 * (i.e. vnic3) to start even if it is marked as "scan-off".
6398 * This occurs when a different function (func2,3) is being marked
6399 * as "scan-off". Real-life scenario for example: if a driver is being
6400 * load-unloaded while func6,7 are down. This will cause the timer to access
6401 * the ilt, translate to a logical address and send a request to read/write.
6402 * Since the ilt for the function that is down is not valid, this will cause
6403 * a translation error which is unrecoverable.
6404 * The Workaround is intended to make sure that when this happens nothing fatal
6405 * will occur. The workaround:
6406 * 1. First PF driver which loads on a path will:
6407 * a. After taking the chip out of reset, by using pretend,
6408 * it will write "0" to the following registers of
6409 * the other vnics.
6410 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6411 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6412 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6413 * And for itself it will write '1' to
6414 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6415 * dmae-operations (writing to pram for example.)
6416 * note: can be done for only function 6,7 but cleaner this
6417 * way.
6418 * b. Write zero+valid to the entire ILT.
6419 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6420 * VNIC3 (of that port). The range allocated will be the
6421 * entire ILT. This is needed to prevent ILT range error.
6422 * 2. Any PF driver load flow:
6423 * a. ILT update with the physical addresses of the allocated
6424 * logical pages.
6425 * b. Wait 20msec. - note that this timeout is needed to make
6426 * sure there are no requests in one of the PXP internal
6427 * queues with "old" ILT addresses.
6428 * c. PF enable in the PGLC.
6429 * d. Clear the was_error of the PF in the PGLC. (could have
6430 * occured while driver was down)
6431 * e. PF enable in the CFC (WEAK + STRONG)
6432 * f. Timers scan enable
6433 * 3. PF driver unload flow:
6434 * a. Clear the Timers scan_en.
6435 * b. Polling for scan_on=0 for that PF.
6436 * c. Clear the PF enable bit in the PXP.
6437 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6438 * e. Write zero+valid to all ILT entries (The valid bit must
6439 * stay set)
6440 * f. If this is VNIC 3 of a port then also init
6441 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6442 * to the last enrty in the ILT.
6443 *
6444 * Notes:
6445 * Currently the PF error in the PGLC is non recoverable.
6446 * In the future the there will be a recovery routine for this error.
6447 * Currently attention is masked.
6448 * Having an MCP lock on the load/unload process does not guarantee that
6449 * there is no Timer disable during Func6/7 enable. This is because the
6450 * Timers scan is currently being cleared by the MCP on FLR.
6451 * Step 2.d can be done only for PF6/7 and the driver can also check if
6452 * there is error before clearing it. But the flow above is simpler and
6453 * more general.
6454 * All ILT entries are written by zero+valid and not just PF6/7
6455 * ILT entries since in the future the ILT entries allocation for
6456 * PF-s might be dynamic.
6457 */
6458 struct ilt_client_info ilt_cli;
6459 struct bnx2x_ilt ilt;
6460 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6461 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6462
6463 /* initialize dummy TM client */
6464 ilt_cli.start = 0;
6465 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6466 ilt_cli.client_num = ILT_CLIENT_TM;
6467
6468 /* Step 1: set zeroes to all ilt page entries with valid bit on
6469 * Step 2: set the timers first/last ilt entry to point
6470 * to the entire range to prevent ILT range error for 3rd/4th
6471 * vnic (this code assumes existance of the vnic)
6472 *
6473 * both steps performed by call to bnx2x_ilt_client_init_op()
6474 * with dummy TM client
6475 *
6476 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6477 * and his brother are split registers
6478 */
6479 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6480 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6481 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6482
6483 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6484 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6485 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6486 }
6487
6488
6489 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6490 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6491
6492 if (!CHIP_IS_E1x(bp)) {
6493 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6494 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6495 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6496
6497 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6498
6499 /* let the HW do it's magic ... */
6500 do {
6501 msleep(200);
6502 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6503 } while (factor-- && (val != 1));
6504
6505 if (val != 1) {
6506 BNX2X_ERR("ATC_INIT failed\n");
6507 return -EBUSY;
6508 }
6509 }
6510
6511 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6512
6513 /* clean the DMAE memory */
6514 bp->dmae_ready = 1;
6515 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6516
6517 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6518
6519 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6520
6521 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6522
6523 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6524
6525 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6526 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6527 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6528 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6529
6530 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6531
6532
6533 /* QM queues pointers table */
6534 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6535
6536 /* soft reset pulse */
6537 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6538 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6539
6540 #ifdef BCM_CNIC
6541 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6542 #endif
6543
6544 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6545 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6546 if (!CHIP_REV_IS_SLOW(bp))
6547 /* enable hw interrupt from doorbell Q */
6548 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6549
6550 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6551
6552 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6553 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6554
6555 if (!CHIP_IS_E1(bp))
6556 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6557
6558 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6559 if (IS_MF_AFEX(bp)) {
6560 /* configure that VNTag and VLAN headers must be
6561 * received in afex mode
6562 */
6563 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6564 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6565 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6566 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6567 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6568 } else {
6569 /* Bit-map indicating which L2 hdrs may appear
6570 * after the basic Ethernet header
6571 */
6572 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6573 bp->path_has_ovlan ? 7 : 6);
6574 }
6575 }
6576
6577 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6578 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6579 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6580 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6581
6582 if (!CHIP_IS_E1x(bp)) {
6583 /* reset VFC memories */
6584 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6585 VFC_MEMORIES_RST_REG_CAM_RST |
6586 VFC_MEMORIES_RST_REG_RAM_RST);
6587 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6588 VFC_MEMORIES_RST_REG_CAM_RST |
6589 VFC_MEMORIES_RST_REG_RAM_RST);
6590
6591 msleep(20);
6592 }
6593
6594 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6595 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6596 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6597 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6598
6599 /* sync semi rtc */
6600 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6601 0x80000000);
6602 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6603 0x80000000);
6604
6605 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6606 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6607 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6608
6609 if (!CHIP_IS_E1x(bp)) {
6610 if (IS_MF_AFEX(bp)) {
6611 /* configure that VNTag and VLAN headers must be
6612 * sent in afex mode
6613 */
6614 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6615 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6616 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6617 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6618 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6619 } else {
6620 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6621 bp->path_has_ovlan ? 7 : 6);
6622 }
6623 }
6624
6625 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6626
6627 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6628
6629 #ifdef BCM_CNIC
6630 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6631 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6632 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6633 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6634 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6635 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6636 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6637 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6638 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6639 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6640 #endif
6641 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6642
6643 if (sizeof(union cdu_context) != 1024)
6644 /* we currently assume that a context is 1024 bytes */
6645 dev_alert(&bp->pdev->dev,
6646 "please adjust the size of cdu_context(%ld)\n",
6647 (long)sizeof(union cdu_context));
6648
6649 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6650 val = (4 << 24) + (0 << 12) + 1024;
6651 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6652
6653 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6654 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6655 /* enable context validation interrupt from CFC */
6656 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6657
6658 /* set the thresholds to prevent CFC/CDU race */
6659 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6660
6661 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6662
6663 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6664 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6665
6666 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6667 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6668
6669 /* Reset PCIE errors for debug */
6670 REG_WR(bp, 0x2814, 0xffffffff);
6671 REG_WR(bp, 0x3820, 0xffffffff);
6672
6673 if (!CHIP_IS_E1x(bp)) {
6674 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6675 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6676 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6677 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6678 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6679 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6680 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6681 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6682 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6683 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6684 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6685 }
6686
6687 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6688 if (!CHIP_IS_E1(bp)) {
6689 /* in E3 this done in per-port section */
6690 if (!CHIP_IS_E3(bp))
6691 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6692 }
6693 if (CHIP_IS_E1H(bp))
6694 /* not applicable for E2 (and above ...) */
6695 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6696
6697 if (CHIP_REV_IS_SLOW(bp))
6698 msleep(200);
6699
6700 /* finish CFC init */
6701 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6702 if (val != 1) {
6703 BNX2X_ERR("CFC LL_INIT failed\n");
6704 return -EBUSY;
6705 }
6706 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6707 if (val != 1) {
6708 BNX2X_ERR("CFC AC_INIT failed\n");
6709 return -EBUSY;
6710 }
6711 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6712 if (val != 1) {
6713 BNX2X_ERR("CFC CAM_INIT failed\n");
6714 return -EBUSY;
6715 }
6716 REG_WR(bp, CFC_REG_DEBUG0, 0);
6717
6718 if (CHIP_IS_E1(bp)) {
6719 /* read NIG statistic
6720 to see if this is our first up since powerup */
6721 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6722 val = *bnx2x_sp(bp, wb_data[0]);
6723
6724 /* do internal memory self test */
6725 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6726 BNX2X_ERR("internal mem self test failed\n");
6727 return -EBUSY;
6728 }
6729 }
6730
6731 bnx2x_setup_fan_failure_detection(bp);
6732
6733 /* clear PXP2 attentions */
6734 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6735
6736 bnx2x_enable_blocks_attention(bp);
6737 bnx2x_enable_blocks_parity(bp);
6738
6739 if (!BP_NOMCP(bp)) {
6740 if (CHIP_IS_E1x(bp))
6741 bnx2x__common_init_phy(bp);
6742 } else
6743 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6744
6745 return 0;
6746 }
6747
6748 /**
6749 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6750 *
6751 * @bp: driver handle
6752 */
6753 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6754 {
6755 int rc = bnx2x_init_hw_common(bp);
6756
6757 if (rc)
6758 return rc;
6759
6760 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6761 if (!BP_NOMCP(bp))
6762 bnx2x__common_init_phy(bp);
6763
6764 return 0;
6765 }
6766
6767 static int bnx2x_init_hw_port(struct bnx2x *bp)
6768 {
6769 int port = BP_PORT(bp);
6770 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6771 u32 low, high;
6772 u32 val;
6773
6774 bnx2x__link_reset(bp);
6775
6776 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6777
6778 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6779
6780 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6781 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6782 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6783
6784 /* Timers bug workaround: disables the pf_master bit in pglue at
6785 * common phase, we need to enable it here before any dmae access are
6786 * attempted. Therefore we manually added the enable-master to the
6787 * port phase (it also happens in the function phase)
6788 */
6789 if (!CHIP_IS_E1x(bp))
6790 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6791
6792 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6793 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6794 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6795 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6796
6797 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6798 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6799 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6800 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6801
6802 /* QM cid (connection) count */
6803 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6804
6805 #ifdef BCM_CNIC
6806 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6807 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6808 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6809 #endif
6810
6811 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6812
6813 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6814 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6815
6816 if (IS_MF(bp))
6817 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6818 else if (bp->dev->mtu > 4096) {
6819 if (bp->flags & ONE_PORT_FLAG)
6820 low = 160;
6821 else {
6822 val = bp->dev->mtu;
6823 /* (24*1024 + val*4)/256 */
6824 low = 96 + (val/64) +
6825 ((val % 64) ? 1 : 0);
6826 }
6827 } else
6828 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6829 high = low + 56; /* 14*1024/256 */
6830 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6831 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6832 }
6833
6834 if (CHIP_MODE_IS_4_PORT(bp))
6835 REG_WR(bp, (BP_PORT(bp) ?
6836 BRB1_REG_MAC_GUARANTIED_1 :
6837 BRB1_REG_MAC_GUARANTIED_0), 40);
6838
6839
6840 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6841 if (CHIP_IS_E3B0(bp)) {
6842 if (IS_MF_AFEX(bp)) {
6843 /* configure headers for AFEX mode */
6844 REG_WR(bp, BP_PORT(bp) ?
6845 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6846 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6847 REG_WR(bp, BP_PORT(bp) ?
6848 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6849 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6850 REG_WR(bp, BP_PORT(bp) ?
6851 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6852 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6853 } else {
6854 /* Ovlan exists only if we are in multi-function +
6855 * switch-dependent mode, in switch-independent there
6856 * is no ovlan headers
6857 */
6858 REG_WR(bp, BP_PORT(bp) ?
6859 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6860 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6861 (bp->path_has_ovlan ? 7 : 6));
6862 }
6863 }
6864
6865 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6866 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6867 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6868 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6869
6870 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6871 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6872 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6873 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6874
6875 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6876 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6877
6878 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6879
6880 if (CHIP_IS_E1x(bp)) {
6881 /* configure PBF to work without PAUSE mtu 9000 */
6882 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6883
6884 /* update threshold */
6885 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6886 /* update init credit */
6887 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6888
6889 /* probe changes */
6890 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6891 udelay(50);
6892 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6893 }
6894
6895 #ifdef BCM_CNIC
6896 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6897 #endif
6898 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6899 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6900
6901 if (CHIP_IS_E1(bp)) {
6902 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6903 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6904 }
6905 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6906
6907 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6908
6909 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6910 /* init aeu_mask_attn_func_0/1:
6911 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6912 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6913 * bits 4-7 are used for "per vn group attention" */
6914 val = IS_MF(bp) ? 0xF7 : 0x7;
6915 /* Enable DCBX attention for all but E1 */
6916 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6917 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6918
6919 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6920
6921 if (!CHIP_IS_E1x(bp)) {
6922 /* Bit-map indicating which L2 hdrs may appear after the
6923 * basic Ethernet header
6924 */
6925 if (IS_MF_AFEX(bp))
6926 REG_WR(bp, BP_PORT(bp) ?
6927 NIG_REG_P1_HDRS_AFTER_BASIC :
6928 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6929 else
6930 REG_WR(bp, BP_PORT(bp) ?
6931 NIG_REG_P1_HDRS_AFTER_BASIC :
6932 NIG_REG_P0_HDRS_AFTER_BASIC,
6933 IS_MF_SD(bp) ? 7 : 6);
6934
6935 if (CHIP_IS_E3(bp))
6936 REG_WR(bp, BP_PORT(bp) ?
6937 NIG_REG_LLH1_MF_MODE :
6938 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6939 }
6940 if (!CHIP_IS_E3(bp))
6941 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6942
6943 if (!CHIP_IS_E1(bp)) {
6944 /* 0x2 disable mf_ov, 0x1 enable */
6945 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6946 (IS_MF_SD(bp) ? 0x1 : 0x2));
6947
6948 if (!CHIP_IS_E1x(bp)) {
6949 val = 0;
6950 switch (bp->mf_mode) {
6951 case MULTI_FUNCTION_SD:
6952 val = 1;
6953 break;
6954 case MULTI_FUNCTION_SI:
6955 case MULTI_FUNCTION_AFEX:
6956 val = 2;
6957 break;
6958 }
6959
6960 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6961 NIG_REG_LLH0_CLS_TYPE), val);
6962 }
6963 {
6964 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6965 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6966 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6967 }
6968 }
6969
6970
6971 /* If SPIO5 is set to generate interrupts, enable it for this port */
6972 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6973 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6974 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6976 val = REG_RD(bp, reg_addr);
6977 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6978 REG_WR(bp, reg_addr, val);
6979 }
6980
6981 return 0;
6982 }
6983
6984 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6985 {
6986 int reg;
6987 u32 wb_write[2];
6988
6989 if (CHIP_IS_E1(bp))
6990 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6991 else
6992 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6993
6994 wb_write[0] = ONCHIP_ADDR1(addr);
6995 wb_write[1] = ONCHIP_ADDR2(addr);
6996 REG_WR_DMAE(bp, reg, wb_write, 2);
6997 }
6998
6999 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
7000 u8 idu_sb_id, bool is_Pf)
7001 {
7002 u32 data, ctl, cnt = 100;
7003 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7004 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7005 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7006 u32 sb_bit = 1 << (idu_sb_id%32);
7007 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7008 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7009
7010 /* Not supported in BC mode */
7011 if (CHIP_INT_MODE_IS_BC(bp))
7012 return;
7013
7014 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7015 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7016 IGU_REGULAR_CLEANUP_SET |
7017 IGU_REGULAR_BCLEANUP;
7018
7019 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7020 func_encode << IGU_CTRL_REG_FID_SHIFT |
7021 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7022
7023 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7024 data, igu_addr_data);
7025 REG_WR(bp, igu_addr_data, data);
7026 mmiowb();
7027 barrier();
7028 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7029 ctl, igu_addr_ctl);
7030 REG_WR(bp, igu_addr_ctl, ctl);
7031 mmiowb();
7032 barrier();
7033
7034 /* wait for clean up to finish */
7035 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7036 msleep(20);
7037
7038
7039 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7040 DP(NETIF_MSG_HW,
7041 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7042 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7043 }
7044 }
7045
7046 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7047 {
7048 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7049 }
7050
7051 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7052 {
7053 u32 i, base = FUNC_ILT_BASE(func);
7054 for (i = base; i < base + ILT_PER_FUNC; i++)
7055 bnx2x_ilt_wr(bp, i, 0);
7056 }
7057
7058 static int bnx2x_init_hw_func(struct bnx2x *bp)
7059 {
7060 int port = BP_PORT(bp);
7061 int func = BP_FUNC(bp);
7062 int init_phase = PHASE_PF0 + func;
7063 struct bnx2x_ilt *ilt = BP_ILT(bp);
7064 u16 cdu_ilt_start;
7065 u32 addr, val;
7066 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7067 int i, main_mem_width, rc;
7068
7069 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7070
7071 /* FLR cleanup - hmmm */
7072 if (!CHIP_IS_E1x(bp)) {
7073 rc = bnx2x_pf_flr_clnup(bp);
7074 if (rc)
7075 return rc;
7076 }
7077
7078 /* set MSI reconfigure capability */
7079 if (bp->common.int_block == INT_BLOCK_HC) {
7080 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7081 val = REG_RD(bp, addr);
7082 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7083 REG_WR(bp, addr, val);
7084 }
7085
7086 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7087 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7088
7089 ilt = BP_ILT(bp);
7090 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7091
7092 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7093 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7094 ilt->lines[cdu_ilt_start + i].page_mapping =
7095 bp->context[i].cxt_mapping;
7096 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7097 }
7098 bnx2x_ilt_init_op(bp, INITOP_SET);
7099
7100 #ifdef BCM_CNIC
7101 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7102
7103 /* T1 hash bits value determines the T1 number of entries */
7104 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7105 #endif
7106
7107 #ifndef BCM_CNIC
7108 /* set NIC mode */
7109 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7110 #endif /* BCM_CNIC */
7111
7112 if (!CHIP_IS_E1x(bp)) {
7113 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7114
7115 /* Turn on a single ISR mode in IGU if driver is going to use
7116 * INT#x or MSI
7117 */
7118 if (!(bp->flags & USING_MSIX_FLAG))
7119 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7120 /*
7121 * Timers workaround bug: function init part.
7122 * Need to wait 20msec after initializing ILT,
7123 * needed to make sure there are no requests in
7124 * one of the PXP internal queues with "old" ILT addresses
7125 */
7126 msleep(20);
7127 /*
7128 * Master enable - Due to WB DMAE writes performed before this
7129 * register is re-initialized as part of the regular function
7130 * init
7131 */
7132 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7133 /* Enable the function in IGU */
7134 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7135 }
7136
7137 bp->dmae_ready = 1;
7138
7139 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7140
7141 if (!CHIP_IS_E1x(bp))
7142 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7143
7144 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7145 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7146 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7147 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7148 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7149 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7150 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7151 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7152 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7153 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7154 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7155 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7156 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7157
7158 if (!CHIP_IS_E1x(bp))
7159 REG_WR(bp, QM_REG_PF_EN, 1);
7160
7161 if (!CHIP_IS_E1x(bp)) {
7162 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7163 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7164 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7165 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7166 }
7167 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7168
7169 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7170 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7171 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7172 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7173 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7174 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7175 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7176 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7177 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7178 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7179 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7180 if (!CHIP_IS_E1x(bp))
7181 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7182
7183 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7184
7185 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7186
7187 if (!CHIP_IS_E1x(bp))
7188 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7189
7190 if (IS_MF(bp)) {
7191 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7192 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7193 }
7194
7195 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7196
7197 /* HC init per function */
7198 if (bp->common.int_block == INT_BLOCK_HC) {
7199 if (CHIP_IS_E1H(bp)) {
7200 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7201
7202 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7203 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7204 }
7205 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7206
7207 } else {
7208 int num_segs, sb_idx, prod_offset;
7209
7210 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7211
7212 if (!CHIP_IS_E1x(bp)) {
7213 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7214 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7215 }
7216
7217 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7218
7219 if (!CHIP_IS_E1x(bp)) {
7220 int dsb_idx = 0;
7221 /**
7222 * Producer memory:
7223 * E2 mode: address 0-135 match to the mapping memory;
7224 * 136 - PF0 default prod; 137 - PF1 default prod;
7225 * 138 - PF2 default prod; 139 - PF3 default prod;
7226 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7227 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7228 * 144-147 reserved.
7229 *
7230 * E1.5 mode - In backward compatible mode;
7231 * for non default SB; each even line in the memory
7232 * holds the U producer and each odd line hold
7233 * the C producer. The first 128 producers are for
7234 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7235 * producers are for the DSB for each PF.
7236 * Each PF has five segments: (the order inside each
7237 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7238 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7239 * 144-147 attn prods;
7240 */
7241 /* non-default-status-blocks */
7242 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7243 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7244 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7245 prod_offset = (bp->igu_base_sb + sb_idx) *
7246 num_segs;
7247
7248 for (i = 0; i < num_segs; i++) {
7249 addr = IGU_REG_PROD_CONS_MEMORY +
7250 (prod_offset + i) * 4;
7251 REG_WR(bp, addr, 0);
7252 }
7253 /* send consumer update with value 0 */
7254 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7255 USTORM_ID, 0, IGU_INT_NOP, 1);
7256 bnx2x_igu_clear_sb(bp,
7257 bp->igu_base_sb + sb_idx);
7258 }
7259
7260 /* default-status-blocks */
7261 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7262 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7263
7264 if (CHIP_MODE_IS_4_PORT(bp))
7265 dsb_idx = BP_FUNC(bp);
7266 else
7267 dsb_idx = BP_VN(bp);
7268
7269 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7270 IGU_BC_BASE_DSB_PROD + dsb_idx :
7271 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7272
7273 /*
7274 * igu prods come in chunks of E1HVN_MAX (4) -
7275 * does not matters what is the current chip mode
7276 */
7277 for (i = 0; i < (num_segs * E1HVN_MAX);
7278 i += E1HVN_MAX) {
7279 addr = IGU_REG_PROD_CONS_MEMORY +
7280 (prod_offset + i)*4;
7281 REG_WR(bp, addr, 0);
7282 }
7283 /* send consumer update with 0 */
7284 if (CHIP_INT_MODE_IS_BC(bp)) {
7285 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7286 USTORM_ID, 0, IGU_INT_NOP, 1);
7287 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7288 CSTORM_ID, 0, IGU_INT_NOP, 1);
7289 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7290 XSTORM_ID, 0, IGU_INT_NOP, 1);
7291 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7292 TSTORM_ID, 0, IGU_INT_NOP, 1);
7293 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7294 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7295 } else {
7296 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7297 USTORM_ID, 0, IGU_INT_NOP, 1);
7298 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7299 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7300 }
7301 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7302
7303 /* !!! these should become driver const once
7304 rf-tool supports split-68 const */
7305 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7306 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7307 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7308 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7309 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7310 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7311 }
7312 }
7313
7314 /* Reset PCIE errors for debug */
7315 REG_WR(bp, 0x2114, 0xffffffff);
7316 REG_WR(bp, 0x2120, 0xffffffff);
7317
7318 if (CHIP_IS_E1x(bp)) {
7319 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7320 main_mem_base = HC_REG_MAIN_MEMORY +
7321 BP_PORT(bp) * (main_mem_size * 4);
7322 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7323 main_mem_width = 8;
7324
7325 val = REG_RD(bp, main_mem_prty_clr);
7326 if (val)
7327 DP(NETIF_MSG_HW,
7328 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7329 val);
7330
7331 /* Clear "false" parity errors in MSI-X table */
7332 for (i = main_mem_base;
7333 i < main_mem_base + main_mem_size * 4;
7334 i += main_mem_width) {
7335 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7336 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7337 i, main_mem_width / 4);
7338 }
7339 /* Clear HC parity attention */
7340 REG_RD(bp, main_mem_prty_clr);
7341 }
7342
7343 #ifdef BNX2X_STOP_ON_ERROR
7344 /* Enable STORMs SP logging */
7345 REG_WR8(bp, BAR_USTRORM_INTMEM +
7346 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7347 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7348 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7349 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7350 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7351 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7352 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7353 #endif
7354
7355 bnx2x_phy_probe(&bp->link_params);
7356
7357 return 0;
7358 }
7359
7360
7361 void bnx2x_free_mem(struct bnx2x *bp)
7362 {
7363 int i;
7364
7365 /* fastpath */
7366 bnx2x_free_fp_mem(bp);
7367 /* end of fastpath */
7368
7369 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7370 sizeof(struct host_sp_status_block));
7371
7372 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7373 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7374
7375 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7376 sizeof(struct bnx2x_slowpath));
7377
7378 for (i = 0; i < L2_ILT_LINES(bp); i++)
7379 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7380 bp->context[i].size);
7381 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7382
7383 BNX2X_FREE(bp->ilt->lines);
7384
7385 #ifdef BCM_CNIC
7386 if (!CHIP_IS_E1x(bp))
7387 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7388 sizeof(struct host_hc_status_block_e2));
7389 else
7390 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7391 sizeof(struct host_hc_status_block_e1x));
7392
7393 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7394 #endif
7395
7396 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7397
7398 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7399 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7400 }
7401
7402 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7403 {
7404 int num_groups;
7405 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7406
7407 /* number of queues for statistics is number of eth queues + FCoE */
7408 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7409
7410 /* Total number of FW statistics requests =
7411 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7412 * num of queues
7413 */
7414 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7415
7416
7417 /* Request is built from stats_query_header and an array of
7418 * stats_query_cmd_group each of which contains
7419 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7420 * configured in the stats_query_header.
7421 */
7422 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7423 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7424
7425 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7426 num_groups * sizeof(struct stats_query_cmd_group);
7427
7428 /* Data for statistics requests + stats_conter
7429 *
7430 * stats_counter holds per-STORM counters that are incremented
7431 * when STORM has finished with the current request.
7432 *
7433 * memory for FCoE offloaded statistics are counted anyway,
7434 * even if they will not be sent.
7435 */
7436 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7437 sizeof(struct per_pf_stats) +
7438 sizeof(struct fcoe_statistics_params) +
7439 sizeof(struct per_queue_stats) * num_queue_stats +
7440 sizeof(struct stats_counter);
7441
7442 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7443 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7444
7445 /* Set shortcuts */
7446 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7447 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7448
7449 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7450 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7451
7452 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7453 bp->fw_stats_req_sz;
7454 return 0;
7455
7456 alloc_mem_err:
7457 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7458 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7459 BNX2X_ERR("Can't allocate memory\n");
7460 return -ENOMEM;
7461 }
7462
7463
7464 int bnx2x_alloc_mem(struct bnx2x *bp)
7465 {
7466 int i, allocated, context_size;
7467
7468 #ifdef BCM_CNIC
7469 if (!CHIP_IS_E1x(bp))
7470 /* size = the status block + ramrod buffers */
7471 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7472 sizeof(struct host_hc_status_block_e2));
7473 else
7474 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7475 sizeof(struct host_hc_status_block_e1x));
7476
7477 /* allocate searcher T2 table */
7478 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7479 #endif
7480
7481
7482 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7483 sizeof(struct host_sp_status_block));
7484
7485 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7486 sizeof(struct bnx2x_slowpath));
7487
7488 #ifdef BCM_CNIC
7489 /* write address to which L5 should insert its values */
7490 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7491 #endif
7492
7493 /* Allocated memory for FW statistics */
7494 if (bnx2x_alloc_fw_stats_mem(bp))
7495 goto alloc_mem_err;
7496
7497 /* Allocate memory for CDU context:
7498 * This memory is allocated separately and not in the generic ILT
7499 * functions because CDU differs in few aspects:
7500 * 1. There are multiple entities allocating memory for context -
7501 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7502 * its own ILT lines.
7503 * 2. Since CDU page-size is not a single 4KB page (which is the case
7504 * for the other ILT clients), to be efficient we want to support
7505 * allocation of sub-page-size in the last entry.
7506 * 3. Context pointers are used by the driver to pass to FW / update
7507 * the context (for the other ILT clients the pointers are used just to
7508 * free the memory during unload).
7509 */
7510 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7511
7512 for (i = 0, allocated = 0; allocated < context_size; i++) {
7513 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7514 (context_size - allocated));
7515 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7516 &bp->context[i].cxt_mapping,
7517 bp->context[i].size);
7518 allocated += bp->context[i].size;
7519 }
7520 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7521
7522 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7523 goto alloc_mem_err;
7524
7525 /* Slow path ring */
7526 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7527
7528 /* EQ */
7529 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7530 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7531
7532
7533 /* fastpath */
7534 /* need to be done at the end, since it's self adjusting to amount
7535 * of memory available for RSS queues
7536 */
7537 if (bnx2x_alloc_fp_mem(bp))
7538 goto alloc_mem_err;
7539 return 0;
7540
7541 alloc_mem_err:
7542 bnx2x_free_mem(bp);
7543 BNX2X_ERR("Can't allocate memory\n");
7544 return -ENOMEM;
7545 }
7546
7547 /*
7548 * Init service functions
7549 */
7550
7551 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7552 struct bnx2x_vlan_mac_obj *obj, bool set,
7553 int mac_type, unsigned long *ramrod_flags)
7554 {
7555 int rc;
7556 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7557
7558 memset(&ramrod_param, 0, sizeof(ramrod_param));
7559
7560 /* Fill general parameters */
7561 ramrod_param.vlan_mac_obj = obj;
7562 ramrod_param.ramrod_flags = *ramrod_flags;
7563
7564 /* Fill a user request section if needed */
7565 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7566 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7567
7568 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7569
7570 /* Set the command: ADD or DEL */
7571 if (set)
7572 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7573 else
7574 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7575 }
7576
7577 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7578 if (rc < 0)
7579 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7580 return rc;
7581 }
7582
7583 int bnx2x_del_all_macs(struct bnx2x *bp,
7584 struct bnx2x_vlan_mac_obj *mac_obj,
7585 int mac_type, bool wait_for_comp)
7586 {
7587 int rc;
7588 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7589
7590 /* Wait for completion of requested */
7591 if (wait_for_comp)
7592 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7593
7594 /* Set the mac type of addresses we want to clear */
7595 __set_bit(mac_type, &vlan_mac_flags);
7596
7597 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7598 if (rc < 0)
7599 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7600
7601 return rc;
7602 }
7603
7604 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7605 {
7606 unsigned long ramrod_flags = 0;
7607
7608 #ifdef BCM_CNIC
7609 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7610 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7611 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7612 "Ignoring Zero MAC for STORAGE SD mode\n");
7613 return 0;
7614 }
7615 #endif
7616
7617 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7618
7619 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7620 /* Eth MAC is set on RSS leading client (fp[0]) */
7621 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7622 set, BNX2X_ETH_MAC, &ramrod_flags);
7623 }
7624
7625 int bnx2x_setup_leading(struct bnx2x *bp)
7626 {
7627 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7628 }
7629
7630 /**
7631 * bnx2x_set_int_mode - configure interrupt mode
7632 *
7633 * @bp: driver handle
7634 *
7635 * In case of MSI-X it will also try to enable MSI-X.
7636 */
7637 void bnx2x_set_int_mode(struct bnx2x *bp)
7638 {
7639 switch (int_mode) {
7640 case INT_MODE_MSI:
7641 bnx2x_enable_msi(bp);
7642 /* falling through... */
7643 case INT_MODE_INTx:
7644 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7645 BNX2X_DEV_INFO("set number of queues to 1\n");
7646 break;
7647 default:
7648 /* if we can't use MSI-X we only need one fp,
7649 * so try to enable MSI-X with the requested number of fp's
7650 * and fallback to MSI or legacy INTx with one fp
7651 */
7652 if (bnx2x_enable_msix(bp) ||
7653 bp->flags & USING_SINGLE_MSIX_FLAG) {
7654 /* failed to enable multiple MSI-X */
7655 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7656 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7657
7658 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7659
7660 /* Try to enable MSI */
7661 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7662 !(bp->flags & DISABLE_MSI_FLAG))
7663 bnx2x_enable_msi(bp);
7664 }
7665 break;
7666 }
7667 }
7668
7669 /* must be called prioir to any HW initializations */
7670 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7671 {
7672 return L2_ILT_LINES(bp);
7673 }
7674
7675 void bnx2x_ilt_set_info(struct bnx2x *bp)
7676 {
7677 struct ilt_client_info *ilt_client;
7678 struct bnx2x_ilt *ilt = BP_ILT(bp);
7679 u16 line = 0;
7680
7681 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7682 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7683
7684 /* CDU */
7685 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7686 ilt_client->client_num = ILT_CLIENT_CDU;
7687 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7688 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7689 ilt_client->start = line;
7690 line += bnx2x_cid_ilt_lines(bp);
7691 #ifdef BCM_CNIC
7692 line += CNIC_ILT_LINES;
7693 #endif
7694 ilt_client->end = line - 1;
7695
7696 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7697 ilt_client->start,
7698 ilt_client->end,
7699 ilt_client->page_size,
7700 ilt_client->flags,
7701 ilog2(ilt_client->page_size >> 12));
7702
7703 /* QM */
7704 if (QM_INIT(bp->qm_cid_count)) {
7705 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7706 ilt_client->client_num = ILT_CLIENT_QM;
7707 ilt_client->page_size = QM_ILT_PAGE_SZ;
7708 ilt_client->flags = 0;
7709 ilt_client->start = line;
7710
7711 /* 4 bytes for each cid */
7712 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7713 QM_ILT_PAGE_SZ);
7714
7715 ilt_client->end = line - 1;
7716
7717 DP(NETIF_MSG_IFUP,
7718 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7719 ilt_client->start,
7720 ilt_client->end,
7721 ilt_client->page_size,
7722 ilt_client->flags,
7723 ilog2(ilt_client->page_size >> 12));
7724
7725 }
7726 /* SRC */
7727 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7728 #ifdef BCM_CNIC
7729 ilt_client->client_num = ILT_CLIENT_SRC;
7730 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7731 ilt_client->flags = 0;
7732 ilt_client->start = line;
7733 line += SRC_ILT_LINES;
7734 ilt_client->end = line - 1;
7735
7736 DP(NETIF_MSG_IFUP,
7737 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7738 ilt_client->start,
7739 ilt_client->end,
7740 ilt_client->page_size,
7741 ilt_client->flags,
7742 ilog2(ilt_client->page_size >> 12));
7743
7744 #else
7745 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7746 #endif
7747
7748 /* TM */
7749 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7750 #ifdef BCM_CNIC
7751 ilt_client->client_num = ILT_CLIENT_TM;
7752 ilt_client->page_size = TM_ILT_PAGE_SZ;
7753 ilt_client->flags = 0;
7754 ilt_client->start = line;
7755 line += TM_ILT_LINES;
7756 ilt_client->end = line - 1;
7757
7758 DP(NETIF_MSG_IFUP,
7759 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7760 ilt_client->start,
7761 ilt_client->end,
7762 ilt_client->page_size,
7763 ilt_client->flags,
7764 ilog2(ilt_client->page_size >> 12));
7765
7766 #else
7767 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7768 #endif
7769 BUG_ON(line > ILT_MAX_LINES);
7770 }
7771
7772 /**
7773 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7774 *
7775 * @bp: driver handle
7776 * @fp: pointer to fastpath
7777 * @init_params: pointer to parameters structure
7778 *
7779 * parameters configured:
7780 * - HC configuration
7781 * - Queue's CDU context
7782 */
7783 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7784 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7785 {
7786
7787 u8 cos;
7788 int cxt_index, cxt_offset;
7789
7790 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7791 if (!IS_FCOE_FP(fp)) {
7792 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7793 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7794
7795 /* If HC is supporterd, enable host coalescing in the transition
7796 * to INIT state.
7797 */
7798 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7799 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7800
7801 /* HC rate */
7802 init_params->rx.hc_rate = bp->rx_ticks ?
7803 (1000000 / bp->rx_ticks) : 0;
7804 init_params->tx.hc_rate = bp->tx_ticks ?
7805 (1000000 / bp->tx_ticks) : 0;
7806
7807 /* FW SB ID */
7808 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7809 fp->fw_sb_id;
7810
7811 /*
7812 * CQ index among the SB indices: FCoE clients uses the default
7813 * SB, therefore it's different.
7814 */
7815 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7816 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7817 }
7818
7819 /* set maximum number of COSs supported by this queue */
7820 init_params->max_cos = fp->max_cos;
7821
7822 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7823 fp->index, init_params->max_cos);
7824
7825 /* set the context pointers queue object */
7826 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7827 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7828 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7829 ILT_PAGE_CIDS);
7830 init_params->cxts[cos] =
7831 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7832 }
7833 }
7834
7835 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7836 struct bnx2x_queue_state_params *q_params,
7837 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7838 int tx_index, bool leading)
7839 {
7840 memset(tx_only_params, 0, sizeof(*tx_only_params));
7841
7842 /* Set the command */
7843 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7844
7845 /* Set tx-only QUEUE flags: don't zero statistics */
7846 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7847
7848 /* choose the index of the cid to send the slow path on */
7849 tx_only_params->cid_index = tx_index;
7850
7851 /* Set general TX_ONLY_SETUP parameters */
7852 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7853
7854 /* Set Tx TX_ONLY_SETUP parameters */
7855 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7856
7857 DP(NETIF_MSG_IFUP,
7858 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7859 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7860 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7861 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7862
7863 /* send the ramrod */
7864 return bnx2x_queue_state_change(bp, q_params);
7865 }
7866
7867
7868 /**
7869 * bnx2x_setup_queue - setup queue
7870 *
7871 * @bp: driver handle
7872 * @fp: pointer to fastpath
7873 * @leading: is leading
7874 *
7875 * This function performs 2 steps in a Queue state machine
7876 * actually: 1) RESET->INIT 2) INIT->SETUP
7877 */
7878
7879 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7880 bool leading)
7881 {
7882 struct bnx2x_queue_state_params q_params = {NULL};
7883 struct bnx2x_queue_setup_params *setup_params =
7884 &q_params.params.setup;
7885 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7886 &q_params.params.tx_only;
7887 int rc;
7888 u8 tx_index;
7889
7890 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7891
7892 /* reset IGU state skip FCoE L2 queue */
7893 if (!IS_FCOE_FP(fp))
7894 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7895 IGU_INT_ENABLE, 0);
7896
7897 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7898 /* We want to wait for completion in this context */
7899 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7900
7901 /* Prepare the INIT parameters */
7902 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7903
7904 /* Set the command */
7905 q_params.cmd = BNX2X_Q_CMD_INIT;
7906
7907 /* Change the state to INIT */
7908 rc = bnx2x_queue_state_change(bp, &q_params);
7909 if (rc) {
7910 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7911 return rc;
7912 }
7913
7914 DP(NETIF_MSG_IFUP, "init complete\n");
7915
7916
7917 /* Now move the Queue to the SETUP state... */
7918 memset(setup_params, 0, sizeof(*setup_params));
7919
7920 /* Set QUEUE flags */
7921 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7922
7923 /* Set general SETUP parameters */
7924 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7925 FIRST_TX_COS_INDEX);
7926
7927 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7928 &setup_params->rxq_params);
7929
7930 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7931 FIRST_TX_COS_INDEX);
7932
7933 /* Set the command */
7934 q_params.cmd = BNX2X_Q_CMD_SETUP;
7935
7936 /* Change the state to SETUP */
7937 rc = bnx2x_queue_state_change(bp, &q_params);
7938 if (rc) {
7939 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7940 return rc;
7941 }
7942
7943 /* loop through the relevant tx-only indices */
7944 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7945 tx_index < fp->max_cos;
7946 tx_index++) {
7947
7948 /* prepare and send tx-only ramrod*/
7949 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7950 tx_only_params, tx_index, leading);
7951 if (rc) {
7952 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7953 fp->index, tx_index);
7954 return rc;
7955 }
7956 }
7957
7958 return rc;
7959 }
7960
7961 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7962 {
7963 struct bnx2x_fastpath *fp = &bp->fp[index];
7964 struct bnx2x_fp_txdata *txdata;
7965 struct bnx2x_queue_state_params q_params = {NULL};
7966 int rc, tx_index;
7967
7968 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7969
7970 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7971 /* We want to wait for completion in this context */
7972 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7973
7974
7975 /* close tx-only connections */
7976 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7977 tx_index < fp->max_cos;
7978 tx_index++){
7979
7980 /* ascertain this is a normal queue*/
7981 txdata = fp->txdata_ptr[tx_index];
7982
7983 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7984 txdata->txq_index);
7985
7986 /* send halt terminate on tx-only connection */
7987 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7988 memset(&q_params.params.terminate, 0,
7989 sizeof(q_params.params.terminate));
7990 q_params.params.terminate.cid_index = tx_index;
7991
7992 rc = bnx2x_queue_state_change(bp, &q_params);
7993 if (rc)
7994 return rc;
7995
7996 /* send halt terminate on tx-only connection */
7997 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7998 memset(&q_params.params.cfc_del, 0,
7999 sizeof(q_params.params.cfc_del));
8000 q_params.params.cfc_del.cid_index = tx_index;
8001 rc = bnx2x_queue_state_change(bp, &q_params);
8002 if (rc)
8003 return rc;
8004 }
8005 /* Stop the primary connection: */
8006 /* ...halt the connection */
8007 q_params.cmd = BNX2X_Q_CMD_HALT;
8008 rc = bnx2x_queue_state_change(bp, &q_params);
8009 if (rc)
8010 return rc;
8011
8012 /* ...terminate the connection */
8013 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8014 memset(&q_params.params.terminate, 0,
8015 sizeof(q_params.params.terminate));
8016 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8017 rc = bnx2x_queue_state_change(bp, &q_params);
8018 if (rc)
8019 return rc;
8020 /* ...delete cfc entry */
8021 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8022 memset(&q_params.params.cfc_del, 0,
8023 sizeof(q_params.params.cfc_del));
8024 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8025 return bnx2x_queue_state_change(bp, &q_params);
8026 }
8027
8028
8029 static void bnx2x_reset_func(struct bnx2x *bp)
8030 {
8031 int port = BP_PORT(bp);
8032 int func = BP_FUNC(bp);
8033 int i;
8034
8035 /* Disable the function in the FW */
8036 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8037 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8038 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8039 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8040
8041 /* FP SBs */
8042 for_each_eth_queue(bp, i) {
8043 struct bnx2x_fastpath *fp = &bp->fp[i];
8044 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8045 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8046 SB_DISABLED);
8047 }
8048
8049 #ifdef BCM_CNIC
8050 /* CNIC SB */
8051 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8052 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8053 SB_DISABLED);
8054 #endif
8055 /* SP SB */
8056 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8057 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8058 SB_DISABLED);
8059
8060 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8061 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8062 0);
8063
8064 /* Configure IGU */
8065 if (bp->common.int_block == INT_BLOCK_HC) {
8066 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8067 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8068 } else {
8069 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8070 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8071 }
8072
8073 #ifdef BCM_CNIC
8074 /* Disable Timer scan */
8075 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8076 /*
8077 * Wait for at least 10ms and up to 2 second for the timers scan to
8078 * complete
8079 */
8080 for (i = 0; i < 200; i++) {
8081 msleep(10);
8082 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8083 break;
8084 }
8085 #endif
8086 /* Clear ILT */
8087 bnx2x_clear_func_ilt(bp, func);
8088
8089 /* Timers workaround bug for E2: if this is vnic-3,
8090 * we need to set the entire ilt range for this timers.
8091 */
8092 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8093 struct ilt_client_info ilt_cli;
8094 /* use dummy TM client */
8095 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8096 ilt_cli.start = 0;
8097 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8098 ilt_cli.client_num = ILT_CLIENT_TM;
8099
8100 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8101 }
8102
8103 /* this assumes that reset_port() called before reset_func()*/
8104 if (!CHIP_IS_E1x(bp))
8105 bnx2x_pf_disable(bp);
8106
8107 bp->dmae_ready = 0;
8108 }
8109
8110 static void bnx2x_reset_port(struct bnx2x *bp)
8111 {
8112 int port = BP_PORT(bp);
8113 u32 val;
8114
8115 /* Reset physical Link */
8116 bnx2x__link_reset(bp);
8117
8118 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8119
8120 /* Do not rcv packets to BRB */
8121 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8122 /* Do not direct rcv packets that are not for MCP to the BRB */
8123 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8124 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8125
8126 /* Configure AEU */
8127 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8128
8129 msleep(100);
8130 /* Check for BRB port occupancy */
8131 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8132 if (val)
8133 DP(NETIF_MSG_IFDOWN,
8134 "BRB1 is not empty %d blocks are occupied\n", val);
8135
8136 /* TODO: Close Doorbell port? */
8137 }
8138
8139 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8140 {
8141 struct bnx2x_func_state_params func_params = {NULL};
8142
8143 /* Prepare parameters for function state transitions */
8144 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8145
8146 func_params.f_obj = &bp->func_obj;
8147 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8148
8149 func_params.params.hw_init.load_phase = load_code;
8150
8151 return bnx2x_func_state_change(bp, &func_params);
8152 }
8153
8154 static int bnx2x_func_stop(struct bnx2x *bp)
8155 {
8156 struct bnx2x_func_state_params func_params = {NULL};
8157 int rc;
8158
8159 /* Prepare parameters for function state transitions */
8160 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8161 func_params.f_obj = &bp->func_obj;
8162 func_params.cmd = BNX2X_F_CMD_STOP;
8163
8164 /*
8165 * Try to stop the function the 'good way'. If fails (in case
8166 * of a parity error during bnx2x_chip_cleanup()) and we are
8167 * not in a debug mode, perform a state transaction in order to
8168 * enable further HW_RESET transaction.
8169 */
8170 rc = bnx2x_func_state_change(bp, &func_params);
8171 if (rc) {
8172 #ifdef BNX2X_STOP_ON_ERROR
8173 return rc;
8174 #else
8175 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8176 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8177 return bnx2x_func_state_change(bp, &func_params);
8178 #endif
8179 }
8180
8181 return 0;
8182 }
8183
8184 /**
8185 * bnx2x_send_unload_req - request unload mode from the MCP.
8186 *
8187 * @bp: driver handle
8188 * @unload_mode: requested function's unload mode
8189 *
8190 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8191 */
8192 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8193 {
8194 u32 reset_code = 0;
8195 int port = BP_PORT(bp);
8196
8197 /* Select the UNLOAD request mode */
8198 if (unload_mode == UNLOAD_NORMAL)
8199 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8200
8201 else if (bp->flags & NO_WOL_FLAG)
8202 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8203
8204 else if (bp->wol) {
8205 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8206 u8 *mac_addr = bp->dev->dev_addr;
8207 u32 val;
8208 u16 pmc;
8209
8210 /* The mac address is written to entries 1-4 to
8211 * preserve entry 0 which is used by the PMF
8212 */
8213 u8 entry = (BP_VN(bp) + 1)*8;
8214
8215 val = (mac_addr[0] << 8) | mac_addr[1];
8216 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8217
8218 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8219 (mac_addr[4] << 8) | mac_addr[5];
8220 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8221
8222 /* Enable the PME and clear the status */
8223 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8224 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8225 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8226
8227 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8228
8229 } else
8230 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8231
8232 /* Send the request to the MCP */
8233 if (!BP_NOMCP(bp))
8234 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8235 else {
8236 int path = BP_PATH(bp);
8237
8238 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8239 path, load_count[path][0], load_count[path][1],
8240 load_count[path][2]);
8241 load_count[path][0]--;
8242 load_count[path][1 + port]--;
8243 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8244 path, load_count[path][0], load_count[path][1],
8245 load_count[path][2]);
8246 if (load_count[path][0] == 0)
8247 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8248 else if (load_count[path][1 + port] == 0)
8249 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8250 else
8251 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8252 }
8253
8254 return reset_code;
8255 }
8256
8257 /**
8258 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8259 *
8260 * @bp: driver handle
8261 */
8262 void bnx2x_send_unload_done(struct bnx2x *bp)
8263 {
8264 /* Report UNLOAD_DONE to MCP */
8265 if (!BP_NOMCP(bp))
8266 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8267 }
8268
8269 static int bnx2x_func_wait_started(struct bnx2x *bp)
8270 {
8271 int tout = 50;
8272 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8273
8274 if (!bp->port.pmf)
8275 return 0;
8276
8277 /*
8278 * (assumption: No Attention from MCP at this stage)
8279 * PMF probably in the middle of TXdisable/enable transaction
8280 * 1. Sync IRS for default SB
8281 * 2. Sync SP queue - this guarantes us that attention handling started
8282 * 3. Wait, that TXdisable/enable transaction completes
8283 *
8284 * 1+2 guranty that if DCBx attention was scheduled it already changed
8285 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8286 * received complettion for the transaction the state is TX_STOPPED.
8287 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8288 * transaction.
8289 */
8290
8291 /* make sure default SB ISR is done */
8292 if (msix)
8293 synchronize_irq(bp->msix_table[0].vector);
8294 else
8295 synchronize_irq(bp->pdev->irq);
8296
8297 flush_workqueue(bnx2x_wq);
8298
8299 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8300 BNX2X_F_STATE_STARTED && tout--)
8301 msleep(20);
8302
8303 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8304 BNX2X_F_STATE_STARTED) {
8305 #ifdef BNX2X_STOP_ON_ERROR
8306 BNX2X_ERR("Wrong function state\n");
8307 return -EBUSY;
8308 #else
8309 /*
8310 * Failed to complete the transaction in a "good way"
8311 * Force both transactions with CLR bit
8312 */
8313 struct bnx2x_func_state_params func_params = {NULL};
8314
8315 DP(NETIF_MSG_IFDOWN,
8316 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8317
8318 func_params.f_obj = &bp->func_obj;
8319 __set_bit(RAMROD_DRV_CLR_ONLY,
8320 &func_params.ramrod_flags);
8321
8322 /* STARTED-->TX_ST0PPED */
8323 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8324 bnx2x_func_state_change(bp, &func_params);
8325
8326 /* TX_ST0PPED-->STARTED */
8327 func_params.cmd = BNX2X_F_CMD_TX_START;
8328 return bnx2x_func_state_change(bp, &func_params);
8329 #endif
8330 }
8331
8332 return 0;
8333 }
8334
8335 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
8336 {
8337 int port = BP_PORT(bp);
8338 int i, rc = 0;
8339 u8 cos;
8340 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8341 u32 reset_code;
8342
8343 /* Wait until tx fastpath tasks complete */
8344 for_each_tx_queue(bp, i) {
8345 struct bnx2x_fastpath *fp = &bp->fp[i];
8346
8347 for_each_cos_in_tx_queue(fp, cos)
8348 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8349 #ifdef BNX2X_STOP_ON_ERROR
8350 if (rc)
8351 return;
8352 #endif
8353 }
8354
8355 /* Give HW time to discard old tx messages */
8356 usleep_range(1000, 1000);
8357
8358 /* Clean all ETH MACs */
8359 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8360 false);
8361 if (rc < 0)
8362 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8363
8364 /* Clean up UC list */
8365 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8366 true);
8367 if (rc < 0)
8368 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8369 rc);
8370
8371 /* Disable LLH */
8372 if (!CHIP_IS_E1(bp))
8373 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8374
8375 /* Set "drop all" (stop Rx).
8376 * We need to take a netif_addr_lock() here in order to prevent
8377 * a race between the completion code and this code.
8378 */
8379 netif_addr_lock_bh(bp->dev);
8380 /* Schedule the rx_mode command */
8381 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8382 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8383 else
8384 bnx2x_set_storm_rx_mode(bp);
8385
8386 /* Cleanup multicast configuration */
8387 rparam.mcast_obj = &bp->mcast_obj;
8388 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8389 if (rc < 0)
8390 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8391
8392 netif_addr_unlock_bh(bp->dev);
8393
8394
8395
8396 /*
8397 * Send the UNLOAD_REQUEST to the MCP. This will return if
8398 * this function should perform FUNC, PORT or COMMON HW
8399 * reset.
8400 */
8401 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8402
8403 /*
8404 * (assumption: No Attention from MCP at this stage)
8405 * PMF probably in the middle of TXdisable/enable transaction
8406 */
8407 rc = bnx2x_func_wait_started(bp);
8408 if (rc) {
8409 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8410 #ifdef BNX2X_STOP_ON_ERROR
8411 return;
8412 #endif
8413 }
8414
8415 /* Close multi and leading connections
8416 * Completions for ramrods are collected in a synchronous way
8417 */
8418 for_each_queue(bp, i)
8419 if (bnx2x_stop_queue(bp, i))
8420 #ifdef BNX2X_STOP_ON_ERROR
8421 return;
8422 #else
8423 goto unload_error;
8424 #endif
8425 /* If SP settings didn't get completed so far - something
8426 * very wrong has happen.
8427 */
8428 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8429 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8430
8431 #ifndef BNX2X_STOP_ON_ERROR
8432 unload_error:
8433 #endif
8434 rc = bnx2x_func_stop(bp);
8435 if (rc) {
8436 BNX2X_ERR("Function stop failed!\n");
8437 #ifdef BNX2X_STOP_ON_ERROR
8438 return;
8439 #endif
8440 }
8441
8442 /* Disable HW interrupts, NAPI */
8443 bnx2x_netif_stop(bp, 1);
8444
8445 /* Release IRQs */
8446 bnx2x_free_irq(bp);
8447
8448 /* Reset the chip */
8449 rc = bnx2x_reset_hw(bp, reset_code);
8450 if (rc)
8451 BNX2X_ERR("HW_RESET failed\n");
8452
8453
8454 /* Report UNLOAD_DONE to MCP */
8455 bnx2x_send_unload_done(bp);
8456 }
8457
8458 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8459 {
8460 u32 val;
8461
8462 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8463
8464 if (CHIP_IS_E1(bp)) {
8465 int port = BP_PORT(bp);
8466 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8467 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8468
8469 val = REG_RD(bp, addr);
8470 val &= ~(0x300);
8471 REG_WR(bp, addr, val);
8472 } else {
8473 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8474 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8475 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8476 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8477 }
8478 }
8479
8480 /* Close gates #2, #3 and #4: */
8481 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8482 {
8483 u32 val;
8484
8485 /* Gates #2 and #4a are closed/opened for "not E1" only */
8486 if (!CHIP_IS_E1(bp)) {
8487 /* #4 */
8488 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8489 /* #2 */
8490 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8491 }
8492
8493 /* #3 */
8494 if (CHIP_IS_E1x(bp)) {
8495 /* Prevent interrupts from HC on both ports */
8496 val = REG_RD(bp, HC_REG_CONFIG_1);
8497 REG_WR(bp, HC_REG_CONFIG_1,
8498 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8499 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8500
8501 val = REG_RD(bp, HC_REG_CONFIG_0);
8502 REG_WR(bp, HC_REG_CONFIG_0,
8503 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8504 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8505 } else {
8506 /* Prevent incomming interrupts in IGU */
8507 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8508
8509 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8510 (!close) ?
8511 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8512 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8513 }
8514
8515 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8516 close ? "closing" : "opening");
8517 mmiowb();
8518 }
8519
8520 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8521
8522 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8523 {
8524 /* Do some magic... */
8525 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8526 *magic_val = val & SHARED_MF_CLP_MAGIC;
8527 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8528 }
8529
8530 /**
8531 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8532 *
8533 * @bp: driver handle
8534 * @magic_val: old value of the `magic' bit.
8535 */
8536 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8537 {
8538 /* Restore the `magic' bit value... */
8539 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8540 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8541 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8542 }
8543
8544 /**
8545 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8546 *
8547 * @bp: driver handle
8548 * @magic_val: old value of 'magic' bit.
8549 *
8550 * Takes care of CLP configurations.
8551 */
8552 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8553 {
8554 u32 shmem;
8555 u32 validity_offset;
8556
8557 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8558
8559 /* Set `magic' bit in order to save MF config */
8560 if (!CHIP_IS_E1(bp))
8561 bnx2x_clp_reset_prep(bp, magic_val);
8562
8563 /* Get shmem offset */
8564 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8565 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8566
8567 /* Clear validity map flags */
8568 if (shmem > 0)
8569 REG_WR(bp, shmem + validity_offset, 0);
8570 }
8571
8572 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8573 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8574
8575 /**
8576 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8577 *
8578 * @bp: driver handle
8579 */
8580 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8581 {
8582 /* special handling for emulation and FPGA,
8583 wait 10 times longer */
8584 if (CHIP_REV_IS_SLOW(bp))
8585 msleep(MCP_ONE_TIMEOUT*10);
8586 else
8587 msleep(MCP_ONE_TIMEOUT);
8588 }
8589
8590 /*
8591 * initializes bp->common.shmem_base and waits for validity signature to appear
8592 */
8593 static int bnx2x_init_shmem(struct bnx2x *bp)
8594 {
8595 int cnt = 0;
8596 u32 val = 0;
8597
8598 do {
8599 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8600 if (bp->common.shmem_base) {
8601 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8602 if (val & SHR_MEM_VALIDITY_MB)
8603 return 0;
8604 }
8605
8606 bnx2x_mcp_wait_one(bp);
8607
8608 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8609
8610 BNX2X_ERR("BAD MCP validity signature\n");
8611
8612 return -ENODEV;
8613 }
8614
8615 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8616 {
8617 int rc = bnx2x_init_shmem(bp);
8618
8619 /* Restore the `magic' bit value */
8620 if (!CHIP_IS_E1(bp))
8621 bnx2x_clp_reset_done(bp, magic_val);
8622
8623 return rc;
8624 }
8625
8626 static void bnx2x_pxp_prep(struct bnx2x *bp)
8627 {
8628 if (!CHIP_IS_E1(bp)) {
8629 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8630 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8631 mmiowb();
8632 }
8633 }
8634
8635 /*
8636 * Reset the whole chip except for:
8637 * - PCIE core
8638 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8639 * one reset bit)
8640 * - IGU
8641 * - MISC (including AEU)
8642 * - GRC
8643 * - RBCN, RBCP
8644 */
8645 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8646 {
8647 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8648 u32 global_bits2, stay_reset2;
8649
8650 /*
8651 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8652 * (per chip) blocks.
8653 */
8654 global_bits2 =
8655 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8656 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8657
8658 /* Don't reset the following blocks */
8659 not_reset_mask1 =
8660 MISC_REGISTERS_RESET_REG_1_RST_HC |
8661 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8662 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8663
8664 not_reset_mask2 =
8665 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8666 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8667 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8668 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8669 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8670 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8671 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8672 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8673 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8674 MISC_REGISTERS_RESET_REG_2_PGLC;
8675
8676 /*
8677 * Keep the following blocks in reset:
8678 * - all xxMACs are handled by the bnx2x_link code.
8679 */
8680 stay_reset2 =
8681 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8682 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8683 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8684 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8685 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8686 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8687 MISC_REGISTERS_RESET_REG_2_XMAC |
8688 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8689
8690 /* Full reset masks according to the chip */
8691 reset_mask1 = 0xffffffff;
8692
8693 if (CHIP_IS_E1(bp))
8694 reset_mask2 = 0xffff;
8695 else if (CHIP_IS_E1H(bp))
8696 reset_mask2 = 0x1ffff;
8697 else if (CHIP_IS_E2(bp))
8698 reset_mask2 = 0xfffff;
8699 else /* CHIP_IS_E3 */
8700 reset_mask2 = 0x3ffffff;
8701
8702 /* Don't reset global blocks unless we need to */
8703 if (!global)
8704 reset_mask2 &= ~global_bits2;
8705
8706 /*
8707 * In case of attention in the QM, we need to reset PXP
8708 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8709 * because otherwise QM reset would release 'close the gates' shortly
8710 * before resetting the PXP, then the PSWRQ would send a write
8711 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8712 * read the payload data from PSWWR, but PSWWR would not
8713 * respond. The write queue in PGLUE would stuck, dmae commands
8714 * would not return. Therefore it's important to reset the second
8715 * reset register (containing the
8716 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8717 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8718 * bit).
8719 */
8720 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8721 reset_mask2 & (~not_reset_mask2));
8722
8723 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8724 reset_mask1 & (~not_reset_mask1));
8725
8726 barrier();
8727 mmiowb();
8728
8729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8730 reset_mask2 & (~stay_reset2));
8731
8732 barrier();
8733 mmiowb();
8734
8735 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8736 mmiowb();
8737 }
8738
8739 /**
8740 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8741 * It should get cleared in no more than 1s.
8742 *
8743 * @bp: driver handle
8744 *
8745 * It should get cleared in no more than 1s. Returns 0 if
8746 * pending writes bit gets cleared.
8747 */
8748 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8749 {
8750 u32 cnt = 1000;
8751 u32 pend_bits = 0;
8752
8753 do {
8754 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8755
8756 if (pend_bits == 0)
8757 break;
8758
8759 usleep_range(1000, 1000);
8760 } while (cnt-- > 0);
8761
8762 if (cnt <= 0) {
8763 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8764 pend_bits);
8765 return -EBUSY;
8766 }
8767
8768 return 0;
8769 }
8770
8771 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8772 {
8773 int cnt = 1000;
8774 u32 val = 0;
8775 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8776
8777
8778 /* Empty the Tetris buffer, wait for 1s */
8779 do {
8780 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8781 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8782 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8783 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8784 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8785 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8786 ((port_is_idle_0 & 0x1) == 0x1) &&
8787 ((port_is_idle_1 & 0x1) == 0x1) &&
8788 (pgl_exp_rom2 == 0xffffffff))
8789 break;
8790 usleep_range(1000, 1000);
8791 } while (cnt-- > 0);
8792
8793 if (cnt <= 0) {
8794 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8795 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8796 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8797 pgl_exp_rom2);
8798 return -EAGAIN;
8799 }
8800
8801 barrier();
8802
8803 /* Close gates #2, #3 and #4 */
8804 bnx2x_set_234_gates(bp, true);
8805
8806 /* Poll for IGU VQs for 57712 and newer chips */
8807 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8808 return -EAGAIN;
8809
8810
8811 /* TBD: Indicate that "process kill" is in progress to MCP */
8812
8813 /* Clear "unprepared" bit */
8814 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8815 barrier();
8816
8817 /* Make sure all is written to the chip before the reset */
8818 mmiowb();
8819
8820 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8821 * PSWHST, GRC and PSWRD Tetris buffer.
8822 */
8823 usleep_range(1000, 1000);
8824
8825 /* Prepare to chip reset: */
8826 /* MCP */
8827 if (global)
8828 bnx2x_reset_mcp_prep(bp, &val);
8829
8830 /* PXP */
8831 bnx2x_pxp_prep(bp);
8832 barrier();
8833
8834 /* reset the chip */
8835 bnx2x_process_kill_chip_reset(bp, global);
8836 barrier();
8837
8838 /* Recover after reset: */
8839 /* MCP */
8840 if (global && bnx2x_reset_mcp_comp(bp, val))
8841 return -EAGAIN;
8842
8843 /* TBD: Add resetting the NO_MCP mode DB here */
8844
8845 /* PXP */
8846 bnx2x_pxp_prep(bp);
8847
8848 /* Open the gates #2, #3 and #4 */
8849 bnx2x_set_234_gates(bp, false);
8850
8851 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8852 * reset state, re-enable attentions. */
8853
8854 return 0;
8855 }
8856
8857 int bnx2x_leader_reset(struct bnx2x *bp)
8858 {
8859 int rc = 0;
8860 bool global = bnx2x_reset_is_global(bp);
8861 u32 load_code;
8862
8863 /* if not going to reset MCP - load "fake" driver to reset HW while
8864 * driver is owner of the HW
8865 */
8866 if (!global && !BP_NOMCP(bp)) {
8867 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8868 if (!load_code) {
8869 BNX2X_ERR("MCP response failure, aborting\n");
8870 rc = -EAGAIN;
8871 goto exit_leader_reset;
8872 }
8873 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8874 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8875 BNX2X_ERR("MCP unexpected resp, aborting\n");
8876 rc = -EAGAIN;
8877 goto exit_leader_reset2;
8878 }
8879 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8880 if (!load_code) {
8881 BNX2X_ERR("MCP response failure, aborting\n");
8882 rc = -EAGAIN;
8883 goto exit_leader_reset2;
8884 }
8885 }
8886
8887 /* Try to recover after the failure */
8888 if (bnx2x_process_kill(bp, global)) {
8889 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8890 BP_PATH(bp));
8891 rc = -EAGAIN;
8892 goto exit_leader_reset2;
8893 }
8894
8895 /*
8896 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8897 * state.
8898 */
8899 bnx2x_set_reset_done(bp);
8900 if (global)
8901 bnx2x_clear_reset_global(bp);
8902
8903 exit_leader_reset2:
8904 /* unload "fake driver" if it was loaded */
8905 if (!global && !BP_NOMCP(bp)) {
8906 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8907 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8908 }
8909 exit_leader_reset:
8910 bp->is_leader = 0;
8911 bnx2x_release_leader_lock(bp);
8912 smp_mb();
8913 return rc;
8914 }
8915
8916 static void bnx2x_recovery_failed(struct bnx2x *bp)
8917 {
8918 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8919
8920 /* Disconnect this device */
8921 netif_device_detach(bp->dev);
8922
8923 /*
8924 * Block ifup for all function on this engine until "process kill"
8925 * or power cycle.
8926 */
8927 bnx2x_set_reset_in_progress(bp);
8928
8929 /* Shut down the power */
8930 bnx2x_set_power_state(bp, PCI_D3hot);
8931
8932 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8933
8934 smp_mb();
8935 }
8936
8937 /*
8938 * Assumption: runs under rtnl lock. This together with the fact
8939 * that it's called only from bnx2x_sp_rtnl() ensure that it
8940 * will never be called when netif_running(bp->dev) is false.
8941 */
8942 static void bnx2x_parity_recover(struct bnx2x *bp)
8943 {
8944 bool global = false;
8945 u32 error_recovered, error_unrecovered;
8946 bool is_parity;
8947
8948 DP(NETIF_MSG_HW, "Handling parity\n");
8949 while (1) {
8950 switch (bp->recovery_state) {
8951 case BNX2X_RECOVERY_INIT:
8952 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8953 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8954 WARN_ON(!is_parity);
8955
8956 /* Try to get a LEADER_LOCK HW lock */
8957 if (bnx2x_trylock_leader_lock(bp)) {
8958 bnx2x_set_reset_in_progress(bp);
8959 /*
8960 * Check if there is a global attention and if
8961 * there was a global attention, set the global
8962 * reset bit.
8963 */
8964
8965 if (global)
8966 bnx2x_set_reset_global(bp);
8967
8968 bp->is_leader = 1;
8969 }
8970
8971 /* Stop the driver */
8972 /* If interface has been removed - break */
8973 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8974 return;
8975
8976 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8977
8978 /* Ensure "is_leader", MCP command sequence and
8979 * "recovery_state" update values are seen on other
8980 * CPUs.
8981 */
8982 smp_mb();
8983 break;
8984
8985 case BNX2X_RECOVERY_WAIT:
8986 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8987 if (bp->is_leader) {
8988 int other_engine = BP_PATH(bp) ? 0 : 1;
8989 bool other_load_status =
8990 bnx2x_get_load_status(bp, other_engine);
8991 bool load_status =
8992 bnx2x_get_load_status(bp, BP_PATH(bp));
8993 global = bnx2x_reset_is_global(bp);
8994
8995 /*
8996 * In case of a parity in a global block, let
8997 * the first leader that performs a
8998 * leader_reset() reset the global blocks in
8999 * order to clear global attentions. Otherwise
9000 * the the gates will remain closed for that
9001 * engine.
9002 */
9003 if (load_status ||
9004 (global && other_load_status)) {
9005 /* Wait until all other functions get
9006 * down.
9007 */
9008 schedule_delayed_work(&bp->sp_rtnl_task,
9009 HZ/10);
9010 return;
9011 } else {
9012 /* If all other functions got down -
9013 * try to bring the chip back to
9014 * normal. In any case it's an exit
9015 * point for a leader.
9016 */
9017 if (bnx2x_leader_reset(bp)) {
9018 bnx2x_recovery_failed(bp);
9019 return;
9020 }
9021
9022 /* If we are here, means that the
9023 * leader has succeeded and doesn't
9024 * want to be a leader any more. Try
9025 * to continue as a none-leader.
9026 */
9027 break;
9028 }
9029 } else { /* non-leader */
9030 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9031 /* Try to get a LEADER_LOCK HW lock as
9032 * long as a former leader may have
9033 * been unloaded by the user or
9034 * released a leadership by another
9035 * reason.
9036 */
9037 if (bnx2x_trylock_leader_lock(bp)) {
9038 /* I'm a leader now! Restart a
9039 * switch case.
9040 */
9041 bp->is_leader = 1;
9042 break;
9043 }
9044
9045 schedule_delayed_work(&bp->sp_rtnl_task,
9046 HZ/10);
9047 return;
9048
9049 } else {
9050 /*
9051 * If there was a global attention, wait
9052 * for it to be cleared.
9053 */
9054 if (bnx2x_reset_is_global(bp)) {
9055 schedule_delayed_work(
9056 &bp->sp_rtnl_task,
9057 HZ/10);
9058 return;
9059 }
9060
9061 error_recovered =
9062 bp->eth_stats.recoverable_error;
9063 error_unrecovered =
9064 bp->eth_stats.unrecoverable_error;
9065 bp->recovery_state =
9066 BNX2X_RECOVERY_NIC_LOADING;
9067 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9068 error_unrecovered++;
9069 netdev_err(bp->dev,
9070 "Recovery failed. Power cycle needed\n");
9071 /* Disconnect this device */
9072 netif_device_detach(bp->dev);
9073 /* Shut down the power */
9074 bnx2x_set_power_state(
9075 bp, PCI_D3hot);
9076 smp_mb();
9077 } else {
9078 bp->recovery_state =
9079 BNX2X_RECOVERY_DONE;
9080 error_recovered++;
9081 smp_mb();
9082 }
9083 bp->eth_stats.recoverable_error =
9084 error_recovered;
9085 bp->eth_stats.unrecoverable_error =
9086 error_unrecovered;
9087
9088 return;
9089 }
9090 }
9091 default:
9092 return;
9093 }
9094 }
9095 }
9096
9097 static int bnx2x_close(struct net_device *dev);
9098
9099 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9100 * scheduled on a general queue in order to prevent a dead lock.
9101 */
9102 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9103 {
9104 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9105
9106 rtnl_lock();
9107
9108 if (!netif_running(bp->dev))
9109 goto sp_rtnl_exit;
9110
9111 /* if stop on error is defined no recovery flows should be executed */
9112 #ifdef BNX2X_STOP_ON_ERROR
9113 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9114 "you will need to reboot when done\n");
9115 goto sp_rtnl_not_reset;
9116 #endif
9117
9118 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9119 /*
9120 * Clear all pending SP commands as we are going to reset the
9121 * function anyway.
9122 */
9123 bp->sp_rtnl_state = 0;
9124 smp_mb();
9125
9126 bnx2x_parity_recover(bp);
9127
9128 goto sp_rtnl_exit;
9129 }
9130
9131 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9132 /*
9133 * Clear all pending SP commands as we are going to reset the
9134 * function anyway.
9135 */
9136 bp->sp_rtnl_state = 0;
9137 smp_mb();
9138
9139 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9140 bnx2x_nic_load(bp, LOAD_NORMAL);
9141
9142 goto sp_rtnl_exit;
9143 }
9144 #ifdef BNX2X_STOP_ON_ERROR
9145 sp_rtnl_not_reset:
9146 #endif
9147 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9148 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9149 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9150 bnx2x_after_function_update(bp);
9151 /*
9152 * in case of fan failure we need to reset id if the "stop on error"
9153 * debug flag is set, since we trying to prevent permanent overheating
9154 * damage
9155 */
9156 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9157 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9158 netif_device_detach(bp->dev);
9159 bnx2x_close(bp->dev);
9160 }
9161
9162 sp_rtnl_exit:
9163 rtnl_unlock();
9164 }
9165
9166 /* end of nic load/unload */
9167
9168 static void bnx2x_period_task(struct work_struct *work)
9169 {
9170 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9171
9172 if (!netif_running(bp->dev))
9173 goto period_task_exit;
9174
9175 if (CHIP_REV_IS_SLOW(bp)) {
9176 BNX2X_ERR("period task called on emulation, ignoring\n");
9177 goto period_task_exit;
9178 }
9179
9180 bnx2x_acquire_phy_lock(bp);
9181 /*
9182 * The barrier is needed to ensure the ordering between the writing to
9183 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9184 * the reading here.
9185 */
9186 smp_mb();
9187 if (bp->port.pmf) {
9188 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9189
9190 /* Re-queue task in 1 sec */
9191 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9192 }
9193
9194 bnx2x_release_phy_lock(bp);
9195 period_task_exit:
9196 return;
9197 }
9198
9199 /*
9200 * Init service functions
9201 */
9202
9203 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9204 {
9205 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9206 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9207 return base + (BP_ABS_FUNC(bp)) * stride;
9208 }
9209
9210 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9211 {
9212 u32 reg = bnx2x_get_pretend_reg(bp);
9213
9214 /* Flush all outstanding writes */
9215 mmiowb();
9216
9217 /* Pretend to be function 0 */
9218 REG_WR(bp, reg, 0);
9219 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9220
9221 /* From now we are in the "like-E1" mode */
9222 bnx2x_int_disable(bp);
9223
9224 /* Flush all outstanding writes */
9225 mmiowb();
9226
9227 /* Restore the original function */
9228 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9229 REG_RD(bp, reg);
9230 }
9231
9232 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9233 {
9234 if (CHIP_IS_E1(bp))
9235 bnx2x_int_disable(bp);
9236 else
9237 bnx2x_undi_int_disable_e1h(bp);
9238 }
9239
9240 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9241 {
9242 u32 val, base_addr, offset, mask, reset_reg;
9243 bool mac_stopped = false;
9244 u8 port = BP_PORT(bp);
9245
9246 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9247
9248 if (!CHIP_IS_E3(bp)) {
9249 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9250 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9251 if ((mask & reset_reg) && val) {
9252 u32 wb_data[2];
9253 BNX2X_DEV_INFO("Disable bmac Rx\n");
9254 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9255 : NIG_REG_INGRESS_BMAC0_MEM;
9256 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9257 : BIGMAC_REGISTER_BMAC_CONTROL;
9258
9259 /*
9260 * use rd/wr since we cannot use dmae. This is safe
9261 * since MCP won't access the bus due to the request
9262 * to unload, and no function on the path can be
9263 * loaded at this time.
9264 */
9265 wb_data[0] = REG_RD(bp, base_addr + offset);
9266 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9267 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9268 REG_WR(bp, base_addr + offset, wb_data[0]);
9269 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9270
9271 }
9272 BNX2X_DEV_INFO("Disable emac Rx\n");
9273 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9274
9275 mac_stopped = true;
9276 } else {
9277 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9278 BNX2X_DEV_INFO("Disable xmac Rx\n");
9279 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9280 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9281 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9282 val & ~(1 << 1));
9283 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9284 val | (1 << 1));
9285 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9286 mac_stopped = true;
9287 }
9288 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9289 if (mask & reset_reg) {
9290 BNX2X_DEV_INFO("Disable umac Rx\n");
9291 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9292 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9293 mac_stopped = true;
9294 }
9295 }
9296
9297 if (mac_stopped)
9298 msleep(20);
9299
9300 }
9301
9302 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9303 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9304 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9305 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9306
9307 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9308 u8 inc)
9309 {
9310 u16 rcq, bd;
9311 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9312
9313 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9314 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9315
9316 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9317 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9318
9319 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9320 port, bd, rcq);
9321 }
9322
9323 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9324 {
9325 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9326 if (!rc) {
9327 BNX2X_ERR("MCP response failure, aborting\n");
9328 return -EBUSY;
9329 }
9330
9331 return 0;
9332 }
9333
9334 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9335 {
9336 struct bnx2x_prev_path_list *tmp_list;
9337 int rc = false;
9338
9339 if (down_trylock(&bnx2x_prev_sem))
9340 return false;
9341
9342 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9343 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9344 bp->pdev->bus->number == tmp_list->bus &&
9345 BP_PATH(bp) == tmp_list->path) {
9346 rc = true;
9347 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9348 BP_PATH(bp));
9349 break;
9350 }
9351 }
9352
9353 up(&bnx2x_prev_sem);
9354
9355 return rc;
9356 }
9357
9358 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9359 {
9360 struct bnx2x_prev_path_list *tmp_list;
9361 int rc;
9362
9363 tmp_list = (struct bnx2x_prev_path_list *)
9364 kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9365 if (!tmp_list) {
9366 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9367 return -ENOMEM;
9368 }
9369
9370 tmp_list->bus = bp->pdev->bus->number;
9371 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9372 tmp_list->path = BP_PATH(bp);
9373
9374 rc = down_interruptible(&bnx2x_prev_sem);
9375 if (rc) {
9376 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9377 kfree(tmp_list);
9378 } else {
9379 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9380 BP_PATH(bp));
9381 list_add(&tmp_list->list, &bnx2x_prev_list);
9382 up(&bnx2x_prev_sem);
9383 }
9384
9385 return rc;
9386 }
9387
9388 static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
9389 {
9390 int pos;
9391 u32 cap;
9392 struct pci_dev *dev = bp->pdev;
9393
9394 pos = pci_pcie_cap(dev);
9395 if (!pos)
9396 return false;
9397
9398 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
9399 if (!(cap & PCI_EXP_DEVCAP_FLR))
9400 return false;
9401
9402 return true;
9403 }
9404
9405 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9406 {
9407 int i, pos;
9408 u16 status;
9409 struct pci_dev *dev = bp->pdev;
9410
9411 /* probe the capability first */
9412 if (bnx2x_can_flr(bp))
9413 return -ENOTTY;
9414
9415 pos = pci_pcie_cap(dev);
9416 if (!pos)
9417 return -ENOTTY;
9418
9419 /* Wait for Transaction Pending bit clean */
9420 for (i = 0; i < 4; i++) {
9421 if (i)
9422 msleep((1 << (i - 1)) * 100);
9423
9424 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9425 if (!(status & PCI_EXP_DEVSTA_TRPND))
9426 goto clear;
9427 }
9428
9429 dev_err(&dev->dev,
9430 "transaction is not cleared; proceeding with reset anyway\n");
9431
9432 clear:
9433 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9434 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9435 bp->common.bc_ver);
9436 return -EINVAL;
9437 }
9438
9439 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9440
9441 return 0;
9442 }
9443
9444 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9445 {
9446 int rc;
9447
9448 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9449
9450 /* Test if previous unload process was already finished for this path */
9451 if (bnx2x_prev_is_path_marked(bp))
9452 return bnx2x_prev_mcp_done(bp);
9453
9454 /* If function has FLR capabilities, and existing FW version matches
9455 * the one required, then FLR will be sufficient to clean any residue
9456 * left by previous driver
9457 */
9458 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp))
9459 return bnx2x_do_flr(bp);
9460
9461 /* Close the MCP request, return failure*/
9462 rc = bnx2x_prev_mcp_done(bp);
9463 if (!rc)
9464 rc = BNX2X_PREV_WAIT_NEEDED;
9465
9466 return rc;
9467 }
9468
9469 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9470 {
9471 u32 reset_reg, tmp_reg = 0, rc;
9472 /* It is possible a previous function received 'common' answer,
9473 * but hasn't loaded yet, therefore creating a scenario of
9474 * multiple functions receiving 'common' on the same path.
9475 */
9476 BNX2X_DEV_INFO("Common unload Flow\n");
9477
9478 if (bnx2x_prev_is_path_marked(bp))
9479 return bnx2x_prev_mcp_done(bp);
9480
9481 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9482
9483 /* Reset should be performed after BRB is emptied */
9484 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9485 u32 timer_count = 1000;
9486 bool prev_undi = false;
9487
9488 /* Close the MAC Rx to prevent BRB from filling up */
9489 bnx2x_prev_unload_close_mac(bp);
9490
9491 /* Check if the UNDI driver was previously loaded
9492 * UNDI driver initializes CID offset for normal bell to 0x7
9493 */
9494 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9495 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9496 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9497 if (tmp_reg == 0x7) {
9498 BNX2X_DEV_INFO("UNDI previously loaded\n");
9499 prev_undi = true;
9500 /* clear the UNDI indication */
9501 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9502 }
9503 }
9504 /* wait until BRB is empty */
9505 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9506 while (timer_count) {
9507 u32 prev_brb = tmp_reg;
9508
9509 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9510 if (!tmp_reg)
9511 break;
9512
9513 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9514
9515 /* reset timer as long as BRB actually gets emptied */
9516 if (prev_brb > tmp_reg)
9517 timer_count = 1000;
9518 else
9519 timer_count--;
9520
9521 /* If UNDI resides in memory, manually increment it */
9522 if (prev_undi)
9523 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9524
9525 udelay(10);
9526 }
9527
9528 if (!timer_count)
9529 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9530
9531 }
9532
9533 /* No packets are in the pipeline, path is ready for reset */
9534 bnx2x_reset_common(bp);
9535
9536 rc = bnx2x_prev_mark_path(bp);
9537 if (rc) {
9538 bnx2x_prev_mcp_done(bp);
9539 return rc;
9540 }
9541
9542 return bnx2x_prev_mcp_done(bp);
9543 }
9544
9545 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9546 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9547 * the addresses of the transaction, resulting in was-error bit set in the pci
9548 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9549 * to clear the interrupt which detected this from the pglueb and the was done
9550 * bit
9551 */
9552 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9553 {
9554 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9555 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9556 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9557 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9558 }
9559 }
9560
9561 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9562 {
9563 int time_counter = 10;
9564 u32 rc, fw, hw_lock_reg, hw_lock_val;
9565 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9566
9567 /* clear hw from errors which may have resulted from an interrupted
9568 * dmae transaction.
9569 */
9570 bnx2x_prev_interrupted_dmae(bp);
9571
9572 /* Release previously held locks */
9573 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9574 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9575 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9576
9577 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9578 if (hw_lock_val) {
9579 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9580 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9581 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9582 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9583 }
9584
9585 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9586 REG_WR(bp, hw_lock_reg, 0xffffffff);
9587 } else
9588 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9589
9590 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9591 BNX2X_DEV_INFO("Release previously held alr\n");
9592 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9593 }
9594
9595
9596 do {
9597 /* Lock MCP using an unload request */
9598 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9599 if (!fw) {
9600 BNX2X_ERR("MCP response failure, aborting\n");
9601 rc = -EBUSY;
9602 break;
9603 }
9604
9605 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9606 rc = bnx2x_prev_unload_common(bp);
9607 break;
9608 }
9609
9610 /* non-common reply from MCP night require looping */
9611 rc = bnx2x_prev_unload_uncommon(bp);
9612 if (rc != BNX2X_PREV_WAIT_NEEDED)
9613 break;
9614
9615 msleep(20);
9616 } while (--time_counter);
9617
9618 if (!time_counter || rc) {
9619 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9620 rc = -EBUSY;
9621 }
9622
9623 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9624
9625 return rc;
9626 }
9627
9628 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9629 {
9630 u32 val, val2, val3, val4, id, boot_mode;
9631 u16 pmc;
9632
9633 /* Get the chip revision id and number. */
9634 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9635 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9636 id = ((val & 0xffff) << 16);
9637 val = REG_RD(bp, MISC_REG_CHIP_REV);
9638 id |= ((val & 0xf) << 12);
9639 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9640 id |= ((val & 0xff) << 4);
9641 val = REG_RD(bp, MISC_REG_BOND_ID);
9642 id |= (val & 0xf);
9643 bp->common.chip_id = id;
9644
9645 /* force 57811 according to MISC register */
9646 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9647 if (CHIP_IS_57810(bp))
9648 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9649 (bp->common.chip_id & 0x0000FFFF);
9650 else if (CHIP_IS_57810_MF(bp))
9651 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9652 (bp->common.chip_id & 0x0000FFFF);
9653 bp->common.chip_id |= 0x1;
9654 }
9655
9656 /* Set doorbell size */
9657 bp->db_size = (1 << BNX2X_DB_SHIFT);
9658
9659 if (!CHIP_IS_E1x(bp)) {
9660 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9661 if ((val & 1) == 0)
9662 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9663 else
9664 val = (val >> 1) & 1;
9665 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9666 "2_PORT_MODE");
9667 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9668 CHIP_2_PORT_MODE;
9669
9670 if (CHIP_MODE_IS_4_PORT(bp))
9671 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9672 else
9673 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9674 } else {
9675 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9676 bp->pfid = bp->pf_num; /* 0..7 */
9677 }
9678
9679 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9680
9681 bp->link_params.chip_id = bp->common.chip_id;
9682 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9683
9684 val = (REG_RD(bp, 0x2874) & 0x55);
9685 if ((bp->common.chip_id & 0x1) ||
9686 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9687 bp->flags |= ONE_PORT_FLAG;
9688 BNX2X_DEV_INFO("single port device\n");
9689 }
9690
9691 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9692 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9693 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9694 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9695 bp->common.flash_size, bp->common.flash_size);
9696
9697 bnx2x_init_shmem(bp);
9698
9699
9700
9701 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9702 MISC_REG_GENERIC_CR_1 :
9703 MISC_REG_GENERIC_CR_0));
9704
9705 bp->link_params.shmem_base = bp->common.shmem_base;
9706 bp->link_params.shmem2_base = bp->common.shmem2_base;
9707 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9708 bp->common.shmem_base, bp->common.shmem2_base);
9709
9710 if (!bp->common.shmem_base) {
9711 BNX2X_DEV_INFO("MCP not active\n");
9712 bp->flags |= NO_MCP_FLAG;
9713 return;
9714 }
9715
9716 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9717 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9718
9719 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9720 SHARED_HW_CFG_LED_MODE_MASK) >>
9721 SHARED_HW_CFG_LED_MODE_SHIFT);
9722
9723 bp->link_params.feature_config_flags = 0;
9724 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9725 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9726 bp->link_params.feature_config_flags |=
9727 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9728 else
9729 bp->link_params.feature_config_flags &=
9730 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9731
9732 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9733 bp->common.bc_ver = val;
9734 BNX2X_DEV_INFO("bc_ver %X\n", val);
9735 if (val < BNX2X_BC_VER) {
9736 /* for now only warn
9737 * later we might need to enforce this */
9738 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9739 BNX2X_BC_VER, val);
9740 }
9741 bp->link_params.feature_config_flags |=
9742 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9743 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9744
9745 bp->link_params.feature_config_flags |=
9746 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9747 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9748 bp->link_params.feature_config_flags |=
9749 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9750 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9751 bp->link_params.feature_config_flags |=
9752 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9753 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9754 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9755 BC_SUPPORTS_PFC_STATS : 0;
9756
9757 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9758 BC_SUPPORTS_FCOE_FEATURES : 0;
9759
9760 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9761 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9762 boot_mode = SHMEM_RD(bp,
9763 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9764 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9765 switch (boot_mode) {
9766 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9767 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9768 break;
9769 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9770 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9771 break;
9772 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9773 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9774 break;
9775 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9776 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9777 break;
9778 }
9779
9780 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9781 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9782
9783 BNX2X_DEV_INFO("%sWoL capable\n",
9784 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9785
9786 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9787 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9788 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9789 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9790
9791 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9792 val, val2, val3, val4);
9793 }
9794
9795 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9796 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9797
9798 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9799 {
9800 int pfid = BP_FUNC(bp);
9801 int igu_sb_id;
9802 u32 val;
9803 u8 fid, igu_sb_cnt = 0;
9804
9805 bp->igu_base_sb = 0xff;
9806 if (CHIP_INT_MODE_IS_BC(bp)) {
9807 int vn = BP_VN(bp);
9808 igu_sb_cnt = bp->igu_sb_cnt;
9809 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9810 FP_SB_MAX_E1x;
9811
9812 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9813 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9814
9815 return;
9816 }
9817
9818 /* IGU in normal mode - read CAM */
9819 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9820 igu_sb_id++) {
9821 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9822 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9823 continue;
9824 fid = IGU_FID(val);
9825 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9826 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9827 continue;
9828 if (IGU_VEC(val) == 0)
9829 /* default status block */
9830 bp->igu_dsb_id = igu_sb_id;
9831 else {
9832 if (bp->igu_base_sb == 0xff)
9833 bp->igu_base_sb = igu_sb_id;
9834 igu_sb_cnt++;
9835 }
9836 }
9837 }
9838
9839 #ifdef CONFIG_PCI_MSI
9840 /*
9841 * It's expected that number of CAM entries for this functions is equal
9842 * to the number evaluated based on the MSI-X table size. We want a
9843 * harsh warning if these values are different!
9844 */
9845 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9846 #endif
9847
9848 if (igu_sb_cnt == 0)
9849 BNX2X_ERR("CAM configuration error\n");
9850 }
9851
9852 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9853 u32 switch_cfg)
9854 {
9855 int cfg_size = 0, idx, port = BP_PORT(bp);
9856
9857 /* Aggregation of supported attributes of all external phys */
9858 bp->port.supported[0] = 0;
9859 bp->port.supported[1] = 0;
9860 switch (bp->link_params.num_phys) {
9861 case 1:
9862 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9863 cfg_size = 1;
9864 break;
9865 case 2:
9866 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9867 cfg_size = 1;
9868 break;
9869 case 3:
9870 if (bp->link_params.multi_phy_config &
9871 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9872 bp->port.supported[1] =
9873 bp->link_params.phy[EXT_PHY1].supported;
9874 bp->port.supported[0] =
9875 bp->link_params.phy[EXT_PHY2].supported;
9876 } else {
9877 bp->port.supported[0] =
9878 bp->link_params.phy[EXT_PHY1].supported;
9879 bp->port.supported[1] =
9880 bp->link_params.phy[EXT_PHY2].supported;
9881 }
9882 cfg_size = 2;
9883 break;
9884 }
9885
9886 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9887 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9888 SHMEM_RD(bp,
9889 dev_info.port_hw_config[port].external_phy_config),
9890 SHMEM_RD(bp,
9891 dev_info.port_hw_config[port].external_phy_config2));
9892 return;
9893 }
9894
9895 if (CHIP_IS_E3(bp))
9896 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9897 else {
9898 switch (switch_cfg) {
9899 case SWITCH_CFG_1G:
9900 bp->port.phy_addr = REG_RD(
9901 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9902 break;
9903 case SWITCH_CFG_10G:
9904 bp->port.phy_addr = REG_RD(
9905 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9906 break;
9907 default:
9908 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9909 bp->port.link_config[0]);
9910 return;
9911 }
9912 }
9913 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9914 /* mask what we support according to speed_cap_mask per configuration */
9915 for (idx = 0; idx < cfg_size; idx++) {
9916 if (!(bp->link_params.speed_cap_mask[idx] &
9917 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9918 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9919
9920 if (!(bp->link_params.speed_cap_mask[idx] &
9921 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9922 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9923
9924 if (!(bp->link_params.speed_cap_mask[idx] &
9925 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9926 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9927
9928 if (!(bp->link_params.speed_cap_mask[idx] &
9929 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9930 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9931
9932 if (!(bp->link_params.speed_cap_mask[idx] &
9933 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9934 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9935 SUPPORTED_1000baseT_Full);
9936
9937 if (!(bp->link_params.speed_cap_mask[idx] &
9938 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9939 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9940
9941 if (!(bp->link_params.speed_cap_mask[idx] &
9942 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9943 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9944
9945 }
9946
9947 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9948 bp->port.supported[1]);
9949 }
9950
9951 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9952 {
9953 u32 link_config, idx, cfg_size = 0;
9954 bp->port.advertising[0] = 0;
9955 bp->port.advertising[1] = 0;
9956 switch (bp->link_params.num_phys) {
9957 case 1:
9958 case 2:
9959 cfg_size = 1;
9960 break;
9961 case 3:
9962 cfg_size = 2;
9963 break;
9964 }
9965 for (idx = 0; idx < cfg_size; idx++) {
9966 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9967 link_config = bp->port.link_config[idx];
9968 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9969 case PORT_FEATURE_LINK_SPEED_AUTO:
9970 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9971 bp->link_params.req_line_speed[idx] =
9972 SPEED_AUTO_NEG;
9973 bp->port.advertising[idx] |=
9974 bp->port.supported[idx];
9975 if (bp->link_params.phy[EXT_PHY1].type ==
9976 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9977 bp->port.advertising[idx] |=
9978 (SUPPORTED_100baseT_Half |
9979 SUPPORTED_100baseT_Full);
9980 } else {
9981 /* force 10G, no AN */
9982 bp->link_params.req_line_speed[idx] =
9983 SPEED_10000;
9984 bp->port.advertising[idx] |=
9985 (ADVERTISED_10000baseT_Full |
9986 ADVERTISED_FIBRE);
9987 continue;
9988 }
9989 break;
9990
9991 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9992 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9993 bp->link_params.req_line_speed[idx] =
9994 SPEED_10;
9995 bp->port.advertising[idx] |=
9996 (ADVERTISED_10baseT_Full |
9997 ADVERTISED_TP);
9998 } else {
9999 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10000 link_config,
10001 bp->link_params.speed_cap_mask[idx]);
10002 return;
10003 }
10004 break;
10005
10006 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10007 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10008 bp->link_params.req_line_speed[idx] =
10009 SPEED_10;
10010 bp->link_params.req_duplex[idx] =
10011 DUPLEX_HALF;
10012 bp->port.advertising[idx] |=
10013 (ADVERTISED_10baseT_Half |
10014 ADVERTISED_TP);
10015 } else {
10016 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10017 link_config,
10018 bp->link_params.speed_cap_mask[idx]);
10019 return;
10020 }
10021 break;
10022
10023 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10024 if (bp->port.supported[idx] &
10025 SUPPORTED_100baseT_Full) {
10026 bp->link_params.req_line_speed[idx] =
10027 SPEED_100;
10028 bp->port.advertising[idx] |=
10029 (ADVERTISED_100baseT_Full |
10030 ADVERTISED_TP);
10031 } else {
10032 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10033 link_config,
10034 bp->link_params.speed_cap_mask[idx]);
10035 return;
10036 }
10037 break;
10038
10039 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10040 if (bp->port.supported[idx] &
10041 SUPPORTED_100baseT_Half) {
10042 bp->link_params.req_line_speed[idx] =
10043 SPEED_100;
10044 bp->link_params.req_duplex[idx] =
10045 DUPLEX_HALF;
10046 bp->port.advertising[idx] |=
10047 (ADVERTISED_100baseT_Half |
10048 ADVERTISED_TP);
10049 } else {
10050 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10051 link_config,
10052 bp->link_params.speed_cap_mask[idx]);
10053 return;
10054 }
10055 break;
10056
10057 case PORT_FEATURE_LINK_SPEED_1G:
10058 if (bp->port.supported[idx] &
10059 SUPPORTED_1000baseT_Full) {
10060 bp->link_params.req_line_speed[idx] =
10061 SPEED_1000;
10062 bp->port.advertising[idx] |=
10063 (ADVERTISED_1000baseT_Full |
10064 ADVERTISED_TP);
10065 } else {
10066 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10067 link_config,
10068 bp->link_params.speed_cap_mask[idx]);
10069 return;
10070 }
10071 break;
10072
10073 case PORT_FEATURE_LINK_SPEED_2_5G:
10074 if (bp->port.supported[idx] &
10075 SUPPORTED_2500baseX_Full) {
10076 bp->link_params.req_line_speed[idx] =
10077 SPEED_2500;
10078 bp->port.advertising[idx] |=
10079 (ADVERTISED_2500baseX_Full |
10080 ADVERTISED_TP);
10081 } else {
10082 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10083 link_config,
10084 bp->link_params.speed_cap_mask[idx]);
10085 return;
10086 }
10087 break;
10088
10089 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10090 if (bp->port.supported[idx] &
10091 SUPPORTED_10000baseT_Full) {
10092 bp->link_params.req_line_speed[idx] =
10093 SPEED_10000;
10094 bp->port.advertising[idx] |=
10095 (ADVERTISED_10000baseT_Full |
10096 ADVERTISED_FIBRE);
10097 } else {
10098 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10099 link_config,
10100 bp->link_params.speed_cap_mask[idx]);
10101 return;
10102 }
10103 break;
10104 case PORT_FEATURE_LINK_SPEED_20G:
10105 bp->link_params.req_line_speed[idx] = SPEED_20000;
10106
10107 break;
10108 default:
10109 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10110 link_config);
10111 bp->link_params.req_line_speed[idx] =
10112 SPEED_AUTO_NEG;
10113 bp->port.advertising[idx] =
10114 bp->port.supported[idx];
10115 break;
10116 }
10117
10118 bp->link_params.req_flow_ctrl[idx] = (link_config &
10119 PORT_FEATURE_FLOW_CONTROL_MASK);
10120 if ((bp->link_params.req_flow_ctrl[idx] ==
10121 BNX2X_FLOW_CTRL_AUTO) &&
10122 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10123 bp->link_params.req_flow_ctrl[idx] =
10124 BNX2X_FLOW_CTRL_NONE;
10125 }
10126
10127 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10128 bp->link_params.req_line_speed[idx],
10129 bp->link_params.req_duplex[idx],
10130 bp->link_params.req_flow_ctrl[idx],
10131 bp->port.advertising[idx]);
10132 }
10133 }
10134
10135 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10136 {
10137 mac_hi = cpu_to_be16(mac_hi);
10138 mac_lo = cpu_to_be32(mac_lo);
10139 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10140 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10141 }
10142
10143 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10144 {
10145 int port = BP_PORT(bp);
10146 u32 config;
10147 u32 ext_phy_type, ext_phy_config, eee_mode;
10148
10149 bp->link_params.bp = bp;
10150 bp->link_params.port = port;
10151
10152 bp->link_params.lane_config =
10153 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10154
10155 bp->link_params.speed_cap_mask[0] =
10156 SHMEM_RD(bp,
10157 dev_info.port_hw_config[port].speed_capability_mask);
10158 bp->link_params.speed_cap_mask[1] =
10159 SHMEM_RD(bp,
10160 dev_info.port_hw_config[port].speed_capability_mask2);
10161 bp->port.link_config[0] =
10162 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10163
10164 bp->port.link_config[1] =
10165 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10166
10167 bp->link_params.multi_phy_config =
10168 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10169 /* If the device is capable of WoL, set the default state according
10170 * to the HW
10171 */
10172 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10173 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10174 (config & PORT_FEATURE_WOL_ENABLED));
10175
10176 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10177 bp->link_params.lane_config,
10178 bp->link_params.speed_cap_mask[0],
10179 bp->port.link_config[0]);
10180
10181 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10182 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10183 bnx2x_phy_probe(&bp->link_params);
10184 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10185
10186 bnx2x_link_settings_requested(bp);
10187
10188 /*
10189 * If connected directly, work with the internal PHY, otherwise, work
10190 * with the external PHY
10191 */
10192 ext_phy_config =
10193 SHMEM_RD(bp,
10194 dev_info.port_hw_config[port].external_phy_config);
10195 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10196 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10197 bp->mdio.prtad = bp->port.phy_addr;
10198
10199 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10200 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10201 bp->mdio.prtad =
10202 XGXS_EXT_PHY_ADDR(ext_phy_config);
10203
10204 /*
10205 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10206 * In MF mode, it is set to cover self test cases
10207 */
10208 if (IS_MF(bp))
10209 bp->port.need_hw_lock = 1;
10210 else
10211 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10212 bp->common.shmem_base,
10213 bp->common.shmem2_base);
10214
10215 /* Configure link feature according to nvram value */
10216 eee_mode = (((SHMEM_RD(bp, dev_info.
10217 port_feature_config[port].eee_power_mode)) &
10218 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10219 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10220 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10221 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10222 EEE_MODE_ENABLE_LPI |
10223 EEE_MODE_OUTPUT_TIME;
10224 } else {
10225 bp->link_params.eee_mode = 0;
10226 }
10227 }
10228
10229 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10230 {
10231 u32 no_flags = NO_ISCSI_FLAG;
10232 #ifdef BCM_CNIC
10233 int port = BP_PORT(bp);
10234
10235 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10236 drv_lic_key[port].max_iscsi_conn);
10237
10238 /* Get the number of maximum allowed iSCSI connections */
10239 bp->cnic_eth_dev.max_iscsi_conn =
10240 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10241 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10242
10243 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10244 bp->cnic_eth_dev.max_iscsi_conn);
10245
10246 /*
10247 * If maximum allowed number of connections is zero -
10248 * disable the feature.
10249 */
10250 if (!bp->cnic_eth_dev.max_iscsi_conn)
10251 bp->flags |= no_flags;
10252 #else
10253 bp->flags |= no_flags;
10254 #endif
10255 }
10256
10257 #ifdef BCM_CNIC
10258 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10259 {
10260 /* Port info */
10261 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10262 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10263 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10264 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10265
10266 /* Node info */
10267 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10268 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10269 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10270 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10271 }
10272 #endif
10273 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10274 {
10275 #ifdef BCM_CNIC
10276 int port = BP_PORT(bp);
10277 int func = BP_ABS_FUNC(bp);
10278
10279 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10280 drv_lic_key[port].max_fcoe_conn);
10281
10282 /* Get the number of maximum allowed FCoE connections */
10283 bp->cnic_eth_dev.max_fcoe_conn =
10284 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10285 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10286
10287 /* Read the WWN: */
10288 if (!IS_MF(bp)) {
10289 /* Port info */
10290 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10291 SHMEM_RD(bp,
10292 dev_info.port_hw_config[port].
10293 fcoe_wwn_port_name_upper);
10294 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10295 SHMEM_RD(bp,
10296 dev_info.port_hw_config[port].
10297 fcoe_wwn_port_name_lower);
10298
10299 /* Node info */
10300 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10301 SHMEM_RD(bp,
10302 dev_info.port_hw_config[port].
10303 fcoe_wwn_node_name_upper);
10304 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10305 SHMEM_RD(bp,
10306 dev_info.port_hw_config[port].
10307 fcoe_wwn_node_name_lower);
10308 } else if (!IS_MF_SD(bp)) {
10309 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10310
10311 /*
10312 * Read the WWN info only if the FCoE feature is enabled for
10313 * this function.
10314 */
10315 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
10316 bnx2x_get_ext_wwn_info(bp, func);
10317
10318 } else if (IS_MF_FCOE_SD(bp))
10319 bnx2x_get_ext_wwn_info(bp, func);
10320
10321 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10322
10323 /*
10324 * If maximum allowed number of connections is zero -
10325 * disable the feature.
10326 */
10327 if (!bp->cnic_eth_dev.max_fcoe_conn)
10328 bp->flags |= NO_FCOE_FLAG;
10329 #else
10330 bp->flags |= NO_FCOE_FLAG;
10331 #endif
10332 }
10333
10334 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10335 {
10336 /*
10337 * iSCSI may be dynamically disabled but reading
10338 * info here we will decrease memory usage by driver
10339 * if the feature is disabled for good
10340 */
10341 bnx2x_get_iscsi_info(bp);
10342 bnx2x_get_fcoe_info(bp);
10343 }
10344
10345 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10346 {
10347 u32 val, val2;
10348 int func = BP_ABS_FUNC(bp);
10349 int port = BP_PORT(bp);
10350 #ifdef BCM_CNIC
10351 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10352 u8 *fip_mac = bp->fip_mac;
10353 #endif
10354
10355 /* Zero primary MAC configuration */
10356 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10357
10358 if (BP_NOMCP(bp)) {
10359 BNX2X_ERROR("warning: random MAC workaround active\n");
10360 eth_hw_addr_random(bp->dev);
10361 } else if (IS_MF(bp)) {
10362 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10363 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10364 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10365 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10366 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10367
10368 #ifdef BCM_CNIC
10369 /*
10370 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10371 * FCoE MAC then the appropriate feature should be disabled.
10372 *
10373 * In non SD mode features configuration comes from
10374 * struct func_ext_config.
10375 */
10376 if (!IS_MF_SD(bp)) {
10377 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10378 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10379 val2 = MF_CFG_RD(bp, func_ext_config[func].
10380 iscsi_mac_addr_upper);
10381 val = MF_CFG_RD(bp, func_ext_config[func].
10382 iscsi_mac_addr_lower);
10383 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10384 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10385 iscsi_mac);
10386 } else
10387 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10388
10389 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10390 val2 = MF_CFG_RD(bp, func_ext_config[func].
10391 fcoe_mac_addr_upper);
10392 val = MF_CFG_RD(bp, func_ext_config[func].
10393 fcoe_mac_addr_lower);
10394 bnx2x_set_mac_buf(fip_mac, val, val2);
10395 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10396 fip_mac);
10397
10398 } else
10399 bp->flags |= NO_FCOE_FLAG;
10400
10401 bp->mf_ext_config = cfg;
10402
10403 } else { /* SD MODE */
10404 if (IS_MF_STORAGE_SD(bp)) {
10405 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10406 /* use primary mac as iscsi mac */
10407 memcpy(iscsi_mac, bp->dev->dev_addr,
10408 ETH_ALEN);
10409
10410 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10411 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10412 iscsi_mac);
10413 } else { /* FCoE */
10414 memcpy(fip_mac, bp->dev->dev_addr,
10415 ETH_ALEN);
10416 BNX2X_DEV_INFO("SD FCoE MODE\n");
10417 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10418 fip_mac);
10419 }
10420 /* Zero primary MAC configuration */
10421 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10422 }
10423 }
10424
10425 if (IS_MF_FCOE_AFEX(bp))
10426 /* use FIP MAC as primary MAC */
10427 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10428
10429 #endif
10430 } else {
10431 /* in SF read MACs from port configuration */
10432 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10433 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10434 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10435
10436 #ifdef BCM_CNIC
10437 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10438 iscsi_mac_upper);
10439 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10440 iscsi_mac_lower);
10441 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10442
10443 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10444 fcoe_fip_mac_upper);
10445 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10446 fcoe_fip_mac_lower);
10447 bnx2x_set_mac_buf(fip_mac, val, val2);
10448 #endif
10449 }
10450
10451 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10452 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10453
10454 #ifdef BCM_CNIC
10455 /* Disable iSCSI if MAC configuration is
10456 * invalid.
10457 */
10458 if (!is_valid_ether_addr(iscsi_mac)) {
10459 bp->flags |= NO_ISCSI_FLAG;
10460 memset(iscsi_mac, 0, ETH_ALEN);
10461 }
10462
10463 /* Disable FCoE if MAC configuration is
10464 * invalid.
10465 */
10466 if (!is_valid_ether_addr(fip_mac)) {
10467 bp->flags |= NO_FCOE_FLAG;
10468 memset(bp->fip_mac, 0, ETH_ALEN);
10469 }
10470 #endif
10471
10472 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10473 dev_err(&bp->pdev->dev,
10474 "bad Ethernet MAC address configuration: %pM\n"
10475 "change it manually before bringing up the appropriate network interface\n",
10476 bp->dev->dev_addr);
10477
10478
10479 }
10480
10481 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10482 {
10483 int /*abs*/func = BP_ABS_FUNC(bp);
10484 int vn;
10485 u32 val = 0;
10486 int rc = 0;
10487
10488 bnx2x_get_common_hwinfo(bp);
10489
10490 /*
10491 * initialize IGU parameters
10492 */
10493 if (CHIP_IS_E1x(bp)) {
10494 bp->common.int_block = INT_BLOCK_HC;
10495
10496 bp->igu_dsb_id = DEF_SB_IGU_ID;
10497 bp->igu_base_sb = 0;
10498 } else {
10499 bp->common.int_block = INT_BLOCK_IGU;
10500
10501 /* do not allow device reset during IGU info preocessing */
10502 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10503
10504 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10505
10506 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10507 int tout = 5000;
10508
10509 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10510
10511 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10512 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10513 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10514
10515 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10516 tout--;
10517 usleep_range(1000, 1000);
10518 }
10519
10520 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10521 dev_err(&bp->pdev->dev,
10522 "FORCING Normal Mode failed!!!\n");
10523 return -EPERM;
10524 }
10525 }
10526
10527 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10528 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10529 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10530 } else
10531 BNX2X_DEV_INFO("IGU Normal Mode\n");
10532
10533 bnx2x_get_igu_cam_info(bp);
10534
10535 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10536 }
10537
10538 /*
10539 * set base FW non-default (fast path) status block id, this value is
10540 * used to initialize the fw_sb_id saved on the fp/queue structure to
10541 * determine the id used by the FW.
10542 */
10543 if (CHIP_IS_E1x(bp))
10544 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10545 else /*
10546 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10547 * the same queue are indicated on the same IGU SB). So we prefer
10548 * FW and IGU SBs to be the same value.
10549 */
10550 bp->base_fw_ndsb = bp->igu_base_sb;
10551
10552 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10553 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10554 bp->igu_sb_cnt, bp->base_fw_ndsb);
10555
10556 /*
10557 * Initialize MF configuration
10558 */
10559
10560 bp->mf_ov = 0;
10561 bp->mf_mode = 0;
10562 vn = BP_VN(bp);
10563
10564 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10565 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10566 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10567 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10568
10569 if (SHMEM2_HAS(bp, mf_cfg_addr))
10570 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10571 else
10572 bp->common.mf_cfg_base = bp->common.shmem_base +
10573 offsetof(struct shmem_region, func_mb) +
10574 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10575 /*
10576 * get mf configuration:
10577 * 1. existence of MF configuration
10578 * 2. MAC address must be legal (check only upper bytes)
10579 * for Switch-Independent mode;
10580 * OVLAN must be legal for Switch-Dependent mode
10581 * 3. SF_MODE configures specific MF mode
10582 */
10583 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10584 /* get mf configuration */
10585 val = SHMEM_RD(bp,
10586 dev_info.shared_feature_config.config);
10587 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10588
10589 switch (val) {
10590 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10591 val = MF_CFG_RD(bp, func_mf_config[func].
10592 mac_upper);
10593 /* check for legal mac (upper bytes)*/
10594 if (val != 0xffff) {
10595 bp->mf_mode = MULTI_FUNCTION_SI;
10596 bp->mf_config[vn] = MF_CFG_RD(bp,
10597 func_mf_config[func].config);
10598 } else
10599 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10600 break;
10601 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10602 if ((!CHIP_IS_E1x(bp)) &&
10603 (MF_CFG_RD(bp, func_mf_config[func].
10604 mac_upper) != 0xffff) &&
10605 (SHMEM2_HAS(bp,
10606 afex_driver_support))) {
10607 bp->mf_mode = MULTI_FUNCTION_AFEX;
10608 bp->mf_config[vn] = MF_CFG_RD(bp,
10609 func_mf_config[func].config);
10610 } else {
10611 BNX2X_DEV_INFO("can not configure afex mode\n");
10612 }
10613 break;
10614 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10615 /* get OV configuration */
10616 val = MF_CFG_RD(bp,
10617 func_mf_config[FUNC_0].e1hov_tag);
10618 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10619
10620 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10621 bp->mf_mode = MULTI_FUNCTION_SD;
10622 bp->mf_config[vn] = MF_CFG_RD(bp,
10623 func_mf_config[func].config);
10624 } else
10625 BNX2X_DEV_INFO("illegal OV for SD\n");
10626 break;
10627 default:
10628 /* Unknown configuration: reset mf_config */
10629 bp->mf_config[vn] = 0;
10630 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10631 }
10632 }
10633
10634 BNX2X_DEV_INFO("%s function mode\n",
10635 IS_MF(bp) ? "multi" : "single");
10636
10637 switch (bp->mf_mode) {
10638 case MULTI_FUNCTION_SD:
10639 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10640 FUNC_MF_CFG_E1HOV_TAG_MASK;
10641 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10642 bp->mf_ov = val;
10643 bp->path_has_ovlan = true;
10644
10645 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10646 func, bp->mf_ov, bp->mf_ov);
10647 } else {
10648 dev_err(&bp->pdev->dev,
10649 "No valid MF OV for func %d, aborting\n",
10650 func);
10651 return -EPERM;
10652 }
10653 break;
10654 case MULTI_FUNCTION_AFEX:
10655 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10656 break;
10657 case MULTI_FUNCTION_SI:
10658 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10659 func);
10660 break;
10661 default:
10662 if (vn) {
10663 dev_err(&bp->pdev->dev,
10664 "VN %d is in a single function mode, aborting\n",
10665 vn);
10666 return -EPERM;
10667 }
10668 break;
10669 }
10670
10671 /* check if other port on the path needs ovlan:
10672 * Since MF configuration is shared between ports
10673 * Possible mixed modes are only
10674 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10675 */
10676 if (CHIP_MODE_IS_4_PORT(bp) &&
10677 !bp->path_has_ovlan &&
10678 !IS_MF(bp) &&
10679 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10680 u8 other_port = !BP_PORT(bp);
10681 u8 other_func = BP_PATH(bp) + 2*other_port;
10682 val = MF_CFG_RD(bp,
10683 func_mf_config[other_func].e1hov_tag);
10684 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10685 bp->path_has_ovlan = true;
10686 }
10687 }
10688
10689 /* adjust igu_sb_cnt to MF for E1x */
10690 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10691 bp->igu_sb_cnt /= E1HVN_MAX;
10692
10693 /* port info */
10694 bnx2x_get_port_hwinfo(bp);
10695
10696 /* Get MAC addresses */
10697 bnx2x_get_mac_hwinfo(bp);
10698
10699 bnx2x_get_cnic_info(bp);
10700
10701 return rc;
10702 }
10703
10704 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10705 {
10706 int cnt, i, block_end, rodi;
10707 char vpd_start[BNX2X_VPD_LEN+1];
10708 char str_id_reg[VENDOR_ID_LEN+1];
10709 char str_id_cap[VENDOR_ID_LEN+1];
10710 char *vpd_data;
10711 char *vpd_extended_data = NULL;
10712 u8 len;
10713
10714 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10715 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10716
10717 if (cnt < BNX2X_VPD_LEN)
10718 goto out_not_found;
10719
10720 /* VPD RO tag should be first tag after identifier string, hence
10721 * we should be able to find it in first BNX2X_VPD_LEN chars
10722 */
10723 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10724 PCI_VPD_LRDT_RO_DATA);
10725 if (i < 0)
10726 goto out_not_found;
10727
10728 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10729 pci_vpd_lrdt_size(&vpd_start[i]);
10730
10731 i += PCI_VPD_LRDT_TAG_SIZE;
10732
10733 if (block_end > BNX2X_VPD_LEN) {
10734 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10735 if (vpd_extended_data == NULL)
10736 goto out_not_found;
10737
10738 /* read rest of vpd image into vpd_extended_data */
10739 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10740 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10741 block_end - BNX2X_VPD_LEN,
10742 vpd_extended_data + BNX2X_VPD_LEN);
10743 if (cnt < (block_end - BNX2X_VPD_LEN))
10744 goto out_not_found;
10745 vpd_data = vpd_extended_data;
10746 } else
10747 vpd_data = vpd_start;
10748
10749 /* now vpd_data holds full vpd content in both cases */
10750
10751 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10752 PCI_VPD_RO_KEYWORD_MFR_ID);
10753 if (rodi < 0)
10754 goto out_not_found;
10755
10756 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10757
10758 if (len != VENDOR_ID_LEN)
10759 goto out_not_found;
10760
10761 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10762
10763 /* vendor specific info */
10764 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10765 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10766 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10767 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10768
10769 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10770 PCI_VPD_RO_KEYWORD_VENDOR0);
10771 if (rodi >= 0) {
10772 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10773
10774 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10775
10776 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10777 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10778 bp->fw_ver[len] = ' ';
10779 }
10780 }
10781 kfree(vpd_extended_data);
10782 return;
10783 }
10784 out_not_found:
10785 kfree(vpd_extended_data);
10786 return;
10787 }
10788
10789 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10790 {
10791 u32 flags = 0;
10792
10793 if (CHIP_REV_IS_FPGA(bp))
10794 SET_FLAGS(flags, MODE_FPGA);
10795 else if (CHIP_REV_IS_EMUL(bp))
10796 SET_FLAGS(flags, MODE_EMUL);
10797 else
10798 SET_FLAGS(flags, MODE_ASIC);
10799
10800 if (CHIP_MODE_IS_4_PORT(bp))
10801 SET_FLAGS(flags, MODE_PORT4);
10802 else
10803 SET_FLAGS(flags, MODE_PORT2);
10804
10805 if (CHIP_IS_E2(bp))
10806 SET_FLAGS(flags, MODE_E2);
10807 else if (CHIP_IS_E3(bp)) {
10808 SET_FLAGS(flags, MODE_E3);
10809 if (CHIP_REV(bp) == CHIP_REV_Ax)
10810 SET_FLAGS(flags, MODE_E3_A0);
10811 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10812 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10813 }
10814
10815 if (IS_MF(bp)) {
10816 SET_FLAGS(flags, MODE_MF);
10817 switch (bp->mf_mode) {
10818 case MULTI_FUNCTION_SD:
10819 SET_FLAGS(flags, MODE_MF_SD);
10820 break;
10821 case MULTI_FUNCTION_SI:
10822 SET_FLAGS(flags, MODE_MF_SI);
10823 break;
10824 case MULTI_FUNCTION_AFEX:
10825 SET_FLAGS(flags, MODE_MF_AFEX);
10826 break;
10827 }
10828 } else
10829 SET_FLAGS(flags, MODE_SF);
10830
10831 #if defined(__LITTLE_ENDIAN)
10832 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10833 #else /*(__BIG_ENDIAN)*/
10834 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10835 #endif
10836 INIT_MODE_FLAGS(bp) = flags;
10837 }
10838
10839 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10840 {
10841 int func;
10842 int rc;
10843
10844 mutex_init(&bp->port.phy_mutex);
10845 mutex_init(&bp->fw_mb_mutex);
10846 spin_lock_init(&bp->stats_lock);
10847 #ifdef BCM_CNIC
10848 mutex_init(&bp->cnic_mutex);
10849 #endif
10850
10851 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10852 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10853 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10854 rc = bnx2x_get_hwinfo(bp);
10855 if (rc)
10856 return rc;
10857
10858 bnx2x_set_modes_bitmap(bp);
10859
10860 rc = bnx2x_alloc_mem_bp(bp);
10861 if (rc)
10862 return rc;
10863
10864 bnx2x_read_fwinfo(bp);
10865
10866 func = BP_FUNC(bp);
10867
10868 /* need to reset chip if undi was active */
10869 if (!BP_NOMCP(bp)) {
10870 /* init fw_seq */
10871 bp->fw_seq =
10872 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10873 DRV_MSG_SEQ_NUMBER_MASK;
10874 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10875
10876 bnx2x_prev_unload(bp);
10877 }
10878
10879
10880 if (CHIP_REV_IS_FPGA(bp))
10881 dev_err(&bp->pdev->dev, "FPGA detected\n");
10882
10883 if (BP_NOMCP(bp) && (func == 0))
10884 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10885
10886 bp->disable_tpa = disable_tpa;
10887
10888 #ifdef BCM_CNIC
10889 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10890 #endif
10891
10892 /* Set TPA flags */
10893 if (bp->disable_tpa) {
10894 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10895 bp->dev->features &= ~NETIF_F_LRO;
10896 } else {
10897 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10898 bp->dev->features |= NETIF_F_LRO;
10899 }
10900
10901 if (CHIP_IS_E1(bp))
10902 bp->dropless_fc = 0;
10903 else
10904 bp->dropless_fc = dropless_fc;
10905
10906 bp->mrrs = mrrs;
10907
10908 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10909
10910 /* make sure that the numbers are in the right granularity */
10911 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10912 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10913
10914 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10915
10916 init_timer(&bp->timer);
10917 bp->timer.expires = jiffies + bp->current_interval;
10918 bp->timer.data = (unsigned long) bp;
10919 bp->timer.function = bnx2x_timer;
10920
10921 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10922 bnx2x_dcbx_init_params(bp);
10923
10924 #ifdef BCM_CNIC
10925 if (CHIP_IS_E1x(bp))
10926 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10927 else
10928 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10929 #endif
10930
10931 /* multiple tx priority */
10932 if (CHIP_IS_E1x(bp))
10933 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10934 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10935 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10936 if (CHIP_IS_E3B0(bp))
10937 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10938
10939 return rc;
10940 }
10941
10942
10943 /****************************************************************************
10944 * General service functions
10945 ****************************************************************************/
10946
10947 /*
10948 * net_device service functions
10949 */
10950
10951 /* called with rtnl_lock */
10952 static int bnx2x_open(struct net_device *dev)
10953 {
10954 struct bnx2x *bp = netdev_priv(dev);
10955 bool global = false;
10956 int other_engine = BP_PATH(bp) ? 0 : 1;
10957 bool other_load_status, load_status;
10958
10959 bp->stats_init = true;
10960
10961 netif_carrier_off(dev);
10962
10963 bnx2x_set_power_state(bp, PCI_D0);
10964
10965 other_load_status = bnx2x_get_load_status(bp, other_engine);
10966 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10967
10968 /*
10969 * If parity had happen during the unload, then attentions
10970 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10971 * want the first function loaded on the current engine to
10972 * complete the recovery.
10973 */
10974 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10975 bnx2x_chk_parity_attn(bp, &global, true))
10976 do {
10977 /*
10978 * If there are attentions and they are in a global
10979 * blocks, set the GLOBAL_RESET bit regardless whether
10980 * it will be this function that will complete the
10981 * recovery or not.
10982 */
10983 if (global)
10984 bnx2x_set_reset_global(bp);
10985
10986 /*
10987 * Only the first function on the current engine should
10988 * try to recover in open. In case of attentions in
10989 * global blocks only the first in the chip should try
10990 * to recover.
10991 */
10992 if ((!load_status &&
10993 (!global || !other_load_status)) &&
10994 bnx2x_trylock_leader_lock(bp) &&
10995 !bnx2x_leader_reset(bp)) {
10996 netdev_info(bp->dev, "Recovered in open\n");
10997 break;
10998 }
10999
11000 /* recovery has failed... */
11001 bnx2x_set_power_state(bp, PCI_D3hot);
11002 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11003
11004 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11005 "If you still see this message after a few retries then power cycle is required.\n");
11006
11007 return -EAGAIN;
11008 } while (0);
11009
11010 bp->recovery_state = BNX2X_RECOVERY_DONE;
11011 return bnx2x_nic_load(bp, LOAD_OPEN);
11012 }
11013
11014 /* called with rtnl_lock */
11015 static int bnx2x_close(struct net_device *dev)
11016 {
11017 struct bnx2x *bp = netdev_priv(dev);
11018
11019 /* Unload the driver, release IRQs */
11020 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
11021
11022 /* Power off */
11023 bnx2x_set_power_state(bp, PCI_D3hot);
11024
11025 return 0;
11026 }
11027
11028 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11029 struct bnx2x_mcast_ramrod_params *p)
11030 {
11031 int mc_count = netdev_mc_count(bp->dev);
11032 struct bnx2x_mcast_list_elem *mc_mac =
11033 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11034 struct netdev_hw_addr *ha;
11035
11036 if (!mc_mac)
11037 return -ENOMEM;
11038
11039 INIT_LIST_HEAD(&p->mcast_list);
11040
11041 netdev_for_each_mc_addr(ha, bp->dev) {
11042 mc_mac->mac = bnx2x_mc_addr(ha);
11043 list_add_tail(&mc_mac->link, &p->mcast_list);
11044 mc_mac++;
11045 }
11046
11047 p->mcast_list_len = mc_count;
11048
11049 return 0;
11050 }
11051
11052 static void bnx2x_free_mcast_macs_list(
11053 struct bnx2x_mcast_ramrod_params *p)
11054 {
11055 struct bnx2x_mcast_list_elem *mc_mac =
11056 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11057 link);
11058
11059 WARN_ON(!mc_mac);
11060 kfree(mc_mac);
11061 }
11062
11063 /**
11064 * bnx2x_set_uc_list - configure a new unicast MACs list.
11065 *
11066 * @bp: driver handle
11067 *
11068 * We will use zero (0) as a MAC type for these MACs.
11069 */
11070 static int bnx2x_set_uc_list(struct bnx2x *bp)
11071 {
11072 int rc;
11073 struct net_device *dev = bp->dev;
11074 struct netdev_hw_addr *ha;
11075 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11076 unsigned long ramrod_flags = 0;
11077
11078 /* First schedule a cleanup up of old configuration */
11079 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11080 if (rc < 0) {
11081 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11082 return rc;
11083 }
11084
11085 netdev_for_each_uc_addr(ha, dev) {
11086 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11087 BNX2X_UC_LIST_MAC, &ramrod_flags);
11088 if (rc < 0) {
11089 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11090 rc);
11091 return rc;
11092 }
11093 }
11094
11095 /* Execute the pending commands */
11096 __set_bit(RAMROD_CONT, &ramrod_flags);
11097 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11098 BNX2X_UC_LIST_MAC, &ramrod_flags);
11099 }
11100
11101 static int bnx2x_set_mc_list(struct bnx2x *bp)
11102 {
11103 struct net_device *dev = bp->dev;
11104 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11105 int rc = 0;
11106
11107 rparam.mcast_obj = &bp->mcast_obj;
11108
11109 /* first, clear all configured multicast MACs */
11110 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11111 if (rc < 0) {
11112 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11113 return rc;
11114 }
11115
11116 /* then, configure a new MACs list */
11117 if (netdev_mc_count(dev)) {
11118 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11119 if (rc) {
11120 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11121 rc);
11122 return rc;
11123 }
11124
11125 /* Now add the new MACs */
11126 rc = bnx2x_config_mcast(bp, &rparam,
11127 BNX2X_MCAST_CMD_ADD);
11128 if (rc < 0)
11129 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11130 rc);
11131
11132 bnx2x_free_mcast_macs_list(&rparam);
11133 }
11134
11135 return rc;
11136 }
11137
11138
11139 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11140 void bnx2x_set_rx_mode(struct net_device *dev)
11141 {
11142 struct bnx2x *bp = netdev_priv(dev);
11143 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11144
11145 if (bp->state != BNX2X_STATE_OPEN) {
11146 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11147 return;
11148 }
11149
11150 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11151
11152 if (dev->flags & IFF_PROMISC)
11153 rx_mode = BNX2X_RX_MODE_PROMISC;
11154 else if ((dev->flags & IFF_ALLMULTI) ||
11155 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11156 CHIP_IS_E1(bp)))
11157 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11158 else {
11159 /* some multicasts */
11160 if (bnx2x_set_mc_list(bp) < 0)
11161 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11162
11163 if (bnx2x_set_uc_list(bp) < 0)
11164 rx_mode = BNX2X_RX_MODE_PROMISC;
11165 }
11166
11167 bp->rx_mode = rx_mode;
11168 #ifdef BCM_CNIC
11169 /* handle ISCSI SD mode */
11170 if (IS_MF_ISCSI_SD(bp))
11171 bp->rx_mode = BNX2X_RX_MODE_NONE;
11172 #endif
11173
11174 /* Schedule the rx_mode command */
11175 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11176 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11177 return;
11178 }
11179
11180 bnx2x_set_storm_rx_mode(bp);
11181 }
11182
11183 /* called with rtnl_lock */
11184 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11185 int devad, u16 addr)
11186 {
11187 struct bnx2x *bp = netdev_priv(netdev);
11188 u16 value;
11189 int rc;
11190
11191 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11192 prtad, devad, addr);
11193
11194 /* The HW expects different devad if CL22 is used */
11195 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11196
11197 bnx2x_acquire_phy_lock(bp);
11198 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11199 bnx2x_release_phy_lock(bp);
11200 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11201
11202 if (!rc)
11203 rc = value;
11204 return rc;
11205 }
11206
11207 /* called with rtnl_lock */
11208 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11209 u16 addr, u16 value)
11210 {
11211 struct bnx2x *bp = netdev_priv(netdev);
11212 int rc;
11213
11214 DP(NETIF_MSG_LINK,
11215 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11216 prtad, devad, addr, value);
11217
11218 /* The HW expects different devad if CL22 is used */
11219 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11220
11221 bnx2x_acquire_phy_lock(bp);
11222 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11223 bnx2x_release_phy_lock(bp);
11224 return rc;
11225 }
11226
11227 /* called with rtnl_lock */
11228 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11229 {
11230 struct bnx2x *bp = netdev_priv(dev);
11231 struct mii_ioctl_data *mdio = if_mii(ifr);
11232
11233 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11234 mdio->phy_id, mdio->reg_num, mdio->val_in);
11235
11236 if (!netif_running(dev))
11237 return -EAGAIN;
11238
11239 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11240 }
11241
11242 #ifdef CONFIG_NET_POLL_CONTROLLER
11243 static void poll_bnx2x(struct net_device *dev)
11244 {
11245 struct bnx2x *bp = netdev_priv(dev);
11246
11247 disable_irq(bp->pdev->irq);
11248 bnx2x_interrupt(bp->pdev->irq, dev);
11249 enable_irq(bp->pdev->irq);
11250 }
11251 #endif
11252
11253 static int bnx2x_validate_addr(struct net_device *dev)
11254 {
11255 struct bnx2x *bp = netdev_priv(dev);
11256
11257 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11258 BNX2X_ERR("Non-valid Ethernet address\n");
11259 return -EADDRNOTAVAIL;
11260 }
11261 return 0;
11262 }
11263
11264 static const struct net_device_ops bnx2x_netdev_ops = {
11265 .ndo_open = bnx2x_open,
11266 .ndo_stop = bnx2x_close,
11267 .ndo_start_xmit = bnx2x_start_xmit,
11268 .ndo_select_queue = bnx2x_select_queue,
11269 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11270 .ndo_set_mac_address = bnx2x_change_mac_addr,
11271 .ndo_validate_addr = bnx2x_validate_addr,
11272 .ndo_do_ioctl = bnx2x_ioctl,
11273 .ndo_change_mtu = bnx2x_change_mtu,
11274 .ndo_fix_features = bnx2x_fix_features,
11275 .ndo_set_features = bnx2x_set_features,
11276 .ndo_tx_timeout = bnx2x_tx_timeout,
11277 #ifdef CONFIG_NET_POLL_CONTROLLER
11278 .ndo_poll_controller = poll_bnx2x,
11279 #endif
11280 .ndo_setup_tc = bnx2x_setup_tc,
11281
11282 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11283 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11284 #endif
11285 };
11286
11287 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11288 {
11289 struct device *dev = &bp->pdev->dev;
11290
11291 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11292 bp->flags |= USING_DAC_FLAG;
11293 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11294 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11295 return -EIO;
11296 }
11297 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11298 dev_err(dev, "System does not support DMA, aborting\n");
11299 return -EIO;
11300 }
11301
11302 return 0;
11303 }
11304
11305 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11306 struct net_device *dev,
11307 unsigned long board_type)
11308 {
11309 struct bnx2x *bp;
11310 int rc;
11311 u32 pci_cfg_dword;
11312 bool chip_is_e1x = (board_type == BCM57710 ||
11313 board_type == BCM57711 ||
11314 board_type == BCM57711E);
11315
11316 SET_NETDEV_DEV(dev, &pdev->dev);
11317 bp = netdev_priv(dev);
11318
11319 bp->dev = dev;
11320 bp->pdev = pdev;
11321 bp->flags = 0;
11322
11323 rc = pci_enable_device(pdev);
11324 if (rc) {
11325 dev_err(&bp->pdev->dev,
11326 "Cannot enable PCI device, aborting\n");
11327 goto err_out;
11328 }
11329
11330 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11331 dev_err(&bp->pdev->dev,
11332 "Cannot find PCI device base address, aborting\n");
11333 rc = -ENODEV;
11334 goto err_out_disable;
11335 }
11336
11337 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11338 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11339 " base address, aborting\n");
11340 rc = -ENODEV;
11341 goto err_out_disable;
11342 }
11343
11344 if (atomic_read(&pdev->enable_cnt) == 1) {
11345 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11346 if (rc) {
11347 dev_err(&bp->pdev->dev,
11348 "Cannot obtain PCI resources, aborting\n");
11349 goto err_out_disable;
11350 }
11351
11352 pci_set_master(pdev);
11353 pci_save_state(pdev);
11354 }
11355
11356 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11357 if (bp->pm_cap == 0) {
11358 dev_err(&bp->pdev->dev,
11359 "Cannot find power management capability, aborting\n");
11360 rc = -EIO;
11361 goto err_out_release;
11362 }
11363
11364 if (!pci_is_pcie(pdev)) {
11365 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11366 rc = -EIO;
11367 goto err_out_release;
11368 }
11369
11370 rc = bnx2x_set_coherency_mask(bp);
11371 if (rc)
11372 goto err_out_release;
11373
11374 dev->mem_start = pci_resource_start(pdev, 0);
11375 dev->base_addr = dev->mem_start;
11376 dev->mem_end = pci_resource_end(pdev, 0);
11377
11378 dev->irq = pdev->irq;
11379
11380 bp->regview = pci_ioremap_bar(pdev, 0);
11381 if (!bp->regview) {
11382 dev_err(&bp->pdev->dev,
11383 "Cannot map register space, aborting\n");
11384 rc = -ENOMEM;
11385 goto err_out_release;
11386 }
11387
11388 /* In E1/E1H use pci device function given by kernel.
11389 * In E2/E3 read physical function from ME register since these chips
11390 * support Physical Device Assignment where kernel BDF maybe arbitrary
11391 * (depending on hypervisor).
11392 */
11393 if (chip_is_e1x)
11394 bp->pf_num = PCI_FUNC(pdev->devfn);
11395 else {/* chip is E2/3*/
11396 pci_read_config_dword(bp->pdev,
11397 PCICFG_ME_REGISTER, &pci_cfg_dword);
11398 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11399 ME_REG_ABS_PF_NUM_SHIFT);
11400 }
11401 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11402
11403 bnx2x_set_power_state(bp, PCI_D0);
11404
11405 /* clean indirect addresses */
11406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11407 PCICFG_VENDOR_ID_OFFSET);
11408 /*
11409 * Clean the following indirect addresses for all functions since it
11410 * is not used by the driver.
11411 */
11412 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11413 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11414 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11415 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11416
11417 if (chip_is_e1x) {
11418 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11419 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11420 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11421 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11422 }
11423
11424 /*
11425 * Enable internal target-read (in case we are probed after PF FLR).
11426 * Must be done prior to any BAR read access. Only for 57712 and up
11427 */
11428 if (!chip_is_e1x)
11429 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11430
11431 /* Reset the load counter */
11432 bnx2x_clear_load_status(bp);
11433
11434 dev->watchdog_timeo = TX_TIMEOUT;
11435
11436 dev->netdev_ops = &bnx2x_netdev_ops;
11437 bnx2x_set_ethtool_ops(dev);
11438
11439 dev->priv_flags |= IFF_UNICAST_FLT;
11440
11441 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11442 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11443 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11444 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11445
11446 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11447 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11448
11449 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11450 if (bp->flags & USING_DAC_FLAG)
11451 dev->features |= NETIF_F_HIGHDMA;
11452
11453 /* Add Loopback capability to the device */
11454 dev->hw_features |= NETIF_F_LOOPBACK;
11455
11456 #ifdef BCM_DCBNL
11457 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11458 #endif
11459
11460 /* get_port_hwinfo() will set prtad and mmds properly */
11461 bp->mdio.prtad = MDIO_PRTAD_NONE;
11462 bp->mdio.mmds = 0;
11463 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11464 bp->mdio.dev = dev;
11465 bp->mdio.mdio_read = bnx2x_mdio_read;
11466 bp->mdio.mdio_write = bnx2x_mdio_write;
11467
11468 return 0;
11469
11470 err_out_release:
11471 if (atomic_read(&pdev->enable_cnt) == 1)
11472 pci_release_regions(pdev);
11473
11474 err_out_disable:
11475 pci_disable_device(pdev);
11476 pci_set_drvdata(pdev, NULL);
11477
11478 err_out:
11479 return rc;
11480 }
11481
11482 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11483 int *width, int *speed)
11484 {
11485 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11486
11487 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11488
11489 /* return value of 1=2.5GHz 2=5GHz */
11490 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11491 }
11492
11493 static int bnx2x_check_firmware(struct bnx2x *bp)
11494 {
11495 const struct firmware *firmware = bp->firmware;
11496 struct bnx2x_fw_file_hdr *fw_hdr;
11497 struct bnx2x_fw_file_section *sections;
11498 u32 offset, len, num_ops;
11499 u16 *ops_offsets;
11500 int i;
11501 const u8 *fw_ver;
11502
11503 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11504 BNX2X_ERR("Wrong FW size\n");
11505 return -EINVAL;
11506 }
11507
11508 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11509 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11510
11511 /* Make sure none of the offsets and sizes make us read beyond
11512 * the end of the firmware data */
11513 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11514 offset = be32_to_cpu(sections[i].offset);
11515 len = be32_to_cpu(sections[i].len);
11516 if (offset + len > firmware->size) {
11517 BNX2X_ERR("Section %d length is out of bounds\n", i);
11518 return -EINVAL;
11519 }
11520 }
11521
11522 /* Likewise for the init_ops offsets */
11523 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11524 ops_offsets = (u16 *)(firmware->data + offset);
11525 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11526
11527 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11528 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11529 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11530 return -EINVAL;
11531 }
11532 }
11533
11534 /* Check FW version */
11535 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11536 fw_ver = firmware->data + offset;
11537 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11538 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11539 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11540 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11541 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11542 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11543 BCM_5710_FW_MAJOR_VERSION,
11544 BCM_5710_FW_MINOR_VERSION,
11545 BCM_5710_FW_REVISION_VERSION,
11546 BCM_5710_FW_ENGINEERING_VERSION);
11547 return -EINVAL;
11548 }
11549
11550 return 0;
11551 }
11552
11553 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11554 {
11555 const __be32 *source = (const __be32 *)_source;
11556 u32 *target = (u32 *)_target;
11557 u32 i;
11558
11559 for (i = 0; i < n/4; i++)
11560 target[i] = be32_to_cpu(source[i]);
11561 }
11562
11563 /*
11564 Ops array is stored in the following format:
11565 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11566 */
11567 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11568 {
11569 const __be32 *source = (const __be32 *)_source;
11570 struct raw_op *target = (struct raw_op *)_target;
11571 u32 i, j, tmp;
11572
11573 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11574 tmp = be32_to_cpu(source[j]);
11575 target[i].op = (tmp >> 24) & 0xff;
11576 target[i].offset = tmp & 0xffffff;
11577 target[i].raw_data = be32_to_cpu(source[j + 1]);
11578 }
11579 }
11580
11581 /* IRO array is stored in the following format:
11582 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11583 */
11584 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11585 {
11586 const __be32 *source = (const __be32 *)_source;
11587 struct iro *target = (struct iro *)_target;
11588 u32 i, j, tmp;
11589
11590 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11591 target[i].base = be32_to_cpu(source[j]);
11592 j++;
11593 tmp = be32_to_cpu(source[j]);
11594 target[i].m1 = (tmp >> 16) & 0xffff;
11595 target[i].m2 = tmp & 0xffff;
11596 j++;
11597 tmp = be32_to_cpu(source[j]);
11598 target[i].m3 = (tmp >> 16) & 0xffff;
11599 target[i].size = tmp & 0xffff;
11600 j++;
11601 }
11602 }
11603
11604 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11605 {
11606 const __be16 *source = (const __be16 *)_source;
11607 u16 *target = (u16 *)_target;
11608 u32 i;
11609
11610 for (i = 0; i < n/2; i++)
11611 target[i] = be16_to_cpu(source[i]);
11612 }
11613
11614 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11615 do { \
11616 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11617 bp->arr = kmalloc(len, GFP_KERNEL); \
11618 if (!bp->arr) \
11619 goto lbl; \
11620 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11621 (u8 *)bp->arr, len); \
11622 } while (0)
11623
11624 static int bnx2x_init_firmware(struct bnx2x *bp)
11625 {
11626 const char *fw_file_name;
11627 struct bnx2x_fw_file_hdr *fw_hdr;
11628 int rc;
11629
11630 if (bp->firmware)
11631 return 0;
11632
11633 if (CHIP_IS_E1(bp))
11634 fw_file_name = FW_FILE_NAME_E1;
11635 else if (CHIP_IS_E1H(bp))
11636 fw_file_name = FW_FILE_NAME_E1H;
11637 else if (!CHIP_IS_E1x(bp))
11638 fw_file_name = FW_FILE_NAME_E2;
11639 else {
11640 BNX2X_ERR("Unsupported chip revision\n");
11641 return -EINVAL;
11642 }
11643 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11644
11645 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11646 if (rc) {
11647 BNX2X_ERR("Can't load firmware file %s\n",
11648 fw_file_name);
11649 goto request_firmware_exit;
11650 }
11651
11652 rc = bnx2x_check_firmware(bp);
11653 if (rc) {
11654 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11655 goto request_firmware_exit;
11656 }
11657
11658 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11659
11660 /* Initialize the pointers to the init arrays */
11661 /* Blob */
11662 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11663
11664 /* Opcodes */
11665 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11666
11667 /* Offsets */
11668 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11669 be16_to_cpu_n);
11670
11671 /* STORMs firmware */
11672 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11673 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11674 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11675 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11676 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11677 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11678 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11679 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11680 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11681 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11682 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11683 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11684 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11685 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11686 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11687 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11688 /* IRO */
11689 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11690
11691 return 0;
11692
11693 iro_alloc_err:
11694 kfree(bp->init_ops_offsets);
11695 init_offsets_alloc_err:
11696 kfree(bp->init_ops);
11697 init_ops_alloc_err:
11698 kfree(bp->init_data);
11699 request_firmware_exit:
11700 release_firmware(bp->firmware);
11701 bp->firmware = NULL;
11702
11703 return rc;
11704 }
11705
11706 static void bnx2x_release_firmware(struct bnx2x *bp)
11707 {
11708 kfree(bp->init_ops_offsets);
11709 kfree(bp->init_ops);
11710 kfree(bp->init_data);
11711 release_firmware(bp->firmware);
11712 bp->firmware = NULL;
11713 }
11714
11715
11716 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11717 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11718 .init_hw_cmn = bnx2x_init_hw_common,
11719 .init_hw_port = bnx2x_init_hw_port,
11720 .init_hw_func = bnx2x_init_hw_func,
11721
11722 .reset_hw_cmn = bnx2x_reset_common,
11723 .reset_hw_port = bnx2x_reset_port,
11724 .reset_hw_func = bnx2x_reset_func,
11725
11726 .gunzip_init = bnx2x_gunzip_init,
11727 .gunzip_end = bnx2x_gunzip_end,
11728
11729 .init_fw = bnx2x_init_firmware,
11730 .release_fw = bnx2x_release_firmware,
11731 };
11732
11733 void bnx2x__init_func_obj(struct bnx2x *bp)
11734 {
11735 /* Prepare DMAE related driver resources */
11736 bnx2x_setup_dmae(bp);
11737
11738 bnx2x_init_func_obj(bp, &bp->func_obj,
11739 bnx2x_sp(bp, func_rdata),
11740 bnx2x_sp_mapping(bp, func_rdata),
11741 bnx2x_sp(bp, func_afex_rdata),
11742 bnx2x_sp_mapping(bp, func_afex_rdata),
11743 &bnx2x_func_sp_drv);
11744 }
11745
11746 /* must be called after sriov-enable */
11747 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11748 {
11749 int cid_count = BNX2X_L2_MAX_CID(bp);
11750
11751 #ifdef BCM_CNIC
11752 cid_count += CNIC_CID_MAX;
11753 #endif
11754 return roundup(cid_count, QM_CID_ROUND);
11755 }
11756
11757 /**
11758 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11759 *
11760 * @dev: pci device
11761 *
11762 */
11763 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11764 {
11765 int pos;
11766 u16 control;
11767
11768 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11769
11770 /*
11771 * If MSI-X is not supported - return number of SBs needed to support
11772 * one fast path queue: one FP queue + SB for CNIC
11773 */
11774 if (!pos)
11775 return 1 + CNIC_PRESENT;
11776
11777 /*
11778 * The value in the PCI configuration space is the index of the last
11779 * entry, namely one less than the actual size of the table, which is
11780 * exactly what we want to return from this function: number of all SBs
11781 * without the default SB.
11782 */
11783 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11784 return control & PCI_MSIX_FLAGS_QSIZE;
11785 }
11786
11787 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11788 const struct pci_device_id *ent)
11789 {
11790 struct net_device *dev = NULL;
11791 struct bnx2x *bp;
11792 int pcie_width, pcie_speed;
11793 int rc, max_non_def_sbs;
11794 int rx_count, tx_count, rss_count, doorbell_size;
11795 /*
11796 * An estimated maximum supported CoS number according to the chip
11797 * version.
11798 * We will try to roughly estimate the maximum number of CoSes this chip
11799 * may support in order to minimize the memory allocated for Tx
11800 * netdev_queue's. This number will be accurately calculated during the
11801 * initialization of bp->max_cos based on the chip versions AND chip
11802 * revision in the bnx2x_init_bp().
11803 */
11804 u8 max_cos_est = 0;
11805
11806 switch (ent->driver_data) {
11807 case BCM57710:
11808 case BCM57711:
11809 case BCM57711E:
11810 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11811 break;
11812
11813 case BCM57712:
11814 case BCM57712_MF:
11815 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11816 break;
11817
11818 case BCM57800:
11819 case BCM57800_MF:
11820 case BCM57810:
11821 case BCM57810_MF:
11822 case BCM57840_O:
11823 case BCM57840_4_10:
11824 case BCM57840_2_20:
11825 case BCM57840_MFO:
11826 case BCM57840_MF:
11827 case BCM57811:
11828 case BCM57811_MF:
11829 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11830 break;
11831
11832 default:
11833 pr_err("Unknown board_type (%ld), aborting\n",
11834 ent->driver_data);
11835 return -ENODEV;
11836 }
11837
11838 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11839
11840 WARN_ON(!max_non_def_sbs);
11841
11842 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11843 rss_count = max_non_def_sbs - CNIC_PRESENT;
11844
11845 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11846 rx_count = rss_count + FCOE_PRESENT;
11847
11848 /*
11849 * Maximum number of netdev Tx queues:
11850 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11851 */
11852 tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11853
11854 /* dev zeroed in init_etherdev */
11855 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11856 if (!dev)
11857 return -ENOMEM;
11858
11859 bp = netdev_priv(dev);
11860
11861 bp->igu_sb_cnt = max_non_def_sbs;
11862 bp->msg_enable = debug;
11863 pci_set_drvdata(pdev, dev);
11864
11865 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11866 if (rc < 0) {
11867 free_netdev(dev);
11868 return rc;
11869 }
11870
11871 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11872
11873 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11874 tx_count, rx_count);
11875
11876 rc = bnx2x_init_bp(bp);
11877 if (rc)
11878 goto init_one_exit;
11879
11880 /*
11881 * Map doorbels here as we need the real value of bp->max_cos which
11882 * is initialized in bnx2x_init_bp().
11883 */
11884 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11885 if (doorbell_size > pci_resource_len(pdev, 2)) {
11886 dev_err(&bp->pdev->dev,
11887 "Cannot map doorbells, bar size too small, aborting\n");
11888 rc = -ENOMEM;
11889 goto init_one_exit;
11890 }
11891 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11892 doorbell_size);
11893 if (!bp->doorbells) {
11894 dev_err(&bp->pdev->dev,
11895 "Cannot map doorbell space, aborting\n");
11896 rc = -ENOMEM;
11897 goto init_one_exit;
11898 }
11899
11900 /* calc qm_cid_count */
11901 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11902
11903 #ifdef BCM_CNIC
11904 /* disable FCOE L2 queue for E1x */
11905 if (CHIP_IS_E1x(bp))
11906 bp->flags |= NO_FCOE_FLAG;
11907
11908 #endif
11909
11910
11911 /* Set bp->num_queues for MSI-X mode*/
11912 bnx2x_set_num_queues(bp);
11913
11914 /* Configure interrupt mode: try to enable MSI-X/MSI if
11915 * needed.
11916 */
11917 bnx2x_set_int_mode(bp);
11918
11919 /* Add all NAPI objects */
11920 bnx2x_add_all_napi(bp);
11921
11922 rc = register_netdev(dev);
11923 if (rc) {
11924 dev_err(&pdev->dev, "Cannot register net device\n");
11925 goto init_one_exit;
11926 }
11927
11928 #ifdef BCM_CNIC
11929 if (!NO_FCOE(bp)) {
11930 /* Add storage MAC address */
11931 rtnl_lock();
11932 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11933 rtnl_unlock();
11934 }
11935 #endif
11936
11937 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11938
11939 BNX2X_DEV_INFO(
11940 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11941 board_info[ent->driver_data].name,
11942 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11943 pcie_width,
11944 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11945 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11946 "5GHz (Gen2)" : "2.5GHz",
11947 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11948
11949 return 0;
11950
11951 init_one_exit:
11952 if (bp->regview)
11953 iounmap(bp->regview);
11954
11955 if (bp->doorbells)
11956 iounmap(bp->doorbells);
11957
11958 free_netdev(dev);
11959
11960 if (atomic_read(&pdev->enable_cnt) == 1)
11961 pci_release_regions(pdev);
11962
11963 pci_disable_device(pdev);
11964 pci_set_drvdata(pdev, NULL);
11965
11966 return rc;
11967 }
11968
11969 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11970 {
11971 struct net_device *dev = pci_get_drvdata(pdev);
11972 struct bnx2x *bp;
11973
11974 if (!dev) {
11975 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11976 return;
11977 }
11978 bp = netdev_priv(dev);
11979
11980 #ifdef BCM_CNIC
11981 /* Delete storage MAC address */
11982 if (!NO_FCOE(bp)) {
11983 rtnl_lock();
11984 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11985 rtnl_unlock();
11986 }
11987 #endif
11988
11989 #ifdef BCM_DCBNL
11990 /* Delete app tlvs from dcbnl */
11991 bnx2x_dcbnl_update_applist(bp, true);
11992 #endif
11993
11994 unregister_netdev(dev);
11995
11996 /* Delete all NAPI objects */
11997 bnx2x_del_all_napi(bp);
11998
11999 /* Power on: we can't let PCI layer write to us while we are in D3 */
12000 bnx2x_set_power_state(bp, PCI_D0);
12001
12002 /* Disable MSI/MSI-X */
12003 bnx2x_disable_msi(bp);
12004
12005 /* Power off */
12006 bnx2x_set_power_state(bp, PCI_D3hot);
12007
12008 /* Make sure RESET task is not scheduled before continuing */
12009 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12010
12011 if (bp->regview)
12012 iounmap(bp->regview);
12013
12014 if (bp->doorbells)
12015 iounmap(bp->doorbells);
12016
12017 bnx2x_release_firmware(bp);
12018
12019 bnx2x_free_mem_bp(bp);
12020
12021 free_netdev(dev);
12022
12023 if (atomic_read(&pdev->enable_cnt) == 1)
12024 pci_release_regions(pdev);
12025
12026 pci_disable_device(pdev);
12027 pci_set_drvdata(pdev, NULL);
12028 }
12029
12030 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12031 {
12032 int i;
12033
12034 bp->state = BNX2X_STATE_ERROR;
12035
12036 bp->rx_mode = BNX2X_RX_MODE_NONE;
12037
12038 #ifdef BCM_CNIC
12039 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12040 #endif
12041 /* Stop Tx */
12042 bnx2x_tx_disable(bp);
12043
12044 bnx2x_netif_stop(bp, 0);
12045
12046 del_timer_sync(&bp->timer);
12047
12048 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12049
12050 /* Release IRQs */
12051 bnx2x_free_irq(bp);
12052
12053 /* Free SKBs, SGEs, TPA pool and driver internals */
12054 bnx2x_free_skbs(bp);
12055
12056 for_each_rx_queue(bp, i)
12057 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12058
12059 bnx2x_free_mem(bp);
12060
12061 bp->state = BNX2X_STATE_CLOSED;
12062
12063 netif_carrier_off(bp->dev);
12064
12065 return 0;
12066 }
12067
12068 static void bnx2x_eeh_recover(struct bnx2x *bp)
12069 {
12070 u32 val;
12071
12072 mutex_init(&bp->port.phy_mutex);
12073
12074
12075 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12076 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12077 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12078 BNX2X_ERR("BAD MCP validity signature\n");
12079 }
12080
12081 /**
12082 * bnx2x_io_error_detected - called when PCI error is detected
12083 * @pdev: Pointer to PCI device
12084 * @state: The current pci connection state
12085 *
12086 * This function is called after a PCI bus error affecting
12087 * this device has been detected.
12088 */
12089 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12090 pci_channel_state_t state)
12091 {
12092 struct net_device *dev = pci_get_drvdata(pdev);
12093 struct bnx2x *bp = netdev_priv(dev);
12094
12095 rtnl_lock();
12096
12097 netif_device_detach(dev);
12098
12099 if (state == pci_channel_io_perm_failure) {
12100 rtnl_unlock();
12101 return PCI_ERS_RESULT_DISCONNECT;
12102 }
12103
12104 if (netif_running(dev))
12105 bnx2x_eeh_nic_unload(bp);
12106
12107 pci_disable_device(pdev);
12108
12109 rtnl_unlock();
12110
12111 /* Request a slot reset */
12112 return PCI_ERS_RESULT_NEED_RESET;
12113 }
12114
12115 /**
12116 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12117 * @pdev: Pointer to PCI device
12118 *
12119 * Restart the card from scratch, as if from a cold-boot.
12120 */
12121 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12122 {
12123 struct net_device *dev = pci_get_drvdata(pdev);
12124 struct bnx2x *bp = netdev_priv(dev);
12125
12126 rtnl_lock();
12127
12128 if (pci_enable_device(pdev)) {
12129 dev_err(&pdev->dev,
12130 "Cannot re-enable PCI device after reset\n");
12131 rtnl_unlock();
12132 return PCI_ERS_RESULT_DISCONNECT;
12133 }
12134
12135 pci_set_master(pdev);
12136 pci_restore_state(pdev);
12137
12138 if (netif_running(dev))
12139 bnx2x_set_power_state(bp, PCI_D0);
12140
12141 rtnl_unlock();
12142
12143 return PCI_ERS_RESULT_RECOVERED;
12144 }
12145
12146 /**
12147 * bnx2x_io_resume - called when traffic can start flowing again
12148 * @pdev: Pointer to PCI device
12149 *
12150 * This callback is called when the error recovery driver tells us that
12151 * its OK to resume normal operation.
12152 */
12153 static void bnx2x_io_resume(struct pci_dev *pdev)
12154 {
12155 struct net_device *dev = pci_get_drvdata(pdev);
12156 struct bnx2x *bp = netdev_priv(dev);
12157
12158 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12159 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12160 return;
12161 }
12162
12163 rtnl_lock();
12164
12165 bnx2x_eeh_recover(bp);
12166
12167 if (netif_running(dev))
12168 bnx2x_nic_load(bp, LOAD_NORMAL);
12169
12170 netif_device_attach(dev);
12171
12172 rtnl_unlock();
12173 }
12174
12175 static struct pci_error_handlers bnx2x_err_handler = {
12176 .error_detected = bnx2x_io_error_detected,
12177 .slot_reset = bnx2x_io_slot_reset,
12178 .resume = bnx2x_io_resume,
12179 };
12180
12181 static struct pci_driver bnx2x_pci_driver = {
12182 .name = DRV_MODULE_NAME,
12183 .id_table = bnx2x_pci_tbl,
12184 .probe = bnx2x_init_one,
12185 .remove = __devexit_p(bnx2x_remove_one),
12186 .suspend = bnx2x_suspend,
12187 .resume = bnx2x_resume,
12188 .err_handler = &bnx2x_err_handler,
12189 };
12190
12191 static int __init bnx2x_init(void)
12192 {
12193 int ret;
12194
12195 pr_info("%s", version);
12196
12197 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12198 if (bnx2x_wq == NULL) {
12199 pr_err("Cannot create workqueue\n");
12200 return -ENOMEM;
12201 }
12202
12203 ret = pci_register_driver(&bnx2x_pci_driver);
12204 if (ret) {
12205 pr_err("Cannot register driver\n");
12206 destroy_workqueue(bnx2x_wq);
12207 }
12208 return ret;
12209 }
12210
12211 static void __exit bnx2x_cleanup(void)
12212 {
12213 struct list_head *pos, *q;
12214 pci_unregister_driver(&bnx2x_pci_driver);
12215
12216 destroy_workqueue(bnx2x_wq);
12217
12218 /* Free globablly allocated resources */
12219 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12220 struct bnx2x_prev_path_list *tmp =
12221 list_entry(pos, struct bnx2x_prev_path_list, list);
12222 list_del(pos);
12223 kfree(tmp);
12224 }
12225 }
12226
12227 void bnx2x_notify_link_changed(struct bnx2x *bp)
12228 {
12229 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12230 }
12231
12232 module_init(bnx2x_init);
12233 module_exit(bnx2x_cleanup);
12234
12235 #ifdef BCM_CNIC
12236 /**
12237 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12238 *
12239 * @bp: driver handle
12240 * @set: set or clear the CAM entry
12241 *
12242 * This function will wait until the ramdord completion returns.
12243 * Return 0 if success, -ENODEV if ramrod doesn't return.
12244 */
12245 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12246 {
12247 unsigned long ramrod_flags = 0;
12248
12249 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12250 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12251 &bp->iscsi_l2_mac_obj, true,
12252 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12253 }
12254
12255 /* count denotes the number of new completions we have seen */
12256 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12257 {
12258 struct eth_spe *spe;
12259 int cxt_index, cxt_offset;
12260
12261 #ifdef BNX2X_STOP_ON_ERROR
12262 if (unlikely(bp->panic))
12263 return;
12264 #endif
12265
12266 spin_lock_bh(&bp->spq_lock);
12267 BUG_ON(bp->cnic_spq_pending < count);
12268 bp->cnic_spq_pending -= count;
12269
12270
12271 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12272 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12273 & SPE_HDR_CONN_TYPE) >>
12274 SPE_HDR_CONN_TYPE_SHIFT;
12275 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12276 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12277
12278 /* Set validation for iSCSI L2 client before sending SETUP
12279 * ramrod
12280 */
12281 if (type == ETH_CONNECTION_TYPE) {
12282 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12283 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12284 ILT_PAGE_CIDS;
12285 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12286 (cxt_index * ILT_PAGE_CIDS);
12287 bnx2x_set_ctx_validation(bp,
12288 &bp->context[cxt_index].
12289 vcxt[cxt_offset].eth,
12290 BNX2X_ISCSI_ETH_CID(bp));
12291 }
12292 }
12293
12294 /*
12295 * There may be not more than 8 L2, not more than 8 L5 SPEs
12296 * and in the air. We also check that number of outstanding
12297 * COMMON ramrods is not more than the EQ and SPQ can
12298 * accommodate.
12299 */
12300 if (type == ETH_CONNECTION_TYPE) {
12301 if (!atomic_read(&bp->cq_spq_left))
12302 break;
12303 else
12304 atomic_dec(&bp->cq_spq_left);
12305 } else if (type == NONE_CONNECTION_TYPE) {
12306 if (!atomic_read(&bp->eq_spq_left))
12307 break;
12308 else
12309 atomic_dec(&bp->eq_spq_left);
12310 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12311 (type == FCOE_CONNECTION_TYPE)) {
12312 if (bp->cnic_spq_pending >=
12313 bp->cnic_eth_dev.max_kwqe_pending)
12314 break;
12315 else
12316 bp->cnic_spq_pending++;
12317 } else {
12318 BNX2X_ERR("Unknown SPE type: %d\n", type);
12319 bnx2x_panic();
12320 break;
12321 }
12322
12323 spe = bnx2x_sp_get_next(bp);
12324 *spe = *bp->cnic_kwq_cons;
12325
12326 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12327 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12328
12329 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12330 bp->cnic_kwq_cons = bp->cnic_kwq;
12331 else
12332 bp->cnic_kwq_cons++;
12333 }
12334 bnx2x_sp_prod_update(bp);
12335 spin_unlock_bh(&bp->spq_lock);
12336 }
12337
12338 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12339 struct kwqe_16 *kwqes[], u32 count)
12340 {
12341 struct bnx2x *bp = netdev_priv(dev);
12342 int i;
12343
12344 #ifdef BNX2X_STOP_ON_ERROR
12345 if (unlikely(bp->panic)) {
12346 BNX2X_ERR("Can't post to SP queue while panic\n");
12347 return -EIO;
12348 }
12349 #endif
12350
12351 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12352 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12353 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12354 return -EAGAIN;
12355 }
12356
12357 spin_lock_bh(&bp->spq_lock);
12358
12359 for (i = 0; i < count; i++) {
12360 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12361
12362 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12363 break;
12364
12365 *bp->cnic_kwq_prod = *spe;
12366
12367 bp->cnic_kwq_pending++;
12368
12369 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12370 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12371 spe->data.update_data_addr.hi,
12372 spe->data.update_data_addr.lo,
12373 bp->cnic_kwq_pending);
12374
12375 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12376 bp->cnic_kwq_prod = bp->cnic_kwq;
12377 else
12378 bp->cnic_kwq_prod++;
12379 }
12380
12381 spin_unlock_bh(&bp->spq_lock);
12382
12383 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12384 bnx2x_cnic_sp_post(bp, 0);
12385
12386 return i;
12387 }
12388
12389 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12390 {
12391 struct cnic_ops *c_ops;
12392 int rc = 0;
12393
12394 mutex_lock(&bp->cnic_mutex);
12395 c_ops = rcu_dereference_protected(bp->cnic_ops,
12396 lockdep_is_held(&bp->cnic_mutex));
12397 if (c_ops)
12398 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12399 mutex_unlock(&bp->cnic_mutex);
12400
12401 return rc;
12402 }
12403
12404 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12405 {
12406 struct cnic_ops *c_ops;
12407 int rc = 0;
12408
12409 rcu_read_lock();
12410 c_ops = rcu_dereference(bp->cnic_ops);
12411 if (c_ops)
12412 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12413 rcu_read_unlock();
12414
12415 return rc;
12416 }
12417
12418 /*
12419 * for commands that have no data
12420 */
12421 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12422 {
12423 struct cnic_ctl_info ctl = {0};
12424
12425 ctl.cmd = cmd;
12426
12427 return bnx2x_cnic_ctl_send(bp, &ctl);
12428 }
12429
12430 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12431 {
12432 struct cnic_ctl_info ctl = {0};
12433
12434 /* first we tell CNIC and only then we count this as a completion */
12435 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12436 ctl.data.comp.cid = cid;
12437 ctl.data.comp.error = err;
12438
12439 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12440 bnx2x_cnic_sp_post(bp, 0);
12441 }
12442
12443
12444 /* Called with netif_addr_lock_bh() taken.
12445 * Sets an rx_mode config for an iSCSI ETH client.
12446 * Doesn't block.
12447 * Completion should be checked outside.
12448 */
12449 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12450 {
12451 unsigned long accept_flags = 0, ramrod_flags = 0;
12452 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12453 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12454
12455 if (start) {
12456 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12457 * because it's the only way for UIO Queue to accept
12458 * multicasts (in non-promiscuous mode only one Queue per
12459 * function will receive multicast packets (leading in our
12460 * case).
12461 */
12462 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12463 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12464 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12465 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12466
12467 /* Clear STOP_PENDING bit if START is requested */
12468 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12469
12470 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12471 } else
12472 /* Clear START_PENDING bit if STOP is requested */
12473 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12474
12475 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12476 set_bit(sched_state, &bp->sp_state);
12477 else {
12478 __set_bit(RAMROD_RX, &ramrod_flags);
12479 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12480 ramrod_flags);
12481 }
12482 }
12483
12484
12485 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12486 {
12487 struct bnx2x *bp = netdev_priv(dev);
12488 int rc = 0;
12489
12490 switch (ctl->cmd) {
12491 case DRV_CTL_CTXTBL_WR_CMD: {
12492 u32 index = ctl->data.io.offset;
12493 dma_addr_t addr = ctl->data.io.dma_addr;
12494
12495 bnx2x_ilt_wr(bp, index, addr);
12496 break;
12497 }
12498
12499 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12500 int count = ctl->data.credit.credit_count;
12501
12502 bnx2x_cnic_sp_post(bp, count);
12503 break;
12504 }
12505
12506 /* rtnl_lock is held. */
12507 case DRV_CTL_START_L2_CMD: {
12508 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12509 unsigned long sp_bits = 0;
12510
12511 /* Configure the iSCSI classification object */
12512 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12513 cp->iscsi_l2_client_id,
12514 cp->iscsi_l2_cid, BP_FUNC(bp),
12515 bnx2x_sp(bp, mac_rdata),
12516 bnx2x_sp_mapping(bp, mac_rdata),
12517 BNX2X_FILTER_MAC_PENDING,
12518 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12519 &bp->macs_pool);
12520
12521 /* Set iSCSI MAC address */
12522 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12523 if (rc)
12524 break;
12525
12526 mmiowb();
12527 barrier();
12528
12529 /* Start accepting on iSCSI L2 ring */
12530
12531 netif_addr_lock_bh(dev);
12532 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12533 netif_addr_unlock_bh(dev);
12534
12535 /* bits to wait on */
12536 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12537 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12538
12539 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12540 BNX2X_ERR("rx_mode completion timed out!\n");
12541
12542 break;
12543 }
12544
12545 /* rtnl_lock is held. */
12546 case DRV_CTL_STOP_L2_CMD: {
12547 unsigned long sp_bits = 0;
12548
12549 /* Stop accepting on iSCSI L2 ring */
12550 netif_addr_lock_bh(dev);
12551 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12552 netif_addr_unlock_bh(dev);
12553
12554 /* bits to wait on */
12555 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12556 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12557
12558 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12559 BNX2X_ERR("rx_mode completion timed out!\n");
12560
12561 mmiowb();
12562 barrier();
12563
12564 /* Unset iSCSI L2 MAC */
12565 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12566 BNX2X_ISCSI_ETH_MAC, true);
12567 break;
12568 }
12569 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12570 int count = ctl->data.credit.credit_count;
12571
12572 smp_mb__before_atomic_inc();
12573 atomic_add(count, &bp->cq_spq_left);
12574 smp_mb__after_atomic_inc();
12575 break;
12576 }
12577 case DRV_CTL_ULP_REGISTER_CMD: {
12578 int ulp_type = ctl->data.register_data.ulp_type;
12579
12580 if (CHIP_IS_E3(bp)) {
12581 int idx = BP_FW_MB_IDX(bp);
12582 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12583 int path = BP_PATH(bp);
12584 int port = BP_PORT(bp);
12585 int i;
12586 u32 scratch_offset;
12587 u32 *host_addr;
12588
12589 /* first write capability to shmem2 */
12590 if (ulp_type == CNIC_ULP_ISCSI)
12591 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12592 else if (ulp_type == CNIC_ULP_FCOE)
12593 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12594 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12595
12596 if ((ulp_type != CNIC_ULP_FCOE) ||
12597 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12598 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12599 break;
12600
12601 /* if reached here - should write fcoe capabilities */
12602 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12603 if (!scratch_offset)
12604 break;
12605 scratch_offset += offsetof(struct glob_ncsi_oem_data,
12606 fcoe_features[path][port]);
12607 host_addr = (u32 *) &(ctl->data.register_data.
12608 fcoe_features);
12609 for (i = 0; i < sizeof(struct fcoe_capabilities);
12610 i += 4)
12611 REG_WR(bp, scratch_offset + i,
12612 *(host_addr + i/4));
12613 }
12614 break;
12615 }
12616
12617 case DRV_CTL_ULP_UNREGISTER_CMD: {
12618 int ulp_type = ctl->data.ulp_type;
12619
12620 if (CHIP_IS_E3(bp)) {
12621 int idx = BP_FW_MB_IDX(bp);
12622 u32 cap;
12623
12624 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12625 if (ulp_type == CNIC_ULP_ISCSI)
12626 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12627 else if (ulp_type == CNIC_ULP_FCOE)
12628 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12629 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12630 }
12631 break;
12632 }
12633
12634 default:
12635 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12636 rc = -EINVAL;
12637 }
12638
12639 return rc;
12640 }
12641
12642 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12643 {
12644 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12645
12646 if (bp->flags & USING_MSIX_FLAG) {
12647 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12648 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12649 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12650 } else {
12651 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12652 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12653 }
12654 if (!CHIP_IS_E1x(bp))
12655 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12656 else
12657 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12658
12659 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12660 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12661 cp->irq_arr[1].status_blk = bp->def_status_blk;
12662 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12663 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12664
12665 cp->num_irq = 2;
12666 }
12667
12668 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12669 {
12670 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12671
12672
12673 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12674 bnx2x_cid_ilt_lines(bp);
12675 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12676 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12677 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12678
12679 if (NO_ISCSI_OOO(bp))
12680 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12681 }
12682
12683 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12684 void *data)
12685 {
12686 struct bnx2x *bp = netdev_priv(dev);
12687 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12688
12689 if (ops == NULL) {
12690 BNX2X_ERR("NULL ops received\n");
12691 return -EINVAL;
12692 }
12693
12694 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12695 if (!bp->cnic_kwq)
12696 return -ENOMEM;
12697
12698 bp->cnic_kwq_cons = bp->cnic_kwq;
12699 bp->cnic_kwq_prod = bp->cnic_kwq;
12700 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12701
12702 bp->cnic_spq_pending = 0;
12703 bp->cnic_kwq_pending = 0;
12704
12705 bp->cnic_data = data;
12706
12707 cp->num_irq = 0;
12708 cp->drv_state |= CNIC_DRV_STATE_REGD;
12709 cp->iro_arr = bp->iro_arr;
12710
12711 bnx2x_setup_cnic_irq_info(bp);
12712
12713 rcu_assign_pointer(bp->cnic_ops, ops);
12714
12715 return 0;
12716 }
12717
12718 static int bnx2x_unregister_cnic(struct net_device *dev)
12719 {
12720 struct bnx2x *bp = netdev_priv(dev);
12721 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12722
12723 mutex_lock(&bp->cnic_mutex);
12724 cp->drv_state = 0;
12725 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12726 mutex_unlock(&bp->cnic_mutex);
12727 synchronize_rcu();
12728 kfree(bp->cnic_kwq);
12729 bp->cnic_kwq = NULL;
12730
12731 return 0;
12732 }
12733
12734 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12735 {
12736 struct bnx2x *bp = netdev_priv(dev);
12737 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12738
12739 /* If both iSCSI and FCoE are disabled - return NULL in
12740 * order to indicate CNIC that it should not try to work
12741 * with this device.
12742 */
12743 if (NO_ISCSI(bp) && NO_FCOE(bp))
12744 return NULL;
12745
12746 cp->drv_owner = THIS_MODULE;
12747 cp->chip_id = CHIP_ID(bp);
12748 cp->pdev = bp->pdev;
12749 cp->io_base = bp->regview;
12750 cp->io_base2 = bp->doorbells;
12751 cp->max_kwqe_pending = 8;
12752 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12753 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12754 bnx2x_cid_ilt_lines(bp);
12755 cp->ctx_tbl_len = CNIC_ILT_LINES;
12756 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12757 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12758 cp->drv_ctl = bnx2x_drv_ctl;
12759 cp->drv_register_cnic = bnx2x_register_cnic;
12760 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12761 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12762 cp->iscsi_l2_client_id =
12763 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12764 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12765
12766 if (NO_ISCSI_OOO(bp))
12767 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12768
12769 if (NO_ISCSI(bp))
12770 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12771
12772 if (NO_FCOE(bp))
12773 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12774
12775 BNX2X_DEV_INFO(
12776 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12777 cp->ctx_blk_size,
12778 cp->ctx_tbl_offset,
12779 cp->ctx_tbl_len,
12780 cp->starting_cid);
12781 return cp;
12782 }
12783 EXPORT_SYMBOL(bnx2x_cnic_probe);
12784
12785 #endif /* BCM_CNIC */
12786
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