| blob | f4beb46c4709af8291ed7aecc373d7a72a366f59 |
1 /* Copyright 2008-2012 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define WC_LANE_MAX 4
39 #define I2C_SWITCH_WIDTH 2
40 #define I2C_BSC0 0
41 #define I2C_BSC1 1
42 #define I2C_WA_RETRY_CNT 3
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
47 /* LED Blink rate that will achieve ~15.9Hz */
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50 /***********************************************************/
51 /* Shortcut definitions */
52 /***********************************************************/
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB default for class 0 E2 */
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
170 /* BRB thresholds for E2*/
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
183 /* BRB default for class 0 E3A0 */
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
189 /* BRB thresholds for E3A0 */
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
202 /* BRB default for E3B0 */
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
208 /* BRB thresholds for E3B0 2 port mode*/
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
221 /* only for E3B0*/
222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
225 /* Lossy +Lossless GUARANTIED == GUART */
226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227 /* Lossless +Lossless*/
228 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
229 /* Lossy +Lossy*/
230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
232 /* Lossy +Lossless*/
233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234 /* Lossless +Lossless*/
235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
236 /* Lossy +Lossy*/
237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
243 /* BRB thresholds for E3B0 4 port mode */
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
256 /* only for E3B0*/
257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259 #define PFC_E3B0_4P_LB_GUART 120
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
267 /* Pause defines*/
268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270 #define DEFAULT_E3B0_LB_GUART 40
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
278 /* ETS defines*/
279 #define DCBX_INVALID_COS (0xFF)
281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
282 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
285 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
287 #define MAX_PACKET_SIZE (9700)
288 #define MAX_KR_LINK_RETRY 4
290 /**********************************************************/
291 /* INTERFACE */
292 /**********************************************************/
294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
295 bnx2x_cl45_write(_bp, _phy, \
296 (_phy)->def_md_devad, \
297 (_bank + (_addr & 0xf)), \
298 _val)
300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
301 bnx2x_cl45_read(_bp, _phy, \
302 (_phy)->def_md_devad, \
303 (_bank + (_addr & 0xf)), \
304 _val)
307 {
313 }
316 {
322 }
324 /******************************************************************/
325 /* EPIO/GPIO section */
326 /******************************************************************/
328 {
331 /* Sanity check */
335 }
338 /* Set this EPIO to output */
343 }
345 {
348 /* Sanity check */
352 }
355 /* Set this EPIO to output */
359 else
364 /* Set the value for this EPIO */
367 }
370 {
379 }
380 }
383 {
392 }
395 }
396 /******************************************************************/
397 /* ETS section */
398 /******************************************************************/
400 {
401 /* ETS disabled configuration*/
406 /* mapping between entry priority to client number (0,1,2 -debug and
407 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
408 * 3bits client num.
409 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
410 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
411 */
414 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
415 * as strict. Bits 0,1,2 - debug and management entries, 3 -
416 * COS0 entry, 4 - COS1 entry.
417 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
418 * bit4 bit3 bit2 bit1 bit0
419 * MCP and debug are strict
420 */
423 /* defines which entries (clients) are subjected to WFQ arbitration */
425 /* For strict priority entries defines the number of consecutive
426 * slots for the highest priority.
427 */
429 /* mapping between the CREDIT_WEIGHT registers and actual client
430 * numbers
431 */
439 /* ETS mode disable */
441 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
442 * weight for COS0/COS1.
443 */
446 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
449 /* Defines the number of consecutive slots for the strict priority */
451 }
452 /******************************************************************************
453 * Description:
454 * Getting min_w_val will be set according to line speed .
455 *.
456 ******************************************************************************/
458 {
460 /* Calculate min_w_val.*/
464 else
468 /* If the link isn't up (static configuration for example ) The
469 * link will be according to 20GBPS.
470 */
472 }
473 /******************************************************************************
474 * Description:
475 * Getting credit upper bound form min_w_val.
476 *.
477 ******************************************************************************/
479 {
481 MAX_PACKET_SIZE);
483 }
484 /******************************************************************************
485 * Description:
486 * Set credit upper bound for NIG.
487 *.
488 ******************************************************************************/
492 {
513 credit_upper_bound);
515 credit_upper_bound);
517 credit_upper_bound);
518 }
519 }
520 /******************************************************************************
521 * Description:
522 * Will return the NIG ETS registers to init values.Except
523 * credit_upper_bound.
524 * That isn't used in this configuration (No WFQ is enabled) and will be
525 * configured acording to spec
526 *.
527 ******************************************************************************/
530 {
534 /* Mapping between entry priority to client number (0,1,2 -debug and
535 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
536 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
537 * reset value or init tool
538 */
545 }
546 /* For strict priority entries defines the number of consecutive
547 * slots for the highest priority.
548 */
551 /* Mapping between the CREDIT_WEIGHT registers and actual client
552 * numbers
553 */
555 /*Port 1 has 6 COS*/
559 /*Port 0 has 9 COS*/
563 }
565 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
566 * as strict. Bits 0,1,2 - debug and management entries, 3 -
567 * COS0 entry, 4 - COS1 entry.
568 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
569 * bit4 bit3 bit2 bit1 bit0
570 * MCP and debug are strict
571 */
574 else
576 /* defines which entries (clients) are subjected to WFQ arbitration */
580 /* Please notice the register address are note continuous and a
581 * for here is note appropriate.In 2 port mode port0 only COS0-5
582 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
583 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
584 * are never used for WFQ
585 */
602 }
605 }
606 /******************************************************************************
607 * Description:
608 * Set credit upper bound for PBF.
609 *.
610 ******************************************************************************/
614 {
622 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
623 * port mode port1 has COS0-2 that can be used for WFQ.
624 */
631 }
635 }
637 /******************************************************************************
638 * Description:
639 * Will return the PBF ETS registers to init values.Except
640 * credit_upper_bound.
641 * That isn't used in this configuration (No WFQ is enabled) and will be
642 * configured acording to spec
643 *.
644 ******************************************************************************/
646 {
654 /* Mapping between entry priority to client number 0 - COS0
655 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
656 * TODO_ETS - Should be done by reset value or init tool
657 */
659 /* 0x688 (|011|0 10|00 1|000) */
661 else
662 /* (10 1|100 |011|0 10|00 1|000) */
665 /* TODO_ETS - Should be done by reset value or init tool */
667 /* 0x688 (|011|0 10|00 1|000)*/
669 else
670 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
682 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
683 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
684 */
691 }
697 }
698 /******************************************************************************
699 * Description:
700 * E3B0 disable will return basicly the values to init values.
701 *.
702 ******************************************************************************/
705 {
712 }
719 }
721 /******************************************************************************
722 * Description:
723 * Disable will return basicly the values to init values.
724 *
725 ******************************************************************************/
728 {
739 }
742 }
744 /******************************************************************************
745 * Description
746 * Set the COS mappimg to SP and BW until this point all the COS are not
747 * set as SP or BW.
748 ******************************************************************************/
753 {
768 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
769 nig_cli_subject2wfq_bitmap);
772 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
773 pbf_cli_subject2wfq_bitmap);
776 }
778 /******************************************************************************
779 * Description:
780 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
781 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
782 ******************************************************************************/
790 {
793 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
799 nig_reg_adress_crd_weight =
801 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
807 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
808 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
814 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
815 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
823 nig_reg_adress_crd_weight =
824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
825 pbf_reg_adress_crd_weight =
826 PBF_REG_COS3_WEIGHT_P0;
831 nig_reg_adress_crd_weight =
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
838 nig_reg_adress_crd_weight =
839 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
842 }
849 }
850 /******************************************************************************
851 * Description:
852 * Calculate the total BW.A value of 0 isn't legal.
853 *
854 ******************************************************************************/
859 {
865 /* Calculate total BW requested */
872 /* This is to prevent a state when ramrods
873 * can't be sent
874 */
877 }
880 }
881 }
883 /* Check total BW is valid */
889 }
892 /* We can handle a case whre the BW isn't 100 this can happen
893 * if the TC are joined.
894 */
895 }
897 }
899 /******************************************************************************
900 * Description:
901 * Invalidate all the sp_pri_to_cos.
902 *
903 ******************************************************************************/
905 {
909 }
910 /******************************************************************************
911 * Description:
912 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
913 * according to sp_pri_to_cos.
914 *
915 ******************************************************************************/
919 {
923 DCBX_E3B0_MAX_NUM_COS_PORT0;
929 }
933 "parameter There can't be two COS's with "
936 }
941 }
943 /******************************************************************************
944 * Description:
945 * Returns the correct value according to COS and priority in
946 * the sp_pri_cli register.
947 *
948 ******************************************************************************/
953 {
959 }
960 /******************************************************************************
961 * Description:
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for NIG.
964 *
965 ******************************************************************************/
967 {
968 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
975 }
976 /******************************************************************************
977 * Description:
978 * Returns the correct value according to COS and priority in the
979 * sp_pri_cli register for PBF.
980 *
981 ******************************************************************************/
983 {
990 }
992 /******************************************************************************
993 * Description:
994 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
995 * according to sp_pri_to_cos.(which COS has higher priority)
996 *
997 ******************************************************************************/
1000 {
1004 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1010 DCBX_E3B0_MAX_NUM_COS_PORT0;
1014 /* Set all the strict priority first */
1019 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1022 }
1030 /* COS is used remove it from bitmap.*/
1033 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034 "invalid There can't be two COS's with"
1037 }
1039 pri_set++;
1040 }
1041 }
1043 /* Set all the Non strict priority i= COS*/
1046 /* Check if COS was already used for SP */
1048 /* COS wasn't used for SP */
1054 /* COS is used remove it from bitmap.*/
1056 pri_set++;
1057 }
1058 }
1064 }
1067 /* Only 6 usable clients*/
1073 /* Only 9 usable clients*/
1078 pri_cli_nig_lsb);
1080 pri_cli_nig_msb);
1083 }
1085 }
1087 /******************************************************************************
1088 * Description:
1089 * Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1094 {
1105 DCBX_E3B0_MAX_NUM_COS_PORT0;
1112 }
1118 }
1120 /* Prepare sp strict priority parameters*/
1123 /* Prepare BW parameters*/
1130 }
1132 /* Upper bound is set according to current link speed (min_w_val
1133 * should be the same for upper bound and COS credit val).
1134 */
1142 /* The function also sets the BW in HW(not the mappin
1143 * yet)
1144 */
1147 total_bw,
1149 port);
1155 params,
1156 sp_pri_to_cos,
1158 cos_entry);
1164 }
1169 }
1170 }
1172 /* Set SP register (which COS has higher priority) */
1174 sp_pri_to_cos);
1180 }
1182 /* Set client mapping of BW and strict */
1184 cos_sp_bitmap,
1185 cos_bw_bitmap);
1190 }
1192 }
1194 {
1195 /* ETS disabled configuration */
1198 /* Defines which entries (clients) are subjected to WFQ arbitration
1199 * COS0 0x8
1200 * COS1 0x10
1201 */
1203 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204 * client numbers (WEIGHT_0 does not actually have to represent
1205 * client 0)
1206 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1207 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1208 */
1212 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1214 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1216 /* ETS mode enabled*/
1219 /* Defines the number of consecutive slots for the strict priority */
1221 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1223 * entry, 4 - COS1 entry.
1224 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225 * bit4 bit3 bit2 bit1 bit0
1226 * MCP and debug are strict
1227 */
1230 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1232 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1234 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1235 }
1239 {
1240 /* ETS disabled configuration*/
1253 }
1256 total_bw;
1258 total_bw;
1267 }
1270 {
1271 /* ETS disabled configuration*/
1276 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277 * as strict. Bits 0,1,2 - debug and management entries,
1278 * 3 - COS0 entry, 4 - COS1 entry.
1279 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280 * bit4 bit3 bit2 bit1 bit0
1281 * MCP and debug are strict
1282 */
1284 /* For strict priority entries defines the number of consecutive slots
1285 * for the highest priority.
1286 */
1288 /* ETS mode disable */
1290 /* Defines the number of consecutive slots for the strict priority */
1293 /* Defines the number of consecutive slots for the strict priority */
1296 /* Mapping between entry priority to client number (0,1,2 -debug and
1297 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1298 * 3bits client num.
1299 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1300 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1301 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1302 */
1307 }
1309 /******************************************************************/
1310 /* EEE section */
1311 /******************************************************************/
1313 {
1321 }
1324 {
1338 }
1341 }
1344 {
1358 }
1361 }
1364 {
1370 /* time value in eee_mode --> used directly*/
1373 /* hsi value in eee_mode --> time */
1375 EEE_MODE_NVRAM_MASK,
1378 }
1380 /* hsi values in nvram --> time*/
1384 eee_power_mode)) &
1385 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
1386 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
1390 }
1393 }
1396 /******************************************************************/
1397 /* PFC section */
1398 /******************************************************************/
1401 u8 is_lb)
1402 {
1404 u32 xmac_base;
1407 /* XMAC base adrr */
1410 /* Initialize pause and pfc registers */
1415 /* No PFC support */
1417 FEATURE_CONFIG_PFC_ENABLED)) {
1419 /* RX flow control - Process pause frame in receive direction
1420 */
1424 /* TX flow control - Send pause packet when buffer is full */
1429 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1430 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1431 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1432 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1433 /* Write pause and PFC registers */
1439 }
1441 /* Write pause and PFC registers */
1447 /* Set MAC address for source TX Pause/PFC frames */
1458 }
1464 {
1465 /* Read pfc statistic */
1473 /* PFC received frames */
1475 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1482 /* PFC received sent */
1484 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1490 }
1492 /* Read pfc statistic*/
1496 {
1497 /* Read pfc statistic */
1508 pfc_frames_received);
1509 }
1510 }
1511 /******************************************************************/
1512 /* MAC/PBF section */
1513 /******************************************************************/
1515 {
1517 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1518 * (a value of 49==0x31) and make sure that the AUTO poll is off
1519 */
1523 else
1527 EMAC_MDIO_MODE_CLOCK_CNT);
1530 else
1537 }
1539 {
1540 u32 port4mode_ovwr_val;
1541 /* Check 4-port override enabled */
1544 /* Return 4-port mode override value */
1546 }
1547 /* Return 4-port mode from input pin */
1549 }
1553 {
1554 /* reset and unreset the emac core */
1558 u32 val;
1559 u16 timeout;
1567 /* init emac - use read-modify-write */
1568 /* self clear reset */
1579 }
1580 timeout--;
1583 /* Set mac address */
1593 }
1596 u16 tx_pause_en,
1597 u8 enable)
1598 {
1602 enable);
1604 enable);
1607 }
1610 {
1617 /* Disable RX and TX */
1619 }
1623 {
1624 u32 val;
1627 /* Reset UMAC */
1637 /* This register opens the gate for the UMAC despite its name */
1641 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1642 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1643 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1661 }
1674 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1684 /* Enable RX and TX */
1687 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1691 /* Remove SW Reset */
1694 /* Check loopback mode */
1699 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1700 * length used by the MAC receive logic to check frames.
1701 */
1707 }
1709 /* Define the XMAC mode */
1711 {
1715 /* In 4-port mode, need to set the mode only once, so if XMAC is
1716 * already out of reset, it means the mode has already been set,
1717 * and it must not* reset the XMAC again, since it controls both
1718 * ports of the path
1719 */
1723 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1727 }
1729 /* Hard reset */
1731 MISC_REGISTERS_RESET_REG_2_XMAC);
1735 MISC_REGISTERS_RESET_REG_2_XMAC);
1739 /* Set the number of ports on the system side to up to 2 */
1742 /* Set the number of ports on the Warp Core to 10G */
1745 /* Set the number of ports on the system side to 1 */
1750 /* Set the number of ports on the Warp Core to 10G */
1755 /* Set the number of ports on the Warp Core to 20G */
1757 }
1758 }
1759 /* Soft reset */
1761 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1765 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1767 }
1770 {
1776 MISC_REGISTERS_RESET_REG_2_XMAC) {
1777 /* Send an indication to change the state in the NIG back to XON
1778 * Clearing this bit enables the next set of this bit to get
1779 * rising edge
1780 */
1788 }
1789 }
1793 {
1802 /* This register determines on which events the MAC will assert
1803 * error on the i/f to the NIG along w/ EOP.
1804 */
1806 /* This register tells the NIG whether to send traffic to UMAC
1807 * or XMAC
1808 */
1811 /* Set Max packet size */
1814 /* CRC append for Tx packets */
1817 /* update PFC */
1826 }
1828 /* Enable TX and RX */
1831 /* Check loopback mode */
1841 }
1845 {
1849 u32 val;
1853 /* Disable BMAC */
1857 /* enable emac and not bmac */
1860 /* ASIC */
1863 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1864 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1867 /* select the master lanes (out of 0-3) */
1869 /* select XGXS */
1874 /* select SerDes */
1876 }
1879 EMAC_RX_MODE_RESET);
1881 EMAC_TX_MODE_RESET);
1883 /* pause enable/disable */
1885 EMAC_RX_MODE_FLOW_EN);
1889 EMAC_TX_MODE_FLOW_EN));
1891 FEATURE_CONFIG_PFC_ENABLED)) {
1894 EMAC_REG_EMAC_RX_MODE,
1895 EMAC_RX_MODE_FLOW_EN);
1899 EMAC_REG_EMAC_TX_MODE,
1901 EMAC_TX_MODE_FLOW_EN));
1904 EMAC_TX_MODE_FLOW_EN);
1906 /* KEEP_VLAN_TAG, promiscuous */
1910 /* Setting this bit causes MAC control frames (except for pause
1911 * frames) to be passed on for processing. This setting has no
1912 * affect on the operation of the pause frames. This bit effects
1913 * all packets regardless of RX Parser packet sorting logic.
1914 * Turn the PFC off to make sure we are in Xon state before
1915 * enabling it.
1916 */
1920 /* Enable PFC again */
1922 EMAC_REG_RX_PFC_MODE_RX_EN |
1923 EMAC_REG_RX_PFC_MODE_TX_EN |
1924 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1928 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1930 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1932 }
1935 /* Set Loopback */
1939 else
1943 /* Enable emac */
1946 /* Enable emac for jumbo packets */
1951 /* Strip CRC */
1954 /* Disable the NIG in/out to the bmac */
1959 /* Enable the NIG in/out to the emac */
1963 FEATURE_CONFIG_PFC_ENABLED) ||
1974 }
1978 {
1982 NIG_REG_INGRESS_BMAC0_MEM;
1986 FEATURE_CONFIG_PFC_ENABLED)) &&
1988 /* Enable BigMAC to react on received Pause packets */
1994 /* TX control */
1997 FEATURE_CONFIG_PFC_ENABLED) &&
2003 }
2007 u8 is_lb)
2008 {
2009 /* Set rx control: Strip CRC and enable BigMAC to relay
2010 * control packets to the system as well
2011 */
2015 NIG_REG_INGRESS_BMAC0_MEM;
2019 FEATURE_CONFIG_PFC_ENABLED)) &&
2021 /* Enable BigMAC to react on received Pause packets */
2028 /* Tx control */
2031 FEATURE_CONFIG_PFC_ENABLED) &&
2040 /* Enable PFC RX & TX & STATS and set 8 COS */
2050 /* Clear the force Xon */
2054 /* Disable PFC RX & TX & STATS and set 8 COS */
2057 }
2061 /* Set Time (based unit is 512 bit time) between automatic
2062 * re-sending of PP packets amd enable automatic re-send of
2063 * Per-Priroity Packet as long as pp_gen is asserted and
2064 * pp_disable is low.
2065 */
2075 /* mac control */
2080 }
2081 /* When PFC enabled, Pass pause frames towards the NIG. */
2088 }
2090 /* PFC BRB internal port configuration params */
2092 u32 pause_xoff;
2093 u32 pause_xon;
2094 u32 full_xoff;
2095 u32 full_xon;
2096 };
2099 u32 per_class_guaranty_mode;
2100 u32 lb_guarantied_hyst;
2101 u32 full_lb_xoff_th;
2102 u32 full_lb_xon_threshold;
2103 u32 lb_guarantied;
2104 u32 mac_0_class_t_guarantied;
2105 u32 mac_0_class_t_guarantied_hyst;
2106 u32 mac_1_class_t_guarantied;
2107 u32 mac_1_class_t_guarantied_hyst;
2108 };
2116 };
2120 {
2130 /* Class0 defaults */
2132 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2134 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2136 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2138 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2139 /* Pause able*/
2141 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2143 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2145 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2147 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2148 /* Non pause able*/
2150 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2152 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2154 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2156 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2158 /* Class0 defaults */
2160 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2162 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2164 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2166 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2167 /* Pause able */
2169 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2171 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2173 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2175 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2176 /* Non pause able*/
2178 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2180 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2182 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2184 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2186 /* Class0 defaults */
2188 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2190 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2192 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2194 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2197 FLAGS_4_PORT_MODE) {
2199 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2201 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2203 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2205 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2206 /* Non pause able*/
2208 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2210 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2212 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2214 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2217 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2219 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2221 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2223 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2224 /* Non pause able*/
2226 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2228 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2230 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2232 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2233 }
2238 }
2242 struct bnx2x_pfc_brb_e3b0_val
2246 {
2252 FLAGS_4_PORT_MODE) {
2254 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2256 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2258 PFC_E3B0_4P_LB_GUART;
2260 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2262 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2264 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2266 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2269 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2271 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2273 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2275 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2277 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2281 /* Nonpauseable= Lossy + pauseable = Lossless*/
2283 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2285 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2287 /* Lossless +Lossless*/
2289 PFC_E3B0_2P_PAUSE_LB_GUART;
2291 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2293 /* Lossy +Lossy*/
2295 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2297 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2298 }
2299 }
2304 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2306 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2308 DEFAULT_E3B0_LB_GUART;
2310 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2312 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2314 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2316 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2317 }
2318 }
2321 struct bnx2x_nig_brb_pfc_port_params
2323 {
2330 FEATURE_CONFIG_PFC_ENABLED;
2335 /* default - pause configuration */
2342 /* First COS */
2345 else
2349 /* The number of free blocks below which the pause signal to class 0
2350 * of MAC #n is asserted. n=0,1
2351 */
2353 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2355 /* The number of free blocks above which the pause signal to class 0
2356 * of MAC #n is de-asserted. n=0,1
2357 */
2360 /* The number of free blocks below which the full signal to class 0
2361 * of MAC #n is asserted. n=0,1
2362 */
2365 /* The number of free blocks above which the full signal to class 0
2366 * of MAC #n is de-asserted. n=0,1
2367 */
2372 /* Second COS */
2375 else
2379 /* The number of free blocks below which the pause signal to
2380 * class 1 of MAC #n is asserted. n=0,1
2381 */
2383 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2386 /* The number of free blocks above which the pause signal to
2387 * class 1 of MAC #n is de-asserted. n=0,1
2388 */
2390 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2392 /* The number of free blocks below which the full signal to
2393 * class 1 of MAC #n is asserted. n=0,1
2394 */
2396 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2398 /* The number of free blocks above which the full signal to
2399 * class 1 of MAC #n is de-asserted. n=0,1
2400 */
2402 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2407 params,
2409 pfc_params,
2410 pfc_enabled);
2415 /* The hysteresis on the guarantied buffer space for the Lb
2416 * port before signaling XON.
2417 */
2421 /* The number of free blocks below which the full signal to the
2422 * LB port is asserted.
2423 */
2426 /* The number of free blocks above which the full signal to the
2427 * LB port is de-asserted.
2428 */
2431 /* The number of blocks guarantied for the MAC #n port. n=0,1
2432 */
2434 /* The number of blocks guarantied for the LB port. */
2438 /* The number of blocks guarantied for the MAC #n port. */
2443 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2444 */
2449 /* The hysteresis on the guarantied buffer space for class in
2450 * MAC0. t=0,1
2451 */
2457 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2458 */
2463 /* The hysteresis on the guarantied buffer space for class #t
2464 * in MAC1. t=0,1
2465 */
2470 }
2473 }
2475 /******************************************************************************
2476 * Description:
2477 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2478 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2479 ******************************************************************************/
2481 u8 cos_entry,
2483 {
2489 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2490 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2494 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2495 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2499 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2500 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2517 }
2522 }
2524 {
2530 }
2533 {
2540 }
2545 {
2553 FEATURE_CONFIG_PFC_ENABLED;
2556 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2557 * MAC control frames (that are not pause packets)
2558 * will be forwarded to the XCM.
2559 */
2561 NIG_REG_LLH0_XCM_MASK);
2562 /* NIG params will override non PFC params, since it's possible to
2563 * do transition from PFC to SAFC
2564 */
2571 else
2574 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2586 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2588 }
2609 /* Output enable for RX_XCM # IF */
2613 /* HW PFC TX enable */
2626 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2630 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2632 }
2634 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2635 pkt_priority_to_cos);
2636 }
2641 {
2642 /* The PFC and pause are orthogonal to one another, meaning when
2643 * PFC is enabled, the pause are disabled, and when PFC is
2644 * disabled, pause are set according to the pause result.
2645 */
2646 u32 val;
2653 else
2658 /* Update NIG params */
2661 /* Update BRB params */
2680 }
2683 else
2688 FEATURE_CONFIG_PFC_ENABLED) ||
2692 }
2694 }
2699 u8 is_lb)
2700 {
2704 NIG_REG_INGRESS_BMAC0_MEM;
2706 u32 val;
2710 /* XGXS control */
2716 /* TX MAC SA */
2725 /* MAC control */
2730 }
2735 /* Set rx mtu */
2742 /* Set tx mtu */
2747 /* Set cnt max size */
2752 /* Configure SAFC */
2759 }
2763 u8 is_lb)
2764 {
2768 NIG_REG_INGRESS_BMAC0_MEM;
2778 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2786 /* TX MAC SA */
2798 /* Configure SAFC */
2805 /* Set RX MTU */
2811 /* Set TX MTU */
2816 /* Set cnt max size */
2824 }
2828 u8 is_lb)
2829 {
2833 u32 val;
2834 /* Reset and unreset the BigMac */
2842 /* Enable access for bmac registers */
2845 /* Enable BMAC according to BMAC type*/
2848 else
2855 FEATURE_CONFIG_PFC_ENABLED) ||
2867 }
2870 {
2872 NIG_REG_INGRESS_BMAC0_MEM;
2876 /* Only if the bmac is out of reset */
2879 nig_bmac_enable) {
2882 /* Clear Rx Enable bit in BMAC_CONTROL register */
2884 BIGMAC2_REGISTER_BMAC_CONTROL,
2888 BIGMAC2_REGISTER_BMAC_CONTROL,
2891 /* Clear Rx Enable bit in BMAC_CONTROL register */
2893 BIGMAC_REGISTER_BMAC_CONTROL,
2897 BIGMAC_REGISTER_BMAC_CONTROL,
2899 }
2901 }
2902 }
2905 u32 line_speed)
2906 {
2912 /* Disable port */
2915 /* Wait for init credit */
2923 count--;
2924 }
2930 }
2938 /* Update threshold */
2940 /* Update init credit */
2947 /* Update threshold */
2949 /* Update init credit */
2956 line_speed);
2958 }
2959 }
2964 /* Probe the credit changes */
2969 /* Enable port */
2972 }
2974 /**
2975 * bnx2x_get_emac_base - retrive emac base address
2976 *
2977 * @bp: driver handle
2978 * @mdc_mdio_access: access type
2979 * @port: port id
2980 *
2981 * This function selects the MDC/MDIO access (through emac0 or
2982 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2983 * phy has a default access mode, which could also be overridden
2984 * by nvram configuration. This parameter, whether this is the
2985 * default phy configuration, or the nvram overrun
2986 * configuration, is passed here as mdc_mdio_access and selects
2987 * the emac_base for the CL45 read/writes operations
2988 */
2991 {
2999 else
3005 else
3016 }
3019 }
3021 /******************************************************************/
3022 /* CL22 access functions */
3023 /******************************************************************/
3027 {
3029 u8 i;
3031 /* Switch to CL22 */
3036 /* Address */
3038 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3039 EMAC_MDIO_COMM_START_BUSY);
3049 }
3050 }
3054 }
3057 }
3062 {
3064 u16 i;
3067 /* Switch to CL22 */
3072 /* Address */
3074 EMAC_MDIO_COMM_COMMAND_READ_22 |
3075 EMAC_MDIO_COMM_START_BUSY);
3086 }
3087 }
3093 }
3096 }
3098 /******************************************************************/
3099 /* CL45 access functions */
3100 /******************************************************************/
3103 {
3104 u32 val;
3105 u16 i;
3109 EMAC_MDIO_STATUS_10MB);
3110 /* Address */
3112 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3113 EMAC_MDIO_COMM_START_BUSY);
3123 }
3124 }
3131 /* Data */
3133 EMAC_MDIO_COMM_COMMAND_READ_45 |
3134 EMAC_MDIO_COMM_START_BUSY);
3141 EMAC_REG_EMAC_MDIO_COMM);
3145 }
3146 }
3152 }
3153 }
3154 /* Work around for E3 A0 */
3158 u16 temp_val;
3160 }
3161 }
3165 EMAC_MDIO_STATUS_10MB);
3167 }
3171 {
3172 u32 tmp;
3173 u8 i;
3177 EMAC_MDIO_STATUS_10MB);
3179 /* Address */
3181 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3182 EMAC_MDIO_COMM_START_BUSY);
3192 }
3193 }
3199 /* Data */
3201 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3202 EMAC_MDIO_COMM_START_BUSY);
3209 EMAC_REG_EMAC_MDIO_COMM);
3213 }
3214 }
3219 }
3220 }
3221 /* Work around for E3 A0 */
3225 u16 temp_val;
3227 }
3228 }
3231 EMAC_MDIO_STATUS_10MB);
3233 }
3234 /******************************************************************/
3235 /* BSC access functions from E3 */
3236 /******************************************************************/
3238 {
3244 /* Read I2C output PINs */
3250 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3252 /* Read I2C output value */
3261 }
3265 u8 sl_devid,
3266 u16 sl_addr,
3267 u8 lc_addr,
3268 u8 xfer_cnt,
3270 {
3278 }
3282 xfer_cnt);
3284 }
3289 /* Enable the engine */
3294 /* Program slave device ID */
3298 /* Start xfer with 0 byte to update the address pointer ???*/
3301 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3305 /* Poll for completion */
3313 i);
3316 }
3317 }
3321 /* Start xfer with read op */
3324 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3329 /* Poll for completion */
3339 }
3340 }
3346 #ifdef __BIG_ENDIAN
3351 #endif
3352 }
3354 }
3358 {
3359 u16 val;
3362 }
3366 {
3367 u8 phy_index;
3368 /* Probe for the phy according to the given phy_addr, and execute
3369 * the read request on it
3370 */
3376 }
3377 }
3379 }
3383 {
3384 u8 phy_index;
3385 /* Probe for the phy according to the given phy_addr, and execute
3386 * the write request on it
3387 */
3393 }
3394 }
3396 }
3399 {
3411 /* Figure out path swap value */
3415 else
3421 /* Figure out port swap value */
3425 else
3434 /* Figure out path swap value */
3435 path_swap_ovr =
3440 path_swap =
3442 }
3447 }
3449 }
3453 {
3454 u32 ser_lane;
3458 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3459 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3466 /* In Dual-lane mode, two lanes are joined together,
3467 * so in order to configure them, the AER broadcast method is
3468 * used here.
3469 * 0x200 is the broadcast address for lanes 0,1
3470 * 0x201 is the broadcast address for lanes 2,3
3471 */
3476 else
3482 }
3484 /******************************************************************/
3485 /* Internal phy section */
3486 /******************************************************************/
3489 {
3492 /* Set Clause 22 */
3498 /* Set Clause 45 */
3500 }
3503 {
3504 u32 val;
3510 /* Reset and unreset the SerDes/XGXS */
3518 DEFAULT_PHY_DEV_ADDR);
3519 }
3522 {
3524 u8 port;
3525 u32 val;
3531 /* Reset and unreset the SerDes/XGXS */
3539 }
3543 {
3546 /* Resolve pause mode and advertisement Please refer to Table
3547 * 28B-3 of the 802.3ab-1999 spec
3548 */
3554 else
3556 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3572 }
3574 }
3578 {
3582 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3584 phy_index++) {
3592 }
3606 SPEED_AUTO_NEG)
3614 }
3615 }
3620 {
3621 u16 val;
3623 /* Read modify write pause advertizing */
3628 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3631 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3632 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3634 }
3636 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3637 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3639 }
3642 }
3664 }
3670 }
3675 {
3678 u16 pause_result;
3691 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3692 lane;
3704 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3707 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3709 }
3712 MDIO_AN_DEVAD,
3715 MDIO_AN_DEVAD,
3717 }
3725 }
3730 {
3734 /* Update the advertised flow-controled of LD/LP in AN */
3737 /* But set the flow-control result as the requested one */
3744 }
3746 }
3747 /******************************************************************/
3748 /* Warpcore section */
3749 /******************************************************************/
3750 /* The init_internal_warpcore should mirror the xgxs,
3751 * i.e. reset the lane (if needed), set aer for the
3752 * init configuration, and set/clear SGMII flag. Internal
3753 * phy init is done purely in phy_init stage.
3754 */
3769 /* Disable Autoneg: re-enable it after adv is done. */
3771 };
3773 /* Set to default registers that may be overriden by 10G force */
3778 /* Check adding advertisement for 1G KX */
3785 /* Enable CL37 1G Parallel Detect */
3788 }
3792 /* Check adding advertisement for 10G KR */
3794 /* Enable 10G Parallel Detect */
3799 }
3801 /* Set Transmit PMD settings */
3809 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3812 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3815 /* Advertised speeds */
3819 /* Advertised and set FEC (Forward Error Correction) */
3821 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3823 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3825 /* Enable CL37 BAM */
3829 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3831 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3834 }
3836 /* Advertise pause */
3838 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3839 */
3845 }
3849 /* Over 1G - AN local device user page 1 */
3853 /* Enable Autoneg */
3857 }
3862 {
3864 u16 i;
3866 /* Disable Autoneg */
3875 /* Disable CL36 PCS Tx */
3877 /* Double Wide Single Data Rate @ pll rate */
3879 /* Leave cl72 training enable, needed for KR */
3881 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3883 };
3889 /* Leave CL72 enabled */
3891 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3894 /* Set speed via PMA/PMD register */
3901 /* Enable encoded forced speed */
3905 /* Turn TX scramble payload only the 64/66 scrambler */
3909 /* Turn RX scramble payload only the 64/66 scrambler */
3913 /* Set and clear loopback to cause a reset to 64/66 decoder */
3919 }
3923 u8 is_xfi)
3924 {
3927 /* Hold rxSeqStart */
3931 /* Hold tx_fifo_reset */
3935 /* Disable CL73 AN */
3938 /* Disable 100FX Enable and Auto-Detect */
3944 /* Disable 100FX Idle detect */
3948 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3954 /* Turn off auto-detect & fiber mode */
3958 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3961 /* Set filter_force_link, disable_false_link and parallel_detect */
3965 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3968 /* Set XFI / SFI */
3979 tx_driver_val =
3989 tx_driver_val =
3993 }
3997 /* Set Transmit PMD settings */
4000 MDIO_WC_REG_TX_FIR_TAP,
4004 tx_driver_val);
4006 /* Enable fiber mode, enable and invert sig_det */
4010 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4014 /* Enable LPI pass through */
4017 MDIO_WC_REG_EEE_COMBO_CONTROL0,
4022 /* 10G XFI Full Duplex */
4026 /* Release tx_fifo_reset */
4032 /* Release rxSeqStart */
4037 }
4041 {
4043 }
4047 u16 lane)
4048 {
4049 /* Rx0 anaRxControl1G */
4053 /* Rx2 anaRxControl1G */
4081 /* Serdes Digital Misc1 */
4085 /* Serdes Digital4 Misc3 */
4089 /* Set Transmit PMD settings */
4091 MDIO_WC_REG_TX_FIR_TAP,
4095 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4101 }
4105 u8 fiber_mode,
4106 u8 always_autoneg)
4107 {
4111 /* Clear XFI clock comp in non-10G single lane mode. */
4118 /* SGMII Autoneg */
4122 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4142 }
4155 }
4157 /* SGMII Slave mode and disable signal detect */
4162 else
4166 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4167 digctrl_kx1);
4169 /* Turn off parallel detect */
4173 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4176 /* Re-enable parallel detect */
4178 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4181 /* Enable autodet */
4183 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4185 }
4189 u8 reset)
4190 {
4191 u16 val;
4192 /* Take lane out of reset after configuration is finished */
4197 else
4203 }
4204 /* Clear SFI/XFI link settings registers */
4207 u16 lane)
4208 {
4210 u16 i;
4226 };
4227 /* Set XFI clock comp as default. */
4239 }
4242 u32 chip_id,
4245 {
4246 u32 cfg_pin;
4253 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4254 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4256 /* Should not happen. This function called upon interrupt
4257 * triggered by GPIO ( since EPIO can only generate interrupts
4258 * to MCP).
4259 * So if this function was called and none of the GPIOs was set,
4260 * it means the shit hit the fan.
4261 */
4266 cfg_pin);
4268 }
4275 }
4278 }
4282 {
4285 u32 gpio_val;
4292 /* Call the handling function in case module is detected */
4295 else
4297 }
4300 {
4310 }
4315 {
4317 u32 serdes_net_if;
4326 /* Return if there is no link partner */
4330 }
4336 PORT_HW_CFG_NET_SERDES_IF_MASK);
4340 /* Do we get link yet? */
4344 /*10G KR*/
4356 /* Reset the lane to see if link comes up.*/
4360 /* Restart Autoneg */
4367 }
4372 }
4376 }
4379 {
4384 SPEED_10000) &&
4391 }
4392 }
4397 {
4399 u32 serdes_net_if;
4400 u8 fiber_mode;
4405 PORT_HW_CFG_NET_SERDES_IF_MASK);
4423 /* Enable KR Auto Neg */
4429 }
4444 }
4446 params,
4447 fiber_mode,
4449 }
4454 /* Issue Module detection */
4465 }
4468 /* Issue Module detection */
4477 }
4485 serdes_net_if);
4487 }
4488 }
4490 /* Take lane out of reset after configuration is finished */
4493 }
4497 u8 tx_en)
4498 {
4500 u32 cfg_pin;
4506 PORT_HW_CFG_TX_LASER_MASK;
4507 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4509 /* For 20G, the expected pin to be used is 3 pins after the current */
4514 }
4518 {
4520 u16 val16;
4524 /* Global register */
4527 /* Clear loopback settings (if any) */
4528 /* 10G & 20G */
4540 /* Update those 1-copy registers */
4543 /* Enable 1G MDIO (1-copy) */
4545 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4548 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4554 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4557 }
4561 {
4563 u16 val16;
4564 u32 lane;
4569 /* 10/100/1000 */
4571 /* Update those 1-copy registers */
4574 /* Enable 1G MDIO (1-copy) */
4576 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4578 /* Set 1G loopback based on lane (1-copy) */
4583 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4586 /* Switch back to 4-copy registers */
4589 /* 10G & 20G */
4591 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4596 }
4597 }
4603 {
4605 u8 link_10g_plus;
4615 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4618 /* Fall thru */
4625 /* Fall thru */
4633 /* Fall thru */
4640 /* Fall thru */
4653 }
4670 }
4675 /* Anything 10 and over uses the bmac */
4681 else
4686 else
4688 }
4698 /* Indicate no mac active */
4704 }
4705 }
4709 {
4713 /* Update PHY configuration */
4722 /* Sync media type */
4730 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4733 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4736 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4739 /* Sync AEU offset */
4746 /* Sync PFC status */
4749 FEATURE_CONFIG_PFC_ENABLED;
4750 else
4758 }
4762 {
4766 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4767 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4769 /* Set the master_ln for AN */
4771 MDIO_REG_BANK_XGXS_BLOCK2,
4772 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4776 MDIO_REG_BANK_XGXS_BLOCK2 ,
4777 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4779 }
4783 u8 set_serdes)
4784 {
4786 u16 mii_control;
4787 u16 i;
4789 MDIO_REG_BANK_COMBO_IEEE0,
4792 /* Reset the unicore */
4794 MDIO_REG_BANK_COMBO_IEEE0,
4795 MDIO_COMBO_IEEE0_MII_CONTROL,
4797 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4801 /* Wait for the reset to self clear */
4805 /* The reset erased the previous bank value */
4807 MDIO_REG_BANK_COMBO_IEEE0,
4808 MDIO_COMBO_IEEE0_MII_CONTROL,
4814 }
4815 }
4823 }
4827 {
4829 /* Each two bits represents a lane number:
4830 * No swap is 0123 => 0x1b no need to enable the swap
4831 */
4835 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4836 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4838 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4839 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4843 MDIO_REG_BANK_XGXS_BLOCK2,
4844 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4846 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4847 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4850 MDIO_REG_BANK_XGXS_BLOCK2,
4852 }
4856 MDIO_REG_BANK_XGXS_BLOCK2,
4857 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4859 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4862 MDIO_REG_BANK_XGXS_BLOCK2,
4864 }
4865 }
4869 {
4871 u16 control2;
4873 MDIO_REG_BANK_SERDES_DIGITAL,
4874 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4878 else
4883 MDIO_REG_BANK_SERDES_DIGITAL,
4884 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4885 control2);
4889 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4893 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4894 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4895 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4898 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4899 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4903 control2 |=
4904 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4907 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4908 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4909 control2);
4911 /* Disable parallel detection of HiG */
4913 MDIO_REG_BANK_XGXS_BLOCK2,
4914 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4915 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4916 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4917 }
4918 }
4923 u8 enable_cl73)
4924 {
4926 u16 reg_val;
4928 /* CL37 Autoneg */
4930 MDIO_REG_BANK_COMBO_IEEE0,
4933 /* CL37 Autoneg Enabled */
4938 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4941 MDIO_REG_BANK_COMBO_IEEE0,
4944 /* Enable/Disable Autodetection */
4947 MDIO_REG_BANK_SERDES_DIGITAL,
4950 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4954 else
4958 MDIO_REG_BANK_SERDES_DIGITAL,
4961 /* Enable TetonII and BAM autoneg */
4963 MDIO_REG_BANK_BAM_NEXT_PAGE,
4964 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4967 /* Enable BAM aneg Mode and TetonII aneg Mode */
4969 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4971 /* TetonII and BAM Autoneg Disabled */
4973 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4974 }
4976 MDIO_REG_BANK_BAM_NEXT_PAGE,
4977 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4978 reg_val);
4981 /* Enable Cl73 FSM status bits */
4983 MDIO_REG_BANK_CL73_USERB0,
4984 MDIO_CL73_USERB0_CL73_UCTRL,
4987 /* Enable BAM Station Manager*/
4989 MDIO_REG_BANK_CL73_USERB0,
4990 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4991 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4992 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4993 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4995 /* Advertise CL73 link speeds */
4997 MDIO_REG_BANK_CL73_IEEEB1,
4998 MDIO_CL73_IEEEB1_AN_ADV2,
5001 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5004 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5008 MDIO_REG_BANK_CL73_IEEEB1,
5009 MDIO_CL73_IEEEB1_AN_ADV2,
5010 reg_val);
5012 /* CL73 Autoneg Enabled */
5019 MDIO_REG_BANK_CL73_IEEEB0,
5021 }
5023 /* Program SerDes, forced speed */
5027 {
5029 u16 reg_val;
5031 /* Program duplex, disable autoneg and sgmii*/
5033 MDIO_REG_BANK_COMBO_IEEE0,
5036 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5037 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5041 MDIO_REG_BANK_COMBO_IEEE0,
5044 /* Program speed
5045 * - needed only if the speed is greater than 1G (2.5G or 10G)
5046 */
5048 MDIO_REG_BANK_SERDES_DIGITAL,
5050 /* Clearing the speed value before setting the right speed */
5054 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5061 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5063 reg_val |=
5064 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5065 }
5068 MDIO_REG_BANK_SERDES_DIGITAL,
5071 }
5075 {
5079 /* Set extended capabilities */
5085 MDIO_REG_BANK_OVER_1G,
5089 MDIO_REG_BANK_OVER_1G,
5091 }
5095 u16 ieee_fc)
5096 {
5098 u16 val;
5099 /* For AN, we are always publishing full duplex */
5102 MDIO_REG_BANK_COMBO_IEEE0,
5105 MDIO_REG_BANK_CL73_IEEEB1,
5110 MDIO_REG_BANK_CL73_IEEEB1,
5112 }
5116 u8 enable_cl73)
5117 {
5119 u16 mii_control;
5122 /* Enable and restart BAM/CL37 aneg */
5126 MDIO_REG_BANK_CL73_IEEEB0,
5127 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5131 MDIO_REG_BANK_CL73_IEEEB0,
5132 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5134 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5135 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5139 MDIO_REG_BANK_COMBO_IEEE0,
5140 MDIO_COMBO_IEEE0_MII_CONTROL,
5144 mii_control);
5146 MDIO_REG_BANK_COMBO_IEEE0,
5147 MDIO_COMBO_IEEE0_MII_CONTROL,
5149 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5150 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5151 }
5152 }
5157 {
5159 u16 control1;
5161 /* In SGMII mode, the unicore is always slave */
5164 MDIO_REG_BANK_SERDES_DIGITAL,
5165 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5168 /* Set sgmii mode (and not fiber) */
5170 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5171 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5173 MDIO_REG_BANK_SERDES_DIGITAL,
5174 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5175 control1);
5177 /* If forced speed */
5179 /* Set speed, disable autoneg */
5180 u16 mii_control;
5183 MDIO_REG_BANK_COMBO_IEEE0,
5184 MDIO_COMBO_IEEE0_MII_CONTROL,
5187 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5188 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5192 mii_control |=
5193 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5196 mii_control |=
5197 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5200 /* There is nothing to set for 10M */
5203 /* Invalid speed for SGMII */
5207 }
5209 /* Setting the full duplex */
5211 mii_control |=
5212 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5214 MDIO_REG_BANK_COMBO_IEEE0,
5215 MDIO_COMBO_IEEE0_MII_CONTROL,
5216 mii_control);
5219 /* Enable and restart AN */
5221 }
5222 }
5224 /* Link management
5225 */
5228 {
5234 MDIO_REG_BANK_SERDES_DIGITAL,
5235 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5238 MDIO_REG_BANK_SERDES_DIGITAL,
5239 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5245 }
5248 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5249 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5256 }
5258 }
5263 u32 gp_status)
5264 {
5267 u16 pause_result;
5271 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5273 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5276 MDIO_REG_BANK_CL73_IEEEB1,
5277 MDIO_CL73_IEEEB1_AN_ADV1,
5280 MDIO_REG_BANK_CL73_IEEEB1,
5281 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5290 MDIO_REG_BANK_COMBO_IEEE0,
5291 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5294 MDIO_REG_BANK_COMBO_IEEE0,
5295 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5302 }
5305 }
5310 u32 gp_status)
5311 {
5315 /* Resolve from gp_status in case of AN complete and not sgmii */
5317 /* Update the advertised flow-controled of LD/LP in AN */
5320 /* But set the flow-control result as the requested one */
5329 }
5331 }
5333 }
5337 {
5341 /* Step 1: Make sure signal is detected */
5343 MDIO_REG_BANK_RX0,
5344 MDIO_RX0_RX_STATUS,
5351 MDIO_REG_BANK_CL73_IEEEB0,
5352 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5353 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5355 }
5356 /* Step 2: Check CL73 state machine */
5358 MDIO_REG_BANK_CL73_USERB0,
5359 MDIO_CL73_USERB0_CL73_USTAT1,
5363 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5365 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5369 }
5370 /* Step 3: Check CL37 Message Pages received to indicate LP
5371 * supports only CL37
5372 */
5374 MDIO_REG_BANK_REMOTE_PHY,
5375 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5379 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5381 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5384 cl37_fsm_received);
5386 }
5387 /* The combined cl37/cl73 fsm state information indicating that
5388 * we are connected to a device which does not support cl73, but
5389 * does support cl37 BAM. In this case we disable cl73 and
5390 * restart cl37 auto-neg
5391 */
5393 /* Disable CL73 */
5395 MDIO_REG_BANK_CL73_IEEEB0,
5396 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5398 /* Restart CL37 autoneg */
5401 }
5406 u32 gp_status)
5407 {
5410 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5414 LINK_STATUS_PARALLEL_DETECTION_USED;
5415 }
5419 u16 is_link_up,
5420 u16 speed_mask,
5421 u16 is_duplex)
5422 {
5437 else
5445 else
5454 else
5462 else
5470 speed_mask);
5489 speed_mask);
5491 }
5500 }
5504 }
5509 {
5515 /* Read gp_status */
5517 MDIO_REG_BANK_GP_STATUS,
5518 MDIO_GP_STATUS_TOP_AN_STATUS1,
5528 duplex);
5537 gp_status);
5538 }
5542 /* Check signal is detected */
5544 }
5545 }
5547 /* Read LP advertised speeds*/
5550 u16 val;
5557 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5559 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5561 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5568 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5571 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5572 }
5577 }
5582 {
5584 u8 lane;
5588 /* Read gp_status */
5590 u16 temp_link_up;
5604 /* Check for either KR or generic link up. */
5611 /* Check Autoneg complete */
5613 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5617 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5619 /* Check parallel detect used */
5621 MDIO_WC_REG_PAR_DET_10G_STATUS,
5625 LINK_STATUS_PARALLEL_DETECTION_USED;
5626 }
5628 }
5629 }
5633 u16 val;
5640 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5642 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5644 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5651 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5654 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5656 }
5665 }
5674 duplex);
5679 }
5681 {
5684 u16 lp_up2;
5685 u16 tx_driver;
5686 u16 bank;
5688 /* Read precomp */
5690 MDIO_REG_BANK_OVER_1G,
5693 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5695 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5696 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5704 bank,
5707 /* Replace tx_driver bits [15:12] */
5713 bank,
5715 }
5716 }
5717 }
5721 {
5728 EMAC_REG_EMAC_MODE,
5730 EMAC_MODE_PORT_MII_10M |
5731 EMAC_MODE_HALF_DUPLEX));
5750 /* 10G not valid for EMAC */
5754 }
5760 mode);
5764 }
5768 {
5776 bank,
5777 MDIO_RX0_RX_EQ_BOOST,
5779 }
5784 bank,
5785 MDIO_TX0_TX_DRIVER,
5787 }
5788 }
5793 {
5800 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5803 /* Forced speed requested? */
5809 /* Disable autoneg */
5812 /* Program speed and duplex */
5818 /* AN enabled */
5821 /* Program duplex & pause advertisement (for aneg) */
5825 /* Enable autoneg */
5828 /* Enable and restart AN */
5830 }
5836 }
5837 }
5842 {
5850 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5852 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5855 else
5864 /* Reset the SerDes and wait for reset bit return low */
5869 /* Setting the masterLn_def again after the reset */
5873 }
5876 }
5881 {
5883 /* Wait for soft reset to get cleared up to 1 sec */
5888 else
5890 MDIO_PMA_DEVAD,
5895 }
5903 }
5906 {
5908 u32 mask;
5911 /* Setting the status to report on link up for either XGXS or SerDes */
5918 NIG_MASK_XGXS0_LINK_STATUS);
5922 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5925 }
5932 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5935 }
5936 }
5939 mask);
5951 }
5954 u8 exp_mi_int)
5955 {
5958 /* Disable the MI INT ( external phy int ) by writing 1 to the
5959 * status register. Link down indication is high-active-signal,
5960 * so in this case we need to write the status to clear the XOR
5961 */
5962 /* Read Latched signals */
5966 /* Handle only those with latched-signal=up.*/
5969 NIG_REG_STATUS_INTERRUPT_PORT0
5971 NIG_STATUS_EMAC0_MI_INT);
5972 else
5974 NIG_REG_STATUS_INTERRUPT_PORT0
5976 NIG_STATUS_EMAC0_MI_INT);
5980 /* For all latched-signal=up : Re-Arm Latch signals */
5983 }
5984 /* For all latched-signal=up,Write original_signal to status */
5985 }
5989 {
5992 u32 mask;
5993 /* First reset all status we assume only one line will be
5994 * change at a time
5995 */
5998 NIG_STATUS_XGXS0_LINK_STATUS |
5999 NIG_STATUS_SERDES0_LINK_STATUS));
6007 /* Disable the link interrupt by writing 1 to
6008 * the relevant lane in the status register
6009 */
6010 u32 ser_lane =
6012 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6013 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6015 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6018 }
6020 mask);
6023 mask);
6024 }
6025 }
6028 {
6032 u8 digit;
6035 /* Need more than 10chars for this format */
6039 }
6049 else
6052 str_ptr++;
6057 str_ptr++;
6060 }
6061 }
6063 }
6067 {
6071 }
6074 u16 len)
6075 {
6085 /* Extract first external phy*/
6091 ver_p,
6094 }
6100 ver_p++;
6101 remain_len--;
6103 spirom_ver,
6104 ver_p,
6107 }
6108 }
6111 }
6115 {
6125 /* Change the uni_phy_addr in the nig */
6131 }
6145 /* Set aer mmd back */
6149 /* And md_devad */
6151 md_devad);
6152 }
6154 u16 mii_ctrl;
6163 mii_ctrl |
6164 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6165 }
6166 }
6170 {
6174 u8 phy_idx;
6175 u32 tmp;
6181 /* In case */
6186 }
6187 }
6194 SHARED_HW_CFG_LED_MAC1);
6198 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6200 EMAC_LED_100MB_OVERRIDE |
6201 EMAC_LED_10MB_OVERRIDE);
6202 else
6209 /* For all other phys, OPER mode is same as ON, so in case
6210 * link is down, do nothing
6211 */
6216 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6218 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6220 /* This is a work-around for E2+8727 Configurations */
6229 /* Return here without enabling traffic
6230 * LED blink and setting rate in ON mode.
6231 * In oper mode, enabling LED blink
6232 * and setting rate is needed.
6233 */
6236 }
6238 /* This is a work-around for HW issue found when link
6239 * is up in CL73
6240 */
6250 else
6252 hw_led_mode);
6254 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6260 /* Break here; otherwise, it'll disable the
6261 * intended override.
6262 */
6266 hw_led_mode);
6269 /* Set blinking rate to ~15.9Hz */
6272 LED_BLINK_RATE_VAL_E3);
6273 else
6275 LED_BLINK_RATE_VAL_E1X_E2);
6287 /* For speeds less than 10G LED scheme is different */
6294 }
6300 mode);
6302 }
6305 }
6307 /* This function comes to reflect the actual link state read DIRECTLY from the
6308 * HW
6309 */
6311 u8 is_serdes)
6312 {
6320 u16 link_up;
6323 /* Check 20G link */
6330 /* Check 10G link and below*/
6333 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6338 }
6343 MDIO_REG_BANK_GP_STATUS,
6344 MDIO_GP_STATUS_TOP_AN_STATUS1,
6346 /* Link is up only if both local phy and external phy are up */
6349 }
6350 /* In XGXS loopback mode, do not check external PHY */
6356 /* No external PHY */
6365 phy_index++) {
6367 ETH_PHY_SFPP_10G_FIBER) ||
6369 ETH_PHY_SFP_1G_FIBER) ||
6371 ETH_PHY_XFP_FIBER) ||
6373 ETH_PHY_DA_TWINAX));
6378 ext_phy_link_up |=
6382 }
6383 }
6385 }
6389 }
6393 {
6397 /* In case of external phy existence, the line speed would be the
6398 * line speed linked up by the external phy. In case it is direct
6399 * only, then the line_speed during initialization will be
6400 * equal to the req_line_speed
6401 */
6404 /* Initialize the internal phy in case this is a direct board
6405 * (no external phys), or this board has external phy which requires
6406 * to first.
6407 */
6410 /* init ext phy and enable link state int */
6424 params,
6425 vars);
6426 }
6428 /* Init external phy*/
6431 SUPPORTED_FIBRE)
6435 phy_index++) {
6436 /* No need to initialize second phy in case of first
6437 * phy only selection. In case of second phy, we do
6438 * need to initialize the first phy, since they are
6439 * connected.
6440 */
6442 SUPPORTED_FIBRE)
6447 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6451 }
6455 }
6456 }
6457 /* Reset the interrupt indication after phy was initialized */
6461 NIG_STATUS_XGXS0_LINK_STATUS |
6462 NIG_STATUS_SERDES0_LINK_STATUS |
6463 NIG_MASK_MI_INT));
6465 }
6469 {
6470 /* Reset the SerDes/XGXS */
6473 }
6477 {
6479 u8 gpio_port;
6480 /* HW reset */
6483 else
6486 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6487 gpio_port);
6489 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6490 gpio_port);
6492 }
6496 {
6503 /* Indicate no mac active */
6506 /* Update shared memory */
6508 LINK_STATUS_LINK_UP |
6509 LINK_STATUS_PHYSICAL_LINK_FLAG |
6510 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6511 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6512 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6513 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6514 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6515 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6519 /* Activate nig drain */
6522 /* Disable emac */
6527 /* Reset BigMac/Xmac */
6532 MISC_REGISTERS_RESET_REG_2_CLEAR,
6534 }
6536 /* Prevent LPI Generation by chip */
6543 SHMEM_EEE_ACTIVE_BIT);
6548 }
6551 }
6555 u8 link_10g)
6556 {
6562 LINK_STATUS_PHYSICAL_LINK_FLAG);
6567 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6571 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6580 }
6594 }
6595 }
6605 }
6613 /* AN complete? */
6615 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6619 }
6620 }
6622 /* PBF - link up */
6627 /* Disable drain */
6630 /* Update shared memory */
6633 /* Check remote fault */
6638 }
6639 }
6642 }
6643 /* The bnx2x_link_update function should be called upon link
6644 * interrupt.
6645 * Link is considered up as follows:
6646 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6647 * to be up
6648 * - SINGLE_MEDIA - The link between the 577xx and the external
6649 * phy (XGXS) need to up as well as the external link of the
6650 * phy (PHY_EXT1)
6651 * - DUAL_MEDIA - The link between the 577xx and the first
6652 * external phy needs to be up, and at least one of the 2
6653 * external phy link must be up.
6654 */
6656 {
6668 phy_index++) {
6676 /* different consideration, since vars holds inner state */
6678 }
6691 is_mi_int,
6698 /* Disable emac */
6702 /* Step 1:
6703 * Check external link change only for external phys, and apply
6704 * priority selection between them in case the link on both phys
6705 * is up. Note that instead of the common vars, a temporary
6706 * vars argument is used since each phy may have different link/
6707 * speed/duplex result
6708 */
6710 phy_index++) {
6714 /* Read link status and params of this ext phy */
6719 phy_index);
6722 phy_index);
6724 }
6733 /* In this option, the first PHY makes sure to pass the
6734 * traffic through itself only.
6735 * Its not clear how to reset the link on the second phy
6736 */
6740 /* In this option, the first PHY makes sure to pass the
6741 * traffic through the second PHY.
6742 */
6746 /* Link indication on both PHYs with the following cases
6747 * is invalid:
6748 * - FIRST_PHY means that second phy wasn't initialized,
6749 * hence its link is expected to be down
6750 * - SECOND_PHY means that first phy should not be able
6751 * to link up by itself (using configuration)
6752 * - DEFAULT should be overriden during initialiazation
6753 */
6759 }
6760 }
6761 }
6763 /* Step 2:
6764 * Read the status of the internal phy. In case of
6765 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6766 * otherwise this is the link between the 577xx and the first
6767 * external phy
6768 */
6773 /* The INT_PHY flow control reside in the vars. This include the
6774 * case where the speed or flow control are not set to AUTO.
6775 * Otherwise, the active external phy flow control result is set
6776 * to the vars. The ext_phy_line_speed is needed to check if the
6777 * speed is different between the internal phy and external phy.
6778 * This case may be result of intermediate link speed change.
6779 */
6782 /* Link speed is taken from the XGXS. AN and FC result from
6783 * the external phy.
6784 */
6787 /* if active_external_phy is first PHY and link is up - disable
6788 * disable TX on second external PHY
6789 */
6797 }
6798 }
6803 SUPPORTED_FIBRE)
6805 else
6811 active_external_phy);
6812 }
6815 phy_index++) {
6817 FLAGS_REARM_LATCH_SIGNAL) {
6819 phy_index ==
6820 active_external_phy);
6822 }
6823 }
6827 /* Upon link speed change set the NIG into drain mode. Comes to
6828 * deals with possible FIFO glitch due to clk change when speed
6829 * is decreased without link down indicator
6830 */
6836 " different than the external"
6838 ext_phy_line_speed);
6844 }
6845 }
6847 /* Anything 10 and over uses the bmac */
6852 /* In case external phy link is up, and internal link is down
6853 * (not initialized yet probably after link initialization, it
6854 * needs to be initialized.
6855 * Note that after link down-up as result of cable plug, the xgxs
6856 * link would probably become up again without the need
6857 * initialize it
6858 */
6864 FLAGS_INIT_XGXS_FIRST);
6866 FLAGS_INIT_XGXS_FIRST)
6871 else
6877 vars);
6878 }
6879 }
6880 /* Link is up only if both local phy and external phy (in case of
6881 * non-direct board) are up and no fault detected on active PHY.
6882 */
6888 /* Update the PFC configuration in case it was changed */
6891 else
6896 else
6899 /* Update MCP link status was changed */
6904 }
6906 /*****************************************************************************/
6907 /* External Phy section */
6908 /*****************************************************************************/
6910 {
6916 }
6920 {
6926 }
6930 u8 port)
6931 {
6940 }
6945 {
6946 u16 val;
6948 MDIO_AN_DEVAD,
6951 MDIO_AN_DEVAD,
6957 }
6959 /******************************************************************/
6960 /* common BCM8073/BCM8727 PHY SECTION */
6961 /******************************************************************/
6965 {
6971 }
6975 u16 pause_result;
6979 MDIO_AN_DEVAD,
6983 MDIO_AN_DEVAD,
6992 pause_result);
6993 }
6994 }
6997 u8 port)
6998 {
7003 /* Boot port from external ROM */
7004 /* EDC grst */
7006 MDIO_PMA_DEVAD,
7007 MDIO_PMA_REG_GEN_CTRL,
7010 /* Ucode reboot and rst */
7012 MDIO_PMA_DEVAD,
7013 MDIO_PMA_REG_GEN_CTRL,
7017 MDIO_PMA_DEVAD,
7020 /* Reset internal microprocessor */
7022 MDIO_PMA_DEVAD,
7023 MDIO_PMA_REG_GEN_CTRL,
7024 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7026 /* Release srst bit */
7028 MDIO_PMA_DEVAD,
7029 MDIO_PMA_REG_GEN_CTRL,
7030 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7032 /* Delay 100ms per the PHY specifications */
7035 /* 8073 sometimes taking longer to download */
7037 count++;
7040 "bnx2x_8073_8727_external_rom_boot port %x:"
7045 }
7048 MDIO_PMA_DEVAD,
7051 MDIO_PMA_DEVAD,
7057 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7059 /* Clear ser_boot_ctl bit */
7061 MDIO_PMA_DEVAD,
7066 "bnx2x_8073_8727_external_rom_boot port %x:"
7071 }
7073 /******************************************************************/
7074 /* BCM8073 PHY SECTION */
7075 /******************************************************************/
7077 {
7078 /* This is only required for 8073A1, version 102 only */
7079 u16 val;
7081 /* Read 8073 HW revision*/
7083 MDIO_PMA_DEVAD,
7087 /* No need to workaround in 8073 A1 */
7089 }
7092 MDIO_PMA_DEVAD,
7095 /* SNR should be applied only for version 0x102 */
7100 }
7103 {
7107 MDIO_PMA_DEVAD,
7111 /* No need to workaround in 8073 A1 */
7113 }
7114 /* XAUI workaround in 8073 A0: */
7116 /* After loading the boot ROM and restarting Autoneg, poll
7117 * Dev1, Reg $C820:
7118 */
7122 MDIO_PMA_DEVAD,
7123 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7125 /* If bit [14] = 0 or bit [13] = 0, continue on with
7126 * system initialization (XAUI work-around not required, as
7127 * these bits indicate 2.5G or 1G link up).
7128 */
7134 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7135 * MSB (bit15) goes to 1 (indicating that the XAUI
7136 * workaround has completed), then continue on with
7137 * system initialization.
7138 */
7141 MDIO_PMA_DEVAD,
7147 }
7149 }
7151 }
7153 }
7156 }
7159 {
7160 /* Force KR or KX */
7169 }
7174 {
7175 u16 cl37_val;
7181 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7184 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7185 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7187 }
7189 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7190 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7192 }
7194 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7195 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7197 }
7204 }
7209 {
7212 u8 gpio_port;
7217 else
7219 /* Restore normal power mode*/
7226 /* Enable LASI */
7242 /* Swap polarity if required - Must be done only in non-1G mode */
7244 /* Configure the 8073 to swap _P and _N of the KR lines */
7246 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7248 MDIO_PMA_DEVAD,
7251 MDIO_PMA_DEVAD,
7252 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7254 }
7257 /* Enable CL37 BAM */
7261 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7264 MDIO_AN_DEVAD,
7267 MDIO_AN_DEVAD,
7270 }
7278 }
7284 /* Note that 2.5G works only when used with 1G
7285 * advertisement
7286 */
7292 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7295 /* Note that 2.5G works only when used with 1G advertisement */
7298 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7301 }
7309 u16 phy_ver;
7310 /* Allow 2.5G for A1 and above */
7317 else
7322 }
7325 /* Add support for CL37 (passive mode) II */
7332 /* Add support for CL37 (passive mode) III */
7335 /* The SNR will improve about 2db by changing BW and FEE main
7336 * tap. Rest commands are executed after link is up
7337 * Change FFE main cursor to 5 in EDC register
7338 */
7344 /* Enable FEC (Forware Error Correction) Request in the AN */
7351 /* Restart autoneg */
7357 }
7362 {
7374 /* Clear the interrupt LASI status register */
7380 /* Clear MSG-OUT */
7384 /* Check the LASI */
7390 /* Check the link status */
7406 }
7412 /* Check the link status on 1.1.2 */
7422 /* The SNR will improve about 2dbby changing the BW and FEE main
7423 * tap. The 1st write to change FFE main tap is set before
7424 * restart AN. Change PLL Bandwidth in EDC register
7425 */
7430 /* Change CDR Bandwidth in EDC register */
7434 }
7439 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7459 }
7462 /* Swap polarity if required */
7464 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7465 /* Configure the 8073 to swap P and N of the KR lines */
7467 MDIO_XS_DEVAD,
7469 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7470 * when it`s in 10G mode.
7471 */
7480 MDIO_XS_DEVAD,
7481 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7482 val1);
7483 }
7487 }
7495 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7498 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7499 }
7502 }
7506 {
7508 u8 gpio_port;
7511 else
7514 gpio_port);
7516 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7517 gpio_port);
7518 }
7520 /******************************************************************/
7521 /* BCM8705 PHY SECTION */
7522 /******************************************************************/
7526 {
7529 /* Restore normal power mode*/
7532 /* HW reset */
7545 /* BCM8705 doesn't have microcode, hence the 0 */
7548 }
7553 {
7579 }
7581 }
7583 /******************************************************************/
7584 /* SFP+ module Section */
7585 /******************************************************************/
7588 u8 pmd_dis)
7589 {
7591 /* Disable transmitter only for bootcodes which can enable it afterwards
7592 * (for D3 link)
7593 */
7596 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7601 }
7605 MDIO_PMA_DEVAD,
7607 }
7610 {
7611 u8 gpio_port;
7616 else
7621 }
7625 u8 tx_en)
7626 {
7627 u16 val;
7630 u32 tx_en_mode;
7632 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7636 PORT_HW_CFG_TX_LASER_MASK;
7643 MDIO_PMA_DEVAD,
7644 MDIO_PMA_REG_PHY_IDENTIFIER,
7649 else
7653 MDIO_PMA_DEVAD,
7654 MDIO_PMA_REG_PHY_IDENTIFIER,
7655 val);
7661 {
7662 u16 gpio_pin;
7666 else
7673 }
7677 }
7678 }
7682 u8 tx_en)
7683 {
7688 else
7690 }
7695 {
7698 u16 i;
7703 }
7704 /* Set the read command byte count */
7709 /* Set the read command address */
7712 addr);
7714 /* Activate read command */
7719 /* Wait up to 500us for command complete status */
7722 MDIO_PMA_DEVAD,
7725 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7728 }
7731 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7736 }
7738 /* Read the buffer */
7741 MDIO_PMA_DEVAD,
7744 }
7748 MDIO_PMA_DEVAD,
7751 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7754 }
7756 }
7760 u8 power)
7761 {
7762 u32 pin_cfg;
7768 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7769 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7775 /* Low ==> corresponding SFP+ module is powered
7776 * high ==> the SFP+ module is powered down
7777 */
7779 }
7784 {
7788 u16 addr32;
7795 }
7797 /* 4 byte aligned address */
7802 /* Note that 100us are not enough here */
7805 }
7807 data_array);
7813 j++;
7814 }
7815 }
7818 }
7823 {
7831 }
7833 /* Need to read from 1.8000 to clear it */
7835 MDIO_PMA_DEVAD,
7836 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7839 /* Set the read command byte count */
7841 MDIO_PMA_DEVAD,
7842 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7845 /* Set the read command address */
7847 MDIO_PMA_DEVAD,
7848 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7849 addr);
7850 /* Set the destination address */
7852 MDIO_PMA_DEVAD,
7854 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7856 /* Activate read command */
7858 MDIO_PMA_DEVAD,
7859 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7861 /* Wait appropriate time for two-wire command to finish before
7862 * polling the status register
7863 */
7866 /* Wait up to 500us for command complete status */
7869 MDIO_PMA_DEVAD,
7872 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7875 }
7878 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7883 }
7885 /* Read the buffer */
7888 MDIO_PMA_DEVAD,
7891 }
7895 MDIO_PMA_DEVAD,
7898 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7901 }
7904 }
7909 {
7925 }
7927 }
7932 {
7939 /* First check for copper cable */
7941 params,
7942 SFP_EEPROM_CON_TYPE_ADDR,
7947 }
7951 {
7952 u8 copper_module_type;
7954 /* Check if its active cable (includes SFP+ module)
7955 * of passive cable
7956 */
7958 params,
7959 SFP_EEPROM_FC_TX_TECH_ADDR,
7963 "Failed to read copper-cable-type"
7966 }
7969 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7973 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7977 EDC_MODE_PASSIVE_DAC;
7981 copper_module_type);
7983 }
7985 }
7989 SFP_EEPROM_COMP_CODE_LR_MASK |
8001 }
8002 }
8005 }
8011 }
8016 /* Update media type for non-PMF sync */
8022 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8025 }
8026 }
8031 params,
8032 SFP_EEPROM_OPTIONS_ADDR,
8033 SFP_EEPROM_OPTIONS_SIZE,
8038 }
8041 else
8043 }
8046 }
8047 /* This function read the relevant field from the module (SFP+), and verify it
8048 * is compliant with this board
8049 */
8052 {
8063 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8066 }
8069 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8070 /* Use specific phy request */
8073 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8074 /* Use first phy request only in case of non-dual media*/
8079 }
8082 /* No support in OPT MDL detection */
8086 }
8093 }
8095 /* Format the warning message */
8097 params,
8098 SFP_EEPROM_VENDOR_NAME_ADDR,
8099 SFP_EEPROM_VENDOR_NAME_SIZE,
8102 else
8105 params,
8106 SFP_EEPROM_PART_NO_ADDR,
8107 SFP_EEPROM_PART_NO_SIZE,
8110 else
8117 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8120 }
8125 {
8126 u8 val;
8128 u16 timeout;
8129 /* Initialization time after hot-plug may take up to 300ms for
8130 * some phys type ( e.g. JDSU )
8131 */
8140 }
8142 }
8144 }
8148 u8 is_power_up) {
8149 /* Make sure GPIOs are not using for LED mode */
8150 u16 val;
8151 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8152 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8153 * output
8154 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8155 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8156 * where the 1st bit is the over-current(only input), and 2nd bit is
8157 * for power( only output )
8158 *
8159 * In case of NOC feature is disabled and power is up, set GPIO control
8160 * as input to enable listening of over-current indication
8161 */
8166 else
8167 /* Set GPIO control to OUTPUT, and set the power bit
8168 * to according to the is_power_up
8169 */
8173 MDIO_PMA_DEVAD,
8174 MDIO_PMA_REG_8727_GPIO_CTRL,
8175 val);
8176 }
8180 u16 edc_mode)
8181 {
8182 u16 cur_limiting_mode;
8185 MDIO_PMA_DEVAD,
8186 MDIO_PMA_REG_ROM_VER2,
8189 cur_limiting_mode);
8194 MDIO_PMA_DEVAD,
8195 MDIO_PMA_REG_ROM_VER2,
8196 EDC_MODE_LIMITING);
8201 /* Changing to LRM mode takes quite few seconds. So do it only
8202 * if current mode is limiting (default is LRM)
8203 */
8208 MDIO_PMA_DEVAD,
8209 MDIO_PMA_REG_LRM_MODE,
8212 MDIO_PMA_DEVAD,
8213 MDIO_PMA_REG_ROM_VER2,
8216 MDIO_PMA_DEVAD,
8217 MDIO_PMA_REG_MISC_CTRL0,
8220 MDIO_PMA_DEVAD,
8221 MDIO_PMA_REG_LRM_MODE,
8223 }
8225 }
8229 u16 edc_mode)
8230 {
8231 u16 phy_identifier;
8232 u16 rom_ver2_val;
8234 MDIO_PMA_DEVAD,
8235 MDIO_PMA_REG_PHY_IDENTIFIER,
8239 MDIO_PMA_DEVAD,
8240 MDIO_PMA_REG_PHY_IDENTIFIER,
8244 MDIO_PMA_DEVAD,
8245 MDIO_PMA_REG_ROM_VER2,
8247 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8249 MDIO_PMA_DEVAD,
8250 MDIO_PMA_REG_ROM_VER2,
8254 MDIO_PMA_DEVAD,
8255 MDIO_PMA_REG_PHY_IDENTIFIER,
8259 }
8263 u32 action)
8264 {
8277 action);
8279 }
8280 }
8283 u8 gpio_mode)
8284 {
8290 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8298 {
8301 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8306 }
8310 fault_led_gpio);
8311 }
8312 }
8315 u8 gpio_mode)
8316 {
8317 u32 pin_cfg;
8323 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8324 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8328 }
8331 u8 gpio_mode)
8332 {
8336 /* Low ==> if SFP+ module is supported otherwise
8337 * High ==> if SFP+ module is not on the approved vendor list
8338 */
8342 }
8346 {
8349 /* Put Warpcore in low power mode */
8352 /* Put LCPLL in low power mode */
8356 }
8360 u8 power)
8361 {
8375 }
8376 }
8379 u16 edc_mode)
8380 {
8386 /* This is a global register which controls all lanes */
8401 }
8406 /* A must read */
8410 /* Restart microcode to re-read the new mode */
8414 }
8418 u16 edc_mode)
8419 {
8431 }
8432 }
8436 {
8438 u16 edc_mode;
8447 /* Power up module */
8453 /* Check SFP+ module compatibility */
8456 /* Turn on fault module-detected led */
8458 MISC_REGISTERS_GPIO_HIGH);
8460 /* Check if need to power down the SFP+ module */
8462 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8466 }
8468 /* Turn off fault module-detected led */
8470 }
8472 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8473 * is done automatically
8474 */
8477 /* Enable transmit for this module if the module is approved, or
8478 * if unapproved modules should also enable the Tx laser
8479 */
8482 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8484 else
8488 }
8491 {
8494 u32 gpio_val;
8498 else
8506 }
8508 /* Set valid module led off */
8511 /* Get current gpio val reflecting module plugged in / out*/
8514 /* Call the handling function in case module is detected */
8521 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8522 gpio_port);
8526 u16 rx_tx_in_reset;
8527 /* In case WC is out of reset, reconfigure the
8528 * link speed while taking into account 1G
8529 * module limitation.
8530 */
8532 MDIO_WC_DEVAD,
8533 MDIO_WC_REG_DIGITAL5_MISC6,
8539 }
8540 }
8543 }
8548 config));
8550 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8551 gpio_port);
8552 /* Module was plugged out.
8553 * Disable transmit for this module
8554 */
8557 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8560 }
8561 }
8563 /******************************************************************/
8564 /* Used by 8706 and 8727 */
8565 /******************************************************************/
8568 u16 alarm_status_offset,
8569 u16 alarm_ctrl_offset)
8570 {
8578 /* Mask or enable the fault event. */
8582 else
8585 }
8586 /******************************************************************/
8587 /* common BCM8706/BCM8726 PHY SECTION */
8588 /******************************************************************/
8592 {
8597 /* Clear RX Alarm*/
8602 MDIO_PMA_LASI_TXCTRL);
8604 /* Clear LASI indication*/
8622 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8623 * are set, or if the autoneg bit 1 is set
8624 */
8629 else
8633 }
8635 /* Capture 10G link fault. Read twice to clear stale value. */
8643 }
8646 }
8648 /******************************************************************/
8649 /* BCM8706 PHY SECTION */
8650 /******************************************************************/
8654 {
8655 u32 tx_en_mode;
8661 /* HW reset */
8666 /* Wait until fw is loaded */
8673 }
8676 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8677 u8 i;
8678 u16 reg;
8682 MDIO_XS_8706_REG_BANK_RX0);
8684 /* Clear first 3 bits of the control */
8686 /* Set control bits according to configuration */
8691 }
8692 }
8693 /* Force speed */
8698 MDIO_PMA_DEVAD,
8703 /* Arm LASI for link and Tx fault. */
8707 /* Force 1Gbps using autoneg with 1G advertisement */
8709 /* Allow CL37 through CL73 */
8714 /* Enable Full-Duplex advertisement on CL37 */
8717 /* Enable CL37 AN */
8720 /* 1G support */
8724 /* Enable clause 73 AN */
8733 }
8736 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8737 * power mode, if TX Laser is disabled
8738 */
8752 }
8755 }
8760 {
8762 }
8764 /******************************************************************/
8765 /* BCM8726 PHY SECTION */
8766 /******************************************************************/
8769 {
8773 }
8777 {
8779 /* Need to wait 100ms after reset */
8782 /* Micro controller re-boot */
8786 /* Set soft reset */
8788 MDIO_PMA_DEVAD,
8789 MDIO_PMA_REG_GEN_CTRL,
8790 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8793 MDIO_PMA_DEVAD,
8797 MDIO_PMA_DEVAD,
8798 MDIO_PMA_REG_GEN_CTRL,
8799 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8801 /* Wait for 150ms for microcode load */
8804 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8806 MDIO_PMA_DEVAD,
8811 }
8816 {
8818 u16 val1;
8828 }
8829 }
8831 }
8837 {
8846 /* Need to call module detected on initialization since the module
8847 * detection triggered by actual module insertion might occur before
8848 * driver is loaded, and when driver is loaded, it reset all
8849 * registers, including the transmitter
8850 */
8866 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8868 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8869 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8871 /* Set Flow control */
8883 /* Enable RX-ALARM control to receive interrupt for 1G speed
8884 * change
8885 */
8895 }
8897 /* Set TX PreEmphasis if needed */
8899 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8905 MDIO_PMA_DEVAD,
8906 MDIO_PMA_REG_8726_TX_CTRL1,
8910 MDIO_PMA_DEVAD,
8911 MDIO_PMA_REG_8726_TX_CTRL2,
8913 }
8917 }
8921 {
8924 /* Set serial boot control for external load */
8926 MDIO_PMA_DEVAD,
8928 }
8930 /******************************************************************/
8931 /* BCM8727 PHY SECTION */
8932 /******************************************************************/
8936 {
8940 u16 val;
8941 /* Only NOC flavor requires to set the LED specifically */
8958 }
8960 MDIO_PMA_DEVAD,
8961 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8966 MDIO_PMA_DEVAD,
8967 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8968 val);
8970 MDIO_PMA_DEVAD,
8971 MDIO_PMA_REG_8727_GPIO_CTRL,
8976 MDIO_PMA_DEVAD,
8977 MDIO_PMA_REG_8727_GPIO_CTRL,
8978 val);
8979 }
8983 u8 port;
8984 /* The PHY reset is controlled by GPIO 1. Fake the port number
8985 * to cancel the swap done in set_gpio()
8986 */
8993 }
8997 {
9000 /* Set option 1G speed */
9011 /* Power down the XAUI until link is up in case of dual-media
9012 * and 1G
9013 */
9016 MDIO_PMA_DEVAD,
9020 MDIO_PMA_DEVAD,
9022 }
9025 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9027 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9028 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9036 /* Since the 8727 has only single reset pin, need to set the 10G
9037 * registers although it is default
9038 */
9049 }
9050 }
9055 {
9056 u32 tx_en_mode;
9058 u16 rx_alarm_ctrl_val;
9059 u16 lasi_ctrl_val;
9061 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9065 /* Should be 0x6 to enable XS on Tx side. */
9069 /* Enable LASI */
9072 rx_alarm_ctrl_val);
9079 /* Initially configure MOD_ABS to interrupt when module is
9080 * presence( bit 8)
9081 */
9084 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9085 * When the EDC is off it locks onto a reference clock and avoids
9086 * becoming 'lost'
9087 */
9095 /* Enable/Disable PHY transmitter output */
9098 /* Make MOD_ABS give interrupt on change */
9105 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9106 * status which reflect SFP+ module over-current
9107 */
9122 /* Set 2-wire transfer rate of SFP+ module EEPROM
9123 * to 100Khz since some DACs(direct attached cables) do
9124 * not work at 400Khz.
9125 */
9130 /* Set TX PreEmphasis if needed */
9132 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9143 }
9145 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9146 * power mode, if TX Laser is disabled
9147 */
9168 }
9171 }
9175 {
9181 config));
9183 MDIO_PMA_DEVAD,
9187 /* Module is absent */
9191 /* 1. Set mod_abs to detect next module
9192 * presence event
9193 * 2. Set EDC off by setting OPTXLOS signal input to low
9194 * (bit 9).
9195 * When the EDC is off it locks onto a reference clock and
9196 * avoids becoming 'lost'.
9197 */
9202 MDIO_PMA_DEVAD,
9205 /* Clear RX alarm since it stays up as long as
9206 * the mod_abs wasn't changed
9207 */
9209 MDIO_PMA_DEVAD,
9213 /* Module is present */
9216 /* First disable transmitter, and if the module is ok, the
9217 * module_detection will enable it
9218 * 1. Set mod_abs to detect next module absent event ( bit 8)
9219 * 2. Restore the default polarity of the OPRXLOS signal and
9220 * this signal will then correctly indicate the presence or
9221 * absence of the Rx signal. (bit 9)
9222 */
9227 MDIO_PMA_DEVAD,
9230 /* Clear RX alarm since it stays up as long as the mod_abs
9231 * wasn't changed. This is need to be done before calling the
9232 * module detection, otherwise it will clear* the link update
9233 * alarm
9234 */
9236 MDIO_PMA_DEVAD,
9241 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9246 else
9249 /* Reconfigure link speed based on module type limitations */
9251 }
9254 rx_alarm_status);
9255 /* No need to check link status in case of module plugged in/out */
9256 }
9262 {
9268 /* If PHY is not initialized, do not check link status */
9275 /* Check the LASI on Rx */
9283 MDIO_PMA_LASI_TXCTRL);
9290 /* Clear MSG-OUT */
9294 /* If a module is present and there is need to check
9295 * for over current
9296 */
9298 /* Check over-current using 8727 GPIO0 input*/
9308 oc_port);
9310 "been detected and the power to "
9311 "that SFP+ module has been removed "
9312 "to prevent failure of the card. "
9313 "Please remove the SFP+ module and "
9314 "restart the system to clear this "
9316 oc_port);
9317 /* Disable all RX_ALARMs except for mod_abs */
9319 MDIO_PMA_DEVAD,
9323 MDIO_PMA_DEVAD,
9325 /* Wait for module_absent_event */
9328 MDIO_PMA_DEVAD,
9330 /* Clear RX alarm */
9332 MDIO_PMA_DEVAD,
9335 }
9338 /* When module absent bit is set, check module */
9341 /* Enable all mod_abs and link detection bits */
9345 }
9353 }
9356 MDIO_PMA_DEVAD,
9359 /* Bits 0..2 --> speed detected,
9360 * Bits 13..15--> link is down
9361 */
9376 }
9378 /* Capture 10G link fault. */
9388 }
9389 }
9395 }
9400 MDIO_PMA_DEVAD,
9402 /* In case of dual-media board and 1G, power up the XAUI side,
9403 * otherwise power it down. For 10G it is done automatically
9404 */
9407 else
9410 MDIO_PMA_DEVAD,
9412 }
9414 }
9418 {
9421 /* Enable/Disable PHY transmitter output */
9424 /* Disable Transmitter */
9426 /* Clear LASI */
9429 }
9431 /******************************************************************/
9432 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9433 /******************************************************************/
9436 u8 port)
9437 {
9445 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9446 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9458 }
9465 }
9468 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9477 }
9484 }
9486 /* lower 16 bits of the register SPI_FW_STATUS */
9488 /* upper 16 bits of register SPI_FW_STATUS */
9493 }
9495 }
9498 {
9501 /* PHYC_CTL_LED_CTL */
9503 MDIO_PMA_DEVAD,
9509 MDIO_PMA_DEVAD,
9513 MDIO_PMA_DEVAD,
9514 MDIO_PMA_REG_8481_LED1_MASK,
9518 MDIO_PMA_DEVAD,
9519 MDIO_PMA_REG_8481_LED2_MASK,
9522 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9524 MDIO_PMA_DEVAD,
9525 MDIO_PMA_REG_8481_LED3_MASK,
9528 /* Select the closest activity blink rate to that in 10/100/1000 */
9530 MDIO_PMA_DEVAD,
9531 MDIO_PMA_REG_8481_LED3_BLINK,
9534 /* Configure the blink rate to ~15.9 Hz */
9536 MDIO_PMA_DEVAD,
9537 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9538 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9542 else
9551 /* 'Interrupt Mask' */
9553 MDIO_AN_DEVAD,
9555 }
9560 {
9565 /* Save spirom version */
9567 }
9568 /* This phy uses the NIG latch mechanism since link indication
9569 * arrives through its LED4 and not via its LASI signal, so we
9570 * get steady signal instead of clear on read
9571 */
9580 /* set 1000 speed advertisement */
9587 MDIO_AN_DEVAD,
9588 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9593 /* Disable forced speed */
9599 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9611 an_1000_val);
9613 /* set 100 speed advertisement */
9617 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9619 /* Enable autoneg and restart autoneg for legacy speeds */
9625 }
9626 /* set 10 speed advertisement */
9630 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9633 SUPPORTED_10baseT_Full)))) {
9639 }
9641 /* Only 10/100 are allowed to work in FORCE mode */
9645 SUPPORTED_100baseT_Full))) {
9647 /* Enabled AUTO-MDIX when autoneg is disabled */
9651 /* The PHY needs this set even for forced link. */
9654 }
9658 SUPPORTED_10baseT_Full))) {
9659 /* Enabled AUTO-MDIX when autoneg is disabled */
9664 }
9668 an_10_100_val);
9673 /* Always write this if this is not 84833.
9674 * For 84833, write it only when it's a forced speed.
9675 */
9679 MDIO_AN_DEVAD,
9684 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9687 /* Restart autoneg for 10G*/
9690 MDIO_AN_DEVAD,
9691 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9694 MDIO_AN_DEVAD,
9695 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9702 MDIO_AN_DEVAD,
9703 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9707 }
9712 {
9714 /* Restore normal power mode*/
9718 /* HW reset */
9724 }
9726 #define PHY84833_CMDHDLR_WAIT 300
9727 #define PHY84833_CMDHDLR_MAX_ARGS 5
9730 u16 fw_cmd,
9732 {
9734 u16 val;
9736 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9738 MDIO_84833_CMD_HDLR_STATUS,
9739 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9746 }
9750 }
9752 /* Prepare argument(s) and issue command */
9757 }
9767 }
9772 }
9773 /* Gather returning data */
9778 }
9780 MDIO_84833_CMD_HDLR_STATUS,
9781 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9783 }
9789 {
9790 u32 pair_swap;
9795 /* Check for configuration. */
9799 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9804 /* Only the second argument is used for this command */
9813 }
9816 u32 shmem_base_path[],
9817 u32 chip_id)
9818 {
9820 u32 idx;
9821 u8 reset_gpios;
9823 /* Assume that these will be GPIOs, not EPIOs. */
9825 /* Map config param to register bit. */
9830 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9831 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9834 }
9837 /* E2, look from diff place of shmem. */
9846 }
9848 }
9851 }
9855 {
9857 u8 reset_gpios;
9860 other_shmem_base_addr));
9864 /* Work around for 84833 LED failure inside RESET status */
9866 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9867 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9869 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9870 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9881 reset_gpios);
9884 }
9888 {
9896 eee_idle);
9902 }
9906 /* eee_idle in 1u --> eee_status in 16u */
9909 SHMEM_EEE_TIME_OUTPUT_BIT;
9914 }
9917 }
9922 {
9929 /* Make Certain LPI is disabled */
9933 /* Prevent Phy from working in EEE and advertising it */
9939 }
9945 }
9950 {
9962 }
9966 /* Mask events preventing LPI generation */
9973 }
9975 #define PHY84833_CONSTANT_LATENCY 1193
9979 {
9982 u16 val;
9991 else
9996 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9997 port);
9999 /* MDIO reset */
10001 MDIO_PMA_DEVAD,
10003 }
10007 /* Wait for GPHY to come out of reset */
10010 /* BCM84823 requires that XGXS links up first @ 10G for normal
10011 * behavior.
10012 */
10013 u16 temp;
10019 }
10024 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10025 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10026 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10027 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10031 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10034 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10035 }
10041 /* Do nothing. Essentially this is like the priority copper */
10050 /* Do nothing here. The first PHY won't be initialized at all */
10056 }
10068 /* Keep AutogrEEEn disabled. */
10075 PHY84833_CMDHDLR_MAX_ARGS);
10078 }
10081 else
10083 /* 84833 PHY has a better feature and doesn't need to support this. */
10088 PORT_HW_CFG_ENABLE_CMS_MASK;
10094 else
10098 }
10103 /* Configure EEE support */
10107 SHMEM_EEE_SUPPORTED_SHIFT;
10108 /* Propogate params' bits --> vars (for migration exposure) */
10111 else
10116 else
10124 }
10131 else
10136 }
10140 }
10143 /* Bring PHY out of super isolate mode as the final step. */
10145 MDIO_CTL_DEVAD,
10149 MDIO_CTL_DEVAD,
10151 }
10153 }
10158 {
10164 /* Check 10G-BaseT link status */
10165 /* Check PMD signal ok */
10173 /* Check link 10G */
10182 /* Enable expansion register 0x42 (Operation mode status) */
10184 MDIO_AN_DEVAD,
10187 /* Get legacy speed operation status */
10189 MDIO_AN_DEVAD,
10190 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10194 legacy_status);
10206 }
10211 else
10218 /* Check legacy speed AN resolution */
10220 MDIO_AN_DEVAD,
10221 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10225 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10227 MDIO_AN_DEVAD,
10228 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10232 LINK_STATUS_PARALLEL_DETECTION_USED;
10233 }
10234 }
10240 /* Read LP advertised speeds */
10245 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10248 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10251 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10254 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10257 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10264 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10267 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10274 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10276 /* Determine if EEE was negotiated */
10287 }
10298 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
10299 }
10300 }
10303 }
10307 {
10309 u32 spirom_ver;
10313 }
10317 {
10322 }
10326 {
10331 }
10335 {
10337 u8 port;
10338 u16 val16;
10342 else
10347 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10348 port);
10351 MDIO_CTL_DEVAD,
10355 MDIO_CTL_DEVAD,
10357 }
10358 }
10362 {
10364 u16 val;
10365 u8 port;
10369 else
10378 SHARED_HW_CFG_LED_EXTPHY1) {
10380 /* Set LED masks */
10382 MDIO_PMA_DEVAD,
10383 MDIO_PMA_REG_8481_LED1_MASK,
10387 MDIO_PMA_DEVAD,
10388 MDIO_PMA_REG_8481_LED2_MASK,
10392 MDIO_PMA_DEVAD,
10393 MDIO_PMA_REG_8481_LED3_MASK,
10397 MDIO_PMA_DEVAD,
10398 MDIO_PMA_REG_8481_LED5_MASK,
10403 MDIO_PMA_DEVAD,
10404 MDIO_PMA_REG_8481_LED1_MASK,
10406 }
10411 port);
10414 SHARED_HW_CFG_LED_EXTPHY1) {
10416 /* Set LED masks */
10418 MDIO_PMA_DEVAD,
10419 MDIO_PMA_REG_8481_LED1_MASK,
10423 MDIO_PMA_DEVAD,
10424 MDIO_PMA_REG_8481_LED2_MASK,
10428 MDIO_PMA_DEVAD,
10429 MDIO_PMA_REG_8481_LED3_MASK,
10433 MDIO_PMA_DEVAD,
10434 MDIO_PMA_REG_8481_LED5_MASK,
10439 MDIO_PMA_DEVAD,
10440 MDIO_PMA_REG_8481_LED1_MASK,
10442 }
10449 SHARED_HW_CFG_LED_EXTPHY1) {
10450 /* Set control reg */
10452 MDIO_PMA_DEVAD,
10453 MDIO_PMA_REG_8481_LINK_SIGNAL,
10459 MDIO_PMA_DEVAD,
10460 MDIO_PMA_REG_8481_LINK_SIGNAL,
10461 val);
10463 /* Set LED masks */
10465 MDIO_PMA_DEVAD,
10466 MDIO_PMA_REG_8481_LED1_MASK,
10470 MDIO_PMA_DEVAD,
10471 MDIO_PMA_REG_8481_LED2_MASK,
10475 MDIO_PMA_DEVAD,
10476 MDIO_PMA_REG_8481_LED3_MASK,
10480 MDIO_PMA_DEVAD,
10481 MDIO_PMA_REG_8481_LED5_MASK,
10485 MDIO_PMA_DEVAD,
10486 MDIO_PMA_REG_8481_LED1_MASK,
10488 }
10496 SHARED_HW_CFG_LED_EXTPHY1) {
10498 /* Set control reg */
10500 MDIO_PMA_DEVAD,
10501 MDIO_PMA_REG_8481_LINK_SIGNAL,
10505 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10509 MDIO_PMA_DEVAD,
10510 MDIO_PMA_REG_8481_LINK_SIGNAL,
10512 }
10514 /* Set LED masks */
10516 MDIO_PMA_DEVAD,
10517 MDIO_PMA_REG_8481_LED1_MASK,
10521 MDIO_PMA_DEVAD,
10522 MDIO_PMA_REG_8481_LED2_MASK,
10526 MDIO_PMA_DEVAD,
10527 MDIO_PMA_REG_8481_LED3_MASK,
10531 MDIO_PMA_DEVAD,
10532 MDIO_PMA_REG_8481_LED5_MASK,
10537 MDIO_PMA_DEVAD,
10538 MDIO_PMA_REG_8481_LED1_MASK,
10541 /* Tell LED3 to blink on source */
10543 MDIO_PMA_DEVAD,
10544 MDIO_PMA_REG_8481_LINK_SIGNAL,
10549 MDIO_PMA_DEVAD,
10550 MDIO_PMA_REG_8481_LINK_SIGNAL,
10551 val);
10552 }
10554 }
10556 /* This is a workaround for E3+84833 until autoneg
10557 * restart is fixed in f/w
10558 */
10562 }
10563 }
10565 /******************************************************************/
10566 /* 54618SE PHY SECTION */
10567 /******************************************************************/
10571 {
10573 u8 port;
10575 u32 cfg_pin;
10580 /* This works with E3 only, no need to check the chip
10581 * before determining the port.
10582 */
10588 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10589 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10591 /* Drive pin high to bring the GPHY out of reset. */
10594 /* wait for GPHY to reset */
10597 /* reset phy */
10602 /* Wait for GPHY to reset */
10605 /* Configure LED4: set to INTR (0x6). */
10606 /* Accessing shadow register 0xe. */
10608 MDIO_REG_GPHY_SHADOW,
10609 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10611 MDIO_REG_GPHY_SHADOW,
10616 MDIO_REG_GPHY_SHADOW,
10618 /* Configure INTR based on link status change. */
10620 MDIO_REG_INTR_MASK,
10623 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10625 MDIO_REG_GPHY_SHADOW,
10626 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10628 MDIO_REG_GPHY_SHADOW,
10632 MDIO_REG_GPHY_SHADOW,
10635 /* Set up fc */
10636 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10640 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10644 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10647 /* Read all advertisement */
10657 MDIO_PMA_REG_CTRL,
10660 /* Disable forced speed */
10667 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10679 an_1000_val);
10684 /* Set 100 speed advertisement */
10688 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10690 /* Enable autoneg and restart autoneg for legacy speeds */
10696 }
10698 /* Set 10 speed advertisement */
10702 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10708 }
10710 /* Only 10/100 are allowed to work in FORCE mode */
10713 /* Enabled AUTO-MDIX when autoneg is disabled */
10718 }
10720 /* Enabled AUTO-MDIX when autoneg is disabled */
10725 }
10727 /* Check if we should turn on Auto-GrEEEn */
10731 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10737 }
10741 MDIO_REG_GPHY_CL45_DATA_REG,
10742 MDIO_REG_GPHY_EEE_ADV);
10744 MDIO_REG_GPHY_CL45_ADDR_REG,
10747 MDIO_REG_GPHY_CL45_DATA_REG,
10748 temp);
10749 }
10762 }
10767 {
10769 u16 temp;
10772 MDIO_REG_GPHY_SHADOW,
10773 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10775 MDIO_REG_GPHY_SHADOW,
10793 }
10795 MDIO_REG_GPHY_SHADOW,
10798 }
10803 {
10805 u32 cfg_pin;
10806 u8 port;
10808 /* In case of no EPIO routed to reset the GPHY, put it
10809 * in low power mode.
10810 */
10812 /* This works with E3 only, no need to check the chip
10813 * before determining the port.
10814 */
10819 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10820 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10822 /* Drive pin low to put GPHY in reset. */
10824 }
10829 {
10831 u16 val;
10835 /* Get speed operation status */
10837 MDIO_REG_GPHY_AUX_STATUS,
10841 /* Read status to clear the PHY interrupt. */
10843 MDIO_REG_INTR_STATUS,
10859 }
10860 /* Omitting 100Base-T4 for now */
10878 /* Check legacy speed AN resolution */
10884 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10890 LINK_STATUS_PARALLEL_DETECTION_USED;
10895 /* Report whether EEE is resolved. */
10899 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10903 MDIO_REG_GPHY_CL45_ADDR_REG,
10904 MDIO_AN_DEVAD);
10906 MDIO_REG_GPHY_CL45_DATA_REG,
10907 MDIO_REG_GPHY_EEE_RESOLVED);
10909 MDIO_REG_GPHY_CL45_ADDR_REG,
10912 MDIO_REG_GPHY_CL45_DATA_REG,
10914 }
10916 }
10921 /* Report LP advertised speeds */
10926 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10929 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10932 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10935 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10938 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10943 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10946 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10947 }
10948 }
10950 }
10954 {
10956 u16 val;
10961 /* Enable master/slave manual mmode and set to master */
10962 /* mii write 9 [bits set 11 12] */
10965 /* forced 1G and disable autoneg */
10966 /* set val [mii read 0] */
10967 /* set val [expr $val & [bits clear 6 12 13]] */
10968 /* set val [expr $val | [bits set 6 8]] */
10969 /* mii write 0 $val */
10975 /* Set external loopback and Tx using 6dB coding */
10976 /* mii write 0x18 7 */
10977 /* set val [mii read 0x18] */
10978 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10983 /* This register opens the gate for the UMAC despite its name */
10986 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10987 * length used by the MAC receive logic to check frames.
10988 */
10990 }
10992 /******************************************************************/
10993 /* SFX7101 PHY SECTION */
10994 /******************************************************************/
10997 {
10999 /* SFX7101_XGXS_TEST1 */
11002 }
11007 {
11012 /* Restore normal power mode*/
11015 /* HW reset */
11026 /* Restart autoneg */
11033 /* Save spirom version */
11042 }
11047 {
11049 u8 link_up;
11064 /* If link is up print the AN outcome of the SFX7101 PHY */
11076 /* Read LP advertised speeds */
11079 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11080 }
11082 }
11085 {
11095 }
11098 {
11102 MDIO_PMA_DEVAD,
11107 /* Writes a self-clearing reset */
11109 MDIO_PMA_DEVAD,
11110 MDIO_PMA_REG_7101_RESET,
11112 /* Wait for clear */
11114 MDIO_PMA_DEVAD,
11119 }
11120 }
11124 /* Low power mode is controlled by GPIO 2 */
11127 /* The PHY reset is controlled by GPIO 1 */
11130 }
11134 {
11148 }
11150 MDIO_PMA_DEVAD,
11151 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11152 val);
11153 }
11155 /******************************************************************/
11156 /* STATIC PHY DECLARATION */
11157 /******************************************************************/
11183 };
11194 SUPPORTED_10baseT_Full |
11195 SUPPORTED_100baseT_Half |
11196 SUPPORTED_100baseT_Full |
11197 SUPPORTED_1000baseT_Full |
11198 SUPPORTED_2500baseX_Full |
11199 SUPPORTED_TP |
11200 SUPPORTED_Autoneg |
11201 SUPPORTED_Pause |
11202 SUPPORTED_Asym_Pause),
11218 };
11229 SUPPORTED_10baseT_Full |
11230 SUPPORTED_100baseT_Half |
11231 SUPPORTED_100baseT_Full |
11232 SUPPORTED_1000baseT_Full |
11233 SUPPORTED_2500baseX_Full |
11234 SUPPORTED_10000baseT_Full |
11235 SUPPORTED_FIBRE |
11236 SUPPORTED_Autoneg |
11237 SUPPORTED_Pause |
11238 SUPPORTED_Asym_Pause),
11254 };
11260 FLAGS_TX_ERROR_CHECK),
11265 SUPPORTED_10baseT_Full |
11266 SUPPORTED_100baseT_Half |
11267 SUPPORTED_100baseT_Full |
11268 SUPPORTED_1000baseT_Full |
11269 SUPPORTED_10000baseT_Full |
11270 SUPPORTED_20000baseKR2_Full |
11271 SUPPORTED_20000baseMLD2_Full |
11272 SUPPORTED_FIBRE |
11273 SUPPORTED_Autoneg |
11274 SUPPORTED_Pause |
11275 SUPPORTED_Asym_Pause),
11291 };
11303 SUPPORTED_TP |
11304 SUPPORTED_Autoneg |
11305 SUPPORTED_Pause |
11306 SUPPORTED_Asym_Pause),
11322 };
11332 SUPPORTED_2500baseX_Full |
11333 SUPPORTED_1000baseT_Full |
11334 SUPPORTED_FIBRE |
11335 SUPPORTED_Autoneg |
11336 SUPPORTED_Pause |
11337 SUPPORTED_Asym_Pause),
11353 };
11363 SUPPORTED_FIBRE |
11364 SUPPORTED_Pause |
11365 SUPPORTED_Asym_Pause),
11381 };
11391 SUPPORTED_1000baseT_Full |
11392 SUPPORTED_FIBRE |
11393 SUPPORTED_Pause |
11394 SUPPORTED_Asym_Pause),
11410 };
11417 FLAGS_INIT_XGXS_FIRST |
11418 FLAGS_TX_ERROR_CHECK),
11423 SUPPORTED_1000baseT_Full |
11424 SUPPORTED_Autoneg |
11425 SUPPORTED_FIBRE |
11426 SUPPORTED_Pause |
11427 SUPPORTED_Asym_Pause),
11443 };
11450 FLAGS_TX_ERROR_CHECK),
11455 SUPPORTED_1000baseT_Full |
11456 SUPPORTED_FIBRE |
11457 SUPPORTED_Pause |
11458 SUPPORTED_Asym_Pause),
11474 };
11480 FLAGS_REARM_LATCH_SIGNAL,
11485 SUPPORTED_10baseT_Full |
11486 SUPPORTED_100baseT_Half |
11487 SUPPORTED_100baseT_Full |
11488 SUPPORTED_1000baseT_Full |
11489 SUPPORTED_10000baseT_Full |
11490 SUPPORTED_TP |
11491 SUPPORTED_Autoneg |
11492 SUPPORTED_Pause |
11493 SUPPORTED_Asym_Pause),
11509 };
11516 FLAGS_REARM_LATCH_SIGNAL |
11517 FLAGS_TX_ERROR_CHECK),
11522 SUPPORTED_10baseT_Full |
11523 SUPPORTED_100baseT_Half |
11524 SUPPORTED_100baseT_Full |
11525 SUPPORTED_1000baseT_Full |
11526 SUPPORTED_10000baseT_Full |
11527 SUPPORTED_TP |
11528 SUPPORTED_Autoneg |
11529 SUPPORTED_Pause |
11530 SUPPORTED_Asym_Pause),
11546 };
11553 FLAGS_REARM_LATCH_SIGNAL |
11554 FLAGS_TX_ERROR_CHECK |
11555 FLAGS_EEE_10GBT),
11560 SUPPORTED_100baseT_Full |
11561 SUPPORTED_1000baseT_Full |
11562 SUPPORTED_10000baseT_Full |
11563 SUPPORTED_TP |
11564 SUPPORTED_Autoneg |
11565 SUPPORTED_Pause |
11566 SUPPORTED_Asym_Pause),
11582 };
11593 SUPPORTED_10baseT_Full |
11594 SUPPORTED_100baseT_Half |
11595 SUPPORTED_100baseT_Full |
11596 SUPPORTED_1000baseT_Full |
11597 SUPPORTED_TP |
11598 SUPPORTED_Autoneg |
11599 SUPPORTED_Pause |
11600 SUPPORTED_Asym_Pause),
11616 };
11617 /*****************************************************************/
11618 /* */
11619 /* Populate the phy according. Main function: bnx2x_populate_phy */
11620 /* */
11621 /*****************************************************************/
11625 u8 phy_index)
11626 {
11627 /* Get the 4 lanes xgxs config rx and tx */
11630 /* INT_PHY and EXT_PHY1 share the same value location in
11631 * the shmem. When num_phys is greater than 1, than this value
11632 * applies only to EXT_PHY1
11633 */
11650 }
11657 }
11658 }
11662 {
11678 }
11681 }
11684 {
11685 u32 phy_addr;
11686 u32 chip_id;
11690 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11696 u32 serdes_net_if;
11698 MISC_REG_WC0_CTRL_PHY_ADDR);
11702 else
11704 /* Check Dual mode */
11708 PORT_HW_CFG_NET_SERDES_IF_MASK);
11709 /* Set the appropriate supported and flags indications per
11710 * interface type of the chip
11711 */
11715 SUPPORTED_10baseT_Full |
11716 SUPPORTED_100baseT_Half |
11717 SUPPORTED_100baseT_Full |
11718 SUPPORTED_1000baseT_Full |
11719 SUPPORTED_FIBRE |
11720 SUPPORTED_Autoneg |
11721 SUPPORTED_Pause |
11722 SUPPORTED_Asym_Pause);
11730 SUPPORTED_10000baseT_Full |
11731 SUPPORTED_FIBRE |
11732 SUPPORTED_Pause |
11733 SUPPORTED_Asym_Pause);
11739 SUPPORTED_10000baseT_Full |
11740 SUPPORTED_FIBRE |
11741 SUPPORTED_Autoneg |
11742 SUPPORTED_Pause |
11743 SUPPORTED_Asym_Pause);
11749 SUPPORTED_FIBRE |
11750 SUPPORTED_Pause |
11751 SUPPORTED_Asym_Pause);
11757 SUPPORTED_FIBRE |
11758 SUPPORTED_Pause |
11759 SUPPORTED_Asym_Pause);
11763 serdes_net_if);
11765 }
11767 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11768 * was not set as expected. For B0, ECO will be enabled so there
11769 * won't be an issue there
11770 */
11773 else
11779 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11785 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11792 }
11793 }
11796 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11797 port);
11800 else
11808 }
11811 u8 phy_index,
11812 u32 shmem_base,
11813 u32 shmem2_base,
11814 u8 port,
11816 {
11822 /* Select the phy type */
11839 /* BCM8727_NOC => BCM8727 no over current */
11870 /* In case external PHY wasn't found */
11875 }
11880 /* The shmem address of the phy version is located on different
11881 * structures. In case this structure is too old, do not set
11882 * the address
11883 */
11890 /* Check specific mdc mdio settings */
11893 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11902 }
11903 /* Check specific mdc mdio settings */
11906 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11908 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11909 }
11914 /* Remove 100Mb link supported for BCM84833 when phy fw
11915 * version lower than or equal to 1.39
11916 */
11921 SUPPORTED_100baseT_Full);
11922 }
11924 /* In case mdc/mdio_access of the external phy is different than the
11925 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11926 * to prevent one port interfere with another port's CL45 operations.
11927 */
11935 }
11939 {
11947 }
11951 u8 phy_index)
11952 {
11954 u32 link_config;
11955 /* Populate the default phy configuration for MF mode */
11962 dev_info.
11970 dev_info.
11972 }
12001 }
12019 }
12020 }
12023 {
12028 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12031 PORT_HW_CFG_PHY_SELECTION_MASK;
12047 }
12052 }
12056 {
12064 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12067 phy_index++) {
12074 }
12084 phy_index);
12087 phy_index++)
12090 }
12095 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12103 /* Update media type for non-PMF sync only for the first time
12104 * In case the media type changes afterwards, it will be updated
12105 * using the update_status function
12106 */
12111 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12113 actual_phy_idx));
12114 }
12119 }
12123 }
12127 {
12139 /* set bmac loopback */
12143 }
12147 {
12158 /* set bmac loopback */
12162 }
12166 {
12171 else
12177 /* Set WC to loopback mode since link is required to provide clock
12178 * to the XMAC in 20G mode
12179 */
12184 params);
12188 }
12192 {
12203 }
12207 {
12214 else
12227 }
12231 else
12233 }
12236 /* set 10G XGXS loopback */
12239 params);
12242 /* set external phy loopback */
12243 u8 phy_index;
12249 params);
12250 }
12251 }
12255 }
12258 {
12274 /* Disable attentions */
12277 NIG_MASK_XGXS0_LINK10G |
12278 NIG_MASK_SERDES0_LINK_STATUS |
12279 NIG_MASK_MI_INT));
12289 }
12314 else
12316 }
12321 }
12326 }
12329 u8 reset_ext_phy)
12330 {
12334 /* Disable attentions */
12338 SHMEM_EEE_ACTIVE_BIT);
12342 NIG_MASK_XGXS0_LINK10G |
12343 NIG_MASK_SERDES0_LINK_STATUS |
12344 NIG_MASK_MI_INT));
12346 /* Activate nig drain */
12349 /* Disable nig egress interface */
12353 }
12355 /* Stop BigMac rx */
12361 }
12362 /* Disable emac */
12367 /* The PHY reset is controlled by GPIO 1
12368 * Hold it as vars low
12369 */
12370 /* Clear link led */
12376 phy_index++) {
12382 params);
12383 }
12385 FLAGS_REARM_LATCH_SIGNAL)
12387 }
12388 }
12391 /* Clear latching indication */
12395 }
12400 /* Disable nig ingress interface */
12402 /* Reset BigMac */
12411 MISC_REGISTERS_RESET_REG_2_XMAC)
12413 XMAC_CTRL_REG_SOFT_RESET);
12414 }
12418 }
12420 /****************************************************************************/
12421 /* Common function */
12422 /****************************************************************************/
12424 u32 shmem_base_path[],
12426 u32 chip_id)
12427 {
12430 u16 val;
12438 /* PART1 - Reset both phys */
12441 /* In E2, same phy is using for port0 of the two paths */
12450 }
12452 /* Extract the ext phy address for the port */
12458 }
12459 /* Disable attentions */
12463 NIG_MASK_XGXS0_LINK10G |
12464 NIG_MASK_SERDES0_LINK_STATUS |
12465 NIG_MASK_MI_INT));
12467 /* Need to take the phy out of low power mode in order
12468 * to write to access its registers
12469 */
12471 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12472 port);
12474 /* Reset the phy */
12476 MDIO_PMA_DEVAD,
12477 MDIO_PMA_REG_CTRL,
12479 }
12481 /* Add delay of 150ms after reset */
12490 }
12492 /* PART2 - Download firmware to both phys */
12496 else
12502 port_of_path))
12505 /* Only set bit 10 = 1 (Tx power down) */
12507 MDIO_PMA_DEVAD,
12510 /* Phase1 of TX_POWER_DOWN reset */
12512 MDIO_PMA_DEVAD,
12513 MDIO_PMA_REG_TX_POWER_DOWN,
12515 }
12517 /* Toggle Transmitter: Power down and then up with 600ms delay
12518 * between
12519 */
12522 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12524 /* Phase2 of POWER_DOWN_RESET */
12525 /* Release bit 10 (Release Tx power down) */
12527 MDIO_PMA_DEVAD,
12531 MDIO_PMA_DEVAD,
12535 /* Read modify write the SPI-ROM version select register */
12537 MDIO_PMA_DEVAD,
12540 MDIO_PMA_DEVAD,
12543 /* set GPIO2 back to LOW */
12546 }
12548 }
12550 u32 shmem_base_path[],
12552 u32 chip_id)
12553 {
12554 u32 val;
12555 s8 port;
12557 /* Use port1 because of the static port-swap */
12558 /* Enable the module detection interrupt */
12569 /* In E2, same phy is using for port0 of the two paths */
12576 }
12577 /* Extract the ext phy address for the port */
12583 }
12585 /* Reset phy*/
12590 /* Set fault module detected LED on */
12592 MISC_REGISTERS_GPIO_HIGH,
12593 port);
12594 }
12597 }
12600 {
12639 /* Don't override the io_gpio and io_port */
12641 }
12642 }
12645 u32 shmem_base_path[],
12647 u32 chip_id)
12648 {
12653 s8 port_of_path;
12660 /* Retrieve the reset gpio/port which control the reset.
12661 * Default is GPIO1, PORT1
12662 */
12666 /* Calculate the port based on port swap */
12669 /* Initiate PHY reset*/
12671 port);
12674 port);
12678 /* PART1 - Reset both phys */
12682 /* In E2, same phy is using for port0 of the two paths */
12691 }
12693 /* Extract the ext phy address for the port */
12699 }
12700 /* disable attentions */
12704 NIG_MASK_XGXS0_LINK10G |
12705 NIG_MASK_SERDES0_LINK_STATUS |
12706 NIG_MASK_MI_INT));
12709 /* Reset the phy */
12712 }
12714 /* Add delay of 150ms after reset */
12722 }
12723 /* PART2 - Download firmware to both phys */
12727 else
12732 port_of_path))
12734 /* Disable PHY transmitter output */
12736 MDIO_PMA_DEVAD,
12739 }
12741 }
12744 u32 shmem_base_path[],
12745 u32 shmem2_base_path[],
12746 u8 phy_index,
12747 u32 chip_id)
12748 {
12749 u8 reset_gpios;
12755 reset_gpios);
12757 }
12761 {
12763 /* Wait for FW completing its initialization. */
12766 MDIO_PMA_DEVAD,
12771 }
12775 }
12777 /* Put the port in super isolate mode. */
12779 MDIO_CTL_DEVAD,
12783 MDIO_CTL_DEVAD,
12786 /* Save spirom version */
12789 }
12792 u32 shmem_base,
12793 u32 shmem2_base,
12794 u32 chip_id)
12795 {
12803 }
12810 }
12812 }
12817 {
12823 shmem2_base_path,
12830 shmem2_base_path,
12835 /* GPIO1 affects both ports, so there's need to pull
12836 * it for single port alone
12837 */
12839 shmem2_base_path,
12843 /* GPIO3's are linked, and so both need to be toggled
12844 * to obtain required 2us pulse.
12845 */
12847 shmem2_base_path,
12856 ext_phy_type);
12858 }
12865 }
12869 {
12878 /* Enable EPIO */
12881 }
12882 /* Check if common init was already done */
12888 phy_ver);
12890 }
12892 /* Read the ext_phy_type for arbitrary port(0) */
12894 phy_index++) {
12900 shmem2_base_path,
12902 chip_id);
12903 }
12905 }
12909 {
12911 u32 cfg_pin;
12913 u32 pin_val;
12918 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12919 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12921 /* Ignore check if no external input PIN available */
12928 " been detected and the power to "
12929 "that SFP+ module has been removed"
12930 " to prevent failure of the card."
12931 " Please remove the SFP+ module and"
12932 " restart the system to clear this"
12936 }
12939 }
12941 /* Returns 0 if no change occured since last check; 1 otherwise. */
12945 {
12947 /* Compare new value with previous value */
12948 u8 led_mode;
12954 /* If values differ */
12964 }
12968 /* a. Update shmem->link_status accordingly
12969 * b. Update link_vars->link_up
12970 */
12977 /* activate nig drain */
12979 /* Set LED mode to off since the PHY doesn't know about these
12980 * errors
12981 */
12990 /* Clear nig drain */
12992 }
12994 /* Update the LED according to the link state */
12997 /* Update link status in the shared memory */
13000 /* C. Trigger General Attention */
13006 }
13008 /******************************************************************************
13009 * Description:
13010 * This function checks for half opened connection change indication.
13011 * When such change occurs, it calls the bnx2x_analyze_link_error
13012 * to check if Remote Fault is set or cleared. Reception of remote fault
13013 * status message in the MAC indicates that the peer's MAC has detected
13014 * a fault, for example, due to break in the TX side of fiber.
13015 *
13016 ******************************************************************************/
13019 u8 notify)
13020 {
13023 u32 mac_base;
13024 /* In case link status is physically up @ 10G do */
13032 /* Check E3 XMAC */
13033 /* Note that link speed cannot be queried here, since it may be
13034 * zero while link is down. In case UMAC is active, LSS will
13035 * simply not be set
13036 */
13039 /* Clear stick bits (Requires rising edge) */
13042 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13043 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13048 PHY_HALF_OPEN_CONN_FLAG,
13052 /* Check E1X / E2 BMAC */
13053 u32 lss_status_reg;
13056 NIG_REG_INGRESS_BMAC0_MEM;
13057 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13060 else
13067 PHY_HALF_OPEN_CONN_FLAG,
13069 }
13071 }
13075 {
13080 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13083 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13084 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13089 }
13092 PHY_SFP_TX_FAULT_FLAG,
13096 /* Change TX_Fault led, set link status for further syncs */
13097 u8 led_mode;
13105 }
13107 /* If module is unapproved, led should be on regardless */
13110 led_mode);
13112 }
13113 }
13114 }
13116 {
13117 u16 phy_idx;
13126 }
13127 }
13140 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13144 LINK_STATUS_SFP_TX_FAULT) {
13145 /* Clean trail, interrupt corrects the leds */
13148 /* Update link status in the shared memory */
13150 }
13151 }
13153 }
13155 }
13158 {
13159 u8 phy_index;
13162 phy_index++) {
13167 }
13171 }
13173 }
13176 u32 shmem_base,
13177 u32 shmem2_base,
13178 u8 port)
13179 {
13183 phy_index++) {
13189 }
13191 FLAGS_FAN_FAILURE_DET_REQ);
13192 }
13194 }
13197 {
13198 u8 phy_index;
13203 NIG_MASK_XGXS0_LINK10G |
13204 NIG_MASK_SERDES0_LINK_STATUS |
13205 NIG_MASK_MI_INT));
13208 phy_index++) {
13212 params);
13214 }
13215 }
13216 }
13220 u8 port)
13221 {
13223 u32 val;
13227 shmem_base,
13228 port,
13235 phy_index++) {
13241 }
13246 }
13247 }
13248 }
13253 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13273 else
13276 /* Open appropriate AEU for interrupts */
13281 /* Enable the GPIO to trigger interrupt */
13285 }