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bnx2x: Add new 57840 device IDs
[linux-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
blob77bcd4cb4ffb945a8c696cc3f6bab1e363733c48
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.72.51-0"
27 #define DRV_MODULE_RELDATE "2012/06/18"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33
34
35 #include "bnx2x_hsi.h"
36
37 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
38 #define BCM_CNIC 1
39 #include "../cnic_if.h"
40 #endif
41
42 #ifdef BCM_CNIC
43 #define BNX2X_MIN_MSIX_VEC_CNT 3
44 #define BNX2X_MSIX_VEC_FP_START 2
45 #else
46 #define BNX2X_MIN_MSIX_VEC_CNT 2
47 #define BNX2X_MSIX_VEC_FP_START 1
48 #endif
49
50 #include <linux/mdio.h>
51
52 #include "bnx2x_reg.h"
53 #include "bnx2x_fw_defs.h"
54 #include "bnx2x_mfw_req.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x_sp.h"
58 #include "bnx2x_dcb.h"
59 #include "bnx2x_stats.h"
60
61 /* error/debug prints */
62
63 #define DRV_MODULE_NAME "bnx2x"
64
65 /* for messages that are currently off */
66 #define BNX2X_MSG_OFF 0x0
67 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
68 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
69 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
71 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
73 #define BNX2X_MSG_IOV 0x0800000
74 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
75 #define BNX2X_MSG_ETHTOOL 0x4000000
76 #define BNX2X_MSG_DCB 0x8000000
77
78 /* regular debug print */
79 #define DP(__mask, fmt, ...) \
80 do { \
81 if (unlikely(bp->msg_enable & (__mask))) \
82 pr_notice("[%s:%d(%s)]" fmt, \
83 __func__, __LINE__, \
84 bp->dev ? (bp->dev->name) : "?", \
85 ##__VA_ARGS__); \
86 } while (0)
87
88 #define DP_CONT(__mask, fmt, ...) \
89 do { \
90 if (unlikely(bp->msg_enable & (__mask))) \
91 pr_cont(fmt, ##__VA_ARGS__); \
92 } while (0)
93
94 /* errors debug print */
95 #define BNX2X_DBG_ERR(fmt, ...) \
96 do { \
97 if (unlikely(netif_msg_probe(bp))) \
98 pr_err("[%s:%d(%s)]" fmt, \
99 __func__, __LINE__, \
100 bp->dev ? (bp->dev->name) : "?", \
101 ##__VA_ARGS__); \
102 } while (0)
103
104 /* for errors (never masked) */
105 #define BNX2X_ERR(fmt, ...) \
106 do { \
107 pr_err("[%s:%d(%s)]" fmt, \
108 __func__, __LINE__, \
109 bp->dev ? (bp->dev->name) : "?", \
110 ##__VA_ARGS__); \
111 } while (0)
112
113 #define BNX2X_ERROR(fmt, ...) \
114 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
115
116
117 /* before we have a dev->name use dev_info() */
118 #define BNX2X_DEV_INFO(fmt, ...) \
119 do { \
120 if (unlikely(netif_msg_probe(bp))) \
121 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
122 } while (0)
123
124 #ifdef BNX2X_STOP_ON_ERROR
125 void bnx2x_int_disable(struct bnx2x *bp);
126 #define bnx2x_panic() \
127 do { \
128 bp->panic = 1; \
129 BNX2X_ERR("driver assert\n"); \
130 bnx2x_int_disable(bp); \
131 bnx2x_panic_dump(bp); \
132 } while (0)
133 #else
134 #define bnx2x_panic() \
135 do { \
136 bp->panic = 1; \
137 BNX2X_ERR("driver assert\n"); \
138 bnx2x_panic_dump(bp); \
139 } while (0)
140 #endif
141
142 #define bnx2x_mc_addr(ha) ((ha)->addr)
143 #define bnx2x_uc_addr(ha) ((ha)->addr)
144
145 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
146 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
147 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
148
149
150 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
151
152 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
153 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
154 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
155
156 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
157 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
158 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
159
160 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
161 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
162
163 #define REG_RD_DMAE(bp, offset, valp, len32) \
164 do { \
165 bnx2x_read_dmae(bp, offset, len32);\
166 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
167 } while (0)
168
169 #define REG_WR_DMAE(bp, offset, valp, len32) \
170 do { \
171 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
172 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
173 offset, len32); \
174 } while (0)
175
176 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
177 REG_WR_DMAE(bp, offset, valp, len32)
178
179 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
180 do { \
181 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
182 bnx2x_write_big_buf_wb(bp, addr, len32); \
183 } while (0)
184
185 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
186 offsetof(struct shmem_region, field))
187 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
188 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
189
190 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
191 offsetof(struct shmem2_region, field))
192 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
193 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
194 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
195 offsetof(struct mf_cfg, field))
196 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
197 offsetof(struct mf2_cfg, field))
198
199 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
200 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
201 MF_CFG_ADDR(bp, field), (val))
202 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
203
204 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
205 (SHMEM2_RD((bp), size) > \
206 offsetof(struct shmem2_region, field)))
207
208 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
209 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
210
211 /* SP SB indices */
212
213 /* General SP events - stats query, cfc delete, etc */
214 #define HC_SP_INDEX_ETH_DEF_CONS 3
215
216 /* EQ completions */
217 #define HC_SP_INDEX_EQ_CONS 7
218
219 /* FCoE L2 connection completions */
220 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
221 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
222 /* iSCSI L2 */
223 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
224 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
225
226 /* Special clients parameters */
227
228 /* SB indices */
229 /* FCoE L2 */
230 #define BNX2X_FCOE_L2_RX_INDEX \
231 (&bp->def_status_blk->sp_sb.\
232 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
233
234 #define BNX2X_FCOE_L2_TX_INDEX \
235 (&bp->def_status_blk->sp_sb.\
236 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
237
238 /**
239 * CIDs and CLIDs:
240 * CLIDs below is a CLID for func 0, then the CLID for other
241 * functions will be calculated by the formula:
242 *
243 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
244 *
245 */
246 enum {
247 BNX2X_ISCSI_ETH_CL_ID_IDX,
248 BNX2X_FCOE_ETH_CL_ID_IDX,
249 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
250 };
251
252 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
253 (bp)->max_cos)
254 /* iSCSI L2 */
255 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
256 /* FCoE L2 */
257 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
258
259 /** Additional rings budgeting */
260 #ifdef BCM_CNIC
261 #define CNIC_PRESENT 1
262 #define FCOE_PRESENT 1
263 #else
264 #define CNIC_PRESENT 0
265 #define FCOE_PRESENT 0
266 #endif /* BCM_CNIC */
267 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
268
269 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
270 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
271
272 #define SM_RX_ID 0
273 #define SM_TX_ID 1
274
275 /* defines for multiple tx priority indices */
276 #define FIRST_TX_ONLY_COS_INDEX 1
277 #define FIRST_TX_COS_INDEX 0
278
279 /* rules for calculating the cids of tx-only connections */
280 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
281 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
282 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
283
284 /* fp index inside class of service range */
285 #define FP_COS_TO_TXQ(fp, cos, bp) \
286 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
287
288 /* Indexes for transmission queues array:
289 * txdata for RSS i CoS j is at location i + (j * num of RSS)
290 * txdata for FCoE (if exist) is at location max cos * num of RSS
291 * txdata for FWD (if exist) is one location after FCoE
292 * txdata for OOO (if exist) is one location after FWD
293 */
294 enum {
295 FCOE_TXQ_IDX_OFFSET,
296 FWD_TXQ_IDX_OFFSET,
297 OOO_TXQ_IDX_OFFSET,
298 };
299 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
300 #ifdef BCM_CNIC
301 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
302 #endif
303
304 /* fast path */
305 /*
306 * This driver uses new build_skb() API :
307 * RX ring buffer contains pointer to kmalloc() data only,
308 * skb are built only after Hardware filled the frame.
309 */
310 struct sw_rx_bd {
311 u8 *data;
312 DEFINE_DMA_UNMAP_ADDR(mapping);
313 };
314
315 struct sw_tx_bd {
316 struct sk_buff *skb;
317 u16 first_bd;
318 u8 flags;
319 /* Set on the first BD descriptor when there is a split BD */
320 #define BNX2X_TSO_SPLIT_BD (1<<0)
321 };
322
323 struct sw_rx_page {
324 struct page *page;
325 DEFINE_DMA_UNMAP_ADDR(mapping);
326 };
327
328 union db_prod {
329 struct doorbell_set_prod data;
330 u32 raw;
331 };
332
333 /* dropless fc FW/HW related params */
334 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
335 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
336 ETH_MAX_AGGREGATION_QUEUES_E1 :\
337 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
338 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
339 #define FW_PREFETCH_CNT 16
340 #define DROPLESS_FC_HEADROOM 100
341
342 /* MC hsi */
343 #define BCM_PAGE_SHIFT 12
344 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
345 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
346 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
347
348 #define PAGES_PER_SGE_SHIFT 0
349 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
350 #define SGE_PAGE_SIZE PAGE_SIZE
351 #define SGE_PAGE_SHIFT PAGE_SHIFT
352 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
353
354 /* SGE ring related macros */
355 #define NUM_RX_SGE_PAGES 2
356 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
357 #define NEXT_PAGE_SGE_DESC_CNT 2
358 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
359 /* RX_SGE_CNT is promised to be a power of 2 */
360 #define RX_SGE_MASK (RX_SGE_CNT - 1)
361 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
362 #define MAX_RX_SGE (NUM_RX_SGE - 1)
363 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
364 (MAX_RX_SGE_CNT - 1)) ? \
365 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
366 (x) + 1)
367 #define RX_SGE(x) ((x) & MAX_RX_SGE)
368
369 /*
370 * Number of required SGEs is the sum of two:
371 * 1. Number of possible opened aggregations (next packet for
372 * these aggregations will probably consume SGE immidiatelly)
373 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
374 * after placement on BD for new TPA aggregation)
375 *
376 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
377 */
378 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
379 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
380 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
381 MAX_RX_SGE_CNT)
382 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
383 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
384 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
385
386 /* Manipulate a bit vector defined as an array of u64 */
387
388 /* Number of bits in one sge_mask array element */
389 #define BIT_VEC64_ELEM_SZ 64
390 #define BIT_VEC64_ELEM_SHIFT 6
391 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
392
393
394 #define __BIT_VEC64_SET_BIT(el, bit) \
395 do { \
396 el = ((el) | ((u64)0x1 << (bit))); \
397 } while (0)
398
399 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
400 do { \
401 el = ((el) & (~((u64)0x1 << (bit)))); \
402 } while (0)
403
404
405 #define BIT_VEC64_SET_BIT(vec64, idx) \
406 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
407 (idx) & BIT_VEC64_ELEM_MASK)
408
409 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
410 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
411 (idx) & BIT_VEC64_ELEM_MASK)
412
413 #define BIT_VEC64_TEST_BIT(vec64, idx) \
414 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
415 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
416
417 /* Creates a bitmask of all ones in less significant bits.
418 idx - index of the most significant bit in the created mask */
419 #define BIT_VEC64_ONES_MASK(idx) \
420 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
421 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
422
423 /*******************************************************/
424
425
426
427 /* Number of u64 elements in SGE mask array */
428 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
429 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
430 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
431
432 union host_hc_status_block {
433 /* pointer to fp status block e1x */
434 struct host_hc_status_block_e1x *e1x_sb;
435 /* pointer to fp status block e2 */
436 struct host_hc_status_block_e2 *e2_sb;
437 };
438
439 struct bnx2x_agg_info {
440 /*
441 * First aggregation buffer is a data buffer, the following - are pages.
442 * We will preallocate the data buffer for each aggregation when
443 * we open the interface and will replace the BD at the consumer
444 * with this one when we receive the TPA_START CQE in order to
445 * keep the Rx BD ring consistent.
446 */
447 struct sw_rx_bd first_buf;
448 u8 tpa_state;
449 #define BNX2X_TPA_START 1
450 #define BNX2X_TPA_STOP 2
451 #define BNX2X_TPA_ERROR 3
452 u8 placement_offset;
453 u16 parsing_flags;
454 u16 vlan_tag;
455 u16 len_on_bd;
456 u32 rxhash;
457 bool l4_rxhash;
458 u16 gro_size;
459 u16 full_page;
460 };
461
462 #define Q_STATS_OFFSET32(stat_name) \
463 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
464
465 struct bnx2x_fp_txdata {
466
467 struct sw_tx_bd *tx_buf_ring;
468
469 union eth_tx_bd_types *tx_desc_ring;
470 dma_addr_t tx_desc_mapping;
471
472 u32 cid;
473
474 union db_prod tx_db;
475
476 u16 tx_pkt_prod;
477 u16 tx_pkt_cons;
478 u16 tx_bd_prod;
479 u16 tx_bd_cons;
480
481 unsigned long tx_pkt;
482
483 __le16 *tx_cons_sb;
484
485 int txq_index;
486 struct bnx2x_fastpath *parent_fp;
487 int tx_ring_size;
488 };
489
490 enum bnx2x_tpa_mode_t {
491 TPA_MODE_LRO,
492 TPA_MODE_GRO
493 };
494
495 struct bnx2x_fastpath {
496 struct bnx2x *bp; /* parent */
497
498 #define BNX2X_NAPI_WEIGHT 128
499 struct napi_struct napi;
500 union host_hc_status_block status_blk;
501 /* chip independed shortcuts into sb structure */
502 __le16 *sb_index_values;
503 __le16 *sb_running_index;
504 /* chip independed shortcut into rx_prods_offset memory */
505 u32 ustorm_rx_prods_offset;
506
507 u32 rx_buf_size;
508
509 dma_addr_t status_blk_mapping;
510
511 enum bnx2x_tpa_mode_t mode;
512
513 u8 max_cos; /* actual number of active tx coses */
514 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
515
516 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
517 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
518
519 struct eth_rx_bd *rx_desc_ring;
520 dma_addr_t rx_desc_mapping;
521
522 union eth_rx_cqe *rx_comp_ring;
523 dma_addr_t rx_comp_mapping;
524
525 /* SGE ring */
526 struct eth_rx_sge *rx_sge_ring;
527 dma_addr_t rx_sge_mapping;
528
529 u64 sge_mask[RX_SGE_MASK_LEN];
530
531 u32 cid;
532
533 __le16 fp_hc_idx;
534
535 u8 index; /* number in fp array */
536 u8 rx_queue; /* index for skb_record */
537 u8 cl_id; /* eth client id */
538 u8 cl_qzone_id;
539 u8 fw_sb_id; /* status block number in FW */
540 u8 igu_sb_id; /* status block number in HW */
541
542 u16 rx_bd_prod;
543 u16 rx_bd_cons;
544 u16 rx_comp_prod;
545 u16 rx_comp_cons;
546 u16 rx_sge_prod;
547 /* The last maximal completed SGE */
548 u16 last_max_sge;
549 __le16 *rx_cons_sb;
550 unsigned long rx_pkt,
551 rx_calls;
552
553 /* TPA related */
554 struct bnx2x_agg_info *tpa_info;
555 u8 disable_tpa;
556 #ifdef BNX2X_STOP_ON_ERROR
557 u64 tpa_queue_used;
558 #endif
559 /* The size is calculated using the following:
560 sizeof name field from netdev structure +
561 4 ('-Xx-' string) +
562 4 (for the digits and to make it DWORD aligned) */
563 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
564 char name[FP_NAME_SIZE];
565 };
566
567 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
568 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
569 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
570 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
571
572 /* Use 2500 as a mini-jumbo MTU for FCoE */
573 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
574
575 #define FCOE_IDX_OFFSET 0
576
577 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
578 FCOE_IDX_OFFSET)
579 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
580 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
581 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
582 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
583 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
584 txdata_ptr[FIRST_TX_COS_INDEX] \
585 ->var)
586
587
588 #define IS_ETH_FP(fp) (fp->index < \
589 BNX2X_NUM_ETH_QUEUES(fp->bp))
590 #ifdef BCM_CNIC
591 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX(fp->bp))
592 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
593 #else
594 #define IS_FCOE_FP(fp) false
595 #define IS_FCOE_IDX(idx) false
596 #endif
597
598
599 /* MC hsi */
600 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
601 #define RX_COPY_THRESH 92
602
603 #define NUM_TX_RINGS 16
604 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
605 #define NEXT_PAGE_TX_DESC_CNT 1
606 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
607 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
608 #define MAX_TX_BD (NUM_TX_BD - 1)
609 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
610 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
611 (MAX_TX_DESC_CNT - 1)) ? \
612 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
613 (x) + 1)
614 #define TX_BD(x) ((x) & MAX_TX_BD)
615 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
616
617 /* number of NEXT_PAGE descriptors may be required during placement */
618 #define NEXT_CNT_PER_TX_PKT(bds) \
619 (((bds) + MAX_TX_DESC_CNT - 1) / \
620 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
621 /* max BDs per tx packet w/o next_pages:
622 * START_BD - describes packed
623 * START_BD(splitted) - includes unpaged data segment for GSO
624 * PARSING_BD - for TSO and CSUM data
625 * Frag BDs - decribes pages for frags
626 */
627 #define BDS_PER_TX_PKT 3
628 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
629 /* max BDs per tx packet including next pages */
630 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
631 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
632
633 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
634 #define NUM_RX_RINGS 8
635 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
636 #define NEXT_PAGE_RX_DESC_CNT 2
637 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
638 #define RX_DESC_MASK (RX_DESC_CNT - 1)
639 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
640 #define MAX_RX_BD (NUM_RX_BD - 1)
641 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
642
643 /* dropless fc calculations for BDs
644 *
645 * Number of BDs should as number of buffers in BRB:
646 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
647 * "next" elements on each page
648 */
649 #define NUM_BD_REQ BRB_SIZE(bp)
650 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
651 MAX_RX_DESC_CNT)
652 #define BD_TH_LO(bp) (NUM_BD_REQ + \
653 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
654 FW_DROP_LEVEL(bp))
655 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
656
657 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
658
659 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
660 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
661 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
662 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
663 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
664 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
665 MIN_RX_AVAIL))
666
667 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
668 (MAX_RX_DESC_CNT - 1)) ? \
669 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
670 (x) + 1)
671 #define RX_BD(x) ((x) & MAX_RX_BD)
672
673 /*
674 * As long as CQE is X times bigger than BD entry we have to allocate X times
675 * more pages for CQ ring in order to keep it balanced with BD ring
676 */
677 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
678 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
679 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
680 #define NEXT_PAGE_RCQ_DESC_CNT 1
681 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
682 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
683 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
684 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
685 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
686 (MAX_RCQ_DESC_CNT - 1)) ? \
687 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
688 (x) + 1)
689 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
690
691 /* dropless fc calculations for RCQs
692 *
693 * Number of RCQs should be as number of buffers in BRB:
694 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
695 * "next" elements on each page
696 */
697 #define NUM_RCQ_REQ BRB_SIZE(bp)
698 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
699 MAX_RCQ_DESC_CNT)
700 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
701 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
702 FW_DROP_LEVEL(bp))
703 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
704
705
706 /* This is needed for determining of last_max */
707 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
708 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
709
710
711 #define BNX2X_SWCID_SHIFT 17
712 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
713
714 /* used on a CID received from the HW */
715 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
716 #define CQE_CMD(x) (le32_to_cpu(x) >> \
717 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
718
719 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
720 le32_to_cpu((bd)->addr_lo))
721 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
722
723 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
724 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
725 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
726 #error "Min DB doorbell stride is 8"
727 #endif
728 #define DPM_TRIGER_TYPE 0x40
729 #define DOORBELL(bp, cid, val) \
730 do { \
731 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
732 DPM_TRIGER_TYPE); \
733 } while (0)
734
735
736 /* TX CSUM helpers */
737 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
738 skb->csum_offset)
739 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
740 skb->csum_offset))
741
742 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
743
744 #define XMIT_PLAIN 0
745 #define XMIT_CSUM_V4 0x1
746 #define XMIT_CSUM_V6 0x2
747 #define XMIT_CSUM_TCP 0x4
748 #define XMIT_GSO_V4 0x8
749 #define XMIT_GSO_V6 0x10
750
751 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
752 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
753
754
755 /* stuff added to make the code fit 80Col */
756 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
757 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
758 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
759 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
760 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
761
762 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
763
764 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
765 (((le16_to_cpu(flags) & \
766 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
767 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
768 == PRS_FLAG_OVERETH_IPV4)
769 #define BNX2X_RX_SUM_FIX(cqe) \
770 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
771
772
773 #define FP_USB_FUNC_OFF \
774 offsetof(struct cstorm_status_block_u, func)
775 #define FP_CSB_FUNC_OFF \
776 offsetof(struct cstorm_status_block_c, func)
777
778 #define HC_INDEX_ETH_RX_CQ_CONS 1
779
780 #define HC_INDEX_OOO_TX_CQ_CONS 4
781
782 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
783
784 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
785
786 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
787
788 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
789
790 #define BNX2X_RX_SB_INDEX \
791 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
792
793 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
794
795 #define BNX2X_TX_SB_INDEX_COS0 \
796 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
797
798 /* end of fast path */
799
800 /* common */
801
802 struct bnx2x_common {
803
804 u32 chip_id;
805 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
806 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
807
808 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
809 #define CHIP_NUM_57710 0x164e
810 #define CHIP_NUM_57711 0x164f
811 #define CHIP_NUM_57711E 0x1650
812 #define CHIP_NUM_57712 0x1662
813 #define CHIP_NUM_57712_MF 0x1663
814 #define CHIP_NUM_57713 0x1651
815 #define CHIP_NUM_57713E 0x1652
816 #define CHIP_NUM_57800 0x168a
817 #define CHIP_NUM_57800_MF 0x16a5
818 #define CHIP_NUM_57810 0x168e
819 #define CHIP_NUM_57810_MF 0x16ae
820 #define CHIP_NUM_57811 0x163d
821 #define CHIP_NUM_57811_MF 0x163e
822 #define CHIP_NUM_57840_OBSOLETE 0x168d
823 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
824 #define CHIP_NUM_57840_4_10 0x16a1
825 #define CHIP_NUM_57840_2_20 0x16a2
826 #define CHIP_NUM_57840_MF 0x16a4
827 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
828 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
829 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
830 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
831 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
832 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
833 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
834 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
835 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
836 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
837 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
838 #define CHIP_IS_57840(bp) \
839 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
840 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
841 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
842 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
843 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
844 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
845 CHIP_IS_57711E(bp))
846 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
847 CHIP_IS_57712_MF(bp))
848 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
849 CHIP_IS_57800_MF(bp) || \
850 CHIP_IS_57810(bp) || \
851 CHIP_IS_57810_MF(bp) || \
852 CHIP_IS_57811(bp) || \
853 CHIP_IS_57811_MF(bp) || \
854 CHIP_IS_57840(bp) || \
855 CHIP_IS_57840_MF(bp))
856 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
857 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
858 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
859
860 #define CHIP_REV_SHIFT 12
861 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
862 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
863 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
864 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
865 /* assume maximum 5 revisions */
866 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
867 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
868 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
869 !(CHIP_REV_VAL(bp) & 0x00001000))
870 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
871 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
872 (CHIP_REV_VAL(bp) & 0x00001000))
873
874 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
875 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
876
877 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
878 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
879 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
880 (CHIP_REV_SHIFT + 1)) \
881 << CHIP_REV_SHIFT)
882 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
883 CHIP_REV_SIM(bp) :\
884 CHIP_REV_VAL(bp))
885 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
886 (CHIP_REV(bp) == CHIP_REV_Bx))
887 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
888 (CHIP_REV(bp) == CHIP_REV_Ax))
889
890 int flash_size;
891 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
892 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
893 #define BNX2X_NVRAM_PAGE_SIZE 256
894
895 u32 shmem_base;
896 u32 shmem2_base;
897 u32 mf_cfg_base;
898 u32 mf2_cfg_base;
899
900 u32 hw_config;
901
902 u32 bc_ver;
903
904 u8 int_block;
905 #define INT_BLOCK_HC 0
906 #define INT_BLOCK_IGU 1
907 #define INT_BLOCK_MODE_NORMAL 0
908 #define INT_BLOCK_MODE_BW_COMP 2
909 #define CHIP_INT_MODE_IS_NBC(bp) \
910 (!CHIP_IS_E1x(bp) && \
911 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
912 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
913
914 u8 chip_port_mode;
915 #define CHIP_4_PORT_MODE 0x0
916 #define CHIP_2_PORT_MODE 0x1
917 #define CHIP_PORT_MODE_NONE 0x2
918 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
919 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
920
921 u32 boot_mode;
922 };
923
924 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
925 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
926 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
927
928 /* end of common */
929
930 /* port */
931
932 struct bnx2x_port {
933 u32 pmf;
934
935 u32 link_config[LINK_CONFIG_SIZE];
936
937 u32 supported[LINK_CONFIG_SIZE];
938 /* link settings - missing defines */
939 #define SUPPORTED_2500baseX_Full (1 << 15)
940
941 u32 advertising[LINK_CONFIG_SIZE];
942 /* link settings - missing defines */
943 #define ADVERTISED_2500baseX_Full (1 << 15)
944
945 u32 phy_addr;
946
947 /* used to synchronize phy accesses */
948 struct mutex phy_mutex;
949 int need_hw_lock;
950
951 u32 port_stx;
952
953 struct nig_stats old_nig_stats;
954 };
955
956 /* end of port */
957
958 #define STATS_OFFSET32(stat_name) \
959 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
960
961 /* slow path */
962
963 /* slow path work-queue */
964 extern struct workqueue_struct *bnx2x_wq;
965
966 #define BNX2X_MAX_NUM_OF_VFS 64
967 #define BNX2X_VF_ID_INVALID 0xFF
968
969 /*
970 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
971 * control by the number of fast-path status blocks supported by the
972 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
973 * status block represents an independent interrupts context that can
974 * serve a regular L2 networking queue. However special L2 queues such
975 * as the FCoE queue do not require a FP-SB and other components like
976 * the CNIC may consume FP-SB reducing the number of possible L2 queues
977 *
978 * If the maximum number of FP-SB available is X then:
979 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
980 * regular L2 queues is Y=X-1
981 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
982 * c. If the FCoE L2 queue is supported the actual number of L2 queues
983 * is Y+1
984 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
985 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
986 * FP interrupt context for the CNIC).
987 * e. The number of HW context (CID count) is always X or X+1 if FCoE
988 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
989 */
990
991 /* fast-path interrupt contexts E1x */
992 #define FP_SB_MAX_E1x 16
993 /* fast-path interrupt contexts E2 */
994 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
995
996 union cdu_context {
997 struct eth_context eth;
998 char pad[1024];
999 };
1000
1001 /* CDU host DB constants */
1002 #define CDU_ILT_PAGE_SZ_HW 2
1003 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1004 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1005
1006 #ifdef BCM_CNIC
1007 #define CNIC_ISCSI_CID_MAX 256
1008 #define CNIC_FCOE_CID_MAX 2048
1009 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1010 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1011 #endif
1012
1013 #define QM_ILT_PAGE_SZ_HW 0
1014 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1015 #define QM_CID_ROUND 1024
1016
1017 #ifdef BCM_CNIC
1018 /* TM (timers) host DB constants */
1019 #define TM_ILT_PAGE_SZ_HW 0
1020 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1021 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1022 #define TM_CONN_NUM 1024
1023 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1024 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1025
1026 /* SRC (Searcher) host DB constants */
1027 #define SRC_ILT_PAGE_SZ_HW 0
1028 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1029 #define SRC_HASH_BITS 10
1030 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1031 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1032 #define SRC_T2_SZ SRC_ILT_SZ
1033 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1034
1035 #endif
1036
1037 #define MAX_DMAE_C 8
1038
1039 /* DMA memory not used in fastpath */
1040 struct bnx2x_slowpath {
1041 union {
1042 struct mac_configuration_cmd e1x;
1043 struct eth_classify_rules_ramrod_data e2;
1044 } mac_rdata;
1045
1046
1047 union {
1048 struct tstorm_eth_mac_filter_config e1x;
1049 struct eth_filter_rules_ramrod_data e2;
1050 } rx_mode_rdata;
1051
1052 union {
1053 struct mac_configuration_cmd e1;
1054 struct eth_multicast_rules_ramrod_data e2;
1055 } mcast_rdata;
1056
1057 struct eth_rss_update_ramrod_data rss_rdata;
1058
1059 /* Queue State related ramrods are always sent under rtnl_lock */
1060 union {
1061 struct client_init_ramrod_data init_data;
1062 struct client_update_ramrod_data update_data;
1063 } q_rdata;
1064
1065 union {
1066 struct function_start_data func_start;
1067 /* pfc configuration for DCBX ramrod */
1068 struct flow_control_configuration pfc_config;
1069 } func_rdata;
1070
1071 /* afex ramrod can not be a part of func_rdata union because these
1072 * events might arrive in parallel to other events from func_rdata.
1073 * Therefore, if they would have been defined in the same union,
1074 * data can get corrupted.
1075 */
1076 struct afex_vif_list_ramrod_data func_afex_rdata;
1077
1078 /* used by dmae command executer */
1079 struct dmae_command dmae[MAX_DMAE_C];
1080
1081 u32 stats_comp;
1082 union mac_stats mac_stats;
1083 struct nig_stats nig_stats;
1084 struct host_port_stats port_stats;
1085 struct host_func_stats func_stats;
1086
1087 u32 wb_comp;
1088 u32 wb_data[4];
1089
1090 union drv_info_to_mcp drv_info_to_mcp;
1091 };
1092
1093 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1094 #define bnx2x_sp_mapping(bp, var) \
1095 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1096
1097
1098 /* attn group wiring */
1099 #define MAX_DYNAMIC_ATTN_GRPS 8
1100
1101 struct attn_route {
1102 u32 sig[5];
1103 };
1104
1105 struct iro {
1106 u32 base;
1107 u16 m1;
1108 u16 m2;
1109 u16 m3;
1110 u16 size;
1111 };
1112
1113 struct hw_context {
1114 union cdu_context *vcxt;
1115 dma_addr_t cxt_mapping;
1116 size_t size;
1117 };
1118
1119 /* forward */
1120 struct bnx2x_ilt;
1121
1122
1123 enum bnx2x_recovery_state {
1124 BNX2X_RECOVERY_DONE,
1125 BNX2X_RECOVERY_INIT,
1126 BNX2X_RECOVERY_WAIT,
1127 BNX2X_RECOVERY_FAILED,
1128 BNX2X_RECOVERY_NIC_LOADING
1129 };
1130
1131 /*
1132 * Event queue (EQ or event ring) MC hsi
1133 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1134 */
1135 #define NUM_EQ_PAGES 1
1136 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1137 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1138 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1139 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1140 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1141
1142 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1143 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1144 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1145
1146 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1147 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1148
1149 #define BNX2X_EQ_INDEX \
1150 (&bp->def_status_blk->sp_sb.\
1151 index_values[HC_SP_INDEX_EQ_CONS])
1152
1153 /* This is a data that will be used to create a link report message.
1154 * We will keep the data used for the last link report in order
1155 * to prevent reporting the same link parameters twice.
1156 */
1157 struct bnx2x_link_report_data {
1158 u16 line_speed; /* Effective line speed */
1159 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1160 };
1161
1162 enum {
1163 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1164 BNX2X_LINK_REPORT_LINK_DOWN,
1165 BNX2X_LINK_REPORT_RX_FC_ON,
1166 BNX2X_LINK_REPORT_TX_FC_ON,
1167 };
1168
1169 enum {
1170 BNX2X_PORT_QUERY_IDX,
1171 BNX2X_PF_QUERY_IDX,
1172 BNX2X_FCOE_QUERY_IDX,
1173 BNX2X_FIRST_QUEUE_QUERY_IDX,
1174 };
1175
1176 struct bnx2x_fw_stats_req {
1177 struct stats_query_header hdr;
1178 struct stats_query_entry query[FP_SB_MAX_E1x+
1179 BNX2X_FIRST_QUEUE_QUERY_IDX];
1180 };
1181
1182 struct bnx2x_fw_stats_data {
1183 struct stats_counter storm_counters;
1184 struct per_port_stats port;
1185 struct per_pf_stats pf;
1186 struct fcoe_statistics_params fcoe;
1187 struct per_queue_stats queue_stats[1];
1188 };
1189
1190 /* Public slow path states */
1191 enum {
1192 BNX2X_SP_RTNL_SETUP_TC,
1193 BNX2X_SP_RTNL_TX_TIMEOUT,
1194 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1195 BNX2X_SP_RTNL_FAN_FAILURE,
1196 };
1197
1198
1199 struct bnx2x_prev_path_list {
1200 u8 bus;
1201 u8 slot;
1202 u8 path;
1203 struct list_head list;
1204 };
1205
1206 struct bnx2x_sp_objs {
1207 /* MACs object */
1208 struct bnx2x_vlan_mac_obj mac_obj;
1209
1210 /* Queue State object */
1211 struct bnx2x_queue_sp_obj q_obj;
1212 };
1213
1214 struct bnx2x_fp_stats {
1215 struct tstorm_per_queue_stats old_tclient;
1216 struct ustorm_per_queue_stats old_uclient;
1217 struct xstorm_per_queue_stats old_xclient;
1218 struct bnx2x_eth_q_stats eth_q_stats;
1219 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1220 };
1221
1222 struct bnx2x {
1223 /* Fields used in the tx and intr/napi performance paths
1224 * are grouped together in the beginning of the structure
1225 */
1226 struct bnx2x_fastpath *fp;
1227 struct bnx2x_sp_objs *sp_objs;
1228 struct bnx2x_fp_stats *fp_stats;
1229 struct bnx2x_fp_txdata *bnx2x_txq;
1230 int bnx2x_txq_size;
1231 void __iomem *regview;
1232 void __iomem *doorbells;
1233 u16 db_size;
1234
1235 u8 pf_num; /* absolute PF number */
1236 u8 pfid; /* per-path PF number */
1237 int base_fw_ndsb; /**/
1238 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1239 #define BP_PORT(bp) (bp->pfid & 1)
1240 #define BP_FUNC(bp) (bp->pfid)
1241 #define BP_ABS_FUNC(bp) (bp->pf_num)
1242 #define BP_VN(bp) ((bp)->pfid >> 1)
1243 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1244 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1245 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1246 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1247 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1248
1249 struct net_device *dev;
1250 struct pci_dev *pdev;
1251
1252 const struct iro *iro_arr;
1253 #define IRO (bp->iro_arr)
1254
1255 enum bnx2x_recovery_state recovery_state;
1256 int is_leader;
1257 struct msix_entry *msix_table;
1258
1259 int tx_ring_size;
1260
1261 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1262 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1263 #define ETH_MIN_PACKET_SIZE 60
1264 #define ETH_MAX_PACKET_SIZE 1500
1265 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1266 /* TCP with Timestamp Option (32) + IPv6 (40) */
1267 #define ETH_MAX_TPA_HEADER_SIZE 72
1268
1269 /* Max supported alignment is 256 (8 shift) */
1270 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1271
1272 /* FW uses 2 Cache lines Alignment for start packet and size
1273 *
1274 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1275 * at the end of skb->data, to avoid wasting a full cache line.
1276 * This reduces memory use (skb->truesize).
1277 */
1278 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1279
1280 #define BNX2X_FW_RX_ALIGN_END \
1281 max(1UL << BNX2X_RX_ALIGN_SHIFT, \
1282 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1283
1284 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1285
1286 struct host_sp_status_block *def_status_blk;
1287 #define DEF_SB_IGU_ID 16
1288 #define DEF_SB_ID HC_SP_SB_ID
1289 __le16 def_idx;
1290 __le16 def_att_idx;
1291 u32 attn_state;
1292 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1293
1294 /* slow path ring */
1295 struct eth_spe *spq;
1296 dma_addr_t spq_mapping;
1297 u16 spq_prod_idx;
1298 struct eth_spe *spq_prod_bd;
1299 struct eth_spe *spq_last_bd;
1300 __le16 *dsb_sp_prod;
1301 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1302 /* used to synchronize spq accesses */
1303 spinlock_t spq_lock;
1304
1305 /* event queue */
1306 union event_ring_elem *eq_ring;
1307 dma_addr_t eq_mapping;
1308 u16 eq_prod;
1309 u16 eq_cons;
1310 __le16 *eq_cons_sb;
1311 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1312
1313
1314
1315 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1316 u16 stats_pending;
1317 /* Counter for completed statistics ramrods */
1318 u16 stats_comp;
1319
1320 /* End of fields used in the performance code paths */
1321
1322 int panic;
1323 int msg_enable;
1324
1325 u32 flags;
1326 #define PCIX_FLAG (1 << 0)
1327 #define PCI_32BIT_FLAG (1 << 1)
1328 #define ONE_PORT_FLAG (1 << 2)
1329 #define NO_WOL_FLAG (1 << 3)
1330 #define USING_DAC_FLAG (1 << 4)
1331 #define USING_MSIX_FLAG (1 << 5)
1332 #define USING_MSI_FLAG (1 << 6)
1333 #define DISABLE_MSI_FLAG (1 << 7)
1334 #define TPA_ENABLE_FLAG (1 << 8)
1335 #define NO_MCP_FLAG (1 << 9)
1336
1337 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1338 #define GRO_ENABLE_FLAG (1 << 10)
1339 #define MF_FUNC_DIS (1 << 11)
1340 #define OWN_CNIC_IRQ (1 << 12)
1341 #define NO_ISCSI_OOO_FLAG (1 << 13)
1342 #define NO_ISCSI_FLAG (1 << 14)
1343 #define NO_FCOE_FLAG (1 << 15)
1344 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1345 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1346 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1347 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1348
1349 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1350 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1351 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1352
1353 int pm_cap;
1354 int mrrs;
1355
1356 struct delayed_work sp_task;
1357 struct delayed_work sp_rtnl_task;
1358
1359 struct delayed_work period_task;
1360 struct timer_list timer;
1361 int current_interval;
1362
1363 u16 fw_seq;
1364 u16 fw_drv_pulse_wr_seq;
1365 u32 func_stx;
1366
1367 struct link_params link_params;
1368 struct link_vars link_vars;
1369 u32 link_cnt;
1370 struct bnx2x_link_report_data last_reported_link;
1371
1372 struct mdio_if_info mdio;
1373
1374 struct bnx2x_common common;
1375 struct bnx2x_port port;
1376
1377 struct cmng_init cmng;
1378
1379 u32 mf_config[E1HVN_MAX];
1380 u32 mf_ext_config;
1381 u32 path_has_ovlan; /* E3 */
1382 u16 mf_ov;
1383 u8 mf_mode;
1384 #define IS_MF(bp) (bp->mf_mode != 0)
1385 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1386 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1387 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1388
1389 u8 wol;
1390
1391 int rx_ring_size;
1392
1393 u16 tx_quick_cons_trip_int;
1394 u16 tx_quick_cons_trip;
1395 u16 tx_ticks_int;
1396 u16 tx_ticks;
1397
1398 u16 rx_quick_cons_trip_int;
1399 u16 rx_quick_cons_trip;
1400 u16 rx_ticks_int;
1401 u16 rx_ticks;
1402 /* Maximal coalescing timeout in us */
1403 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1404
1405 u32 lin_cnt;
1406
1407 u16 state;
1408 #define BNX2X_STATE_CLOSED 0
1409 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1410 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1411 #define BNX2X_STATE_OPEN 0x3000
1412 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1413 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1414
1415 #define BNX2X_STATE_DIAG 0xe000
1416 #define BNX2X_STATE_ERROR 0xf000
1417
1418 #define BNX2X_MAX_PRIORITY 8
1419 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1420 #define BNX2X_MAX_COS 3
1421 #define BNX2X_MAX_TX_COS 2
1422 int num_queues;
1423 int num_napi_queues;
1424 int disable_tpa;
1425
1426 u32 rx_mode;
1427 #define BNX2X_RX_MODE_NONE 0
1428 #define BNX2X_RX_MODE_NORMAL 1
1429 #define BNX2X_RX_MODE_ALLMULTI 2
1430 #define BNX2X_RX_MODE_PROMISC 3
1431 #define BNX2X_MAX_MULTICAST 64
1432
1433 u8 igu_dsb_id;
1434 u8 igu_base_sb;
1435 u8 igu_sb_cnt;
1436
1437 dma_addr_t def_status_blk_mapping;
1438
1439 struct bnx2x_slowpath *slowpath;
1440 dma_addr_t slowpath_mapping;
1441
1442 /* Total number of FW statistics requests */
1443 u8 fw_stats_num;
1444
1445 /*
1446 * This is a memory buffer that will contain both statistics
1447 * ramrod request and data.
1448 */
1449 void *fw_stats;
1450 dma_addr_t fw_stats_mapping;
1451
1452 /*
1453 * FW statistics request shortcut (points at the
1454 * beginning of fw_stats buffer).
1455 */
1456 struct bnx2x_fw_stats_req *fw_stats_req;
1457 dma_addr_t fw_stats_req_mapping;
1458 int fw_stats_req_sz;
1459
1460 /*
1461 * FW statistics data shortcut (points at the begining of
1462 * fw_stats buffer + fw_stats_req_sz).
1463 */
1464 struct bnx2x_fw_stats_data *fw_stats_data;
1465 dma_addr_t fw_stats_data_mapping;
1466 int fw_stats_data_sz;
1467
1468 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1469 * context size we need 8 ILT entries.
1470 */
1471 #define ILT_MAX_L2_LINES 8
1472 struct hw_context context[ILT_MAX_L2_LINES];
1473
1474 struct bnx2x_ilt *ilt;
1475 #define BP_ILT(bp) ((bp)->ilt)
1476 #define ILT_MAX_LINES 256
1477 /*
1478 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1479 * to CNIC.
1480 */
1481 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1482
1483 /*
1484 * Maximum CID count that might be required by the bnx2x:
1485 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1486 */
1487 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1488 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1489 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1490 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1491 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1492 ILT_PAGE_CIDS))
1493
1494 int qm_cid_count;
1495
1496 int dropless_fc;
1497
1498 #ifdef BCM_CNIC
1499 u32 cnic_flags;
1500 #define BNX2X_CNIC_FLAG_MAC_SET 1
1501 void *t2;
1502 dma_addr_t t2_mapping;
1503 struct cnic_ops __rcu *cnic_ops;
1504 void *cnic_data;
1505 u32 cnic_tag;
1506 struct cnic_eth_dev cnic_eth_dev;
1507 union host_hc_status_block cnic_sb;
1508 dma_addr_t cnic_sb_mapping;
1509 struct eth_spe *cnic_kwq;
1510 struct eth_spe *cnic_kwq_prod;
1511 struct eth_spe *cnic_kwq_cons;
1512 struct eth_spe *cnic_kwq_last;
1513 u16 cnic_kwq_pending;
1514 u16 cnic_spq_pending;
1515 u8 fip_mac[ETH_ALEN];
1516 struct mutex cnic_mutex;
1517 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1518
1519 /* Start index of the "special" (CNIC related) L2 cleints */
1520 u8 cnic_base_cl_id;
1521 #endif
1522
1523 int dmae_ready;
1524 /* used to synchronize dmae accesses */
1525 spinlock_t dmae_lock;
1526
1527 /* used to protect the FW mail box */
1528 struct mutex fw_mb_mutex;
1529
1530 /* used to synchronize stats collecting */
1531 int stats_state;
1532
1533 /* used for synchronization of concurrent threads statistics handling */
1534 spinlock_t stats_lock;
1535
1536 /* used by dmae command loader */
1537 struct dmae_command stats_dmae;
1538 int executer_idx;
1539
1540 u16 stats_counter;
1541 struct bnx2x_eth_stats eth_stats;
1542 struct host_func_stats func_stats;
1543 struct bnx2x_eth_stats_old eth_stats_old;
1544 struct bnx2x_net_stats_old net_stats_old;
1545 struct bnx2x_fw_port_stats_old fw_stats_old;
1546 bool stats_init;
1547
1548 struct z_stream_s *strm;
1549 void *gunzip_buf;
1550 dma_addr_t gunzip_mapping;
1551 int gunzip_outlen;
1552 #define FW_BUF_SIZE 0x8000
1553 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1554 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1555 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1556
1557 struct raw_op *init_ops;
1558 /* Init blocks offsets inside init_ops */
1559 u16 *init_ops_offsets;
1560 /* Data blob - has 32 bit granularity */
1561 u32 *init_data;
1562 u32 init_mode_flags;
1563 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1564 /* Zipped PRAM blobs - raw data */
1565 const u8 *tsem_int_table_data;
1566 const u8 *tsem_pram_data;
1567 const u8 *usem_int_table_data;
1568 const u8 *usem_pram_data;
1569 const u8 *xsem_int_table_data;
1570 const u8 *xsem_pram_data;
1571 const u8 *csem_int_table_data;
1572 const u8 *csem_pram_data;
1573 #define INIT_OPS(bp) (bp->init_ops)
1574 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1575 #define INIT_DATA(bp) (bp->init_data)
1576 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1577 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1578 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1579 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1580 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1581 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1582 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1583 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1584
1585 #define PHY_FW_VER_LEN 20
1586 char fw_ver[32];
1587 const struct firmware *firmware;
1588
1589 /* DCB support on/off */
1590 u16 dcb_state;
1591 #define BNX2X_DCB_STATE_OFF 0
1592 #define BNX2X_DCB_STATE_ON 1
1593
1594 /* DCBX engine mode */
1595 int dcbx_enabled;
1596 #define BNX2X_DCBX_ENABLED_OFF 0
1597 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1598 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1599 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1600
1601 bool dcbx_mode_uset;
1602
1603 struct bnx2x_config_dcbx_params dcbx_config_params;
1604 struct bnx2x_dcbx_port_params dcbx_port_params;
1605 int dcb_version;
1606
1607 /* CAM credit pools */
1608 struct bnx2x_credit_pool_obj macs_pool;
1609
1610 /* RX_MODE object */
1611 struct bnx2x_rx_mode_obj rx_mode_obj;
1612
1613 /* MCAST object */
1614 struct bnx2x_mcast_obj mcast_obj;
1615
1616 /* RSS configuration object */
1617 struct bnx2x_rss_config_obj rss_conf_obj;
1618
1619 /* Function State controlling object */
1620 struct bnx2x_func_sp_obj func_obj;
1621
1622 unsigned long sp_state;
1623
1624 /* operation indication for the sp_rtnl task */
1625 unsigned long sp_rtnl_state;
1626
1627 /* DCBX Negotation results */
1628 struct dcbx_features dcbx_local_feat;
1629 u32 dcbx_error;
1630
1631 #ifdef BCM_DCBNL
1632 struct dcbx_features dcbx_remote_feat;
1633 u32 dcbx_remote_flags;
1634 #endif
1635 /* AFEX: store default vlan used */
1636 int afex_def_vlan_tag;
1637 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1638 u32 pending_max;
1639
1640 /* multiple tx classes of service */
1641 u8 max_cos;
1642
1643 /* priority to cos mapping */
1644 u8 prio_to_cos[8];
1645 };
1646
1647 /* Tx queues may be less or equal to Rx queues */
1648 extern int num_queues;
1649 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1650 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1651 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1652 NON_ETH_CONTEXT_USE)
1653 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1654
1655 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1656
1657 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1658 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1659
1660 #define RSS_IPV4_CAP_MASK \
1661 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1662
1663 #define RSS_IPV4_TCP_CAP_MASK \
1664 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1665
1666 #define RSS_IPV6_CAP_MASK \
1667 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1668
1669 #define RSS_IPV6_TCP_CAP_MASK \
1670 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1671
1672 /* func init flags */
1673 #define FUNC_FLG_RSS 0x0001
1674 #define FUNC_FLG_STATS 0x0002
1675 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1676 #define FUNC_FLG_TPA 0x0008
1677 #define FUNC_FLG_SPQ 0x0010
1678 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1679
1680
1681 struct bnx2x_func_init_params {
1682 /* dma */
1683 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1684 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1685
1686 u16 func_flgs;
1687 u16 func_id; /* abs fid */
1688 u16 pf_id;
1689 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1690 };
1691
1692 #define for_each_eth_queue(bp, var) \
1693 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1694
1695 #define for_each_nondefault_eth_queue(bp, var) \
1696 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1697
1698 #define for_each_queue(bp, var) \
1699 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1700 if (skip_queue(bp, var)) \
1701 continue; \
1702 else
1703
1704 /* Skip forwarding FP */
1705 #define for_each_rx_queue(bp, var) \
1706 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1707 if (skip_rx_queue(bp, var)) \
1708 continue; \
1709 else
1710
1711 #define for_each_napi_rx_queue(bp, var) \
1712 for ((var) = 0; (var) < bp->num_napi_queues; (var)++)
1713
1714 /* Skip OOO FP */
1715 #define for_each_tx_queue(bp, var) \
1716 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1717 if (skip_tx_queue(bp, var)) \
1718 continue; \
1719 else
1720
1721 #define for_each_nondefault_queue(bp, var) \
1722 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1723 if (skip_queue(bp, var)) \
1724 continue; \
1725 else
1726
1727 #define for_each_cos_in_tx_queue(fp, var) \
1728 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1729
1730 /* skip rx queue
1731 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1732 */
1733 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1734
1735 /* skip tx queue
1736 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1737 */
1738 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1739
1740 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1741
1742
1743
1744
1745 /**
1746 * bnx2x_set_mac_one - configure a single MAC address
1747 *
1748 * @bp: driver handle
1749 * @mac: MAC to configure
1750 * @obj: MAC object handle
1751 * @set: if 'true' add a new MAC, otherwise - delete
1752 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1753 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1754 *
1755 * Configures one MAC according to provided parameters or continues the
1756 * execution of previously scheduled commands if RAMROD_CONT is set in
1757 * ramrod_flags.
1758 *
1759 * Returns zero if operation has successfully completed, a positive value if the
1760 * operation has been successfully scheduled and a negative - if a requested
1761 * operations has failed.
1762 */
1763 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1764 struct bnx2x_vlan_mac_obj *obj, bool set,
1765 int mac_type, unsigned long *ramrod_flags);
1766 /**
1767 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1768 *
1769 * @bp: driver handle
1770 * @mac_obj: MAC object handle
1771 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1772 * @wait_for_comp: if 'true' block until completion
1773 *
1774 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1775 *
1776 * Returns zero if operation has successfully completed, a positive value if the
1777 * operation has been successfully scheduled and a negative - if a requested
1778 * operations has failed.
1779 */
1780 int bnx2x_del_all_macs(struct bnx2x *bp,
1781 struct bnx2x_vlan_mac_obj *mac_obj,
1782 int mac_type, bool wait_for_comp);
1783
1784 /* Init Function API */
1785 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1786 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1787 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1788 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1789 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1790 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1791
1792
1793 /* dmae */
1794 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1795 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1796 u32 len32);
1797 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1798 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1799 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1800 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1801 bool with_comp, u8 comp_type);
1802
1803
1804 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1805 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1806 u32 data_hi, u32 data_lo, int cmd_type);
1807 void bnx2x_update_coalesce(struct bnx2x *bp);
1808 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1809
1810 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1811 int wait)
1812 {
1813 u32 val;
1814
1815 do {
1816 val = REG_RD(bp, reg);
1817 if (val == expected)
1818 break;
1819 ms -= wait;
1820 msleep(wait);
1821
1822 } while (ms > 0);
1823
1824 return val;
1825 }
1826
1827 #define BNX2X_ILT_ZALLOC(x, y, size) \
1828 do { \
1829 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1830 if (x) \
1831 memset(x, 0, size); \
1832 } while (0)
1833
1834 #define BNX2X_ILT_FREE(x, y, size) \
1835 do { \
1836 if (x) { \
1837 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1838 x = NULL; \
1839 y = 0; \
1840 } \
1841 } while (0)
1842
1843 #define ILOG2(x) (ilog2((x)))
1844
1845 #define ILT_NUM_PAGE_ENTRIES (3072)
1846 /* In 57710/11 we use whole table since we have 8 func
1847 * In 57712 we have only 4 func, but use same size per func, then only half of
1848 * the table in use
1849 */
1850 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1851
1852 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1853 /*
1854 * the phys address is shifted right 12 bits and has an added
1855 * 1=valid bit added to the 53rd bit
1856 * then since this is a wide register(TM)
1857 * we split it into two 32 bit writes
1858 */
1859 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1860 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1861
1862 /* load/unload mode */
1863 #define LOAD_NORMAL 0
1864 #define LOAD_OPEN 1
1865 #define LOAD_DIAG 2
1866 #define LOAD_LOOPBACK_EXT 3
1867 #define UNLOAD_NORMAL 0
1868 #define UNLOAD_CLOSE 1
1869 #define UNLOAD_RECOVERY 2
1870
1871
1872 /* DMAE command defines */
1873 #define DMAE_TIMEOUT -1
1874 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1875 #define DMAE_NOT_RDY -3
1876 #define DMAE_PCI_ERR_FLAG 0x80000000
1877
1878 #define DMAE_SRC_PCI 0
1879 #define DMAE_SRC_GRC 1
1880
1881 #define DMAE_DST_NONE 0
1882 #define DMAE_DST_PCI 1
1883 #define DMAE_DST_GRC 2
1884
1885 #define DMAE_COMP_PCI 0
1886 #define DMAE_COMP_GRC 1
1887
1888 /* E2 and onward - PCI error handling in the completion */
1889
1890 #define DMAE_COMP_REGULAR 0
1891 #define DMAE_COM_SET_ERR 1
1892
1893 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1894 DMAE_COMMAND_SRC_SHIFT)
1895 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1896 DMAE_COMMAND_SRC_SHIFT)
1897
1898 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1899 DMAE_COMMAND_DST_SHIFT)
1900 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1901 DMAE_COMMAND_DST_SHIFT)
1902
1903 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1904 DMAE_COMMAND_C_DST_SHIFT)
1905 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1906 DMAE_COMMAND_C_DST_SHIFT)
1907
1908 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1909
1910 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1911 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1912 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1913 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1914
1915 #define DMAE_CMD_PORT_0 0
1916 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1917
1918 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1919 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1920 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1921
1922 #define DMAE_SRC_PF 0
1923 #define DMAE_SRC_VF 1
1924
1925 #define DMAE_DST_PF 0
1926 #define DMAE_DST_VF 1
1927
1928 #define DMAE_C_SRC 0
1929 #define DMAE_C_DST 1
1930
1931 #define DMAE_LEN32_RD_MAX 0x80
1932 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1933
1934 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1935 indicates eror */
1936
1937 #define MAX_DMAE_C_PER_PORT 8
1938 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1939 BP_VN(bp))
1940 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1941 E1HVN_MAX)
1942
1943 /* PCIE link and speed */
1944 #define PCICFG_LINK_WIDTH 0x1f00000
1945 #define PCICFG_LINK_WIDTH_SHIFT 20
1946 #define PCICFG_LINK_SPEED 0xf0000
1947 #define PCICFG_LINK_SPEED_SHIFT 16
1948
1949 #define BNX2X_NUM_TESTS_SF 7
1950 #define BNX2X_NUM_TESTS_MF 3
1951 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
1952 BNX2X_NUM_TESTS_SF)
1953
1954 #define BNX2X_PHY_LOOPBACK 0
1955 #define BNX2X_MAC_LOOPBACK 1
1956 #define BNX2X_EXT_LOOPBACK 2
1957 #define BNX2X_PHY_LOOPBACK_FAILED 1
1958 #define BNX2X_MAC_LOOPBACK_FAILED 2
1959 #define BNX2X_EXT_LOOPBACK_FAILED 3
1960 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1961 BNX2X_PHY_LOOPBACK_FAILED)
1962
1963
1964 #define STROM_ASSERT_ARRAY_SIZE 50
1965
1966
1967 /* must be used on a CID before placing it on a HW ring */
1968 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1969 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1970 (x))
1971
1972 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1973 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1974
1975
1976 #define BNX2X_BTR 4
1977 #define MAX_SPQ_PENDING 8
1978
1979 /* CMNG constants, as derived from system spec calculations */
1980 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1981 #define DEF_MIN_RATE 100
1982 /* resolution of the rate shaping timer - 400 usec */
1983 #define RS_PERIODIC_TIMEOUT_USEC 400
1984 /* number of bytes in single QM arbitration cycle -
1985 * coefficient for calculating the fairness timer */
1986 #define QM_ARB_BYTES 160000
1987 /* resolution of Min algorithm 1:100 */
1988 #define MIN_RES 100
1989 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1990 #define MIN_ABOVE_THRESH 32768
1991 /* Fairness algorithm integration time coefficient -
1992 * for calculating the actual Tfair */
1993 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1994 /* Memory of fairness algorithm . 2 cycles */
1995 #define FAIR_MEM 2
1996
1997
1998 #define ATTN_NIG_FOR_FUNC (1L << 8)
1999 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2000 #define GPIO_2_FUNC (1L << 10)
2001 #define GPIO_3_FUNC (1L << 11)
2002 #define GPIO_4_FUNC (1L << 12)
2003 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2004 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2005 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2006 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2007 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2008 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2009
2010 #define ATTN_HARD_WIRED_MASK 0xff00
2011 #define ATTENTION_ID 4
2012
2013
2014 /* stuff added to make the code fit 80Col */
2015
2016 #define BNX2X_PMF_LINK_ASSERT \
2017 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2018
2019 #define BNX2X_MC_ASSERT_BITS \
2020 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2021 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2022 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2023 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2024
2025 #define BNX2X_MCP_ASSERT \
2026 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2027
2028 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2029 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2030 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2031 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2032 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2033 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2034 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2035
2036 #define HW_INTERRUT_ASSERT_SET_0 \
2037 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2038 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2039 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2040 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2041 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2042 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2043 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2044 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2045 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2046 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2047 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2048 #define HW_INTERRUT_ASSERT_SET_1 \
2049 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2050 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2051 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2052 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2053 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2054 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2055 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2056 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2057 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2058 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2059 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2060 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2061 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2062 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2063 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2064 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2065 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2066 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2067 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2068 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2069 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2070 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2071 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2072 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2073 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2074 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2075 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2076 #define HW_INTERRUT_ASSERT_SET_2 \
2077 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2078 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2079 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2080 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2081 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2082 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2083 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2084 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2085 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2086 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2087 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2088 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2089 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2090
2091 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2092 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2093 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2094 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2095
2096 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2097 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2098
2099 #define MULTI_MASK 0x7f
2100
2101
2102 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2103 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2104 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2105 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2106
2107 #define DEF_USB_IGU_INDEX_OFF \
2108 offsetof(struct cstorm_def_status_block_u, igu_index)
2109 #define DEF_CSB_IGU_INDEX_OFF \
2110 offsetof(struct cstorm_def_status_block_c, igu_index)
2111 #define DEF_XSB_IGU_INDEX_OFF \
2112 offsetof(struct xstorm_def_status_block, igu_index)
2113 #define DEF_TSB_IGU_INDEX_OFF \
2114 offsetof(struct tstorm_def_status_block, igu_index)
2115
2116 #define DEF_USB_SEGMENT_OFF \
2117 offsetof(struct cstorm_def_status_block_u, segment)
2118 #define DEF_CSB_SEGMENT_OFF \
2119 offsetof(struct cstorm_def_status_block_c, segment)
2120 #define DEF_XSB_SEGMENT_OFF \
2121 offsetof(struct xstorm_def_status_block, segment)
2122 #define DEF_TSB_SEGMENT_OFF \
2123 offsetof(struct tstorm_def_status_block, segment)
2124
2125 #define BNX2X_SP_DSB_INDEX \
2126 (&bp->def_status_blk->sp_sb.\
2127 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2128
2129 #define SET_FLAG(value, mask, flag) \
2130 do {\
2131 (value) &= ~(mask);\
2132 (value) |= ((flag) << (mask##_SHIFT));\
2133 } while (0)
2134
2135 #define GET_FLAG(value, mask) \
2136 (((value) & (mask)) >> (mask##_SHIFT))
2137
2138 #define GET_FIELD(value, fname) \
2139 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2140
2141 #define CAM_IS_INVALID(x) \
2142 (GET_FLAG(x.flags, \
2143 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2144 (T_ETH_MAC_COMMAND_INVALIDATE))
2145
2146 /* Number of u32 elements in MC hash array */
2147 #define MC_HASH_SIZE 8
2148 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2149 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2150
2151
2152 #ifndef PXP2_REG_PXP2_INT_STS
2153 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2154 #endif
2155
2156 #ifndef ETH_MAX_RX_CLIENTS_E2
2157 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2158 #endif
2159
2160 #define BNX2X_VPD_LEN 128
2161 #define VENDOR_ID_LEN 4
2162
2163 /* Congestion management fairness mode */
2164 #define CMNG_FNS_NONE 0
2165 #define CMNG_FNS_MINMAX 1
2166
2167 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2168 #define HC_SEG_ACCESS_ATTN 4
2169 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2170
2171 static const u32 dmae_reg_go_c[] = {
2172 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2173 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2174 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2175 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2176 };
2177
2178 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2179 void bnx2x_notify_link_changed(struct bnx2x *bp);
2180
2181
2182 #define BNX2X_MF_SD_PROTOCOL(bp) \
2183 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2184
2185 #ifdef BCM_CNIC
2186 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2187 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2188
2189 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2190 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2191
2192 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2193 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2194
2195 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2196 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2197
2198 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2199 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2200 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2201 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2202 #else
2203 #define IS_MF_FCOE_AFEX(bp) false
2204 #endif
2205
2206
2207 #endif /* bnx2x.h */
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