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memcg: remove impossible conditional when committing
[linux-2.6.git] / drivers / ata / sata_fsl.c
blob0f91e583892e19a4578501407d0b816584bac83e
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007, 2011 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_platform.h>
28
29 /* Controller information */
30 enum {
31 SATA_FSL_QUEUE_DEPTH = 16,
32 SATA_FSL_MAX_PRD = 63,
33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
35
36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contiguous) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83 };
84
85 /*
86 * Host Controller command register set - per port
87 */
88 enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE_V1 = (1 << 22),
161 DATA_SNOOP_ENABLE_V2 = (1 << 28),
162 };
163
164 /*
165 * SATA Superset Registers
166 */
167 enum {
168 SSTATUS = 0,
169 SERROR = 4,
170 SCONTROL = 8,
171 SNOTIFY = 0xC,
172 };
173
174 /*
175 * Control Status Register Set
176 */
177 enum {
178 TRANSCFG = 0,
179 TRANSSTATUS = 4,
180 LINKCFG = 8,
181 LINKCFG1 = 0xC,
182 LINKCFG2 = 0x10,
183 LINKSTATUS = 0x14,
184 LINKSTATUS1 = 0x18,
185 PHYCTRLCFG = 0x1C,
186 COMMANDSTAT = 0x20,
187 };
188
189 /* TRANSCFG (transport-layer) configuration control */
190 enum {
191 TRANSCFG_RX_WATER_MARK = (1 << 4),
192 };
193
194 /* PHY (link-layer) configuration control */
195 enum {
196 PHY_BIST_ENABLE = 0x01,
197 };
198
199 /*
200 * Command Header Table entry, i.e, command slot
201 * 4 Dwords per command slot, command header size == 64 Dwords.
202 */
203 struct cmdhdr_tbl_entry {
204 u32 cda;
205 u32 prde_fis_len;
206 u32 ttl;
207 u32 desc_info;
208 };
209
210 /*
211 * Description information bitdefs
212 */
213 enum {
214 CMD_DESC_RES = (1 << 11),
215 VENDOR_SPECIFIC_BIST = (1 << 10),
216 CMD_DESC_SNOOP_ENABLE = (1 << 9),
217 FPDMA_QUEUED_CMD = (1 << 8),
218 SRST_CMD = (1 << 7),
219 BIST = (1 << 6),
220 ATAPI_CMD = (1 << 5),
221 };
222
223 /*
224 * Command Descriptor
225 */
226 struct command_desc {
227 u8 cfis[8 * 4];
228 u8 sfis[8 * 4];
229 u8 acmd[4 * 4];
230 u8 fill[4 * 4];
231 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
232 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
233 };
234
235 /*
236 * Physical region table descriptor(PRD)
237 */
238
239 struct prde {
240 u32 dba;
241 u8 fill[2 * 4];
242 u32 ddc_and_ext;
243 };
244
245 /*
246 * ata_port private data
247 * This is our per-port instance data.
248 */
249 struct sata_fsl_port_priv {
250 struct cmdhdr_tbl_entry *cmdslot;
251 dma_addr_t cmdslot_paddr;
252 struct command_desc *cmdentry;
253 dma_addr_t cmdentry_paddr;
254 };
255
256 /*
257 * ata_port->host_set private data
258 */
259 struct sata_fsl_host_priv {
260 void __iomem *hcr_base;
261 void __iomem *ssr_base;
262 void __iomem *csr_base;
263 int irq;
264 int data_snoop;
265 };
266
267 static inline unsigned int sata_fsl_tag(unsigned int tag,
268 void __iomem *hcr_base)
269 {
270 /* We let libATA core do actual (queue) tag allocation */
271
272 /* all non NCQ/queued commands should have tag#0 */
273 if (ata_tag_internal(tag)) {
274 DPRINTK("mapping internal cmds to tag#0\n");
275 return 0;
276 }
277
278 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
279 DPRINTK("tag %d invalid : out of range\n", tag);
280 return 0;
281 }
282
283 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
284 DPRINTK("tag %d invalid : in use!!\n", tag);
285 return 0;
286 }
287
288 return tag;
289 }
290
291 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
292 unsigned int tag, u32 desc_info,
293 u32 data_xfer_len, u8 num_prde,
294 u8 fis_len)
295 {
296 dma_addr_t cmd_descriptor_address;
297
298 cmd_descriptor_address = pp->cmdentry_paddr +
299 tag * SATA_FSL_CMD_DESC_SIZE;
300
301 /* NOTE: both data_xfer_len & fis_len are Dword counts */
302
303 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
304 pp->cmdslot[tag].prde_fis_len =
305 cpu_to_le32((num_prde << 16) | (fis_len << 2));
306 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
307 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
308
309 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
310 pp->cmdslot[tag].cda,
311 pp->cmdslot[tag].prde_fis_len,
312 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
313
314 }
315
316 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
317 u32 *ttl, dma_addr_t cmd_desc_paddr,
318 int data_snoop)
319 {
320 struct scatterlist *sg;
321 unsigned int num_prde = 0;
322 u32 ttl_dwords = 0;
323
324 /*
325 * NOTE : direct & indirect prdt's are contiguously allocated
326 */
327 struct prde *prd = (struct prde *)&((struct command_desc *)
328 cmd_desc)->prdt;
329
330 struct prde *prd_ptr_to_indirect_ext = NULL;
331 unsigned indirect_ext_segment_sz = 0;
332 dma_addr_t indirect_ext_segment_paddr;
333 unsigned int si;
334
335 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
336
337 indirect_ext_segment_paddr = cmd_desc_paddr +
338 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
339
340 for_each_sg(qc->sg, sg, qc->n_elem, si) {
341 dma_addr_t sg_addr = sg_dma_address(sg);
342 u32 sg_len = sg_dma_len(sg);
343
344 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
345 (unsigned long long)sg_addr, sg_len);
346
347 /* warn if each s/g element is not dword aligned */
348 if (sg_addr & 0x03)
349 ata_port_printk(qc->ap, KERN_ERR,
350 "s/g addr unaligned : 0x%llx\n",
351 (unsigned long long)sg_addr);
352 if (sg_len & 0x03)
353 ata_port_printk(qc->ap, KERN_ERR,
354 "s/g len unaligned : 0x%x\n", sg_len);
355
356 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
357 sg_next(sg) != NULL) {
358 VPRINTK("setting indirect prde\n");
359 prd_ptr_to_indirect_ext = prd;
360 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
361 indirect_ext_segment_sz = 0;
362 ++prd;
363 ++num_prde;
364 }
365
366 ttl_dwords += sg_len;
367 prd->dba = cpu_to_le32(sg_addr);
368 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
369
370 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
371 ttl_dwords, prd->dba, prd->ddc_and_ext);
372
373 ++num_prde;
374 ++prd;
375 if (prd_ptr_to_indirect_ext)
376 indirect_ext_segment_sz += sg_len;
377 }
378
379 if (prd_ptr_to_indirect_ext) {
380 /* set indirect extension flag along with indirect ext. size */
381 prd_ptr_to_indirect_ext->ddc_and_ext =
382 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
383 data_snoop |
384 (indirect_ext_segment_sz & ~0x03)));
385 }
386
387 *ttl = ttl_dwords;
388 return num_prde;
389 }
390
391 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
392 {
393 struct ata_port *ap = qc->ap;
394 struct sata_fsl_port_priv *pp = ap->private_data;
395 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
396 void __iomem *hcr_base = host_priv->hcr_base;
397 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
398 struct command_desc *cd;
399 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
400 u32 num_prde = 0;
401 u32 ttl_dwords = 0;
402 dma_addr_t cd_paddr;
403
404 cd = (struct command_desc *)pp->cmdentry + tag;
405 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
406
407 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
408
409 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
410 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
411
412 if (qc->tf.protocol == ATA_PROT_NCQ) {
413 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
414 cd->cfis[3], cd->cfis[11]);
415 }
416
417 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
418 if (ata_is_atapi(qc->tf.protocol)) {
419 desc_info |= ATAPI_CMD;
420 memset((void *)&cd->acmd, 0, 32);
421 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
422 }
423
424 if (qc->flags & ATA_QCFLAG_DMAMAP)
425 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
426 &ttl_dwords, cd_paddr,
427 host_priv->data_snoop);
428
429 if (qc->tf.protocol == ATA_PROT_NCQ)
430 desc_info |= FPDMA_QUEUED_CMD;
431
432 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
433 num_prde, 5);
434
435 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
436 desc_info, ttl_dwords, num_prde);
437 }
438
439 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
440 {
441 struct ata_port *ap = qc->ap;
442 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
443 void __iomem *hcr_base = host_priv->hcr_base;
444 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
445
446 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
447 ioread32(CQ + hcr_base),
448 ioread32(CA + hcr_base),
449 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
450
451 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
452
453 /* Simply queue command to the controller/device */
454 iowrite32(1 << tag, CQ + hcr_base);
455
456 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
457 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
458
459 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
460 ioread32(CE + hcr_base),
461 ioread32(DE + hcr_base),
462 ioread32(CC + hcr_base),
463 ioread32(COMMANDSTAT + host_priv->csr_base));
464
465 return 0;
466 }
467
468 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
469 {
470 struct sata_fsl_port_priv *pp = qc->ap->private_data;
471 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
472 void __iomem *hcr_base = host_priv->hcr_base;
473 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
474 struct command_desc *cd;
475
476 cd = pp->cmdentry + tag;
477
478 ata_tf_from_fis(cd->sfis, &qc->result_tf);
479 return true;
480 }
481
482 static int sata_fsl_scr_write(struct ata_link *link,
483 unsigned int sc_reg_in, u32 val)
484 {
485 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
486 void __iomem *ssr_base = host_priv->ssr_base;
487 unsigned int sc_reg;
488
489 switch (sc_reg_in) {
490 case SCR_STATUS:
491 case SCR_ERROR:
492 case SCR_CONTROL:
493 case SCR_ACTIVE:
494 sc_reg = sc_reg_in;
495 break;
496 default:
497 return -EINVAL;
498 }
499
500 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
501
502 iowrite32(val, ssr_base + (sc_reg * 4));
503 return 0;
504 }
505
506 static int sata_fsl_scr_read(struct ata_link *link,
507 unsigned int sc_reg_in, u32 *val)
508 {
509 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
510 void __iomem *ssr_base = host_priv->ssr_base;
511 unsigned int sc_reg;
512
513 switch (sc_reg_in) {
514 case SCR_STATUS:
515 case SCR_ERROR:
516 case SCR_CONTROL:
517 case SCR_ACTIVE:
518 sc_reg = sc_reg_in;
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
525
526 *val = ioread32(ssr_base + (sc_reg * 4));
527 return 0;
528 }
529
530 static void sata_fsl_freeze(struct ata_port *ap)
531 {
532 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
533 void __iomem *hcr_base = host_priv->hcr_base;
534 u32 temp;
535
536 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
537 ioread32(CQ + hcr_base),
538 ioread32(CA + hcr_base),
539 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
540 VPRINTK("CmdStat = 0x%x\n",
541 ioread32(host_priv->csr_base + COMMANDSTAT));
542
543 /* disable interrupts on the controller/port */
544 temp = ioread32(hcr_base + HCONTROL);
545 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
546
547 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
548 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
549 }
550
551 static void sata_fsl_thaw(struct ata_port *ap)
552 {
553 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
554 void __iomem *hcr_base = host_priv->hcr_base;
555 u32 temp;
556
557 /* ack. any pending IRQs for this controller/port */
558 temp = ioread32(hcr_base + HSTATUS);
559
560 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
561
562 if (temp & 0x3F)
563 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
564
565 /* enable interrupts on the controller/port */
566 temp = ioread32(hcr_base + HCONTROL);
567 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
568
569 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
570 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
571 }
572
573 static void sata_fsl_pmp_attach(struct ata_port *ap)
574 {
575 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
576 void __iomem *hcr_base = host_priv->hcr_base;
577 u32 temp;
578
579 temp = ioread32(hcr_base + HCONTROL);
580 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
581 }
582
583 static void sata_fsl_pmp_detach(struct ata_port *ap)
584 {
585 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
586 void __iomem *hcr_base = host_priv->hcr_base;
587 u32 temp;
588
589 temp = ioread32(hcr_base + HCONTROL);
590 temp &= ~HCONTROL_PMP_ATTACHED;
591 iowrite32(temp, hcr_base + HCONTROL);
592
593 /* enable interrupts on the controller/port */
594 temp = ioread32(hcr_base + HCONTROL);
595 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
596
597 }
598
599 static int sata_fsl_port_start(struct ata_port *ap)
600 {
601 struct device *dev = ap->host->dev;
602 struct sata_fsl_port_priv *pp;
603 void *mem;
604 dma_addr_t mem_dma;
605 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
606 void __iomem *hcr_base = host_priv->hcr_base;
607 u32 temp;
608
609 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
610 if (!pp)
611 return -ENOMEM;
612
613 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
614 GFP_KERNEL);
615 if (!mem) {
616 kfree(pp);
617 return -ENOMEM;
618 }
619 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
620
621 pp->cmdslot = mem;
622 pp->cmdslot_paddr = mem_dma;
623
624 mem += SATA_FSL_CMD_SLOT_SIZE;
625 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
626
627 pp->cmdentry = mem;
628 pp->cmdentry_paddr = mem_dma;
629
630 ap->private_data = pp;
631
632 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
633 pp->cmdslot_paddr, pp->cmdentry_paddr);
634
635 /* Now, update the CHBA register in host controller cmd register set */
636 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
637
638 /*
639 * Now, we can bring the controller on-line & also initiate
640 * the COMINIT sequence, we simply return here and the boot-probing
641 * & device discovery process is re-initiated by libATA using a
642 * Softreset EH (dummy) session. Hence, boot probing and device
643 * discovey will be part of sata_fsl_softreset() callback.
644 */
645
646 temp = ioread32(hcr_base + HCONTROL);
647 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
648
649 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
650 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
651 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
652
653 #ifdef CONFIG_MPC8315_DS
654 /*
655 * Workaround for 8315DS board 3gbps link-up issue,
656 * currently limit SATA port to GEN1 speed
657 */
658 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
659 temp &= ~(0xF << 4);
660 temp |= (0x1 << 4);
661 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
662
663 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
664 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
665 temp);
666 #endif
667
668 return 0;
669 }
670
671 static void sata_fsl_port_stop(struct ata_port *ap)
672 {
673 struct device *dev = ap->host->dev;
674 struct sata_fsl_port_priv *pp = ap->private_data;
675 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
676 void __iomem *hcr_base = host_priv->hcr_base;
677 u32 temp;
678
679 /*
680 * Force host controller to go off-line, aborting current operations
681 */
682 temp = ioread32(hcr_base + HCONTROL);
683 temp &= ~HCONTROL_ONLINE_PHY_RST;
684 temp |= HCONTROL_FORCE_OFFLINE;
685 iowrite32(temp, hcr_base + HCONTROL);
686
687 /* Poll for controller to go offline - should happen immediately */
688 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
689
690 ap->private_data = NULL;
691 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
692 pp->cmdslot, pp->cmdslot_paddr);
693
694 kfree(pp);
695 }
696
697 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
698 {
699 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
700 void __iomem *hcr_base = host_priv->hcr_base;
701 struct ata_taskfile tf;
702 u32 temp;
703
704 temp = ioread32(hcr_base + SIGNATURE);
705
706 VPRINTK("raw sig = 0x%x\n", temp);
707 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
708 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
709
710 tf.lbah = (temp >> 24) & 0xff;
711 tf.lbam = (temp >> 16) & 0xff;
712 tf.lbal = (temp >> 8) & 0xff;
713 tf.nsect = temp & 0xff;
714
715 return ata_dev_classify(&tf);
716 }
717
718 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
719 unsigned long deadline)
720 {
721 struct ata_port *ap = link->ap;
722 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
723 void __iomem *hcr_base = host_priv->hcr_base;
724 u32 temp;
725 int i = 0;
726 unsigned long start_jiffies;
727
728 DPRINTK("in xx_hardreset\n");
729
730 try_offline_again:
731 /*
732 * Force host controller to go off-line, aborting current operations
733 */
734 temp = ioread32(hcr_base + HCONTROL);
735 temp &= ~HCONTROL_ONLINE_PHY_RST;
736 iowrite32(temp, hcr_base + HCONTROL);
737
738 /* Poll for controller to go offline */
739 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
740 1, 500);
741
742 if (temp & ONLINE) {
743 ata_port_printk(ap, KERN_ERR,
744 "Hardreset failed, not off-lined %d\n", i);
745
746 /*
747 * Try to offline controller atleast twice
748 */
749 i++;
750 if (i == 2)
751 goto err;
752 else
753 goto try_offline_again;
754 }
755
756 DPRINTK("hardreset, controller off-lined\n");
757 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
758 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
759
760 /*
761 * PHY reset should remain asserted for atleast 1ms
762 */
763 ata_msleep(ap, 1);
764
765 /*
766 * Now, bring the host controller online again, this can take time
767 * as PHY reset and communication establishment, 1st D2H FIS and
768 * device signature update is done, on safe side assume 500ms
769 * NOTE : Host online status may be indicated immediately!!
770 */
771
772 temp = ioread32(hcr_base + HCONTROL);
773 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
774 temp |= HCONTROL_PMP_ATTACHED;
775 iowrite32(temp, hcr_base + HCONTROL);
776
777 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
778
779 if (!(temp & ONLINE)) {
780 ata_port_printk(ap, KERN_ERR,
781 "Hardreset failed, not on-lined\n");
782 goto err;
783 }
784
785 DPRINTK("hardreset, controller off-lined & on-lined\n");
786 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
787 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
788
789 /*
790 * First, wait for the PHYRDY change to occur before waiting for
791 * the signature, and also verify if SStatus indicates device
792 * presence
793 */
794
795 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
796 if ((!(temp & 0x10)) || ata_link_offline(link)) {
797 ata_port_printk(ap, KERN_WARNING,
798 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
799 ioread32(hcr_base + HSTATUS));
800 *class = ATA_DEV_NONE;
801 return 0;
802 }
803
804 /*
805 * Wait for the first D2H from device,i.e,signature update notification
806 */
807 start_jiffies = jiffies;
808 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
809 500, jiffies_to_msecs(deadline - start_jiffies));
810
811 if ((temp & 0xFF) != 0x18) {
812 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
813 *class = ATA_DEV_NONE;
814 goto do_followup_srst;
815 } else {
816 ata_port_printk(ap, KERN_INFO,
817 "Signature Update detected @ %d msecs\n",
818 jiffies_to_msecs(jiffies - start_jiffies));
819 *class = sata_fsl_dev_classify(ap);
820 return 0;
821 }
822
823 do_followup_srst:
824 /*
825 * request libATA to perform follow-up softreset
826 */
827 return -EAGAIN;
828
829 err:
830 return -EIO;
831 }
832
833 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
834 unsigned long deadline)
835 {
836 struct ata_port *ap = link->ap;
837 struct sata_fsl_port_priv *pp = ap->private_data;
838 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
839 void __iomem *hcr_base = host_priv->hcr_base;
840 int pmp = sata_srst_pmp(link);
841 u32 temp;
842 struct ata_taskfile tf;
843 u8 *cfis;
844 u32 Serror;
845
846 DPRINTK("in xx_softreset\n");
847
848 if (ata_link_offline(link)) {
849 DPRINTK("PHY reports no device\n");
850 *class = ATA_DEV_NONE;
851 return 0;
852 }
853
854 /*
855 * Send a device reset (SRST) explicitly on command slot #0
856 * Check : will the command queue (reg) be cleared during offlining ??
857 * Also we will be online only if Phy commn. has been established
858 * and device presence has been detected, therefore if we have
859 * reached here, we can send a command to the target device
860 */
861
862 DPRINTK("Sending SRST/device reset\n");
863
864 ata_tf_init(link->device, &tf);
865 cfis = (u8 *) &pp->cmdentry->cfis;
866
867 /* device reset/SRST is a control register update FIS, uses tag0 */
868 sata_fsl_setup_cmd_hdr_entry(pp, 0,
869 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
870
871 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
872 ata_tf_to_fis(&tf, pmp, 0, cfis);
873
874 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
875 cfis[0], cfis[1], cfis[2], cfis[3]);
876
877 /*
878 * Queue SRST command to the controller/device, ensure that no
879 * other commands are active on the controller/device
880 */
881
882 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
883 ioread32(CQ + hcr_base),
884 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
885
886 iowrite32(0xFFFF, CC + hcr_base);
887 if (pmp != SATA_PMP_CTRL_PORT)
888 iowrite32(pmp, CQPMP + hcr_base);
889 iowrite32(1, CQ + hcr_base);
890
891 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
892 if (temp & 0x1) {
893 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
894
895 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
896 ioread32(CQ + hcr_base),
897 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
898
899 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
900
901 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
902 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
903 DPRINTK("Serror = 0x%x\n", Serror);
904 goto err;
905 }
906
907 ata_msleep(ap, 1);
908
909 /*
910 * SATA device enters reset state after receving a Control register
911 * FIS with SRST bit asserted and it awaits another H2D Control reg.
912 * FIS with SRST bit cleared, then the device does internal diags &
913 * initialization, followed by indicating it's initialization status
914 * using ATA signature D2H register FIS to the host controller.
915 */
916
917 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
918 0, 0, 5);
919
920 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
921 ata_tf_to_fis(&tf, pmp, 0, cfis);
922
923 if (pmp != SATA_PMP_CTRL_PORT)
924 iowrite32(pmp, CQPMP + hcr_base);
925 iowrite32(1, CQ + hcr_base);
926 ata_msleep(ap, 150); /* ?? */
927
928 /*
929 * The above command would have signalled an interrupt on command
930 * complete, which needs special handling, by clearing the Nth
931 * command bit of the CCreg
932 */
933 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
934
935 DPRINTK("SATA FSL : Now checking device signature\n");
936
937 *class = ATA_DEV_NONE;
938
939 /* Verify if SStatus indicates device presence */
940 if (ata_link_online(link)) {
941 /*
942 * if we are here, device presence has been detected,
943 * 1st D2H FIS would have been received, but sfis in
944 * command desc. is not updated, but signature register
945 * would have been updated
946 */
947
948 *class = sata_fsl_dev_classify(ap);
949
950 DPRINTK("class = %d\n", *class);
951 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
952 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
953 }
954
955 return 0;
956
957 err:
958 return -EIO;
959 }
960
961 static void sata_fsl_error_handler(struct ata_port *ap)
962 {
963
964 DPRINTK("in xx_error_handler\n");
965 sata_pmp_error_handler(ap);
966
967 }
968
969 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
970 {
971 if (qc->flags & ATA_QCFLAG_FAILED)
972 qc->err_mask |= AC_ERR_OTHER;
973
974 if (qc->err_mask) {
975 /* make DMA engine forget about the failed command */
976
977 }
978 }
979
980 static void sata_fsl_error_intr(struct ata_port *ap)
981 {
982 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
983 void __iomem *hcr_base = host_priv->hcr_base;
984 u32 hstatus, dereg=0, cereg = 0, SError = 0;
985 unsigned int err_mask = 0, action = 0;
986 int freeze = 0, abort=0;
987 struct ata_link *link = NULL;
988 struct ata_queued_cmd *qc = NULL;
989 struct ata_eh_info *ehi;
990
991 hstatus = ioread32(hcr_base + HSTATUS);
992 cereg = ioread32(hcr_base + CE);
993
994 /* first, analyze and record host port events */
995 link = &ap->link;
996 ehi = &link->eh_info;
997 ata_ehi_clear_desc(ehi);
998
999 /*
1000 * Handle & Clear SError
1001 */
1002
1003 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1004 if (unlikely(SError & 0xFFFF0000))
1005 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1006
1007 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1008 hstatus, cereg, ioread32(hcr_base + DE), SError);
1009
1010 /* handle fatal errors */
1011 if (hstatus & FATAL_ERROR_DECODE) {
1012 ehi->err_mask |= AC_ERR_ATA_BUS;
1013 ehi->action |= ATA_EH_SOFTRESET;
1014
1015 freeze = 1;
1016 }
1017
1018 /* Handle SDB FIS receive & notify update */
1019 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1020 sata_async_notification(ap);
1021
1022 /* Handle PHYRDY change notification */
1023 if (hstatus & INT_ON_PHYRDY_CHG) {
1024 DPRINTK("SATA FSL: PHYRDY change indication\n");
1025
1026 /* Setup a soft-reset EH action */
1027 ata_ehi_hotplugged(ehi);
1028 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1029 freeze = 1;
1030 }
1031
1032 /* handle single device errors */
1033 if (cereg) {
1034 /*
1035 * clear the command error, also clears queue to the device
1036 * in error, and we can (re)issue commands to this device.
1037 * When a device is in error all commands queued into the
1038 * host controller and at the device are considered aborted
1039 * and the queue for that device is stopped. Now, after
1040 * clearing the device error, we can issue commands to the
1041 * device to interrogate it to find the source of the error.
1042 */
1043 abort = 1;
1044
1045 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1046 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1047
1048 /* find out the offending link and qc */
1049 if (ap->nr_pmp_links) {
1050 unsigned int dev_num;
1051
1052 dereg = ioread32(hcr_base + DE);
1053 iowrite32(dereg, hcr_base + DE);
1054 iowrite32(cereg, hcr_base + CE);
1055
1056 dev_num = ffs(dereg) - 1;
1057 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1058 link = &ap->pmp_link[dev_num];
1059 ehi = &link->eh_info;
1060 qc = ata_qc_from_tag(ap, link->active_tag);
1061 /*
1062 * We should consider this as non fatal error,
1063 * and TF must be updated as done below.
1064 */
1065
1066 err_mask |= AC_ERR_DEV;
1067
1068 } else {
1069 err_mask |= AC_ERR_HSM;
1070 action |= ATA_EH_HARDRESET;
1071 freeze = 1;
1072 }
1073 } else {
1074 dereg = ioread32(hcr_base + DE);
1075 iowrite32(dereg, hcr_base + DE);
1076 iowrite32(cereg, hcr_base + CE);
1077
1078 qc = ata_qc_from_tag(ap, link->active_tag);
1079 /*
1080 * We should consider this as non fatal error,
1081 * and TF must be updated as done below.
1082 */
1083 err_mask |= AC_ERR_DEV;
1084 }
1085 }
1086
1087 /* record error info */
1088 if (qc)
1089 qc->err_mask |= err_mask;
1090 else
1091 ehi->err_mask |= err_mask;
1092
1093 ehi->action |= action;
1094
1095 /* freeze or abort */
1096 if (freeze)
1097 ata_port_freeze(ap);
1098 else if (abort) {
1099 if (qc)
1100 ata_link_abort(qc->dev->link);
1101 else
1102 ata_port_abort(ap);
1103 }
1104 }
1105
1106 static void sata_fsl_host_intr(struct ata_port *ap)
1107 {
1108 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1109 void __iomem *hcr_base = host_priv->hcr_base;
1110 u32 hstatus, done_mask = 0;
1111 struct ata_queued_cmd *qc;
1112 u32 SError;
1113
1114 hstatus = ioread32(hcr_base + HSTATUS);
1115
1116 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1117
1118 if (unlikely(SError & 0xFFFF0000)) {
1119 DPRINTK("serror @host_intr : 0x%x\n", SError);
1120 sata_fsl_error_intr(ap);
1121 }
1122
1123 if (unlikely(hstatus & INT_ON_ERROR)) {
1124 DPRINTK("error interrupt!!\n");
1125 sata_fsl_error_intr(ap);
1126 return;
1127 }
1128
1129 /* Read command completed register */
1130 done_mask = ioread32(hcr_base + CC);
1131
1132 VPRINTK("Status of all queues :\n");
1133 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1134 done_mask,
1135 ioread32(hcr_base + CA),
1136 ioread32(hcr_base + CE),
1137 ioread32(hcr_base + CQ),
1138 ap->qc_active);
1139
1140 if (done_mask & ap->qc_active) {
1141 int i;
1142 /* clear CC bit, this will also complete the interrupt */
1143 iowrite32(done_mask, hcr_base + CC);
1144
1145 DPRINTK("Status of all queues :\n");
1146 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1147 done_mask, ioread32(hcr_base + CA),
1148 ioread32(hcr_base + CE));
1149
1150 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1151 if (done_mask & (1 << i))
1152 DPRINTK
1153 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1154 i, ioread32(hcr_base + CC),
1155 ioread32(hcr_base + CA));
1156 }
1157 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1158 return;
1159
1160 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1161 iowrite32(1, hcr_base + CC);
1162 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1163
1164 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1165 ioread32(hcr_base + CC));
1166
1167 if (qc) {
1168 ata_qc_complete(qc);
1169 }
1170 } else {
1171 /* Spurious Interrupt!! */
1172 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1173 ioread32(hcr_base + CC));
1174 iowrite32(done_mask, hcr_base + CC);
1175 return;
1176 }
1177 }
1178
1179 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1180 {
1181 struct ata_host *host = dev_instance;
1182 struct sata_fsl_host_priv *host_priv = host->private_data;
1183 void __iomem *hcr_base = host_priv->hcr_base;
1184 u32 interrupt_enables;
1185 unsigned handled = 0;
1186 struct ata_port *ap;
1187
1188 /* ack. any pending IRQs for this controller/port */
1189 interrupt_enables = ioread32(hcr_base + HSTATUS);
1190 interrupt_enables &= 0x3F;
1191
1192 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1193
1194 if (!interrupt_enables)
1195 return IRQ_NONE;
1196
1197 spin_lock(&host->lock);
1198
1199 /* Assuming one port per host controller */
1200
1201 ap = host->ports[0];
1202 if (ap) {
1203 sata_fsl_host_intr(ap);
1204 } else {
1205 dev_printk(KERN_WARNING, host->dev,
1206 "interrupt on disabled port 0\n");
1207 }
1208
1209 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1210 handled = 1;
1211
1212 spin_unlock(&host->lock);
1213
1214 return IRQ_RETVAL(handled);
1215 }
1216
1217 /*
1218 * Multiple ports are represented by multiple SATA controllers with
1219 * one port per controller
1220 */
1221 static int sata_fsl_init_controller(struct ata_host *host)
1222 {
1223 struct sata_fsl_host_priv *host_priv = host->private_data;
1224 void __iomem *hcr_base = host_priv->hcr_base;
1225 u32 temp;
1226
1227 /*
1228 * NOTE : We cannot bring the controller online before setting
1229 * the CHBA, hence main controller initialization is done as
1230 * part of the port_start() callback
1231 */
1232
1233 /* ack. any pending IRQs for this controller/port */
1234 temp = ioread32(hcr_base + HSTATUS);
1235 if (temp & 0x3F)
1236 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1237
1238 /* Keep interrupts disabled on the controller */
1239 temp = ioread32(hcr_base + HCONTROL);
1240 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1241
1242 /* Disable interrupt coalescing control(icc), for the moment */
1243 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1244 iowrite32(0x01000000, hcr_base + ICC);
1245
1246 /* clear error registers, SError is cleared by libATA */
1247 iowrite32(0x00000FFFF, hcr_base + CE);
1248 iowrite32(0x00000FFFF, hcr_base + DE);
1249
1250 /*
1251 * host controller will be brought on-line, during xx_port_start()
1252 * callback, that should also initiate the OOB, COMINIT sequence
1253 */
1254
1255 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1256 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1257
1258 return 0;
1259 }
1260
1261 /*
1262 * scsi mid-layer and libata interface structures
1263 */
1264 static struct scsi_host_template sata_fsl_sht = {
1265 ATA_NCQ_SHT("sata_fsl"),
1266 .can_queue = SATA_FSL_QUEUE_DEPTH,
1267 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1268 .dma_boundary = ATA_DMA_BOUNDARY,
1269 };
1270
1271 static struct ata_port_operations sata_fsl_ops = {
1272 .inherits = &sata_pmp_port_ops,
1273
1274 .qc_defer = ata_std_qc_defer,
1275 .qc_prep = sata_fsl_qc_prep,
1276 .qc_issue = sata_fsl_qc_issue,
1277 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1278
1279 .scr_read = sata_fsl_scr_read,
1280 .scr_write = sata_fsl_scr_write,
1281
1282 .freeze = sata_fsl_freeze,
1283 .thaw = sata_fsl_thaw,
1284 .softreset = sata_fsl_softreset,
1285 .hardreset = sata_fsl_hardreset,
1286 .pmp_softreset = sata_fsl_softreset,
1287 .error_handler = sata_fsl_error_handler,
1288 .post_internal_cmd = sata_fsl_post_internal_cmd,
1289
1290 .port_start = sata_fsl_port_start,
1291 .port_stop = sata_fsl_port_stop,
1292
1293 .pmp_attach = sata_fsl_pmp_attach,
1294 .pmp_detach = sata_fsl_pmp_detach,
1295 };
1296
1297 static const struct ata_port_info sata_fsl_port_info[] = {
1298 {
1299 .flags = SATA_FSL_HOST_FLAGS,
1300 .pio_mask = ATA_PIO4,
1301 .udma_mask = ATA_UDMA6,
1302 .port_ops = &sata_fsl_ops,
1303 },
1304 };
1305
1306 static int sata_fsl_probe(struct platform_device *ofdev)
1307 {
1308 int retval = -ENXIO;
1309 void __iomem *hcr_base = NULL;
1310 void __iomem *ssr_base = NULL;
1311 void __iomem *csr_base = NULL;
1312 struct sata_fsl_host_priv *host_priv = NULL;
1313 int irq;
1314 struct ata_host *host;
1315 u32 temp;
1316
1317 struct ata_port_info pi = sata_fsl_port_info[0];
1318 const struct ata_port_info *ppi[] = { &pi, NULL };
1319
1320 dev_printk(KERN_INFO, &ofdev->dev,
1321 "Sata FSL Platform/CSB Driver init\n");
1322
1323 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1324 if (!hcr_base)
1325 goto error_exit_with_cleanup;
1326
1327 ssr_base = hcr_base + 0x100;
1328 csr_base = hcr_base + 0x140;
1329
1330 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1331 temp = ioread32(csr_base + TRANSCFG);
1332 temp = temp & 0xffffffe0;
1333 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1334 }
1335
1336 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1337 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1338 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1339
1340 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1341 if (!host_priv)
1342 goto error_exit_with_cleanup;
1343
1344 host_priv->hcr_base = hcr_base;
1345 host_priv->ssr_base = ssr_base;
1346 host_priv->csr_base = csr_base;
1347
1348 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1349 if (irq < 0) {
1350 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1351 goto error_exit_with_cleanup;
1352 }
1353 host_priv->irq = irq;
1354
1355 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1356 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1357 else
1358 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1359
1360 /* allocate host structure */
1361 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1362
1363 /* host->iomap is not used currently */
1364 host->private_data = host_priv;
1365
1366 /* initialize host controller */
1367 sata_fsl_init_controller(host);
1368
1369 /*
1370 * Now, register with libATA core, this will also initiate the
1371 * device discovery process, invoking our port_start() handler &
1372 * error_handler() to execute a dummy Softreset EH session
1373 */
1374 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1375 &sata_fsl_sht);
1376
1377 dev_set_drvdata(&ofdev->dev, host);
1378
1379 return 0;
1380
1381 error_exit_with_cleanup:
1382
1383 if (hcr_base)
1384 iounmap(hcr_base);
1385 if (host_priv)
1386 kfree(host_priv);
1387
1388 return retval;
1389 }
1390
1391 static int sata_fsl_remove(struct platform_device *ofdev)
1392 {
1393 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1394 struct sata_fsl_host_priv *host_priv = host->private_data;
1395
1396 ata_host_detach(host);
1397
1398 dev_set_drvdata(&ofdev->dev, NULL);
1399
1400 irq_dispose_mapping(host_priv->irq);
1401 iounmap(host_priv->hcr_base);
1402 kfree(host_priv);
1403
1404 return 0;
1405 }
1406
1407 #ifdef CONFIG_PM
1408 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1409 {
1410 struct ata_host *host = dev_get_drvdata(&op->dev);
1411 return ata_host_suspend(host, state);
1412 }
1413
1414 static int sata_fsl_resume(struct platform_device *op)
1415 {
1416 struct ata_host *host = dev_get_drvdata(&op->dev);
1417 struct sata_fsl_host_priv *host_priv = host->private_data;
1418 int ret;
1419 void __iomem *hcr_base = host_priv->hcr_base;
1420 struct ata_port *ap = host->ports[0];
1421 struct sata_fsl_port_priv *pp = ap->private_data;
1422
1423 ret = sata_fsl_init_controller(host);
1424 if (ret) {
1425 dev_printk(KERN_ERR, &op->dev,
1426 "Error initialize hardware\n");
1427 return ret;
1428 }
1429
1430 /* Recovery the CHBA register in host controller cmd register set */
1431 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1432
1433 ata_host_resume(host);
1434 return 0;
1435 }
1436 #endif
1437
1438 static struct of_device_id fsl_sata_match[] = {
1439 {
1440 .compatible = "fsl,pq-sata",
1441 },
1442 {
1443 .compatible = "fsl,pq-sata-v2",
1444 },
1445 {},
1446 };
1447
1448 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1449
1450 static struct platform_driver fsl_sata_driver = {
1451 .driver = {
1452 .name = "fsl-sata",
1453 .owner = THIS_MODULE,
1454 .of_match_table = fsl_sata_match,
1455 },
1456 .probe = sata_fsl_probe,
1457 .remove = sata_fsl_remove,
1458 #ifdef CONFIG_PM
1459 .suspend = sata_fsl_suspend,
1460 .resume = sata_fsl_resume,
1461 #endif
1462 };
1463
1464 static int __init sata_fsl_init(void)
1465 {
1466 platform_driver_register(&fsl_sata_driver);
1467 return 0;
1468 }
1469
1470 static void __exit sata_fsl_exit(void)
1471 {
1472 platform_driver_unregister(&fsl_sata_driver);
1473 }
1474
1475 MODULE_LICENSE("GPL");
1476 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1477 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1478 MODULE_VERSION("1.10");
1479
1480 module_init(sata_fsl_init);
1481 module_exit(sata_fsl_exit);
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