arch/x86/kernel/aperture_64.c

   1 /*
   2  * Firmware replacement code.
   3  *
   4  * Work around broken BIOSes that don't set an aperture or only set the
   5  * aperture in the AGP bridge.
   6  * If all fails map the aperture over some low memory.  This is cheaper than
   7  * doing bounce buffering. The memory is lost. This is done at early boot
   8  * because only the bootmem allocator can allocate 32+MB.
   9  *
  10  * Copyright 2002 Andi Kleen, SuSE Labs.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/init.h>
  15 #include <linux/bootmem.h>
  16 #include <linux/mmzone.h>
  17 #include <linux/pci_ids.h>
  18 #include <linux/pci.h>
  19 #include <linux/bitops.h>
  20 #include <linux/ioport.h>
  21 #include <asm/e820.h>
  22 #include <asm/io.h>
  23 #include <asm/gart.h>
  24 #include <asm/pci-direct.h>
  25 #include <asm/dma.h>
  26 #include <asm/k8.h>
  27
  28 int gart_iommu_aperture;
  29 int gart_iommu_aperture_disabled __initdata = 0;
  30 int gart_iommu_aperture_allowed __initdata = 0;
  31
  32 int fallback_aper_order __initdata = 1; /* 64MB */
  33 int fallback_aper_force __initdata = 0;
  34
  35 int fix_aperture __initdata = 1;
  36
  37 static struct resource gart_resource = {
  38         .name   = "GART",
  39         .flags  = IORESOURCE_MEM,
  40 };
  41
  42 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
  43 {
  44         gart_resource.start = aper_base;
  45         gart_resource.end = aper_base + aper_size - 1;
  46         insert_resource(&iomem_resource, &gart_resource);
  47 }
  48
  49 /* This code runs before the PCI subsystem is initialized, so just
  50    access the northbridge directly. */
  51
  52 static u32 __init allocate_aperture(void)
  53 {
  54         u32 aper_size;
  55         void *p;
  56
  57         if (fallback_aper_order > 7)
  58                 fallback_aper_order = 7;
  59         aper_size = (32 * 1024 * 1024) << fallback_aper_order;
  60
  61         /*
  62          * Aperture has to be naturally aligned. This means a 2GB aperture
  63          * won't have much chance of finding a place in the lower 4GB of
  64          * memory. Unfortunately we cannot move it up because that would
  65          * make the IOMMU useless.
  66          */
  67         p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
  68         if (!p || __pa(p)+aper_size > 0xffffffff) {
  69                 printk("Cannot allocate aperture memory hole (%p,%uK)\n",
  70                        p, aper_size>>10);
  71                 if (p)
  72                         free_bootmem(__pa(p), aper_size);
  73                 return 0;
  74         }
  75         printk("Mapping aperture over %d KB of RAM @ %lx\n",
  76                aper_size >> 10, __pa(p));
  77         insert_aperture_resource((u32)__pa(p), aper_size);
  78
  79         return (u32)__pa(p);
  80 }
  81
  82 static int __init aperture_valid(u64 aper_base, u32 aper_size)
  83 {
  84         if (!aper_base)
  85                 return 0;
  86         if (aper_size < 64*1024*1024) {
  87                 printk("Aperture too small (%d MB)\n", aper_size>>20);
  88                 return 0;
  89         }
  90         if (aper_base + aper_size > 0x100000000UL) {
  91                 printk("Aperture beyond 4GB. Ignoring.\n");
  92                 return 0;
  93         }
  94         if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
  95                 printk("Aperture pointing to e820 RAM. Ignoring.\n");
  96                 return 0;
  97         }
  98         return 1;
  99 }
 100
 101 /* Find a PCI capability */
 102 static __u32 __init find_cap(int num, int slot, int func, int cap)
 103 {
 104         int bytes;
 105         u8 pos;
 106
 107         if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
 108                                                 PCI_STATUS_CAP_LIST))
 109                 return 0;
 110
 111         pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
 112         for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
 113                 u8 id;
 114
 115                 pos &= ~3;
 116                 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
 117                 if (id == 0xff)
 118                         break;
 119                 if (id == cap)
 120                         return pos;
 121                 pos = read_pci_config_byte(num, slot, func,
 122                                                 pos+PCI_CAP_LIST_NEXT);
 123         }
 124         return 0;
 125 }
 126
 127 /* Read a standard AGPv3 bridge header */
 128 static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
 129 {
 130         u32 apsize;
 131         u32 apsizereg;
 132         int nbits;
 133         u32 aper_low, aper_hi;
 134         u64 aper;
 135
 136         printk("AGP bridge at %02x:%02x:%02x\n", num, slot, func);
 137         apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
 138         if (apsizereg == 0xffffffff) {
 139                 printk("APSIZE in AGP bridge unreadable\n");
 140                 return 0;
 141         }
 142
 143         apsize = apsizereg & 0xfff;
 144         /* Some BIOS use weird encodings not in the AGPv3 table. */
 145         if (apsize & 0xff)
 146                 apsize |= 0xf00;
 147         nbits = hweight16(apsize);
 148         *order = 7 - nbits;
 149         if ((int)*order < 0) /* < 32MB */
 150                 *order = 0;
 151
 152         aper_low = read_pci_config(num, slot, func, 0x10);
 153         aper_hi = read_pci_config(num, slot, func, 0x14);
 154         aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
 155
 156         printk("Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
 157                aper, 32 << *order, apsizereg);
 158
 159         if (!aperture_valid(aper, (32*1024*1024) << *order))
 160                 return 0;
 161         return (u32)aper;
 162 }
 163
 164 /*
 165  * Look for an AGP bridge. Windows only expects the aperture in the
 166  * AGP bridge and some BIOS forget to initialize the Northbridge too.
 167  * Work around this here.
 168  *
 169  * Do an PCI bus scan by hand because we're running before the PCI
 170  * subsystem.
 171  *
 172  * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
 173  * generically. It's probably overkill to always scan all slots because
 174  * the AGP bridges should be always an own bus on the HT hierarchy,
 175  * but do it here for future safety.
 176  */
 177 static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
 178 {
 179         int num, slot, func;
 180
 181         /* Poor man's PCI discovery */
 182         for (num = 0; num < 256; num++) {
 183                 for (slot = 0; slot < 32; slot++) {
 184                         for (func = 0; func < 8; func++) {
 185                                 u32 class, cap;
 186                                 u8 type;
 187                                 class = read_pci_config(num, slot, func,
 188                                                         PCI_CLASS_REVISION);
 189                                 if (class == 0xffffffff)
 190                                         break;
 191
 192                                 switch (class >> 16) {
 193                                 case PCI_CLASS_BRIDGE_HOST:
 194                                 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
 195                                         /* AGP bridge? */
 196                                         cap = find_cap(num, slot, func,
 197                                                         PCI_CAP_ID_AGP);
 198                                         if (!cap)
 199                                                 break;
 200                                         *valid_agp = 1;
 201                                         return read_agp(num, slot, func, cap,
 202                                                         order);
 203                                 }
 204
 205                                 /* No multi-function device? */
 206                                 type = read_pci_config_byte(num, slot, func,
 207                                                                PCI_HEADER_TYPE);
 208                                 if (!(type & 0x80))
 209                                         break;
 210                         }
 211                 }
 212         }
 213         printk("No AGP bridge found\n");
 214
 215         return 0;
 216 }
 217
 218 void __init gart_iommu_hole_init(void)
 219 {
 220         u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
 221         u64 aper_base, last_aper_base = 0;
 222         int fix, num, valid_agp = 0;
 223
 224         if (gart_iommu_aperture_disabled || !fix_aperture ||
 225             !early_pci_allowed())
 226                 return;
 227
 228         printk(KERN_INFO  "Checking aperture...\n");
 229
 230         fix = 0;
 231         for (num = 24; num < 32; num++) {
 232                 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
 233                         continue;
 234
 235                 iommu_detected = 1;
 236                 gart_iommu_aperture = 1;
 237
 238                 aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
 239                 aper_size = (32 * 1024 * 1024) << aper_order;
 240                 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
 241                 aper_base <<= 25;
 242
 243                 printk("CPU %d: aperture @ %Lx size %u MB\n", num-24,
 244                        aper_base, aper_size>>20);
 245
 246                 if (!aperture_valid(aper_base, aper_size)) {
 247                         fix = 1;
 248                         break;
 249                 }
 250
 251                 if ((last_aper_order && aper_order != last_aper_order) ||
 252                     (last_aper_base && aper_base != last_aper_base)) {
 253                         fix = 1;
 254                         break;
 255                 }
 256                 last_aper_order = aper_order;
 257                 last_aper_base = aper_base;
 258         }
 259
 260         if (!fix && !fallback_aper_force) {
 261                 if (last_aper_base) {
 262                         unsigned long n = (32 * 1024 * 1024) << last_aper_order;
 263
 264                         insert_aperture_resource((u32)last_aper_base, n);
 265                 }
 266                 return;
 267         }
 268
 269         if (!fallback_aper_force)
 270                 aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
 271
 272         if (aper_alloc) {
 273                 /* Got the aperture from the AGP bridge */
 274         } else if (swiotlb && !valid_agp) {
 275                 /* Do nothing */
 276         } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
 277                    force_iommu ||
 278                    valid_agp ||
 279                    fallback_aper_force) {
 280                 printk("Your BIOS doesn't leave a aperture memory hole\n");
 281                 printk("Please enable the IOMMU option in the BIOS setup\n");
 282                 printk("This costs you %d MB of RAM\n",
 283                        32 << fallback_aper_order);
 284
 285                 aper_order = fallback_aper_order;
 286                 aper_alloc = allocate_aperture();
 287                 if (!aper_alloc) {
 288                         /*
 289                          * Could disable AGP and IOMMU here, but it's
 290                          * probably not worth it. But the later users
 291                          * cannot deal with bad apertures and turning
 292                          * on the aperture over memory causes very
 293                          * strange problems, so it's better to panic
 294                          * early.
 295                          */
 296                         panic("Not enough memory for aperture");
 297                 }
 298         } else {
 299                 return;
 300         }
 301
 302         /* Fix up the north bridges */
 303         for (num = 24; num < 32; num++) {
 304                 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
 305                         continue;
 306
 307                 /*
 308                  * Don't enable translation yet. That is done later.
 309                  * Assume this BIOS didn't initialise the GART so
 310                  * just overwrite all previous bits
 311                  */
 312                 write_pci_config(0, num, 3, 0x90, aper_order<<1);
 313                 write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
 314         }
 315 }