arch/arm/mach-kirkwood/pcie.c

   1 /*
   2  * arch/arm/mach-kirkwood/pcie.c
   3  *
   4  * PCIe functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/mbus.h>
  16 #include <video/vga.h>
  17 #include <asm/irq.h>
  18 #include <asm/mach/pci.h>
  19 #include <plat/pcie.h>
  20 #include <mach/bridge-regs.h>
  21 #include "common.h"
  22
  23 static void kirkwood_enable_pcie_clk(const char *port)
  24 {
  25         struct clk *clk;
  26
  27         clk = clk_get_sys("pcie", port);
  28         if (IS_ERR(clk)) {
  29                 pr_err("PCIE clock %s missing\n", port);
  30                 return;
  31         }
  32         clk_prepare_enable(clk);
  33         clk_put(clk);
  34 }
  35
  36 /* This function is called very early in the boot when probing the
  37    hardware to determine what we actually are, and what rate tclk is
  38    ticking at. Hence calling kirkwood_enable_pcie_clk() is not
  39    possible since the clk tree has not been created yet. */
  40 void kirkwood_enable_pcie(void)
  41 {
  42         u32 curr = readl(CLOCK_GATING_CTRL);
  43         if (!(curr & CGC_PEX0))
  44                 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
  45 }
  46
  47 void kirkwood_pcie_id(u32 *dev, u32 *rev)
  48 {
  49         kirkwood_enable_pcie();
  50         *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
  51         *rev = orion_pcie_rev(PCIE_VIRT_BASE);
  52 }
  53
  54 struct pcie_port {
  55         u8                      root_bus_nr;
  56         void __iomem            *base;
  57         spinlock_t              conf_lock;
  58         int                     irq;
  59         struct resource         res;
  60 };
  61
  62 static int pcie_port_map[2];
  63 static int num_pcie_ports;
  64
  65 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
  66 {
  67         /*
  68          * Don't go out when trying to access --
  69          * 1. nonexisting device on local bus
  70          * 2. where there's no device connected (no link)
  71          */
  72         if (bus == pp->root_bus_nr && dev == 0)
  73                 return 1;
  74
  75         if (!orion_pcie_link_up(pp->base))
  76                 return 0;
  77
  78         if (bus == pp->root_bus_nr && dev != 1)
  79                 return 0;
  80
  81         return 1;
  82 }
  83
  84
  85 /*
  86  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  87  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  88  * transactions are atomic.
  89  */
  90
  91 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  92                         int size, u32 *val)
  93 {
  94         struct pci_sys_data *sys = bus->sysdata;
  95         struct pcie_port *pp = sys->private_data;
  96         unsigned long flags;
  97         int ret;
  98
  99         if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 100                 *val = 0xffffffff;
 101                 return PCIBIOS_DEVICE_NOT_FOUND;
 102         }
 103
 104         spin_lock_irqsave(&pp->conf_lock, flags);
 105         ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
 106         spin_unlock_irqrestore(&pp->conf_lock, flags);
 107
 108         return ret;
 109 }
 110
 111 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 112                         int where, int size, u32 val)
 113 {
 114         struct pci_sys_data *sys = bus->sysdata;
 115         struct pcie_port *pp = sys->private_data;
 116         unsigned long flags;
 117         int ret;
 118
 119         if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 120                 return PCIBIOS_DEVICE_NOT_FOUND;
 121
 122         spin_lock_irqsave(&pp->conf_lock, flags);
 123         ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
 124         spin_unlock_irqrestore(&pp->conf_lock, flags);
 125
 126         return ret;
 127 }
 128
 129 static struct pci_ops pcie_ops = {
 130         .read = pcie_rd_conf,
 131         .write = pcie_wr_conf,
 132 };
 133
 134 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 135 {
 136         pp->base = PCIE_VIRT_BASE;
 137         pp->irq = IRQ_KIRKWOOD_PCIE;
 138
 139         /*
 140          * IORESOURCE_MEM
 141          */
 142         pp->res.name = "PCIe 0 MEM";
 143         pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 144         pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
 145         pp->res.flags = IORESOURCE_MEM;
 146 }
 147
 148 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 149 {
 150         pp->base = PCIE1_VIRT_BASE;
 151         pp->irq = IRQ_KIRKWOOD_PCIE1;
 152
 153         /*
 154          * IORESOURCE_MEM
 155          */
 156         pp->res.name = "PCIe 1 MEM";
 157         pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
 158         pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
 159         pp->res.flags = IORESOURCE_MEM;
 160 }
 161
 162 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
 163 {
 164         struct pcie_port *pp;
 165         int index;
 166
 167         if (nr >= num_pcie_ports)
 168                 return 0;
 169
 170         index = pcie_port_map[nr];
 171         pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
 172
 173         pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 174         if (!pp)
 175                 panic("PCIe: failed to allocate pcie_port data");
 176         sys->private_data = pp;
 177         pp->root_bus_nr = sys->busnr;
 178         spin_lock_init(&pp->conf_lock);
 179
 180         switch (index) {
 181         case 0:
 182                 kirkwood_enable_pcie_clk("0");
 183                 pcie0_ioresources_init(pp);
 184                 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
 185                 break;
 186         case 1:
 187                 kirkwood_enable_pcie_clk("1");
 188                 pcie1_ioresources_init(pp);
 189                 pci_ioremap_io(SZ_64K * sys->busnr,
 190                                KIRKWOOD_PCIE1_IO_PHYS_BASE);
 191                 break;
 192         default:
 193                 panic("PCIe setup: invalid controller %d", index);
 194         }
 195
 196         if (request_resource(&iomem_resource, &pp->res))
 197                 panic("Request PCIe%d Memory resource failed\n", index);
 198
 199         pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 200
 201         /*
 202          * Generic PCIe unit setup.
 203          */
 204         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
 205
 206         orion_pcie_setup(pp->base);
 207
 208         return 1;
 209 }
 210
 211 /*
 212  * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
 213  * is operating as a root complex this needs to be switched to
 214  * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
 215  * the device. Decoding setup is handled by the orion code.
 216  */
 217 static void rc_pci_fixup(struct pci_dev *dev)
 218 {
 219         if (dev->bus->parent == NULL && dev->devfn == 0) {
 220                 int i;
 221
 222                 dev->class &= 0xff;
 223                 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
 224                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 225                         dev->resource[i].start = 0;
 226                         dev->resource[i].end   = 0;
 227                         dev->resource[i].flags = 0;
 228                 }
 229         }
 230 }
 231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 232
 233 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
 234         u8 pin)
 235 {
 236         struct pci_sys_data *sys = dev->sysdata;
 237         struct pcie_port *pp = sys->private_data;
 238
 239         return pp->irq;
 240 }
 241
 242 static struct hw_pci kirkwood_pci __initdata = {
 243         .setup          = kirkwood_pcie_setup,
 244         .map_irq        = kirkwood_pcie_map_irq,
 245         .ops            = &pcie_ops,
 246 };
 247
 248 static void __init add_pcie_port(int index, void __iomem *base)
 249 {
 250         pcie_port_map[num_pcie_ports++] = index;
 251         pr_info("Kirkwood PCIe port %d: link %s\n", index,
 252                 orion_pcie_link_up(base) ? "up" : "down");
 253 }
 254
 255 void __init kirkwood_pcie_init(unsigned int portmask)
 256 {
 257         mvebu_mbus_add_window_remap_flags("pcie0.0",
 258                                           KIRKWOOD_PCIE_IO_PHYS_BASE,
 259                                           KIRKWOOD_PCIE_IO_SIZE,
 260                                           KIRKWOOD_PCIE_IO_BUS_BASE,
 261                                           MVEBU_MBUS_PCI_IO);
 262         mvebu_mbus_add_window_remap_flags("pcie0.0",
 263                                           KIRKWOOD_PCIE_MEM_PHYS_BASE,
 264                                           KIRKWOOD_PCIE_MEM_SIZE,
 265                                           MVEBU_MBUS_NO_REMAP,
 266                                           MVEBU_MBUS_PCI_MEM);
 267         mvebu_mbus_add_window_remap_flags("pcie1.0",
 268                                           KIRKWOOD_PCIE1_IO_PHYS_BASE,
 269                                           KIRKWOOD_PCIE1_IO_SIZE,
 270                                           KIRKWOOD_PCIE1_IO_BUS_BASE,
 271                                           MVEBU_MBUS_PCI_IO);
 272         mvebu_mbus_add_window_remap_flags("pcie1.0",
 273                                           KIRKWOOD_PCIE1_MEM_PHYS_BASE,
 274                                           KIRKWOOD_PCIE1_MEM_SIZE,
 275                                           MVEBU_MBUS_NO_REMAP,
 276                                           MVEBU_MBUS_PCI_MEM);
 277
 278         vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 279
 280         if (portmask & KW_PCIE0)
 281                 add_pcie_port(0, PCIE_VIRT_BASE);
 282
 283         if (portmask & KW_PCIE1)
 284                 add_pcie_port(1, PCIE1_VIRT_BASE);
 285
 286         kirkwood_pci.nr_controllers = num_pcie_ports;
 287         pci_common_init(&kirkwood_pci);
 288 }