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m68knommu: clean up init code in ColdFire 532x startup
[linux-2.6.git] / arch / arm / mach-tegra / usb_phy.c
blob37576a721aeb7c6b549b7201a9999901f901956f
1 /*
2 * arch/arm/mach-tegra/usb_phy.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #include <linux/resource.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/ulpi.h>
30 #include <asm/mach-types.h>
31 #include <mach/gpio-tegra.h>
32 #include <mach/usb_phy.h>
33 #include <mach/iomap.h>
34
35 #define ULPI_VIEWPORT 0x170
36
37 #define USB_PORTSC1 0x184
38 #define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
39 #define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
40 #define USB_PORTSC1_PHCD (1 << 23)
41 #define USB_PORTSC1_WKOC (1 << 22)
42 #define USB_PORTSC1_WKDS (1 << 21)
43 #define USB_PORTSC1_WKCN (1 << 20)
44 #define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
45 #define USB_PORTSC1_PP (1 << 12)
46 #define USB_PORTSC1_SUSP (1 << 7)
47 #define USB_PORTSC1_PE (1 << 2)
48 #define USB_PORTSC1_CCS (1 << 0)
49
50 #define USB_SUSP_CTRL 0x400
51 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
52 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
53 #define USB_SUSP_CLR (1 << 5)
54 #define USB_PHY_CLK_VALID (1 << 7)
55 #define UTMIP_RESET (1 << 11)
56 #define UHSIC_RESET (1 << 11)
57 #define UTMIP_PHY_ENABLE (1 << 12)
58 #define ULPI_PHY_ENABLE (1 << 13)
59 #define USB_SUSP_SET (1 << 14)
60 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
61
62 #define USB1_LEGACY_CTRL 0x410
63 #define USB1_NO_LEGACY_MODE (1 << 0)
64 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
65 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
66 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
67 (1 << 1)
68 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
69 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
70
71 #define ULPI_TIMING_CTRL_0 0x424
72 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
73 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
74
75 #define ULPI_TIMING_CTRL_1 0x428
76 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
77 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
78 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
79 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
80 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
81 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
82
83 #define UTMIP_PLL_CFG1 0x804
84 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
85 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
86
87 #define UTMIP_XCVR_CFG0 0x808
88 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
89 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
90 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
91 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
92 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
93 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
94 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
95
96 #define UTMIP_BIAS_CFG0 0x80c
97 #define UTMIP_OTGPD (1 << 11)
98 #define UTMIP_BIASPD (1 << 10)
99
100 #define UTMIP_HSRX_CFG0 0x810
101 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
102 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
103
104 #define UTMIP_HSRX_CFG1 0x814
105 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
106
107 #define UTMIP_TX_CFG0 0x820
108 #define UTMIP_FS_PREABMLE_J (1 << 19)
109 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
110
111 #define UTMIP_MISC_CFG0 0x824
112 #define UTMIP_DPDM_OBSERVE (1 << 26)
113 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
114 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
115 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
116 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
117 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
118 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
119
120 #define UTMIP_MISC_CFG1 0x828
121 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
122 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
123
124 #define UTMIP_DEBOUNCE_CFG0 0x82c
125 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
126
127 #define UTMIP_BAT_CHRG_CFG0 0x830
128 #define UTMIP_PD_CHRG (1 << 0)
129
130 #define UTMIP_SPARE_CFG0 0x834
131 #define FUSE_SETUP_SEL (1 << 3)
132
133 #define UTMIP_XCVR_CFG1 0x838
134 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
135 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
136 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
137 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
138
139 #define UTMIP_BIAS_CFG1 0x83c
140 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
141
142 static DEFINE_SPINLOCK(utmip_pad_lock);
143 static int utmip_pad_count;
144
145 struct tegra_xtal_freq {
146 int freq;
147 u8 enable_delay;
148 u8 stable_count;
149 u8 active_delay;
150 u8 xtal_freq_count;
151 u16 debounce;
152 };
153
154 static const struct tegra_xtal_freq tegra_freq_table[] = {
155 {
156 .freq = 12000000,
157 .enable_delay = 0x02,
158 .stable_count = 0x2F,
159 .active_delay = 0x04,
160 .xtal_freq_count = 0x76,
161 .debounce = 0x7530,
162 },
163 {
164 .freq = 13000000,
165 .enable_delay = 0x02,
166 .stable_count = 0x33,
167 .active_delay = 0x05,
168 .xtal_freq_count = 0x7F,
169 .debounce = 0x7EF4,
170 },
171 {
172 .freq = 19200000,
173 .enable_delay = 0x03,
174 .stable_count = 0x4B,
175 .active_delay = 0x06,
176 .xtal_freq_count = 0xBB,
177 .debounce = 0xBB80,
178 },
179 {
180 .freq = 26000000,
181 .enable_delay = 0x04,
182 .stable_count = 0x66,
183 .active_delay = 0x09,
184 .xtal_freq_count = 0xFE,
185 .debounce = 0xFDE8,
186 },
187 };
188
189 static struct tegra_utmip_config utmip_default[] = {
190 [0] = {
191 .hssync_start_delay = 9,
192 .idle_wait_delay = 17,
193 .elastic_limit = 16,
194 .term_range_adj = 6,
195 .xcvr_setup = 9,
196 .xcvr_lsfslew = 1,
197 .xcvr_lsrslew = 1,
198 },
199 [2] = {
200 .hssync_start_delay = 9,
201 .idle_wait_delay = 17,
202 .elastic_limit = 16,
203 .term_range_adj = 6,
204 .xcvr_setup = 9,
205 .xcvr_lsfslew = 2,
206 .xcvr_lsrslew = 2,
207 },
208 };
209
210 static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
211 {
212 return (phy->instance == 1);
213 }
214
215 static int utmip_pad_open(struct tegra_usb_phy *phy)
216 {
217 phy->pad_clk = clk_get_sys("utmip-pad", NULL);
218 if (IS_ERR(phy->pad_clk)) {
219 pr_err("%s: can't get utmip pad clock\n", __func__);
220 return PTR_ERR(phy->pad_clk);
221 }
222
223 if (phy->instance == 0) {
224 phy->pad_regs = phy->regs;
225 } else {
226 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
227 if (!phy->pad_regs) {
228 pr_err("%s: can't remap usb registers\n", __func__);
229 clk_put(phy->pad_clk);
230 return -ENOMEM;
231 }
232 }
233 return 0;
234 }
235
236 static void utmip_pad_close(struct tegra_usb_phy *phy)
237 {
238 if (phy->instance != 0)
239 iounmap(phy->pad_regs);
240 clk_put(phy->pad_clk);
241 }
242
243 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
244 {
245 unsigned long val, flags;
246 void __iomem *base = phy->pad_regs;
247
248 clk_enable(phy->pad_clk);
249
250 spin_lock_irqsave(&utmip_pad_lock, flags);
251
252 if (utmip_pad_count++ == 0) {
253 val = readl(base + UTMIP_BIAS_CFG0);
254 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
255 writel(val, base + UTMIP_BIAS_CFG0);
256 }
257
258 spin_unlock_irqrestore(&utmip_pad_lock, flags);
259
260 clk_disable(phy->pad_clk);
261 }
262
263 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
264 {
265 unsigned long val, flags;
266 void __iomem *base = phy->pad_regs;
267
268 if (!utmip_pad_count) {
269 pr_err("%s: utmip pad already powered off\n", __func__);
270 return -EINVAL;
271 }
272
273 clk_enable(phy->pad_clk);
274
275 spin_lock_irqsave(&utmip_pad_lock, flags);
276
277 if (--utmip_pad_count == 0) {
278 val = readl(base + UTMIP_BIAS_CFG0);
279 val |= UTMIP_OTGPD | UTMIP_BIASPD;
280 writel(val, base + UTMIP_BIAS_CFG0);
281 }
282
283 spin_unlock_irqrestore(&utmip_pad_lock, flags);
284
285 clk_disable(phy->pad_clk);
286
287 return 0;
288 }
289
290 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
291 {
292 unsigned long timeout = 2000;
293 do {
294 if ((readl(reg) & mask) == result)
295 return 0;
296 udelay(1);
297 timeout--;
298 } while (timeout);
299 return -1;
300 }
301
302 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
303 {
304 unsigned long val;
305 void __iomem *base = phy->regs;
306
307 if (phy->instance == 0) {
308 val = readl(base + USB_SUSP_CTRL);
309 val |= USB_SUSP_SET;
310 writel(val, base + USB_SUSP_CTRL);
311
312 udelay(10);
313
314 val = readl(base + USB_SUSP_CTRL);
315 val &= ~USB_SUSP_SET;
316 writel(val, base + USB_SUSP_CTRL);
317 }
318
319 if (phy->instance == 2) {
320 val = readl(base + USB_PORTSC1);
321 val |= USB_PORTSC1_PHCD;
322 writel(val, base + USB_PORTSC1);
323 }
324
325 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
326 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
327 }
328
329 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
330 {
331 unsigned long val;
332 void __iomem *base = phy->regs;
333
334 if (phy->instance == 0) {
335 val = readl(base + USB_SUSP_CTRL);
336 val |= USB_SUSP_CLR;
337 writel(val, base + USB_SUSP_CTRL);
338
339 udelay(10);
340
341 val = readl(base + USB_SUSP_CTRL);
342 val &= ~USB_SUSP_CLR;
343 writel(val, base + USB_SUSP_CTRL);
344 }
345
346 if (phy->instance == 2) {
347 val = readl(base + USB_PORTSC1);
348 val &= ~USB_PORTSC1_PHCD;
349 writel(val, base + USB_PORTSC1);
350 }
351
352 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
353 USB_PHY_CLK_VALID))
354 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
355 }
356
357 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
358 {
359 unsigned long val;
360 void __iomem *base = phy->regs;
361 struct tegra_utmip_config *config = phy->config;
362
363 val = readl(base + USB_SUSP_CTRL);
364 val |= UTMIP_RESET;
365 writel(val, base + USB_SUSP_CTRL);
366
367 if (phy->instance == 0) {
368 val = readl(base + USB1_LEGACY_CTRL);
369 val |= USB1_NO_LEGACY_MODE;
370 writel(val, base + USB1_LEGACY_CTRL);
371 }
372
373 val = readl(base + UTMIP_TX_CFG0);
374 val &= ~UTMIP_FS_PREABMLE_J;
375 writel(val, base + UTMIP_TX_CFG0);
376
377 val = readl(base + UTMIP_HSRX_CFG0);
378 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
379 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
380 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
381 writel(val, base + UTMIP_HSRX_CFG0);
382
383 val = readl(base + UTMIP_HSRX_CFG1);
384 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
385 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
386 writel(val, base + UTMIP_HSRX_CFG1);
387
388 val = readl(base + UTMIP_DEBOUNCE_CFG0);
389 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
390 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
391 writel(val, base + UTMIP_DEBOUNCE_CFG0);
392
393 val = readl(base + UTMIP_MISC_CFG0);
394 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
395 writel(val, base + UTMIP_MISC_CFG0);
396
397 val = readl(base + UTMIP_MISC_CFG1);
398 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
399 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
400 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
401 writel(val, base + UTMIP_MISC_CFG1);
402
403 val = readl(base + UTMIP_PLL_CFG1);
404 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
405 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
406 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
407 writel(val, base + UTMIP_PLL_CFG1);
408
409 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
410 val = readl(base + USB_SUSP_CTRL);
411 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
412 writel(val, base + USB_SUSP_CTRL);
413 }
414
415 utmip_pad_power_on(phy);
416
417 val = readl(base + UTMIP_XCVR_CFG0);
418 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
419 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
420 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
421 UTMIP_XCVR_HSSLEW_MSB(~0));
422 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
423 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
424 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
425 writel(val, base + UTMIP_XCVR_CFG0);
426
427 val = readl(base + UTMIP_XCVR_CFG1);
428 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
429 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
430 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
431 writel(val, base + UTMIP_XCVR_CFG1);
432
433 val = readl(base + UTMIP_BAT_CHRG_CFG0);
434 val &= ~UTMIP_PD_CHRG;
435 writel(val, base + UTMIP_BAT_CHRG_CFG0);
436
437 val = readl(base + UTMIP_BIAS_CFG1);
438 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
439 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
440 writel(val, base + UTMIP_BIAS_CFG1);
441
442 if (phy->instance == 0) {
443 val = readl(base + UTMIP_SPARE_CFG0);
444 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
445 val &= ~FUSE_SETUP_SEL;
446 else
447 val |= FUSE_SETUP_SEL;
448 writel(val, base + UTMIP_SPARE_CFG0);
449 }
450
451 if (phy->instance == 2) {
452 val = readl(base + USB_SUSP_CTRL);
453 val |= UTMIP_PHY_ENABLE;
454 writel(val, base + USB_SUSP_CTRL);
455 }
456
457 val = readl(base + USB_SUSP_CTRL);
458 val &= ~UTMIP_RESET;
459 writel(val, base + USB_SUSP_CTRL);
460
461 if (phy->instance == 0) {
462 val = readl(base + USB1_LEGACY_CTRL);
463 val &= ~USB1_VBUS_SENSE_CTL_MASK;
464 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
465 writel(val, base + USB1_LEGACY_CTRL);
466
467 val = readl(base + USB_SUSP_CTRL);
468 val &= ~USB_SUSP_SET;
469 writel(val, base + USB_SUSP_CTRL);
470 }
471
472 utmi_phy_clk_enable(phy);
473
474 if (phy->instance == 2) {
475 val = readl(base + USB_PORTSC1);
476 val &= ~USB_PORTSC1_PTS(~0);
477 writel(val, base + USB_PORTSC1);
478 }
479
480 return 0;
481 }
482
483 static void utmi_phy_power_off(struct tegra_usb_phy *phy)
484 {
485 unsigned long val;
486 void __iomem *base = phy->regs;
487
488 utmi_phy_clk_disable(phy);
489
490 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
491 val = readl(base + USB_SUSP_CTRL);
492 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
493 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
494 writel(val, base + USB_SUSP_CTRL);
495 }
496
497 val = readl(base + USB_SUSP_CTRL);
498 val |= UTMIP_RESET;
499 writel(val, base + USB_SUSP_CTRL);
500
501 val = readl(base + UTMIP_BAT_CHRG_CFG0);
502 val |= UTMIP_PD_CHRG;
503 writel(val, base + UTMIP_BAT_CHRG_CFG0);
504
505 val = readl(base + UTMIP_XCVR_CFG0);
506 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
507 UTMIP_FORCE_PDZI_POWERDOWN;
508 writel(val, base + UTMIP_XCVR_CFG0);
509
510 val = readl(base + UTMIP_XCVR_CFG1);
511 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
512 UTMIP_FORCE_PDDR_POWERDOWN;
513 writel(val, base + UTMIP_XCVR_CFG1);
514
515 utmip_pad_power_off(phy);
516 }
517
518 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
519 {
520 unsigned long val;
521 void __iomem *base = phy->regs;
522
523 val = readl(base + UTMIP_TX_CFG0);
524 val |= UTMIP_HS_DISCON_DISABLE;
525 writel(val, base + UTMIP_TX_CFG0);
526 }
527
528 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
529 {
530 unsigned long val;
531 void __iomem *base = phy->regs;
532
533 val = readl(base + UTMIP_TX_CFG0);
534 val &= ~UTMIP_HS_DISCON_DISABLE;
535 writel(val, base + UTMIP_TX_CFG0);
536 }
537
538 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
539 enum tegra_usb_phy_port_speed port_speed)
540 {
541 unsigned long val;
542 void __iomem *base = phy->regs;
543
544 val = readl(base + UTMIP_MISC_CFG0);
545 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
546 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
547 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
548 else
549 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
550 writel(val, base + UTMIP_MISC_CFG0);
551 udelay(1);
552
553 val = readl(base + UTMIP_MISC_CFG0);
554 val |= UTMIP_DPDM_OBSERVE;
555 writel(val, base + UTMIP_MISC_CFG0);
556 udelay(10);
557 }
558
559 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
560 {
561 unsigned long val;
562 void __iomem *base = phy->regs;
563
564 val = readl(base + UTMIP_MISC_CFG0);
565 val &= ~UTMIP_DPDM_OBSERVE;
566 writel(val, base + UTMIP_MISC_CFG0);
567 udelay(10);
568 }
569
570 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
571 {
572 int ret;
573 unsigned long val;
574 void __iomem *base = phy->regs;
575 struct tegra_ulpi_config *config = phy->config;
576
577 gpio_direction_output(config->reset_gpio, 0);
578 msleep(5);
579 gpio_direction_output(config->reset_gpio, 1);
580
581 clk_enable(phy->clk);
582 msleep(1);
583
584 val = readl(base + USB_SUSP_CTRL);
585 val |= UHSIC_RESET;
586 writel(val, base + USB_SUSP_CTRL);
587
588 val = readl(base + ULPI_TIMING_CTRL_0);
589 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
590 writel(val, base + ULPI_TIMING_CTRL_0);
591
592 val = readl(base + USB_SUSP_CTRL);
593 val |= ULPI_PHY_ENABLE;
594 writel(val, base + USB_SUSP_CTRL);
595
596 val = 0;
597 writel(val, base + ULPI_TIMING_CTRL_1);
598
599 val |= ULPI_DATA_TRIMMER_SEL(4);
600 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
601 val |= ULPI_DIR_TRIMMER_SEL(4);
602 writel(val, base + ULPI_TIMING_CTRL_1);
603 udelay(10);
604
605 val |= ULPI_DATA_TRIMMER_LOAD;
606 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
607 val |= ULPI_DIR_TRIMMER_LOAD;
608 writel(val, base + ULPI_TIMING_CTRL_1);
609
610 /* Fix VbusInvalid due to floating VBUS */
611 ret = otg_io_write(phy->ulpi, 0x40, 0x08);
612 if (ret) {
613 pr_err("%s: ulpi write failed\n", __func__);
614 return ret;
615 }
616
617 ret = otg_io_write(phy->ulpi, 0x80, 0x0B);
618 if (ret) {
619 pr_err("%s: ulpi write failed\n", __func__);
620 return ret;
621 }
622
623 val = readl(base + USB_PORTSC1);
624 val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
625 writel(val, base + USB_PORTSC1);
626
627 val = readl(base + USB_SUSP_CTRL);
628 val |= USB_SUSP_CLR;
629 writel(val, base + USB_SUSP_CTRL);
630 udelay(100);
631
632 val = readl(base + USB_SUSP_CTRL);
633 val &= ~USB_SUSP_CLR;
634 writel(val, base + USB_SUSP_CTRL);
635
636 return 0;
637 }
638
639 static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
640 {
641 unsigned long val;
642 void __iomem *base = phy->regs;
643 struct tegra_ulpi_config *config = phy->config;
644
645 /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
646 * Controller to immediately bring the ULPI PHY out of low power
647 */
648 val = readl(base + USB_PORTSC1);
649 val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
650 writel(val, base + USB_PORTSC1);
651
652 gpio_direction_output(config->reset_gpio, 0);
653 clk_disable(phy->clk);
654 }
655
656 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
657 void *config, enum tegra_usb_phy_mode phy_mode)
658 {
659 struct tegra_usb_phy *phy;
660 struct tegra_ulpi_config *ulpi_config;
661 unsigned long parent_rate;
662 int i;
663 int err;
664
665 phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
666 if (!phy)
667 return ERR_PTR(-ENOMEM);
668
669 phy->instance = instance;
670 phy->regs = regs;
671 phy->config = config;
672 phy->mode = phy_mode;
673
674 if (!phy->config) {
675 if (phy_is_ulpi(phy)) {
676 pr_err("%s: ulpi phy configuration missing", __func__);
677 err = -EINVAL;
678 goto err0;
679 } else {
680 phy->config = &utmip_default[instance];
681 }
682 }
683
684 phy->pll_u = clk_get_sys(NULL, "pll_u");
685 if (IS_ERR(phy->pll_u)) {
686 pr_err("Can't get pll_u clock\n");
687 err = PTR_ERR(phy->pll_u);
688 goto err0;
689 }
690 clk_enable(phy->pll_u);
691
692 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
693 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
694 if (tegra_freq_table[i].freq == parent_rate) {
695 phy->freq = &tegra_freq_table[i];
696 break;
697 }
698 }
699 if (!phy->freq) {
700 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
701 err = -EINVAL;
702 goto err1;
703 }
704
705 if (phy_is_ulpi(phy)) {
706 ulpi_config = config;
707 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
708 if (IS_ERR(phy->clk)) {
709 pr_err("%s: can't get ulpi clock\n", __func__);
710 err = -ENXIO;
711 goto err1;
712 }
713 tegra_gpio_enable(ulpi_config->reset_gpio);
714 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
715 gpio_direction_output(ulpi_config->reset_gpio, 0);
716 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
717 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
718 } else {
719 err = utmip_pad_open(phy);
720 if (err < 0)
721 goto err1;
722 }
723
724 return phy;
725
726 err1:
727 clk_disable(phy->pll_u);
728 clk_put(phy->pll_u);
729 err0:
730 kfree(phy);
731 return ERR_PTR(err);
732 }
733
734 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
735 {
736 if (phy_is_ulpi(phy))
737 return ulpi_phy_power_on(phy);
738 else
739 return utmi_phy_power_on(phy);
740 }
741
742 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
743 {
744 if (phy_is_ulpi(phy))
745 ulpi_phy_power_off(phy);
746 else
747 utmi_phy_power_off(phy);
748 }
749
750 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
751 {
752 if (!phy_is_ulpi(phy))
753 utmi_phy_preresume(phy);
754 }
755
756 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
757 {
758 if (!phy_is_ulpi(phy))
759 utmi_phy_postresume(phy);
760 }
761
762 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
763 enum tegra_usb_phy_port_speed port_speed)
764 {
765 if (!phy_is_ulpi(phy))
766 utmi_phy_restore_start(phy, port_speed);
767 }
768
769 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
770 {
771 if (!phy_is_ulpi(phy))
772 utmi_phy_restore_end(phy);
773 }
774
775 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
776 {
777 if (!phy_is_ulpi(phy))
778 utmi_phy_clk_disable(phy);
779 }
780
781 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
782 {
783 if (!phy_is_ulpi(phy))
784 utmi_phy_clk_enable(phy);
785 }
786
787 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
788 {
789 if (phy_is_ulpi(phy))
790 clk_put(phy->clk);
791 else
792 utmip_pad_close(phy);
793 clk_disable(phy->pll_u);
794 clk_put(phy->pll_u);
795 kfree(phy);
796 }
Linus' kernel tree