2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/u64_stats_sync.h>
72 #include <asm/system.h>
74 #define TX_WORK_PER_LOOP 64
75 #define RX_WORK_PER_LOOP 64
81 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
82 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
83 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
84 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
85 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
86 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
87 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
88 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
89 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
90 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
91 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
92 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
93 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
94 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
95 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
96 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
97 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
98 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
99 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
100 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
101 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
102 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
103 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
104 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
105 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
106 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
107 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
110 NvRegIrqStatus
= 0x000,
111 #define NVREG_IRQSTAT_MIIEVENT 0x040
112 #define NVREG_IRQSTAT_MASK 0x83ff
113 NvRegIrqMask
= 0x004,
114 #define NVREG_IRQ_RX_ERROR 0x0001
115 #define NVREG_IRQ_RX 0x0002
116 #define NVREG_IRQ_RX_NOBUF 0x0004
117 #define NVREG_IRQ_TX_ERR 0x0008
118 #define NVREG_IRQ_TX_OK 0x0010
119 #define NVREG_IRQ_TIMER 0x0020
120 #define NVREG_IRQ_LINK 0x0040
121 #define NVREG_IRQ_RX_FORCED 0x0080
122 #define NVREG_IRQ_TX_FORCED 0x0100
123 #define NVREG_IRQ_RECOVER_ERROR 0x8200
124 #define NVREG_IRQMASK_THROUGHPUT 0x00df
125 #define NVREG_IRQMASK_CPU 0x0060
126 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
127 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
128 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
130 NvRegUnknownSetupReg6
= 0x008,
131 #define NVREG_UNKSETUP6_VAL 3
134 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
135 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
137 NvRegPollingInterval
= 0x00c,
138 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
139 #define NVREG_POLL_DEFAULT_CPU 13
140 NvRegMSIMap0
= 0x020,
141 NvRegMSIMap1
= 0x024,
142 NvRegMSIIrqMask
= 0x030,
143 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
145 #define NVREG_MISC1_PAUSE_TX 0x01
146 #define NVREG_MISC1_HD 0x02
147 #define NVREG_MISC1_FORCE 0x3b0f3c
149 NvRegMacReset
= 0x34,
150 #define NVREG_MAC_RESET_ASSERT 0x0F3
151 NvRegTransmitterControl
= 0x084,
152 #define NVREG_XMITCTL_START 0x01
153 #define NVREG_XMITCTL_MGMT_ST 0x40000000
154 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
155 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
156 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
157 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
158 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
159 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
160 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
161 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
162 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
163 #define NVREG_XMITCTL_DATA_START 0x00100000
164 #define NVREG_XMITCTL_DATA_READY 0x00010000
165 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
166 NvRegTransmitterStatus
= 0x088,
167 #define NVREG_XMITSTAT_BUSY 0x01
169 NvRegPacketFilterFlags
= 0x8c,
170 #define NVREG_PFF_PAUSE_RX 0x08
171 #define NVREG_PFF_ALWAYS 0x7F0000
172 #define NVREG_PFF_PROMISC 0x80
173 #define NVREG_PFF_MYADDR 0x20
174 #define NVREG_PFF_LOOPBACK 0x10
176 NvRegOffloadConfig
= 0x90,
177 #define NVREG_OFFLOAD_HOMEPHY 0x601
178 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
179 NvRegReceiverControl
= 0x094,
180 #define NVREG_RCVCTL_START 0x01
181 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
182 NvRegReceiverStatus
= 0x98,
183 #define NVREG_RCVSTAT_BUSY 0x01
185 NvRegSlotTime
= 0x9c,
186 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
187 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
188 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
189 #define NVREG_SLOTTIME_HALF 0x0000ff00
190 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
191 #define NVREG_SLOTTIME_MASK 0x000000ff
193 NvRegTxDeferral
= 0xA0,
194 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
195 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
196 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
199 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
200 NvRegRxDeferral
= 0xA4,
201 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
202 NvRegMacAddrA
= 0xA8,
203 NvRegMacAddrB
= 0xAC,
204 NvRegMulticastAddrA
= 0xB0,
205 #define NVREG_MCASTADDRA_FORCE 0x01
206 NvRegMulticastAddrB
= 0xB4,
207 NvRegMulticastMaskA
= 0xB8,
208 #define NVREG_MCASTMASKA_NONE 0xffffffff
209 NvRegMulticastMaskB
= 0xBC,
210 #define NVREG_MCASTMASKB_NONE 0xffff
212 NvRegPhyInterface
= 0xC0,
213 #define PHY_RGMII 0x10000000
214 NvRegBackOffControl
= 0xC4,
215 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
216 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
217 #define NVREG_BKOFFCTRL_SELECT 24
218 #define NVREG_BKOFFCTRL_GEAR 12
220 NvRegTxRingPhysAddr
= 0x100,
221 NvRegRxRingPhysAddr
= 0x104,
222 NvRegRingSizes
= 0x108,
223 #define NVREG_RINGSZ_TXSHIFT 0
224 #define NVREG_RINGSZ_RXSHIFT 16
225 NvRegTransmitPoll
= 0x10c,
226 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
227 NvRegLinkSpeed
= 0x110,
228 #define NVREG_LINKSPEED_FORCE 0x10000
229 #define NVREG_LINKSPEED_10 1000
230 #define NVREG_LINKSPEED_100 100
231 #define NVREG_LINKSPEED_1000 50
232 #define NVREG_LINKSPEED_MASK (0xFFF)
233 NvRegUnknownSetupReg5
= 0x130,
234 #define NVREG_UNKSETUP5_BIT31 (1<<31)
235 NvRegTxWatermark
= 0x13c,
236 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
237 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
238 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
239 NvRegTxRxControl
= 0x144,
240 #define NVREG_TXRXCTL_KICK 0x0001
241 #define NVREG_TXRXCTL_BIT1 0x0002
242 #define NVREG_TXRXCTL_BIT2 0x0004
243 #define NVREG_TXRXCTL_IDLE 0x0008
244 #define NVREG_TXRXCTL_RESET 0x0010
245 #define NVREG_TXRXCTL_RXCHECK 0x0400
246 #define NVREG_TXRXCTL_DESC_1 0
247 #define NVREG_TXRXCTL_DESC_2 0x002100
248 #define NVREG_TXRXCTL_DESC_3 0xc02200
249 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
250 #define NVREG_TXRXCTL_VLANINS 0x00080
251 NvRegTxRingPhysAddrHigh
= 0x148,
252 NvRegRxRingPhysAddrHigh
= 0x14C,
253 NvRegTxPauseFrame
= 0x170,
254 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
257 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
258 NvRegTxPauseFrameLimit
= 0x174,
259 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
260 NvRegMIIStatus
= 0x180,
261 #define NVREG_MIISTAT_ERROR 0x0001
262 #define NVREG_MIISTAT_LINKCHANGE 0x0008
263 #define NVREG_MIISTAT_MASK_RW 0x0007
264 #define NVREG_MIISTAT_MASK_ALL 0x000f
265 NvRegMIIMask
= 0x184,
266 #define NVREG_MII_LINKCHANGE 0x0008
268 NvRegAdapterControl
= 0x188,
269 #define NVREG_ADAPTCTL_START 0x02
270 #define NVREG_ADAPTCTL_LINKUP 0x04
271 #define NVREG_ADAPTCTL_PHYVALID 0x40000
272 #define NVREG_ADAPTCTL_RUNNING 0x100000
273 #define NVREG_ADAPTCTL_PHYSHIFT 24
274 NvRegMIISpeed
= 0x18c,
275 #define NVREG_MIISPEED_BIT8 (1<<8)
276 #define NVREG_MIIDELAY 5
277 NvRegMIIControl
= 0x190,
278 #define NVREG_MIICTL_INUSE 0x08000
279 #define NVREG_MIICTL_WRITE 0x00400
280 #define NVREG_MIICTL_ADDRSHIFT 5
281 NvRegMIIData
= 0x194,
282 NvRegTxUnicast
= 0x1a0,
283 NvRegTxMulticast
= 0x1a4,
284 NvRegTxBroadcast
= 0x1a8,
285 NvRegWakeUpFlags
= 0x200,
286 #define NVREG_WAKEUPFLAGS_VAL 0x7770
287 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
288 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
289 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
290 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
291 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
292 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
293 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
294 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
295 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
296 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
298 NvRegMgmtUnitGetVersion
= 0x204,
299 #define NVREG_MGMTUNITGETVERSION 0x01
300 NvRegMgmtUnitVersion
= 0x208,
301 #define NVREG_MGMTUNITVERSION 0x08
302 NvRegPowerCap
= 0x268,
303 #define NVREG_POWERCAP_D3SUPP (1<<30)
304 #define NVREG_POWERCAP_D2SUPP (1<<26)
305 #define NVREG_POWERCAP_D1SUPP (1<<25)
306 NvRegPowerState
= 0x26c,
307 #define NVREG_POWERSTATE_POWEREDUP 0x8000
308 #define NVREG_POWERSTATE_VALID 0x0100
309 #define NVREG_POWERSTATE_MASK 0x0003
310 #define NVREG_POWERSTATE_D0 0x0000
311 #define NVREG_POWERSTATE_D1 0x0001
312 #define NVREG_POWERSTATE_D2 0x0002
313 #define NVREG_POWERSTATE_D3 0x0003
314 NvRegMgmtUnitControl
= 0x278,
315 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
317 NvRegTxZeroReXmt
= 0x284,
318 NvRegTxOneReXmt
= 0x288,
319 NvRegTxManyReXmt
= 0x28c,
320 NvRegTxLateCol
= 0x290,
321 NvRegTxUnderflow
= 0x294,
322 NvRegTxLossCarrier
= 0x298,
323 NvRegTxExcessDef
= 0x29c,
324 NvRegTxRetryErr
= 0x2a0,
325 NvRegRxFrameErr
= 0x2a4,
326 NvRegRxExtraByte
= 0x2a8,
327 NvRegRxLateCol
= 0x2ac,
329 NvRegRxFrameTooLong
= 0x2b4,
330 NvRegRxOverflow
= 0x2b8,
331 NvRegRxFCSErr
= 0x2bc,
332 NvRegRxFrameAlignErr
= 0x2c0,
333 NvRegRxLenErr
= 0x2c4,
334 NvRegRxUnicast
= 0x2c8,
335 NvRegRxMulticast
= 0x2cc,
336 NvRegRxBroadcast
= 0x2d0,
338 NvRegTxFrame
= 0x2d8,
340 NvRegTxPause
= 0x2e0,
341 NvRegRxPause
= 0x2e4,
342 NvRegRxDropFrame
= 0x2e8,
343 NvRegVlanControl
= 0x300,
344 #define NVREG_VLANCONTROL_ENABLE 0x2000
345 NvRegMSIXMap0
= 0x3e0,
346 NvRegMSIXMap1
= 0x3e4,
347 NvRegMSIXIrqStatus
= 0x3f0,
349 NvRegPowerState2
= 0x600,
350 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
351 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
352 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
353 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
356 /* Big endian: should work, but is untested */
362 struct ring_desc_ex
{
370 struct ring_desc
*orig
;
371 struct ring_desc_ex
*ex
;
374 #define FLAG_MASK_V1 0xffff0000
375 #define FLAG_MASK_V2 0xffffc000
376 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
377 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
379 #define NV_TX_LASTPACKET (1<<16)
380 #define NV_TX_RETRYERROR (1<<19)
381 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
382 #define NV_TX_FORCED_INTERRUPT (1<<24)
383 #define NV_TX_DEFERRED (1<<26)
384 #define NV_TX_CARRIERLOST (1<<27)
385 #define NV_TX_LATECOLLISION (1<<28)
386 #define NV_TX_UNDERFLOW (1<<29)
387 #define NV_TX_ERROR (1<<30)
388 #define NV_TX_VALID (1<<31)
390 #define NV_TX2_LASTPACKET (1<<29)
391 #define NV_TX2_RETRYERROR (1<<18)
392 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
393 #define NV_TX2_FORCED_INTERRUPT (1<<30)
394 #define NV_TX2_DEFERRED (1<<25)
395 #define NV_TX2_CARRIERLOST (1<<26)
396 #define NV_TX2_LATECOLLISION (1<<27)
397 #define NV_TX2_UNDERFLOW (1<<28)
398 /* error and valid are the same for both */
399 #define NV_TX2_ERROR (1<<30)
400 #define NV_TX2_VALID (1<<31)
401 #define NV_TX2_TSO (1<<28)
402 #define NV_TX2_TSO_SHIFT 14
403 #define NV_TX2_TSO_MAX_SHIFT 14
404 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
405 #define NV_TX2_CHECKSUM_L3 (1<<27)
406 #define NV_TX2_CHECKSUM_L4 (1<<26)
408 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
410 #define NV_RX_DESCRIPTORVALID (1<<16)
411 #define NV_RX_MISSEDFRAME (1<<17)
412 #define NV_RX_SUBSTRACT1 (1<<18)
413 #define NV_RX_ERROR1 (1<<23)
414 #define NV_RX_ERROR2 (1<<24)
415 #define NV_RX_ERROR3 (1<<25)
416 #define NV_RX_ERROR4 (1<<26)
417 #define NV_RX_CRCERR (1<<27)
418 #define NV_RX_OVERFLOW (1<<28)
419 #define NV_RX_FRAMINGERR (1<<29)
420 #define NV_RX_ERROR (1<<30)
421 #define NV_RX_AVAIL (1<<31)
422 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
424 #define NV_RX2_CHECKSUMMASK (0x1C000000)
425 #define NV_RX2_CHECKSUM_IP (0x10000000)
426 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
427 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
428 #define NV_RX2_DESCRIPTORVALID (1<<29)
429 #define NV_RX2_SUBSTRACT1 (1<<25)
430 #define NV_RX2_ERROR1 (1<<18)
431 #define NV_RX2_ERROR2 (1<<19)
432 #define NV_RX2_ERROR3 (1<<20)
433 #define NV_RX2_ERROR4 (1<<21)
434 #define NV_RX2_CRCERR (1<<22)
435 #define NV_RX2_OVERFLOW (1<<23)
436 #define NV_RX2_FRAMINGERR (1<<24)
437 /* error and avail are the same for both */
438 #define NV_RX2_ERROR (1<<30)
439 #define NV_RX2_AVAIL (1<<31)
440 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
442 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
443 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
445 /* Miscellaneous hardware related defines: */
446 #define NV_PCI_REGSZ_VER1 0x270
447 #define NV_PCI_REGSZ_VER2 0x2d4
448 #define NV_PCI_REGSZ_VER3 0x604
449 #define NV_PCI_REGSZ_MAX 0x604
451 /* various timeout delays: all in usec */
452 #define NV_TXRX_RESET_DELAY 4
453 #define NV_TXSTOP_DELAY1 10
454 #define NV_TXSTOP_DELAY1MAX 500000
455 #define NV_TXSTOP_DELAY2 100
456 #define NV_RXSTOP_DELAY1 10
457 #define NV_RXSTOP_DELAY1MAX 500000
458 #define NV_RXSTOP_DELAY2 100
459 #define NV_SETUP5_DELAY 5
460 #define NV_SETUP5_DELAYMAX 50000
461 #define NV_POWERUP_DELAY 5
462 #define NV_POWERUP_DELAYMAX 5000
463 #define NV_MIIBUSY_DELAY 50
464 #define NV_MIIPHY_DELAY 10
465 #define NV_MIIPHY_DELAYMAX 10000
466 #define NV_MAC_RESET_DELAY 64
468 #define NV_WAKEUPPATTERNS 5
469 #define NV_WAKEUPMASKENTRIES 4
471 /* General driver defaults */
472 #define NV_WATCHDOG_TIMEO (5*HZ)
474 #define RX_RING_DEFAULT 512
475 #define TX_RING_DEFAULT 256
476 #define RX_RING_MIN 128
477 #define TX_RING_MIN 64
478 #define RING_MAX_DESC_VER_1 1024
479 #define RING_MAX_DESC_VER_2_3 16384
481 /* rx/tx mac addr + type + vlan + align + slack*/
482 #define NV_RX_HEADERS (64)
483 /* even more slack. */
484 #define NV_RX_ALLOC_PAD (64)
486 /* maximum mtu size */
487 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
488 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
490 #define OOM_REFILL (1+HZ/20)
491 #define POLL_WAIT (1+HZ/100)
492 #define LINK_TIMEOUT (3*HZ)
493 #define STATS_INTERVAL (10*HZ)
497 * The nic supports three different descriptor types:
498 * - DESC_VER_1: Original
499 * - DESC_VER_2: support for jumbo frames.
500 * - DESC_VER_3: 64-bit format.
507 #define PHY_OUI_MARVELL 0x5043
508 #define PHY_OUI_CICADA 0x03f1
509 #define PHY_OUI_VITESSE 0x01c1
510 #define PHY_OUI_REALTEK 0x0732
511 #define PHY_OUI_REALTEK2 0x0020
512 #define PHYID1_OUI_MASK 0x03ff
513 #define PHYID1_OUI_SHFT 6
514 #define PHYID2_OUI_MASK 0xfc00
515 #define PHYID2_OUI_SHFT 10
516 #define PHYID2_MODEL_MASK 0x03f0
517 #define PHY_MODEL_REALTEK_8211 0x0110
518 #define PHY_REV_MASK 0x0001
519 #define PHY_REV_REALTEK_8211B 0x0000
520 #define PHY_REV_REALTEK_8211C 0x0001
521 #define PHY_MODEL_REALTEK_8201 0x0200
522 #define PHY_MODEL_MARVELL_E3016 0x0220
523 #define PHY_MARVELL_E3016_INITMASK 0x0300
524 #define PHY_CICADA_INIT1 0x0f000
525 #define PHY_CICADA_INIT2 0x0e00
526 #define PHY_CICADA_INIT3 0x01000
527 #define PHY_CICADA_INIT4 0x0200
528 #define PHY_CICADA_INIT5 0x0004
529 #define PHY_CICADA_INIT6 0x02000
530 #define PHY_VITESSE_INIT_REG1 0x1f
531 #define PHY_VITESSE_INIT_REG2 0x10
532 #define PHY_VITESSE_INIT_REG3 0x11
533 #define PHY_VITESSE_INIT_REG4 0x12
534 #define PHY_VITESSE_INIT_MSK1 0xc
535 #define PHY_VITESSE_INIT_MSK2 0x0180
536 #define PHY_VITESSE_INIT1 0x52b5
537 #define PHY_VITESSE_INIT2 0xaf8a
538 #define PHY_VITESSE_INIT3 0x8
539 #define PHY_VITESSE_INIT4 0x8f8a
540 #define PHY_VITESSE_INIT5 0xaf86
541 #define PHY_VITESSE_INIT6 0x8f86
542 #define PHY_VITESSE_INIT7 0xaf82
543 #define PHY_VITESSE_INIT8 0x0100
544 #define PHY_VITESSE_INIT9 0x8f82
545 #define PHY_VITESSE_INIT10 0x0
546 #define PHY_REALTEK_INIT_REG1 0x1f
547 #define PHY_REALTEK_INIT_REG2 0x19
548 #define PHY_REALTEK_INIT_REG3 0x13
549 #define PHY_REALTEK_INIT_REG4 0x14
550 #define PHY_REALTEK_INIT_REG5 0x18
551 #define PHY_REALTEK_INIT_REG6 0x11
552 #define PHY_REALTEK_INIT_REG7 0x01
553 #define PHY_REALTEK_INIT1 0x0000
554 #define PHY_REALTEK_INIT2 0x8e00
555 #define PHY_REALTEK_INIT3 0x0001
556 #define PHY_REALTEK_INIT4 0xad17
557 #define PHY_REALTEK_INIT5 0xfb54
558 #define PHY_REALTEK_INIT6 0xf5c7
559 #define PHY_REALTEK_INIT7 0x1000
560 #define PHY_REALTEK_INIT8 0x0003
561 #define PHY_REALTEK_INIT9 0x0008
562 #define PHY_REALTEK_INIT10 0x0005
563 #define PHY_REALTEK_INIT11 0x0200
564 #define PHY_REALTEK_INIT_MSK1 0x0003
566 #define PHY_GIGABIT 0x0100
568 #define PHY_TIMEOUT 0x1
569 #define PHY_ERROR 0x2
573 #define PHY_HALF 0x100
575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
577 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
578 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
579 #define NV_PAUSEFRAME_RX_REQ 0x0010
580 #define NV_PAUSEFRAME_TX_REQ 0x0020
581 #define NV_PAUSEFRAME_AUTONEG 0x0040
583 /* MSI/MSI-X defines */
584 #define NV_MSI_X_MAX_VECTORS 8
585 #define NV_MSI_X_VECTORS_MASK 0x000f
586 #define NV_MSI_CAPABLE 0x0010
587 #define NV_MSI_X_CAPABLE 0x0020
588 #define NV_MSI_ENABLED 0x0040
589 #define NV_MSI_X_ENABLED 0x0080
591 #define NV_MSI_X_VECTOR_ALL 0x0
592 #define NV_MSI_X_VECTOR_RX 0x0
593 #define NV_MSI_X_VECTOR_TX 0x1
594 #define NV_MSI_X_VECTOR_OTHER 0x2
596 #define NV_MSI_PRIV_OFFSET 0x68
597 #define NV_MSI_PRIV_VALUE 0xffffffff
599 #define NV_RESTART_TX 0x1
600 #define NV_RESTART_RX 0x2
602 #define NV_TX_LIMIT_COUNT 16
604 #define NV_DYNAMIC_THRESHOLD 4
605 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
608 struct nv_ethtool_str
{
609 char name
[ETH_GSTRING_LEN
];
612 static const struct nv_ethtool_str nv_estats_str
[] = {
613 { "tx_bytes" }, /* includes Ethernet FCS CRC */
617 { "tx_late_collision" },
618 { "tx_fifo_errors" },
619 { "tx_carrier_errors" },
620 { "tx_excess_deferral" },
621 { "tx_retry_error" },
622 { "rx_frame_error" },
624 { "rx_late_collision" },
626 { "rx_frame_too_long" },
627 { "rx_over_errors" },
629 { "rx_frame_align_error" },
630 { "rx_length_error" },
635 { "rx_errors_total" },
636 { "tx_errors_total" },
638 /* version 2 stats */
641 { "rx_bytes" }, /* includes Ethernet FCS CRC */
646 /* version 3 stats */
652 struct nv_ethtool_stats
{
653 u64 tx_bytes
; /* should be ifconfig->tx_bytes + 4*tx_packets */
657 u64 tx_late_collision
;
659 u64 tx_carrier_errors
;
660 u64 tx_excess_deferral
;
664 u64 rx_late_collision
;
666 u64 rx_frame_too_long
;
669 u64 rx_frame_align_error
;
674 u64 rx_packets
; /* should be ifconfig->rx_packets */
678 /* version 2 stats */
680 u64 tx_packets
; /* should be ifconfig->tx_packets */
681 u64 rx_bytes
; /* should be ifconfig->rx_bytes + 4*rx_packets */
686 /* version 3 stats */
692 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
693 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
694 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
697 #define NV_TEST_COUNT_BASE 3
698 #define NV_TEST_COUNT_EXTENDED 4
700 static const struct nv_ethtool_str nv_etests_str
[] = {
701 { "link (online/offline)" },
702 { "register (offline) " },
703 { "interrupt (offline) " },
704 { "loopback (offline) " }
707 struct register_test
{
712 static const struct register_test nv_registers_test
[] = {
713 { NvRegUnknownSetupReg6
, 0x01 },
714 { NvRegMisc1
, 0x03c },
715 { NvRegOffloadConfig
, 0x03ff },
716 { NvRegMulticastAddrA
, 0xffffffff },
717 { NvRegTxWatermark
, 0x0ff },
718 { NvRegWakeUpFlags
, 0x07777 },
725 unsigned int dma_len
:31;
726 unsigned int dma_single
:1;
727 struct ring_desc_ex
*first_tx_desc
;
728 struct nv_skb_map
*next_tx_ctx
;
733 * All hardware access under netdev_priv(dev)->lock, except the performance
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
736 * by the arch code for interrupts.
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
741 * Hardware stats updates are protected by hwstats_lock:
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
743 * integer wraparound in the NIC stats registers, at low frequency
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
747 * Software stats are accessed only through 64b synchronization points
748 * and are not subject to other synchronization techniques (single
749 * update thread on the TX or RX paths).
752 /* in dev: base, irq */
756 struct net_device
*dev
;
757 struct napi_struct napi
;
759 /* hardware stats are updated in syscall and timer */
760 spinlock_t hwstats_lock
;
761 struct nv_ethtool_stats estats
;
770 unsigned int phy_oui
;
771 unsigned int phy_model
;
772 unsigned int phy_rev
;
778 /* General data: RO fields */
779 dma_addr_t ring_addr
;
780 struct pci_dev
*pci_dev
;
796 /* rx specific fields.
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
799 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
800 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
801 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
802 struct nv_skb_map
*rx_skb
;
804 union ring_type rx_ring
;
805 unsigned int rx_buf_sz
;
806 unsigned int pkt_limit
;
807 struct timer_list oom_kick
;
808 struct timer_list nic_poll
;
809 struct timer_list stats_poll
;
813 /* RX software stats */
814 struct u64_stats_sync swstats_rx_syncp
;
816 u64 stat_rx_bytes
; /* not always available in HW */
817 u64 stat_rx_missed_errors
;
820 /* media detection workaround.
821 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
824 unsigned long link_timeout
;
826 * tx specific fields.
828 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
829 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
830 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
831 struct nv_skb_map
*tx_skb
;
833 union ring_type tx_ring
;
837 u32 tx_pkts_in_progress
;
838 struct nv_skb_map
*tx_change_owner
;
839 struct nv_skb_map
*tx_end_flip
;
842 /* TX software stats */
843 struct u64_stats_sync swstats_tx_syncp
;
844 u64 stat_tx_packets
; /* not always available in HW */
848 /* msi/msi-x fields */
850 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
855 /* power saved state */
856 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
858 /* for different msi-x irq type */
859 char name_rx
[IFNAMSIZ
+ 3]; /* -rx */
860 char name_tx
[IFNAMSIZ
+ 3]; /* -tx */
861 char name_other
[IFNAMSIZ
+ 6]; /* -other */
865 * Maximum number of loops until we assume that a bit in the irq mask
866 * is stuck. Overridable with module param.
868 static int max_interrupt_work
= 4;
871 * Optimization can be either throuput mode or cpu mode
873 * Throughput Mode: Every tx and rx packet will generate an interrupt.
874 * CPU Mode: Interrupts are controlled by a timer.
877 NV_OPTIMIZATION_MODE_THROUGHPUT
,
878 NV_OPTIMIZATION_MODE_CPU
,
879 NV_OPTIMIZATION_MODE_DYNAMIC
881 static int optimization_mode
= NV_OPTIMIZATION_MODE_DYNAMIC
;
884 * Poll interval for timer irq
886 * This interval determines how frequent an interrupt is generated.
887 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
888 * Min = 0, and Max = 65535
890 static int poll_interval
= -1;
899 static int msi
= NV_MSI_INT_ENABLED
;
905 NV_MSIX_INT_DISABLED
,
908 static int msix
= NV_MSIX_INT_ENABLED
;
914 NV_DMA_64BIT_DISABLED
,
917 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
920 * Debug output control for tx_timeout
922 static bool debug_tx_timeout
= false;
925 * Crossover Detection
926 * Realtek 8201 phy + some OEM boards do not work properly.
929 NV_CROSSOVER_DETECTION_DISABLED
,
930 NV_CROSSOVER_DETECTION_ENABLED
932 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
935 * Power down phy when interface is down (persists through reboot;
936 * older Linux and other OSes may not power it up again)
938 static int phy_power_down
;
940 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
942 return netdev_priv(dev
);
945 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
947 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
950 static inline void pci_push(u8 __iomem
*base
)
952 /* force out pending posted writes */
956 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
958 return le32_to_cpu(prd
->flaglen
)
959 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
962 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
964 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
967 static bool nv_optimized(struct fe_priv
*np
)
969 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
974 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
975 int delay
, int delaymax
)
977 u8 __iomem
*base
= get_hwbase(dev
);
985 } while ((readl(base
+ offset
) & mask
) != target
);
989 #define NV_SETUP_RX_RING 0x01
990 #define NV_SETUP_TX_RING 0x02
992 static inline u32
dma_low(dma_addr_t addr
)
997 static inline u32
dma_high(dma_addr_t addr
)
999 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
1002 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
1004 struct fe_priv
*np
= get_nvpriv(dev
);
1005 u8 __iomem
*base
= get_hwbase(dev
);
1007 if (!nv_optimized(np
)) {
1008 if (rxtx_flags
& NV_SETUP_RX_RING
)
1009 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
1010 if (rxtx_flags
& NV_SETUP_TX_RING
)
1011 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1013 if (rxtx_flags
& NV_SETUP_RX_RING
) {
1014 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
1015 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
1017 if (rxtx_flags
& NV_SETUP_TX_RING
) {
1018 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
1019 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
1024 static void free_rings(struct net_device
*dev
)
1026 struct fe_priv
*np
= get_nvpriv(dev
);
1028 if (!nv_optimized(np
)) {
1029 if (np
->rx_ring
.orig
)
1030 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1031 np
->rx_ring
.orig
, np
->ring_addr
);
1034 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1035 np
->rx_ring
.ex
, np
->ring_addr
);
1041 static int using_multi_irqs(struct net_device
*dev
)
1043 struct fe_priv
*np
= get_nvpriv(dev
);
1045 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1046 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1047 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
1053 static void nv_txrx_gate(struct net_device
*dev
, bool gate
)
1055 struct fe_priv
*np
= get_nvpriv(dev
);
1056 u8 __iomem
*base
= get_hwbase(dev
);
1059 if (!np
->mac_in_use
&&
1060 (np
->driver_data
& DEV_HAS_POWER_CNTRL
)) {
1061 powerstate
= readl(base
+ NvRegPowerState2
);
1063 powerstate
|= NVREG_POWERSTATE2_GATE_CLOCKS
;
1065 powerstate
&= ~NVREG_POWERSTATE2_GATE_CLOCKS
;
1066 writel(powerstate
, base
+ NvRegPowerState2
);
1070 static void nv_enable_irq(struct net_device
*dev
)
1072 struct fe_priv
*np
= get_nvpriv(dev
);
1074 if (!using_multi_irqs(dev
)) {
1075 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1076 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1078 enable_irq(np
->pci_dev
->irq
);
1080 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1081 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1082 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1086 static void nv_disable_irq(struct net_device
*dev
)
1088 struct fe_priv
*np
= get_nvpriv(dev
);
1090 if (!using_multi_irqs(dev
)) {
1091 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1092 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1094 disable_irq(np
->pci_dev
->irq
);
1096 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1097 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1098 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1102 /* In MSIX mode, a write to irqmask behaves as XOR */
1103 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1105 u8 __iomem
*base
= get_hwbase(dev
);
1107 writel(mask
, base
+ NvRegIrqMask
);
1110 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1112 struct fe_priv
*np
= get_nvpriv(dev
);
1113 u8 __iomem
*base
= get_hwbase(dev
);
1115 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1116 writel(mask
, base
+ NvRegIrqMask
);
1118 if (np
->msi_flags
& NV_MSI_ENABLED
)
1119 writel(0, base
+ NvRegMSIIrqMask
);
1120 writel(0, base
+ NvRegIrqMask
);
1124 static void nv_napi_enable(struct net_device
*dev
)
1126 struct fe_priv
*np
= get_nvpriv(dev
);
1128 napi_enable(&np
->napi
);
1131 static void nv_napi_disable(struct net_device
*dev
)
1133 struct fe_priv
*np
= get_nvpriv(dev
);
1135 napi_disable(&np
->napi
);
1138 #define MII_READ (-1)
1139 /* mii_rw: read/write a register on the PHY.
1141 * Caller must guarantee serialization
1143 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1145 u8 __iomem
*base
= get_hwbase(dev
);
1149 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1151 reg
= readl(base
+ NvRegMIIControl
);
1152 if (reg
& NVREG_MIICTL_INUSE
) {
1153 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1154 udelay(NV_MIIBUSY_DELAY
);
1157 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1158 if (value
!= MII_READ
) {
1159 writel(value
, base
+ NvRegMIIData
);
1160 reg
|= NVREG_MIICTL_WRITE
;
1162 writel(reg
, base
+ NvRegMIIControl
);
1164 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1165 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
)) {
1167 } else if (value
!= MII_READ
) {
1168 /* it was a write operation - fewer failures are detectable */
1170 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1173 retval
= readl(base
+ NvRegMIIData
);
1179 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1181 struct fe_priv
*np
= netdev_priv(dev
);
1183 unsigned int tries
= 0;
1185 miicontrol
= BMCR_RESET
| bmcr_setup
;
1186 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
))
1189 /* wait for 500ms */
1192 /* must wait till reset is deasserted */
1193 while (miicontrol
& BMCR_RESET
) {
1194 usleep_range(10000, 20000);
1195 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1196 /* FIXME: 100 tries seem excessive */
1203 static int init_realtek_8211b(struct net_device
*dev
, struct fe_priv
*np
)
1205 static const struct {
1209 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
},
1210 { PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
},
1211 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
},
1212 { PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
},
1213 { PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
},
1214 { PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
},
1215 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
},
1219 for (i
= 0; i
< ARRAY_SIZE(ri
); i
++) {
1220 if (mii_rw(dev
, np
->phyaddr
, ri
[i
].reg
, ri
[i
].init
))
1227 static int init_realtek_8211c(struct net_device
*dev
, struct fe_priv
*np
)
1230 u8 __iomem
*base
= get_hwbase(dev
);
1231 u32 powerstate
= readl(base
+ NvRegPowerState2
);
1233 /* need to perform hw phy reset */
1234 powerstate
|= NVREG_POWERSTATE2_PHY_RESET
;
1235 writel(powerstate
, base
+ NvRegPowerState2
);
1238 powerstate
&= ~NVREG_POWERSTATE2_PHY_RESET
;
1239 writel(powerstate
, base
+ NvRegPowerState2
);
1242 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1243 reg
|= PHY_REALTEK_INIT9
;
1244 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, reg
))
1246 if (mii_rw(dev
, np
->phyaddr
,
1247 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT10
))
1249 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, MII_READ
);
1250 if (!(reg
& PHY_REALTEK_INIT11
)) {
1251 reg
|= PHY_REALTEK_INIT11
;
1252 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, reg
))
1255 if (mii_rw(dev
, np
->phyaddr
,
1256 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
))
1262 static int init_realtek_8201(struct net_device
*dev
, struct fe_priv
*np
)
1266 if (np
->driver_data
& DEV_NEED_PHY_INIT_FIX
) {
1267 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1268 PHY_REALTEK_INIT_REG6
, MII_READ
);
1269 phy_reserved
|= PHY_REALTEK_INIT7
;
1270 if (mii_rw(dev
, np
->phyaddr
,
1271 PHY_REALTEK_INIT_REG6
, phy_reserved
))
1278 static int init_realtek_8201_cross(struct net_device
*dev
, struct fe_priv
*np
)
1282 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1283 if (mii_rw(dev
, np
->phyaddr
,
1284 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
))
1286 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1287 PHY_REALTEK_INIT_REG2
, MII_READ
);
1288 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1289 phy_reserved
|= PHY_REALTEK_INIT3
;
1290 if (mii_rw(dev
, np
->phyaddr
,
1291 PHY_REALTEK_INIT_REG2
, phy_reserved
))
1293 if (mii_rw(dev
, np
->phyaddr
,
1294 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
))
1301 static int init_cicada(struct net_device
*dev
, struct fe_priv
*np
,
1306 if (phyinterface
& PHY_RGMII
) {
1307 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1308 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1309 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1310 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
))
1312 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1313 phy_reserved
|= PHY_CICADA_INIT5
;
1314 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
))
1317 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1318 phy_reserved
|= PHY_CICADA_INIT6
;
1319 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
))
1325 static int init_vitesse(struct net_device
*dev
, struct fe_priv
*np
)
1329 if (mii_rw(dev
, np
->phyaddr
,
1330 PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
))
1332 if (mii_rw(dev
, np
->phyaddr
,
1333 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
))
1335 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1336 PHY_VITESSE_INIT_REG4
, MII_READ
);
1337 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1339 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1340 PHY_VITESSE_INIT_REG3
, MII_READ
);
1341 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1342 phy_reserved
|= PHY_VITESSE_INIT3
;
1343 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1345 if (mii_rw(dev
, np
->phyaddr
,
1346 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
))
1348 if (mii_rw(dev
, np
->phyaddr
,
1349 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
))
1351 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1352 PHY_VITESSE_INIT_REG4
, MII_READ
);
1353 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1354 phy_reserved
|= PHY_VITESSE_INIT3
;
1355 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1357 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1358 PHY_VITESSE_INIT_REG3
, MII_READ
);
1359 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1361 if (mii_rw(dev
, np
->phyaddr
,
1362 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
))
1364 if (mii_rw(dev
, np
->phyaddr
,
1365 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
))
1367 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1368 PHY_VITESSE_INIT_REG4
, MII_READ
);
1369 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1371 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1372 PHY_VITESSE_INIT_REG3
, MII_READ
);
1373 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1374 phy_reserved
|= PHY_VITESSE_INIT8
;
1375 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1377 if (mii_rw(dev
, np
->phyaddr
,
1378 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
))
1380 if (mii_rw(dev
, np
->phyaddr
,
1381 PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
))
1387 static int phy_init(struct net_device
*dev
)
1389 struct fe_priv
*np
= get_nvpriv(dev
);
1390 u8 __iomem
*base
= get_hwbase(dev
);
1392 u32 mii_status
, mii_control
, mii_control_1000
, reg
;
1394 /* phy errata for E3016 phy */
1395 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1396 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1397 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1398 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1399 netdev_info(dev
, "%s: phy write to errata reg failed\n",
1400 pci_name(np
->pci_dev
));
1404 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1405 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1406 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1407 if (init_realtek_8211b(dev
, np
)) {
1408 netdev_info(dev
, "%s: phy init failed\n",
1409 pci_name(np
->pci_dev
));
1412 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1413 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1414 if (init_realtek_8211c(dev
, np
)) {
1415 netdev_info(dev
, "%s: phy init failed\n",
1416 pci_name(np
->pci_dev
));
1419 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1420 if (init_realtek_8201(dev
, np
)) {
1421 netdev_info(dev
, "%s: phy init failed\n",
1422 pci_name(np
->pci_dev
));
1428 /* set advertise register */
1429 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1430 reg
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1431 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
1432 ADVERTISE_PAUSE_ASYM
| ADVERTISE_PAUSE_CAP
);
1433 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1434 netdev_info(dev
, "%s: phy write to advertise failed\n",
1435 pci_name(np
->pci_dev
));
1439 /* get phy interface type */
1440 phyinterface
= readl(base
+ NvRegPhyInterface
);
1442 /* see if gigabit phy */
1443 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1444 if (mii_status
& PHY_GIGABIT
) {
1445 np
->gigabit
= PHY_GIGABIT
;
1446 mii_control_1000
= mii_rw(dev
, np
->phyaddr
,
1447 MII_CTRL1000
, MII_READ
);
1448 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1449 if (phyinterface
& PHY_RGMII
)
1450 mii_control_1000
|= ADVERTISE_1000FULL
;
1452 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1454 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1455 netdev_info(dev
, "%s: phy init failed\n",
1456 pci_name(np
->pci_dev
));
1462 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1463 mii_control
|= BMCR_ANENABLE
;
1465 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
1466 np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1467 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1468 /* start autoneg since we already performed hw reset above */
1469 mii_control
|= BMCR_ANRESTART
;
1470 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1471 netdev_info(dev
, "%s: phy init failed\n",
1472 pci_name(np
->pci_dev
));
1477 * (certain phys need bmcr to be setup with reset)
1479 if (phy_reset(dev
, mii_control
)) {
1480 netdev_info(dev
, "%s: phy reset failed\n",
1481 pci_name(np
->pci_dev
));
1486 /* phy vendor specific configuration */
1487 if ((np
->phy_oui
== PHY_OUI_CICADA
)) {
1488 if (init_cicada(dev
, np
, phyinterface
)) {
1489 netdev_info(dev
, "%s: phy init failed\n",
1490 pci_name(np
->pci_dev
));
1493 } else if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1494 if (init_vitesse(dev
, np
)) {
1495 netdev_info(dev
, "%s: phy init failed\n",
1496 pci_name(np
->pci_dev
));
1499 } else if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1500 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1501 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1502 /* reset could have cleared these out, set them back */
1503 if (init_realtek_8211b(dev
, np
)) {
1504 netdev_info(dev
, "%s: phy init failed\n",
1505 pci_name(np
->pci_dev
));
1508 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1509 if (init_realtek_8201(dev
, np
) ||
1510 init_realtek_8201_cross(dev
, np
)) {
1511 netdev_info(dev
, "%s: phy init failed\n",
1512 pci_name(np
->pci_dev
));
1518 /* some phys clear out pause advertisement on reset, set it back */
1519 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1521 /* restart auto negotiation, power down phy */
1522 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1523 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1525 mii_control
|= BMCR_PDOWN
;
1526 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
))
1532 static void nv_start_rx(struct net_device
*dev
)
1534 struct fe_priv
*np
= netdev_priv(dev
);
1535 u8 __iomem
*base
= get_hwbase(dev
);
1536 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1538 /* Already running? Stop it. */
1539 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1540 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1541 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1544 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1546 rx_ctrl
|= NVREG_RCVCTL_START
;
1548 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1549 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1553 static void nv_stop_rx(struct net_device
*dev
)
1555 struct fe_priv
*np
= netdev_priv(dev
);
1556 u8 __iomem
*base
= get_hwbase(dev
);
1557 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1559 if (!np
->mac_in_use
)
1560 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1562 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1563 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1564 if (reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1565 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
))
1566 netdev_info(dev
, "%s: ReceiverStatus remained busy\n",
1569 udelay(NV_RXSTOP_DELAY2
);
1570 if (!np
->mac_in_use
)
1571 writel(0, base
+ NvRegLinkSpeed
);
1574 static void nv_start_tx(struct net_device
*dev
)
1576 struct fe_priv
*np
= netdev_priv(dev
);
1577 u8 __iomem
*base
= get_hwbase(dev
);
1578 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1580 tx_ctrl
|= NVREG_XMITCTL_START
;
1582 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1583 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1587 static void nv_stop_tx(struct net_device
*dev
)
1589 struct fe_priv
*np
= netdev_priv(dev
);
1590 u8 __iomem
*base
= get_hwbase(dev
);
1591 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1593 if (!np
->mac_in_use
)
1594 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1596 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1597 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1598 if (reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1599 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
))
1600 netdev_info(dev
, "%s: TransmitterStatus remained busy\n",
1603 udelay(NV_TXSTOP_DELAY2
);
1604 if (!np
->mac_in_use
)
1605 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1606 base
+ NvRegTransmitPoll
);
1609 static void nv_start_rxtx(struct net_device
*dev
)
1615 static void nv_stop_rxtx(struct net_device
*dev
)
1621 static void nv_txrx_reset(struct net_device
*dev
)
1623 struct fe_priv
*np
= netdev_priv(dev
);
1624 u8 __iomem
*base
= get_hwbase(dev
);
1626 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1628 udelay(NV_TXRX_RESET_DELAY
);
1629 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1633 static void nv_mac_reset(struct net_device
*dev
)
1635 struct fe_priv
*np
= netdev_priv(dev
);
1636 u8 __iomem
*base
= get_hwbase(dev
);
1637 u32 temp1
, temp2
, temp3
;
1639 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1642 /* save registers since they will be cleared on reset */
1643 temp1
= readl(base
+ NvRegMacAddrA
);
1644 temp2
= readl(base
+ NvRegMacAddrB
);
1645 temp3
= readl(base
+ NvRegTransmitPoll
);
1647 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1649 udelay(NV_MAC_RESET_DELAY
);
1650 writel(0, base
+ NvRegMacReset
);
1652 udelay(NV_MAC_RESET_DELAY
);
1654 /* restore saved registers */
1655 writel(temp1
, base
+ NvRegMacAddrA
);
1656 writel(temp2
, base
+ NvRegMacAddrB
);
1657 writel(temp3
, base
+ NvRegTransmitPoll
);
1659 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1663 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664 static void nv_update_stats(struct net_device
*dev
)
1666 struct fe_priv
*np
= netdev_priv(dev
);
1667 u8 __iomem
*base
= get_hwbase(dev
);
1669 /* If it happens that this is run in top-half context, then
1670 * replace the spin_lock of hwstats_lock with
1671 * spin_lock_irqsave() in calling functions. */
1672 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673 assert_spin_locked(&np
->hwstats_lock
);
1675 /* query hardware */
1676 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1677 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1678 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1679 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1680 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1681 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1682 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1683 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1684 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1685 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1686 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1687 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1688 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1689 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1690 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1691 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1692 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1693 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1694 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1695 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1696 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1697 np
->estats
.rx_packets
=
1698 np
->estats
.rx_unicast
+
1699 np
->estats
.rx_multicast
+
1700 np
->estats
.rx_broadcast
;
1701 np
->estats
.rx_errors_total
=
1702 np
->estats
.rx_crc_errors
+
1703 np
->estats
.rx_over_errors
+
1704 np
->estats
.rx_frame_error
+
1705 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1706 np
->estats
.rx_late_collision
+
1707 np
->estats
.rx_runt
+
1708 np
->estats
.rx_frame_too_long
;
1709 np
->estats
.tx_errors_total
=
1710 np
->estats
.tx_late_collision
+
1711 np
->estats
.tx_fifo_errors
+
1712 np
->estats
.tx_carrier_errors
+
1713 np
->estats
.tx_excess_deferral
+
1714 np
->estats
.tx_retry_error
;
1716 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1717 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1718 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1719 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1720 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1721 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1722 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1723 np
->estats
.rx_errors_total
+= np
->estats
.rx_drop_frame
;
1726 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
) {
1727 np
->estats
.tx_unicast
+= readl(base
+ NvRegTxUnicast
);
1728 np
->estats
.tx_multicast
+= readl(base
+ NvRegTxMulticast
);
1729 np
->estats
.tx_broadcast
+= readl(base
+ NvRegTxBroadcast
);
1734 * nv_get_stats64: dev->ndo_get_stats64 function
1735 * Get latest stats value from the nic.
1736 * Called with read_lock(&dev_base_lock) held for read -
1737 * only synchronized against unregister_netdevice.
1739 static struct rtnl_link_stats64
*
1740 nv_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*storage
)
1741 __acquires(&netdev_priv(dev
)->hwstats_lock
)
1742 __releases(&netdev_priv(dev
)->hwstats_lock
)
1744 struct fe_priv
*np
= netdev_priv(dev
);
1745 unsigned int syncp_start
;
1748 * Note: because HW stats are not always available and for
1749 * consistency reasons, the following ifconfig stats are
1750 * managed by software: rx_bytes, tx_bytes, rx_packets and
1751 * tx_packets. The related hardware stats reported by ethtool
1752 * should be equivalent to these ifconfig stats, with 4
1753 * additional bytes per packet (Ethernet FCS CRC), except for
1754 * tx_packets when TSO kicks in.
1757 /* software stats */
1759 syncp_start
= u64_stats_fetch_begin_bh(&np
->swstats_rx_syncp
);
1760 storage
->rx_packets
= np
->stat_rx_packets
;
1761 storage
->rx_bytes
= np
->stat_rx_bytes
;
1762 storage
->rx_dropped
= np
->stat_rx_dropped
;
1763 storage
->rx_missed_errors
= np
->stat_rx_missed_errors
;
1764 } while (u64_stats_fetch_retry_bh(&np
->swstats_rx_syncp
, syncp_start
));
1767 syncp_start
= u64_stats_fetch_begin_bh(&np
->swstats_tx_syncp
);
1768 storage
->tx_packets
= np
->stat_tx_packets
;
1769 storage
->tx_bytes
= np
->stat_tx_bytes
;
1770 storage
->tx_dropped
= np
->stat_tx_dropped
;
1771 } while (u64_stats_fetch_retry_bh(&np
->swstats_tx_syncp
, syncp_start
));
1773 /* If the nic supports hw counters then retrieve latest values */
1774 if (np
->driver_data
& DEV_HAS_STATISTICS_V123
) {
1775 spin_lock_bh(&np
->hwstats_lock
);
1777 nv_update_stats(dev
);
1780 storage
->rx_errors
= np
->estats
.rx_errors_total
;
1781 storage
->tx_errors
= np
->estats
.tx_errors_total
;
1783 /* meaningful only when NIC supports stats v3 */
1784 storage
->multicast
= np
->estats
.rx_multicast
;
1786 /* detailed rx_errors */
1787 storage
->rx_length_errors
= np
->estats
.rx_length_error
;
1788 storage
->rx_over_errors
= np
->estats
.rx_over_errors
;
1789 storage
->rx_crc_errors
= np
->estats
.rx_crc_errors
;
1790 storage
->rx_frame_errors
= np
->estats
.rx_frame_align_error
;
1791 storage
->rx_fifo_errors
= np
->estats
.rx_drop_frame
;
1793 /* detailed tx_errors */
1794 storage
->tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1795 storage
->tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1797 spin_unlock_bh(&np
->hwstats_lock
);
1804 * nv_alloc_rx: fill rx ring entries.
1805 * Return 1 if the allocations for the skbs failed and the
1806 * rx engine is without Available descriptors
1808 static int nv_alloc_rx(struct net_device
*dev
)
1810 struct fe_priv
*np
= netdev_priv(dev
);
1811 struct ring_desc
*less_rx
;
1813 less_rx
= np
->get_rx
.orig
;
1814 if (less_rx
-- == np
->first_rx
.orig
)
1815 less_rx
= np
->last_rx
.orig
;
1817 while (np
->put_rx
.orig
!= less_rx
) {
1818 struct sk_buff
*skb
= netdev_alloc_skb(dev
, np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1820 np
->put_rx_ctx
->skb
= skb
;
1821 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1824 PCI_DMA_FROMDEVICE
);
1825 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1826 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1828 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1829 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1830 np
->put_rx
.orig
= np
->first_rx
.orig
;
1831 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1832 np
->put_rx_ctx
= np
->first_rx_ctx
;
1834 u64_stats_update_begin(&np
->swstats_rx_syncp
);
1835 np
->stat_rx_dropped
++;
1836 u64_stats_update_end(&np
->swstats_rx_syncp
);
1843 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1845 struct fe_priv
*np
= netdev_priv(dev
);
1846 struct ring_desc_ex
*less_rx
;
1848 less_rx
= np
->get_rx
.ex
;
1849 if (less_rx
-- == np
->first_rx
.ex
)
1850 less_rx
= np
->last_rx
.ex
;
1852 while (np
->put_rx
.ex
!= less_rx
) {
1853 struct sk_buff
*skb
= netdev_alloc_skb(dev
, np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1855 np
->put_rx_ctx
->skb
= skb
;
1856 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1859 PCI_DMA_FROMDEVICE
);
1860 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1861 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1862 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1864 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1865 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1866 np
->put_rx
.ex
= np
->first_rx
.ex
;
1867 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1868 np
->put_rx_ctx
= np
->first_rx_ctx
;
1870 u64_stats_update_begin(&np
->swstats_rx_syncp
);
1871 np
->stat_rx_dropped
++;
1872 u64_stats_update_end(&np
->swstats_rx_syncp
);
1879 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1880 static void nv_do_rx_refill(unsigned long data
)
1882 struct net_device
*dev
= (struct net_device
*) data
;
1883 struct fe_priv
*np
= netdev_priv(dev
);
1885 /* Just reschedule NAPI rx processing */
1886 napi_schedule(&np
->napi
);
1889 static void nv_init_rx(struct net_device
*dev
)
1891 struct fe_priv
*np
= netdev_priv(dev
);
1894 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1896 if (!nv_optimized(np
))
1897 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1899 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1900 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1901 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1903 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1904 if (!nv_optimized(np
)) {
1905 np
->rx_ring
.orig
[i
].flaglen
= 0;
1906 np
->rx_ring
.orig
[i
].buf
= 0;
1908 np
->rx_ring
.ex
[i
].flaglen
= 0;
1909 np
->rx_ring
.ex
[i
].txvlan
= 0;
1910 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1911 np
->rx_ring
.ex
[i
].buflow
= 0;
1913 np
->rx_skb
[i
].skb
= NULL
;
1914 np
->rx_skb
[i
].dma
= 0;
1918 static void nv_init_tx(struct net_device
*dev
)
1920 struct fe_priv
*np
= netdev_priv(dev
);
1923 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1925 if (!nv_optimized(np
))
1926 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1928 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1929 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1930 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1931 netdev_reset_queue(np
->dev
);
1932 np
->tx_pkts_in_progress
= 0;
1933 np
->tx_change_owner
= NULL
;
1934 np
->tx_end_flip
= NULL
;
1937 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1938 if (!nv_optimized(np
)) {
1939 np
->tx_ring
.orig
[i
].flaglen
= 0;
1940 np
->tx_ring
.orig
[i
].buf
= 0;
1942 np
->tx_ring
.ex
[i
].flaglen
= 0;
1943 np
->tx_ring
.ex
[i
].txvlan
= 0;
1944 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1945 np
->tx_ring
.ex
[i
].buflow
= 0;
1947 np
->tx_skb
[i
].skb
= NULL
;
1948 np
->tx_skb
[i
].dma
= 0;
1949 np
->tx_skb
[i
].dma_len
= 0;
1950 np
->tx_skb
[i
].dma_single
= 0;
1951 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1952 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1956 static int nv_init_ring(struct net_device
*dev
)
1958 struct fe_priv
*np
= netdev_priv(dev
);
1963 if (!nv_optimized(np
))
1964 return nv_alloc_rx(dev
);
1966 return nv_alloc_rx_optimized(dev
);
1969 static void nv_unmap_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
1972 if (tx_skb
->dma_single
)
1973 pci_unmap_single(np
->pci_dev
, tx_skb
->dma
,
1977 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1984 static int nv_release_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
1986 nv_unmap_txskb(np
, tx_skb
);
1988 dev_kfree_skb_any(tx_skb
->skb
);
1995 static void nv_drain_tx(struct net_device
*dev
)
1997 struct fe_priv
*np
= netdev_priv(dev
);
2000 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
2001 if (!nv_optimized(np
)) {
2002 np
->tx_ring
.orig
[i
].flaglen
= 0;
2003 np
->tx_ring
.orig
[i
].buf
= 0;
2005 np
->tx_ring
.ex
[i
].flaglen
= 0;
2006 np
->tx_ring
.ex
[i
].txvlan
= 0;
2007 np
->tx_ring
.ex
[i
].bufhigh
= 0;
2008 np
->tx_ring
.ex
[i
].buflow
= 0;
2010 if (nv_release_txskb(np
, &np
->tx_skb
[i
])) {
2011 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2012 np
->stat_tx_dropped
++;
2013 u64_stats_update_end(&np
->swstats_tx_syncp
);
2015 np
->tx_skb
[i
].dma
= 0;
2016 np
->tx_skb
[i
].dma_len
= 0;
2017 np
->tx_skb
[i
].dma_single
= 0;
2018 np
->tx_skb
[i
].first_tx_desc
= NULL
;
2019 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
2021 np
->tx_pkts_in_progress
= 0;
2022 np
->tx_change_owner
= NULL
;
2023 np
->tx_end_flip
= NULL
;
2026 static void nv_drain_rx(struct net_device
*dev
)
2028 struct fe_priv
*np
= netdev_priv(dev
);
2031 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
2032 if (!nv_optimized(np
)) {
2033 np
->rx_ring
.orig
[i
].flaglen
= 0;
2034 np
->rx_ring
.orig
[i
].buf
= 0;
2036 np
->rx_ring
.ex
[i
].flaglen
= 0;
2037 np
->rx_ring
.ex
[i
].txvlan
= 0;
2038 np
->rx_ring
.ex
[i
].bufhigh
= 0;
2039 np
->rx_ring
.ex
[i
].buflow
= 0;
2042 if (np
->rx_skb
[i
].skb
) {
2043 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
2044 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
2045 np
->rx_skb
[i
].skb
->data
),
2046 PCI_DMA_FROMDEVICE
);
2047 dev_kfree_skb(np
->rx_skb
[i
].skb
);
2048 np
->rx_skb
[i
].skb
= NULL
;
2053 static void nv_drain_rxtx(struct net_device
*dev
)
2059 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
2061 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
2064 static void nv_legacybackoff_reseed(struct net_device
*dev
)
2066 u8 __iomem
*base
= get_hwbase(dev
);
2071 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
2072 get_random_bytes(&low
, sizeof(low
));
2073 reg
|= low
& NVREG_SLOTTIME_MASK
;
2075 /* Need to stop tx before change takes effect.
2076 * Caller has already gained np->lock.
2078 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
2082 writel(reg
, base
+ NvRegSlotTime
);
2088 /* Gear Backoff Seeds */
2089 #define BACKOFF_SEEDSET_ROWS 8
2090 #define BACKOFF_SEEDSET_LFSRS 15
2092 /* Known Good seed sets */
2093 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2094 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2095 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2096 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2097 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2098 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2099 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2100 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2101 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2103 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2104 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2105 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2106 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2107 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2108 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2109 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2110 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2111 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2113 static void nv_gear_backoff_reseed(struct net_device
*dev
)
2115 u8 __iomem
*base
= get_hwbase(dev
);
2116 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
2117 u32 temp
, seedset
, combinedSeed
;
2120 /* Setup seed for free running LFSR */
2121 /* We are going to read the time stamp counter 3 times
2122 and swizzle bits around to increase randomness */
2123 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
2124 miniseed1
&= 0x0fff;
2128 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
2129 miniseed2
&= 0x0fff;
2132 miniseed2_reversed
=
2133 ((miniseed2
& 0xF00) >> 8) |
2134 (miniseed2
& 0x0F0) |
2135 ((miniseed2
& 0x00F) << 8);
2137 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
2138 miniseed3
&= 0x0fff;
2141 miniseed3_reversed
=
2142 ((miniseed3
& 0xF00) >> 8) |
2143 (miniseed3
& 0x0F0) |
2144 ((miniseed3
& 0x00F) << 8);
2146 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
2147 (miniseed2
^ miniseed3_reversed
);
2149 /* Seeds can not be zero */
2150 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
2151 combinedSeed
|= 0x08;
2152 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
2153 combinedSeed
|= 0x8000;
2155 /* No need to disable tx here */
2156 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
2157 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
2158 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
2159 writel(temp
, base
+ NvRegBackOffControl
);
2161 /* Setup seeds for all gear LFSRs. */
2162 get_random_bytes(&seedset
, sizeof(seedset
));
2163 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
2164 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++) {
2165 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
2166 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
2167 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
2168 writel(temp
, base
+ NvRegBackOffControl
);
2173 * nv_start_xmit: dev->hard_start_xmit function
2174 * Called with netif_tx_lock held.
2176 static netdev_tx_t
nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2178 struct fe_priv
*np
= netdev_priv(dev
);
2180 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2181 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2185 u32 size
= skb_headlen(skb
);
2186 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2188 struct ring_desc
*put_tx
;
2189 struct ring_desc
*start_tx
;
2190 struct ring_desc
*prev_tx
;
2191 struct nv_skb_map
*prev_tx_ctx
;
2192 unsigned long flags
;
2194 /* add fragments to entries count */
2195 for (i
= 0; i
< fragments
; i
++) {
2196 u32 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[i
]);
2198 entries
+= (frag_size
>> NV_TX2_TSO_MAX_SHIFT
) +
2199 ((frag_size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2202 spin_lock_irqsave(&np
->lock
, flags
);
2203 empty_slots
= nv_get_empty_tx_slots(np
);
2204 if (unlikely(empty_slots
<= entries
)) {
2205 netif_stop_queue(dev
);
2207 spin_unlock_irqrestore(&np
->lock
, flags
);
2208 return NETDEV_TX_BUSY
;
2210 spin_unlock_irqrestore(&np
->lock
, flags
);
2212 start_tx
= put_tx
= np
->put_tx
.orig
;
2214 /* setup the header buffer */
2217 prev_tx_ctx
= np
->put_tx_ctx
;
2218 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2219 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2221 np
->put_tx_ctx
->dma_len
= bcnt
;
2222 np
->put_tx_ctx
->dma_single
= 1;
2223 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2224 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2226 tx_flags
= np
->tx_flags
;
2229 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2230 put_tx
= np
->first_tx
.orig
;
2231 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2232 np
->put_tx_ctx
= np
->first_tx_ctx
;
2235 /* setup the fragments */
2236 for (i
= 0; i
< fragments
; i
++) {
2237 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2238 u32 frag_size
= skb_frag_size(frag
);
2243 prev_tx_ctx
= np
->put_tx_ctx
;
2244 bcnt
= (frag_size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: frag_size
;
2245 np
->put_tx_ctx
->dma
= skb_frag_dma_map(
2250 np
->put_tx_ctx
->dma_len
= bcnt
;
2251 np
->put_tx_ctx
->dma_single
= 0;
2252 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2253 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2257 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2258 put_tx
= np
->first_tx
.orig
;
2259 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2260 np
->put_tx_ctx
= np
->first_tx_ctx
;
2261 } while (frag_size
);
2264 /* set last fragment flag */
2265 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2267 /* save skb in this slot's context area */
2268 prev_tx_ctx
->skb
= skb
;
2270 if (skb_is_gso(skb
))
2271 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2273 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2274 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2276 spin_lock_irqsave(&np
->lock
, flags
);
2279 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2281 netdev_sent_queue(np
->dev
, skb
->len
);
2283 np
->put_tx
.orig
= put_tx
;
2285 spin_unlock_irqrestore(&np
->lock
, flags
);
2287 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2288 return NETDEV_TX_OK
;
2291 static netdev_tx_t
nv_start_xmit_optimized(struct sk_buff
*skb
,
2292 struct net_device
*dev
)
2294 struct fe_priv
*np
= netdev_priv(dev
);
2297 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2301 u32 size
= skb_headlen(skb
);
2302 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2304 struct ring_desc_ex
*put_tx
;
2305 struct ring_desc_ex
*start_tx
;
2306 struct ring_desc_ex
*prev_tx
;
2307 struct nv_skb_map
*prev_tx_ctx
;
2308 struct nv_skb_map
*start_tx_ctx
;
2309 unsigned long flags
;
2311 /* add fragments to entries count */
2312 for (i
= 0; i
< fragments
; i
++) {
2313 u32 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[i
]);
2315 entries
+= (frag_size
>> NV_TX2_TSO_MAX_SHIFT
) +
2316 ((frag_size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2319 spin_lock_irqsave(&np
->lock
, flags
);
2320 empty_slots
= nv_get_empty_tx_slots(np
);
2321 if (unlikely(empty_slots
<= entries
)) {
2322 netif_stop_queue(dev
);
2324 spin_unlock_irqrestore(&np
->lock
, flags
);
2325 return NETDEV_TX_BUSY
;
2327 spin_unlock_irqrestore(&np
->lock
, flags
);
2329 start_tx
= put_tx
= np
->put_tx
.ex
;
2330 start_tx_ctx
= np
->put_tx_ctx
;
2332 /* setup the header buffer */
2335 prev_tx_ctx
= np
->put_tx_ctx
;
2336 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2337 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2339 np
->put_tx_ctx
->dma_len
= bcnt
;
2340 np
->put_tx_ctx
->dma_single
= 1;
2341 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2342 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2343 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2345 tx_flags
= NV_TX2_VALID
;
2348 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2349 put_tx
= np
->first_tx
.ex
;
2350 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2351 np
->put_tx_ctx
= np
->first_tx_ctx
;
2354 /* setup the fragments */
2355 for (i
= 0; i
< fragments
; i
++) {
2356 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2357 u32 frag_size
= skb_frag_size(frag
);
2362 prev_tx_ctx
= np
->put_tx_ctx
;
2363 bcnt
= (frag_size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: frag_size
;
2364 np
->put_tx_ctx
->dma
= skb_frag_dma_map(
2369 np
->put_tx_ctx
->dma_len
= bcnt
;
2370 np
->put_tx_ctx
->dma_single
= 0;
2371 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2372 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2373 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2377 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2378 put_tx
= np
->first_tx
.ex
;
2379 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2380 np
->put_tx_ctx
= np
->first_tx_ctx
;
2381 } while (frag_size
);
2384 /* set last fragment flag */
2385 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2387 /* save skb in this slot's context area */
2388 prev_tx_ctx
->skb
= skb
;
2390 if (skb_is_gso(skb
))
2391 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2393 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2394 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2397 if (vlan_tx_tag_present(skb
))
2398 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
|
2399 vlan_tx_tag_get(skb
));
2401 start_tx
->txvlan
= 0;
2403 spin_lock_irqsave(&np
->lock
, flags
);
2406 /* Limit the number of outstanding tx. Setup all fragments, but
2407 * do not set the VALID bit on the first descriptor. Save a pointer
2408 * to that descriptor and also for next skb_map element.
2411 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2412 if (!np
->tx_change_owner
)
2413 np
->tx_change_owner
= start_tx_ctx
;
2415 /* remove VALID bit */
2416 tx_flags
&= ~NV_TX2_VALID
;
2417 start_tx_ctx
->first_tx_desc
= start_tx
;
2418 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2419 np
->tx_end_flip
= np
->put_tx_ctx
;
2421 np
->tx_pkts_in_progress
++;
2426 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2428 netdev_sent_queue(np
->dev
, skb
->len
);
2430 np
->put_tx
.ex
= put_tx
;
2432 spin_unlock_irqrestore(&np
->lock
, flags
);
2434 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2435 return NETDEV_TX_OK
;
2438 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2440 struct fe_priv
*np
= netdev_priv(dev
);
2442 np
->tx_pkts_in_progress
--;
2443 if (np
->tx_change_owner
) {
2444 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2445 cpu_to_le32(NV_TX2_VALID
);
2446 np
->tx_pkts_in_progress
++;
2448 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2449 if (np
->tx_change_owner
== np
->tx_end_flip
)
2450 np
->tx_change_owner
= NULL
;
2452 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2457 * nv_tx_done: check for completed packets, release the skbs.
2459 * Caller must own np->lock.
2461 static int nv_tx_done(struct net_device
*dev
, int limit
)
2463 struct fe_priv
*np
= netdev_priv(dev
);
2466 struct ring_desc
*orig_get_tx
= np
->get_tx
.orig
;
2467 unsigned int bytes_compl
= 0;
2469 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2470 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
) &&
2471 (tx_work
< limit
)) {
2473 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2475 if (np
->desc_ver
== DESC_VER_1
) {
2476 if (flags
& NV_TX_LASTPACKET
) {
2477 if (flags
& NV_TX_ERROR
) {
2478 if ((flags
& NV_TX_RETRYERROR
)
2479 && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2480 nv_legacybackoff_reseed(dev
);
2482 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2483 np
->stat_tx_packets
++;
2484 np
->stat_tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2485 u64_stats_update_end(&np
->swstats_tx_syncp
);
2487 bytes_compl
+= np
->get_tx_ctx
->skb
->len
;
2488 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2489 np
->get_tx_ctx
->skb
= NULL
;
2493 if (flags
& NV_TX2_LASTPACKET
) {
2494 if (flags
& NV_TX2_ERROR
) {
2495 if ((flags
& NV_TX2_RETRYERROR
)
2496 && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2497 nv_legacybackoff_reseed(dev
);
2499 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2500 np
->stat_tx_packets
++;
2501 np
->stat_tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2502 u64_stats_update_end(&np
->swstats_tx_syncp
);
2504 bytes_compl
+= np
->get_tx_ctx
->skb
->len
;
2505 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2506 np
->get_tx_ctx
->skb
= NULL
;
2510 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2511 np
->get_tx
.orig
= np
->first_tx
.orig
;
2512 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2513 np
->get_tx_ctx
= np
->first_tx_ctx
;
2516 netdev_completed_queue(np
->dev
, tx_work
, bytes_compl
);
2518 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2520 netif_wake_queue(dev
);
2525 static int nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2527 struct fe_priv
*np
= netdev_priv(dev
);
2530 struct ring_desc_ex
*orig_get_tx
= np
->get_tx
.ex
;
2531 unsigned long bytes_cleaned
= 0;
2533 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2534 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX2_VALID
) &&
2535 (tx_work
< limit
)) {
2537 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2539 if (flags
& NV_TX2_LASTPACKET
) {
2540 if (flags
& NV_TX2_ERROR
) {
2541 if ((flags
& NV_TX2_RETRYERROR
)
2542 && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2543 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2544 nv_gear_backoff_reseed(dev
);
2546 nv_legacybackoff_reseed(dev
);
2549 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2550 np
->stat_tx_packets
++;
2551 np
->stat_tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2552 u64_stats_update_end(&np
->swstats_tx_syncp
);
2555 bytes_cleaned
+= np
->get_tx_ctx
->skb
->len
;
2556 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2557 np
->get_tx_ctx
->skb
= NULL
;
2561 nv_tx_flip_ownership(dev
);
2564 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2565 np
->get_tx
.ex
= np
->first_tx
.ex
;
2566 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2567 np
->get_tx_ctx
= np
->first_tx_ctx
;
2570 netdev_completed_queue(np
->dev
, tx_work
, bytes_cleaned
);
2572 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2574 netif_wake_queue(dev
);
2580 * nv_tx_timeout: dev->tx_timeout function
2581 * Called with netif_tx_lock held.
2583 static void nv_tx_timeout(struct net_device
*dev
)
2585 struct fe_priv
*np
= netdev_priv(dev
);
2586 u8 __iomem
*base
= get_hwbase(dev
);
2588 union ring_type put_tx
;
2591 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2592 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2594 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2596 netdev_warn(dev
, "Got tx_timeout. irq status: %08x\n", status
);
2598 if (unlikely(debug_tx_timeout
)) {
2601 netdev_info(dev
, "Ring at %lx\n", (unsigned long)np
->ring_addr
);
2602 netdev_info(dev
, "Dumping tx registers\n");
2603 for (i
= 0; i
<= np
->register_size
; i
+= 32) {
2605 "%3x: %08x %08x %08x %08x "
2606 "%08x %08x %08x %08x\n",
2608 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2609 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2610 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2611 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2613 netdev_info(dev
, "Dumping tx ring\n");
2614 for (i
= 0; i
< np
->tx_ring_size
; i
+= 4) {
2615 if (!nv_optimized(np
)) {
2617 "%03x: %08x %08x // %08x %08x "
2618 "// %08x %08x // %08x %08x\n",
2620 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2621 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2622 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2623 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2624 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2625 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2626 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2627 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2630 "%03x: %08x %08x %08x "
2631 "// %08x %08x %08x "
2632 "// %08x %08x %08x "
2633 "// %08x %08x %08x\n",
2635 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2636 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2637 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2638 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2639 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2640 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2641 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2642 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2643 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2644 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2645 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2646 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2651 spin_lock_irq(&np
->lock
);
2653 /* 1) stop tx engine */
2656 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2657 saved_tx_limit
= np
->tx_limit
;
2658 np
->tx_limit
= 0; /* prevent giving HW any limited pkts */
2659 np
->tx_stop
= 0; /* prevent waking tx queue */
2660 if (!nv_optimized(np
))
2661 nv_tx_done(dev
, np
->tx_ring_size
);
2663 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2665 /* save current HW position */
2666 if (np
->tx_change_owner
)
2667 put_tx
.ex
= np
->tx_change_owner
->first_tx_desc
;
2669 put_tx
= np
->put_tx
;
2671 /* 3) clear all tx state */
2675 /* 4) restore state to current HW position */
2676 np
->get_tx
= np
->put_tx
= put_tx
;
2677 np
->tx_limit
= saved_tx_limit
;
2679 /* 5) restart tx engine */
2681 netif_wake_queue(dev
);
2682 spin_unlock_irq(&np
->lock
);
2686 * Called when the nic notices a mismatch between the actual data len on the
2687 * wire and the len indicated in the 802 header
2689 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2691 int hdrlen
; /* length of the 802 header */
2692 int protolen
; /* length as stored in the proto field */
2694 /* 1) calculate len according to header */
2695 if (((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2696 protolen
= ntohs(((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2699 protolen
= ntohs(((struct ethhdr
*)packet
)->h_proto
);
2702 if (protolen
> ETH_DATA_LEN
)
2703 return datalen
; /* Value in proto field not a len, no checks possible */
2706 /* consistency checks: */
2707 if (datalen
> ETH_ZLEN
) {
2708 if (datalen
>= protolen
) {
2709 /* more data on wire than in 802 header, trim of
2714 /* less data on wire than mentioned in header.
2715 * Discard the packet.
2720 /* short packet. Accept only if 802 values are also short */
2721 if (protolen
> ETH_ZLEN
) {
2728 static int nv_rx_process(struct net_device
*dev
, int limit
)
2730 struct fe_priv
*np
= netdev_priv(dev
);
2733 struct sk_buff
*skb
;
2736 while ((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2737 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2738 (rx_work
< limit
)) {
2741 * the packet is for us - immediately tear down the pci mapping.
2742 * TODO: check if a prefetch of the first cacheline improves
2745 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2746 np
->get_rx_ctx
->dma_len
,
2747 PCI_DMA_FROMDEVICE
);
2748 skb
= np
->get_rx_ctx
->skb
;
2749 np
->get_rx_ctx
->skb
= NULL
;
2751 /* look at what we actually got: */
2752 if (np
->desc_ver
== DESC_VER_1
) {
2753 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2754 len
= flags
& LEN_MASK_V1
;
2755 if (unlikely(flags
& NV_RX_ERROR
)) {
2756 if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_ERROR4
) {
2757 len
= nv_getlen(dev
, skb
->data
, len
);
2763 /* framing errors are soft errors */
2764 else if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_FRAMINGERR
) {
2765 if (flags
& NV_RX_SUBSTRACT1
)
2768 /* the rest are hard errors */
2770 if (flags
& NV_RX_MISSEDFRAME
) {
2771 u64_stats_update_begin(&np
->swstats_rx_syncp
);
2772 np
->stat_rx_missed_errors
++;
2773 u64_stats_update_end(&np
->swstats_rx_syncp
);
2784 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2785 len
= flags
& LEN_MASK_V2
;
2786 if (unlikely(flags
& NV_RX2_ERROR
)) {
2787 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2788 len
= nv_getlen(dev
, skb
->data
, len
);
2794 /* framing errors are soft errors */
2795 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2796 if (flags
& NV_RX2_SUBSTRACT1
)
2799 /* the rest are hard errors */
2805 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2806 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2807 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2813 /* got a valid packet - forward it to the network core */
2815 skb
->protocol
= eth_type_trans(skb
, dev
);
2816 napi_gro_receive(&np
->napi
, skb
);
2817 u64_stats_update_begin(&np
->swstats_rx_syncp
);
2818 np
->stat_rx_packets
++;
2819 np
->stat_rx_bytes
+= len
;
2820 u64_stats_update_end(&np
->swstats_rx_syncp
);
2822 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2823 np
->get_rx
.orig
= np
->first_rx
.orig
;
2824 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2825 np
->get_rx_ctx
= np
->first_rx_ctx
;
2833 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2835 struct fe_priv
*np
= netdev_priv(dev
);
2839 struct sk_buff
*skb
;
2842 while ((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2843 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2844 (rx_work
< limit
)) {
2847 * the packet is for us - immediately tear down the pci mapping.
2848 * TODO: check if a prefetch of the first cacheline improves
2851 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2852 np
->get_rx_ctx
->dma_len
,
2853 PCI_DMA_FROMDEVICE
);
2854 skb
= np
->get_rx_ctx
->skb
;
2855 np
->get_rx_ctx
->skb
= NULL
;
2857 /* look at what we actually got: */
2858 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2859 len
= flags
& LEN_MASK_V2
;
2860 if (unlikely(flags
& NV_RX2_ERROR
)) {
2861 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2862 len
= nv_getlen(dev
, skb
->data
, len
);
2868 /* framing errors are soft errors */
2869 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2870 if (flags
& NV_RX2_SUBSTRACT1
)
2873 /* the rest are hard errors */
2880 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2881 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2882 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2884 /* got a valid packet - forward it to the network core */
2886 skb
->protocol
= eth_type_trans(skb
, dev
);
2887 prefetch(skb
->data
);
2889 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2892 * There's need to check for NETIF_F_HW_VLAN_RX here.
2893 * Even if vlan rx accel is disabled,
2894 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2896 if (dev
->features
& NETIF_F_HW_VLAN_RX
&&
2897 vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2898 u16 vid
= vlanflags
& NV_RX3_VLAN_TAG_MASK
;
2900 __vlan_hwaccel_put_tag(skb
, vid
);
2902 napi_gro_receive(&np
->napi
, skb
);
2903 u64_stats_update_begin(&np
->swstats_rx_syncp
);
2904 np
->stat_rx_packets
++;
2905 np
->stat_rx_bytes
+= len
;
2906 u64_stats_update_end(&np
->swstats_rx_syncp
);
2911 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2912 np
->get_rx
.ex
= np
->first_rx
.ex
;
2913 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2914 np
->get_rx_ctx
= np
->first_rx_ctx
;
2922 static void set_bufsize(struct net_device
*dev
)
2924 struct fe_priv
*np
= netdev_priv(dev
);
2926 if (dev
->mtu
<= ETH_DATA_LEN
)
2927 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2929 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2933 * nv_change_mtu: dev->change_mtu function
2934 * Called with dev_base_lock held for read.
2936 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2938 struct fe_priv
*np
= netdev_priv(dev
);
2941 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2947 /* return early if the buffer sizes will not change */
2948 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2950 if (old_mtu
== new_mtu
)
2953 /* synchronized against open : rtnl_lock() held by caller */
2954 if (netif_running(dev
)) {
2955 u8 __iomem
*base
= get_hwbase(dev
);
2957 * It seems that the nic preloads valid ring entries into an
2958 * internal buffer. The procedure for flushing everything is
2959 * guessed, there is probably a simpler approach.
2960 * Changing the MTU is a rare event, it shouldn't matter.
2962 nv_disable_irq(dev
);
2963 nv_napi_disable(dev
);
2964 netif_tx_lock_bh(dev
);
2965 netif_addr_lock(dev
);
2966 spin_lock(&np
->lock
);
2970 /* drain rx queue */
2972 /* reinit driver view of the rx queue */
2974 if (nv_init_ring(dev
)) {
2975 if (!np
->in_shutdown
)
2976 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2978 /* reinit nic view of the rx queue */
2979 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2980 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2981 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
2982 base
+ NvRegRingSizes
);
2984 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2987 /* restart rx engine */
2989 spin_unlock(&np
->lock
);
2990 netif_addr_unlock(dev
);
2991 netif_tx_unlock_bh(dev
);
2992 nv_napi_enable(dev
);
2998 static void nv_copy_mac_to_hw(struct net_device
*dev
)
3000 u8 __iomem
*base
= get_hwbase(dev
);
3003 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
3004 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
3005 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
3007 writel(mac
[0], base
+ NvRegMacAddrA
);
3008 writel(mac
[1], base
+ NvRegMacAddrB
);
3012 * nv_set_mac_address: dev->set_mac_address function
3013 * Called with rtnl_lock() held.
3015 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
3017 struct fe_priv
*np
= netdev_priv(dev
);
3018 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
3020 if (!is_valid_ether_addr(macaddr
->sa_data
))
3021 return -EADDRNOTAVAIL
;
3023 /* synchronized against open : rtnl_lock() held by caller */
3024 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
3025 dev
->addr_assign_type
&= ~NET_ADDR_RANDOM
;
3027 if (netif_running(dev
)) {
3028 netif_tx_lock_bh(dev
);
3029 netif_addr_lock(dev
);
3030 spin_lock_irq(&np
->lock
);
3032 /* stop rx engine */
3035 /* set mac address */
3036 nv_copy_mac_to_hw(dev
);
3038 /* restart rx engine */
3040 spin_unlock_irq(&np
->lock
);
3041 netif_addr_unlock(dev
);
3042 netif_tx_unlock_bh(dev
);
3044 nv_copy_mac_to_hw(dev
);
3050 * nv_set_multicast: dev->set_multicast function
3051 * Called with netif_tx_lock held.
3053 static void nv_set_multicast(struct net_device
*dev
)
3055 struct fe_priv
*np
= netdev_priv(dev
);
3056 u8 __iomem
*base
= get_hwbase(dev
);
3059 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
3061 memset(addr
, 0, sizeof(addr
));
3062 memset(mask
, 0, sizeof(mask
));
3064 if (dev
->flags
& IFF_PROMISC
) {
3065 pff
|= NVREG_PFF_PROMISC
;
3067 pff
|= NVREG_PFF_MYADDR
;
3069 if (dev
->flags
& IFF_ALLMULTI
|| !netdev_mc_empty(dev
)) {
3073 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
3074 if (dev
->flags
& IFF_ALLMULTI
) {
3075 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
3077 struct netdev_hw_addr
*ha
;
3079 netdev_for_each_mc_addr(ha
, dev
) {
3080 unsigned char *hw_addr
= ha
->addr
;
3083 a
= le32_to_cpu(*(__le32
*) hw_addr
);
3084 b
= le16_to_cpu(*(__le16
*) (&hw_addr
[4]));
3091 addr
[0] = alwaysOn
[0];
3092 addr
[1] = alwaysOn
[1];
3093 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
3094 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
3096 mask
[0] = NVREG_MCASTMASKA_NONE
;
3097 mask
[1] = NVREG_MCASTMASKB_NONE
;
3100 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
3101 pff
|= NVREG_PFF_ALWAYS
;
3102 spin_lock_irq(&np
->lock
);
3104 writel(addr
[0], base
+ NvRegMulticastAddrA
);
3105 writel(addr
[1], base
+ NvRegMulticastAddrB
);
3106 writel(mask
[0], base
+ NvRegMulticastMaskA
);
3107 writel(mask
[1], base
+ NvRegMulticastMaskB
);
3108 writel(pff
, base
+ NvRegPacketFilterFlags
);
3110 spin_unlock_irq(&np
->lock
);
3113 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
3115 struct fe_priv
*np
= netdev_priv(dev
);
3116 u8 __iomem
*base
= get_hwbase(dev
);
3118 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
3120 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
3121 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
3122 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
3123 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
3124 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3126 writel(pff
, base
+ NvRegPacketFilterFlags
);
3129 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
3130 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
3131 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
3132 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
3133 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
3134 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3135 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
) {
3136 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3137 /* limit the number of tx pause frames to a default of 8 */
3138 writel(readl(base
+ NvRegTxPauseFrameLimit
)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE
, base
+ NvRegTxPauseFrameLimit
);
3140 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3141 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3142 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3144 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3145 writel(regmisc
, base
+ NvRegMisc1
);
3150 static void nv_force_linkspeed(struct net_device
*dev
, int speed
, int duplex
)
3152 struct fe_priv
*np
= netdev_priv(dev
);
3153 u8 __iomem
*base
= get_hwbase(dev
);
3157 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|speed
;
3158 np
->duplex
= duplex
;
3160 /* see if gigabit phy */
3161 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3162 if (mii_status
& PHY_GIGABIT
) {
3163 np
->gigabit
= PHY_GIGABIT
;
3164 phyreg
= readl(base
+ NvRegSlotTime
);
3165 phyreg
&= ~(0x3FF00);
3166 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
3167 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3168 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
3169 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3170 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3171 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3172 writel(phyreg
, base
+ NvRegSlotTime
);
3175 phyreg
= readl(base
+ NvRegPhyInterface
);
3176 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3177 if (np
->duplex
== 0)
3179 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3181 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3182 NVREG_LINKSPEED_1000
)
3184 writel(phyreg
, base
+ NvRegPhyInterface
);
3186 if (phyreg
& PHY_RGMII
) {
3187 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3188 NVREG_LINKSPEED_1000
)
3189 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3191 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3193 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3195 writel(txreg
, base
+ NvRegTxDeferral
);
3197 if (np
->desc_ver
== DESC_VER_1
) {
3198 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3200 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3201 NVREG_LINKSPEED_1000
)
3202 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3204 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3206 writel(txreg
, base
+ NvRegTxWatermark
);
3208 writel(NVREG_MISC1_FORCE
| (np
->duplex
? 0 : NVREG_MISC1_HD
),
3211 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3218 * nv_update_linkspeed: Setup the MAC according to the link partner
3219 * @dev: Network device to be configured
3221 * The function queries the PHY and checks if there is a link partner.
3222 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3223 * set to 10 MBit HD.
3225 * The function returns 0 if there is no link partner and 1 if there is
3226 * a good link partner.
3228 static int nv_update_linkspeed(struct net_device
*dev
)
3230 struct fe_priv
*np
= netdev_priv(dev
);
3231 u8 __iomem
*base
= get_hwbase(dev
);
3234 int adv_lpa
, adv_pause
, lpa_pause
;
3235 int newls
= np
->linkspeed
;
3236 int newdup
= np
->duplex
;
3240 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3244 /* If device loopback is enabled, set carrier on and enable max link
3247 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3248 if (bmcr
& BMCR_LOOPBACK
) {
3249 if (netif_running(dev
)) {
3250 nv_force_linkspeed(dev
, NVREG_LINKSPEED_1000
, 1);
3251 if (!netif_carrier_ok(dev
))
3252 netif_carrier_on(dev
);
3257 /* BMSR_LSTATUS is latched, read it twice:
3258 * we want the current value.
3260 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3261 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3263 if (!(mii_status
& BMSR_LSTATUS
)) {
3264 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3270 if (np
->autoneg
== 0) {
3271 if (np
->fixed_mode
& LPA_100FULL
) {
3272 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3274 } else if (np
->fixed_mode
& LPA_100HALF
) {
3275 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3277 } else if (np
->fixed_mode
& LPA_10FULL
) {
3278 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3281 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3287 /* check auto negotiation is complete */
3288 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3289 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3290 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3296 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3297 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3300 if (np
->gigabit
== PHY_GIGABIT
) {
3301 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3302 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3304 if ((control_1000
& ADVERTISE_1000FULL
) &&
3305 (status_1000
& LPA_1000FULL
)) {
3306 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3312 /* FIXME: handle parallel detection properly */
3313 adv_lpa
= lpa
& adv
;
3314 if (adv_lpa
& LPA_100FULL
) {
3315 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3317 } else if (adv_lpa
& LPA_100HALF
) {
3318 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3320 } else if (adv_lpa
& LPA_10FULL
) {
3321 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3323 } else if (adv_lpa
& LPA_10HALF
) {
3324 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3327 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3332 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3335 np
->duplex
= newdup
;
3336 np
->linkspeed
= newls
;
3338 /* The transmitter and receiver must be restarted for safe update */
3339 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3340 txrxFlags
|= NV_RESTART_TX
;
3343 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3344 txrxFlags
|= NV_RESTART_RX
;
3348 if (np
->gigabit
== PHY_GIGABIT
) {
3349 phyreg
= readl(base
+ NvRegSlotTime
);
3350 phyreg
&= ~(0x3FF00);
3351 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3352 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3353 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3354 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3355 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3356 writel(phyreg
, base
+ NvRegSlotTime
);
3359 phyreg
= readl(base
+ NvRegPhyInterface
);
3360 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3361 if (np
->duplex
== 0)
3363 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3365 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3367 writel(phyreg
, base
+ NvRegPhyInterface
);
3369 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3370 if (phyreg
& PHY_RGMII
) {
3371 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3372 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3374 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3375 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3376 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3378 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3380 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3384 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3385 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3387 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3389 writel(txreg
, base
+ NvRegTxDeferral
);
3391 if (np
->desc_ver
== DESC_VER_1
) {
3392 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3394 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3395 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3397 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3399 writel(txreg
, base
+ NvRegTxWatermark
);
3401 writel(NVREG_MISC1_FORCE
| (np
->duplex
? 0 : NVREG_MISC1_HD
),
3404 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3408 /* setup pause frame */
3409 if (np
->duplex
!= 0) {
3410 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3411 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3412 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3414 switch (adv_pause
) {
3415 case ADVERTISE_PAUSE_CAP
:
3416 if (lpa_pause
& LPA_PAUSE_CAP
) {
3417 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3418 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3419 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3422 case ADVERTISE_PAUSE_ASYM
:
3423 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3424 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3426 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3427 if (lpa_pause
& LPA_PAUSE_CAP
) {
3428 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3429 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3430 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3432 if (lpa_pause
== LPA_PAUSE_ASYM
)
3433 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3437 pause_flags
= np
->pause_flags
;
3440 nv_update_pause(dev
, pause_flags
);
3442 if (txrxFlags
& NV_RESTART_TX
)
3444 if (txrxFlags
& NV_RESTART_RX
)
3450 static void nv_linkchange(struct net_device
*dev
)
3452 if (nv_update_linkspeed(dev
)) {
3453 if (!netif_carrier_ok(dev
)) {
3454 netif_carrier_on(dev
);
3455 netdev_info(dev
, "link up\n");
3456 nv_txrx_gate(dev
, false);
3460 if (netif_carrier_ok(dev
)) {
3461 netif_carrier_off(dev
);
3462 netdev_info(dev
, "link down\n");
3463 nv_txrx_gate(dev
, true);
3469 static void nv_link_irq(struct net_device
*dev
)
3471 u8 __iomem
*base
= get_hwbase(dev
);
3474 miistat
= readl(base
+ NvRegMIIStatus
);
3475 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3477 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3481 static void nv_msi_workaround(struct fe_priv
*np
)
3484 /* Need to toggle the msi irq mask within the ethernet device,
3485 * otherwise, future interrupts will not be detected.
3487 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3488 u8 __iomem
*base
= np
->base
;
3490 writel(0, base
+ NvRegMSIIrqMask
);
3491 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3495 static inline int nv_change_interrupt_mode(struct net_device
*dev
, int total_work
)
3497 struct fe_priv
*np
= netdev_priv(dev
);
3499 if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
) {
3500 if (total_work
> NV_DYNAMIC_THRESHOLD
) {
3501 /* transition to poll based interrupts */
3502 np
->quiet_count
= 0;
3503 if (np
->irqmask
!= NVREG_IRQMASK_CPU
) {
3504 np
->irqmask
= NVREG_IRQMASK_CPU
;
3508 if (np
->quiet_count
< NV_DYNAMIC_MAX_QUIET_COUNT
) {
3511 /* reached a period of low activity, switch
3512 to per tx/rx packet interrupts */
3513 if (np
->irqmask
!= NVREG_IRQMASK_THROUGHPUT
) {
3514 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3523 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3525 struct net_device
*dev
= (struct net_device
*) data
;
3526 struct fe_priv
*np
= netdev_priv(dev
);
3527 u8 __iomem
*base
= get_hwbase(dev
);
3529 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3530 np
->events
= readl(base
+ NvRegIrqStatus
);
3531 writel(np
->events
, base
+ NvRegIrqStatus
);
3533 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3534 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3536 if (!(np
->events
& np
->irqmask
))
3539 nv_msi_workaround(np
);
3541 if (napi_schedule_prep(&np
->napi
)) {
3543 * Disable further irq's (msix not enabled with napi)
3545 writel(0, base
+ NvRegIrqMask
);
3546 __napi_schedule(&np
->napi
);
3553 * All _optimized functions are used to help increase performance
3554 * (reduce CPU and increase throughput). They use descripter version 3,
3555 * compiler directives, and reduce memory accesses.
3557 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3559 struct net_device
*dev
= (struct net_device
*) data
;
3560 struct fe_priv
*np
= netdev_priv(dev
);
3561 u8 __iomem
*base
= get_hwbase(dev
);
3563 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3564 np
->events
= readl(base
+ NvRegIrqStatus
);
3565 writel(np
->events
, base
+ NvRegIrqStatus
);
3567 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3568 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3570 if (!(np
->events
& np
->irqmask
))
3573 nv_msi_workaround(np
);
3575 if (napi_schedule_prep(&np
->napi
)) {
3577 * Disable further irq's (msix not enabled with napi)
3579 writel(0, base
+ NvRegIrqMask
);
3580 __napi_schedule(&np
->napi
);
3586 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3588 struct net_device
*dev
= (struct net_device
*) data
;
3589 struct fe_priv
*np
= netdev_priv(dev
);
3590 u8 __iomem
*base
= get_hwbase(dev
);
3593 unsigned long flags
;
3596 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3597 writel(events
, base
+ NvRegMSIXIrqStatus
);
3598 netdev_dbg(dev
, "tx irq events: %08x\n", events
);
3599 if (!(events
& np
->irqmask
))
3602 spin_lock_irqsave(&np
->lock
, flags
);
3603 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3604 spin_unlock_irqrestore(&np
->lock
, flags
);
3606 if (unlikely(i
> max_interrupt_work
)) {
3607 spin_lock_irqsave(&np
->lock
, flags
);
3608 /* disable interrupts on the nic */
3609 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3612 if (!np
->in_shutdown
) {
3613 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3614 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3616 spin_unlock_irqrestore(&np
->lock
, flags
);
3617 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3624 return IRQ_RETVAL(i
);
3627 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3629 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3630 struct net_device
*dev
= np
->dev
;
3631 u8 __iomem
*base
= get_hwbase(dev
);
3632 unsigned long flags
;
3634 int rx_count
, tx_work
= 0, rx_work
= 0;
3637 if (!nv_optimized(np
)) {
3638 spin_lock_irqsave(&np
->lock
, flags
);
3639 tx_work
+= nv_tx_done(dev
, np
->tx_ring_size
);
3640 spin_unlock_irqrestore(&np
->lock
, flags
);
3642 rx_count
= nv_rx_process(dev
, budget
- rx_work
);
3643 retcode
= nv_alloc_rx(dev
);
3645 spin_lock_irqsave(&np
->lock
, flags
);
3646 tx_work
+= nv_tx_done_optimized(dev
, np
->tx_ring_size
);
3647 spin_unlock_irqrestore(&np
->lock
, flags
);
3649 rx_count
= nv_rx_process_optimized(dev
,
3651 retcode
= nv_alloc_rx_optimized(dev
);
3653 } while (retcode
== 0 &&
3654 rx_count
> 0 && (rx_work
+= rx_count
) < budget
);
3657 spin_lock_irqsave(&np
->lock
, flags
);
3658 if (!np
->in_shutdown
)
3659 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3660 spin_unlock_irqrestore(&np
->lock
, flags
);
3663 nv_change_interrupt_mode(dev
, tx_work
+ rx_work
);
3665 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3666 spin_lock_irqsave(&np
->lock
, flags
);
3668 spin_unlock_irqrestore(&np
->lock
, flags
);
3670 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3671 spin_lock_irqsave(&np
->lock
, flags
);
3673 spin_unlock_irqrestore(&np
->lock
, flags
);
3674 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3676 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3677 spin_lock_irqsave(&np
->lock
, flags
);
3678 if (!np
->in_shutdown
) {
3679 np
->nic_poll_irq
= np
->irqmask
;
3680 np
->recover_error
= 1;
3681 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3683 spin_unlock_irqrestore(&np
->lock
, flags
);
3684 napi_complete(napi
);
3688 if (rx_work
< budget
) {
3689 /* re-enable interrupts
3690 (msix not enabled in napi) */
3691 napi_complete(napi
);
3693 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3698 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3700 struct net_device
*dev
= (struct net_device
*) data
;
3701 struct fe_priv
*np
= netdev_priv(dev
);
3702 u8 __iomem
*base
= get_hwbase(dev
);
3705 unsigned long flags
;
3708 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3709 writel(events
, base
+ NvRegMSIXIrqStatus
);
3710 netdev_dbg(dev
, "rx irq events: %08x\n", events
);
3711 if (!(events
& np
->irqmask
))
3714 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3715 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3716 spin_lock_irqsave(&np
->lock
, flags
);
3717 if (!np
->in_shutdown
)
3718 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3719 spin_unlock_irqrestore(&np
->lock
, flags
);
3723 if (unlikely(i
> max_interrupt_work
)) {
3724 spin_lock_irqsave(&np
->lock
, flags
);
3725 /* disable interrupts on the nic */
3726 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3729 if (!np
->in_shutdown
) {
3730 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3731 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3733 spin_unlock_irqrestore(&np
->lock
, flags
);
3734 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3740 return IRQ_RETVAL(i
);
3743 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3745 struct net_device
*dev
= (struct net_device
*) data
;
3746 struct fe_priv
*np
= netdev_priv(dev
);
3747 u8 __iomem
*base
= get_hwbase(dev
);
3750 unsigned long flags
;
3753 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3754 writel(events
, base
+ NvRegMSIXIrqStatus
);
3755 netdev_dbg(dev
, "irq events: %08x\n", events
);
3756 if (!(events
& np
->irqmask
))
3759 /* check tx in case we reached max loop limit in tx isr */
3760 spin_lock_irqsave(&np
->lock
, flags
);
3761 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3762 spin_unlock_irqrestore(&np
->lock
, flags
);
3764 if (events
& NVREG_IRQ_LINK
) {
3765 spin_lock_irqsave(&np
->lock
, flags
);
3767 spin_unlock_irqrestore(&np
->lock
, flags
);
3769 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3770 spin_lock_irqsave(&np
->lock
, flags
);
3772 spin_unlock_irqrestore(&np
->lock
, flags
);
3773 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3775 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3776 spin_lock_irq(&np
->lock
);
3777 /* disable interrupts on the nic */
3778 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3781 if (!np
->in_shutdown
) {
3782 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3783 np
->recover_error
= 1;
3784 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3786 spin_unlock_irq(&np
->lock
);
3789 if (unlikely(i
> max_interrupt_work
)) {
3790 spin_lock_irqsave(&np
->lock
, flags
);
3791 /* disable interrupts on the nic */
3792 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3795 if (!np
->in_shutdown
) {
3796 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3797 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3799 spin_unlock_irqrestore(&np
->lock
, flags
);
3800 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3807 return IRQ_RETVAL(i
);
3810 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3812 struct net_device
*dev
= (struct net_device
*) data
;
3813 struct fe_priv
*np
= netdev_priv(dev
);
3814 u8 __iomem
*base
= get_hwbase(dev
);
3817 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3818 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3819 writel(events
& NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3821 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3822 writel(events
& NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3825 if (!(events
& NVREG_IRQ_TIMER
))
3826 return IRQ_RETVAL(0);
3828 nv_msi_workaround(np
);
3830 spin_lock(&np
->lock
);
3832 spin_unlock(&np
->lock
);
3834 return IRQ_RETVAL(1);
3837 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3839 u8 __iomem
*base
= get_hwbase(dev
);
3843 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3844 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3845 * the remaining 8 interrupts.
3847 for (i
= 0; i
< 8; i
++) {
3848 if ((irqmask
>> i
) & 0x1)
3849 msixmap
|= vector
<< (i
<< 2);
3851 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3854 for (i
= 0; i
< 8; i
++) {
3855 if ((irqmask
>> (i
+ 8)) & 0x1)
3856 msixmap
|= vector
<< (i
<< 2);
3858 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3861 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3863 struct fe_priv
*np
= get_nvpriv(dev
);
3864 u8 __iomem
*base
= get_hwbase(dev
);
3867 irqreturn_t (*handler
)(int foo
, void *data
);
3870 handler
= nv_nic_irq_test
;
3872 if (nv_optimized(np
))
3873 handler
= nv_nic_irq_optimized
;
3875 handler
= nv_nic_irq
;
3878 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3879 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++)
3880 np
->msi_x_entry
[i
].entry
= i
;
3881 ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
));
3883 np
->msi_flags
|= NV_MSI_X_ENABLED
;
3884 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
3885 /* Request irq for rx handling */
3886 sprintf(np
->name_rx
, "%s-rx", dev
->name
);
3887 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
,
3888 nv_nic_irq_rx
, IRQF_SHARED
, np
->name_rx
, dev
) != 0) {
3890 "request_irq failed for rx %d\n",
3892 pci_disable_msix(np
->pci_dev
);
3893 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3896 /* Request irq for tx handling */
3897 sprintf(np
->name_tx
, "%s-tx", dev
->name
);
3898 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
,
3899 nv_nic_irq_tx
, IRQF_SHARED
, np
->name_tx
, dev
) != 0) {
3901 "request_irq failed for tx %d\n",
3903 pci_disable_msix(np
->pci_dev
);
3904 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3907 /* Request irq for link and timer handling */
3908 sprintf(np
->name_other
, "%s-other", dev
->name
);
3909 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
,
3910 nv_nic_irq_other
, IRQF_SHARED
, np
->name_other
, dev
) != 0) {
3912 "request_irq failed for link %d\n",
3914 pci_disable_msix(np
->pci_dev
);
3915 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3918 /* map interrupts to their respective vector */
3919 writel(0, base
+ NvRegMSIXMap0
);
3920 writel(0, base
+ NvRegMSIXMap1
);
3921 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
3922 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
3923 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
3925 /* Request irq for all interrupts */
3926 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3928 "request_irq failed %d\n",
3930 pci_disable_msix(np
->pci_dev
);
3931 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3935 /* map interrupts to vector 0 */
3936 writel(0, base
+ NvRegMSIXMap0
);
3937 writel(0, base
+ NvRegMSIXMap1
);
3939 netdev_info(dev
, "MSI-X enabled\n");
3942 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
3943 ret
= pci_enable_msi(np
->pci_dev
);
3945 np
->msi_flags
|= NV_MSI_ENABLED
;
3946 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3947 netdev_info(dev
, "request_irq failed %d\n",
3949 pci_disable_msi(np
->pci_dev
);
3950 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3954 /* map interrupts to vector 0 */
3955 writel(0, base
+ NvRegMSIMap0
);
3956 writel(0, base
+ NvRegMSIMap1
);
3957 /* enable msi vector 0 */
3958 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3959 netdev_info(dev
, "MSI enabled\n");
3963 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
3970 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
3972 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
3977 static void nv_free_irq(struct net_device
*dev
)
3979 struct fe_priv
*np
= get_nvpriv(dev
);
3982 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
3983 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++)
3984 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
3985 pci_disable_msix(np
->pci_dev
);
3986 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3988 free_irq(np
->pci_dev
->irq
, dev
);
3989 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3990 pci_disable_msi(np
->pci_dev
);
3991 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3996 static void nv_do_nic_poll(unsigned long data
)
3998 struct net_device
*dev
= (struct net_device
*) data
;
3999 struct fe_priv
*np
= netdev_priv(dev
);
4000 u8 __iomem
*base
= get_hwbase(dev
);
4004 * First disable irq(s) and then
4005 * reenable interrupts on the nic, we have to do this before calling
4006 * nv_nic_irq because that may decide to do otherwise
4009 if (!using_multi_irqs(dev
)) {
4010 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4011 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4013 disable_irq_lockdep(np
->pci_dev
->irq
);
4016 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4017 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4018 mask
|= NVREG_IRQ_RX_ALL
;
4020 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4021 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4022 mask
|= NVREG_IRQ_TX_ALL
;
4024 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4025 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4026 mask
|= NVREG_IRQ_OTHER
;
4029 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4031 if (np
->recover_error
) {
4032 np
->recover_error
= 0;
4033 netdev_info(dev
, "MAC in recoverable error state\n");
4034 if (netif_running(dev
)) {
4035 netif_tx_lock_bh(dev
);
4036 netif_addr_lock(dev
);
4037 spin_lock(&np
->lock
);
4040 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
4043 /* drain rx queue */
4045 /* reinit driver view of the rx queue */
4047 if (nv_init_ring(dev
)) {
4048 if (!np
->in_shutdown
)
4049 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4051 /* reinit nic view of the rx queue */
4052 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4053 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4054 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4055 base
+ NvRegRingSizes
);
4057 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4059 /* clear interrupts */
4060 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4061 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4063 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4065 /* restart rx engine */
4067 spin_unlock(&np
->lock
);
4068 netif_addr_unlock(dev
);
4069 netif_tx_unlock_bh(dev
);
4073 writel(mask
, base
+ NvRegIrqMask
);
4076 if (!using_multi_irqs(dev
)) {
4077 np
->nic_poll_irq
= 0;
4078 if (nv_optimized(np
))
4079 nv_nic_irq_optimized(0, dev
);
4082 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4083 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4085 enable_irq_lockdep(np
->pci_dev
->irq
);
4087 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4088 np
->nic_poll_irq
&= ~NVREG_IRQ_RX_ALL
;
4089 nv_nic_irq_rx(0, dev
);
4090 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4092 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4093 np
->nic_poll_irq
&= ~NVREG_IRQ_TX_ALL
;
4094 nv_nic_irq_tx(0, dev
);
4095 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4097 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4098 np
->nic_poll_irq
&= ~NVREG_IRQ_OTHER
;
4099 nv_nic_irq_other(0, dev
);
4100 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4106 #ifdef CONFIG_NET_POLL_CONTROLLER
4107 static void nv_poll_controller(struct net_device
*dev
)
4109 nv_do_nic_poll((unsigned long) dev
);
4113 static void nv_do_stats_poll(unsigned long data
)
4114 __acquires(&netdev_priv(dev
)->hwstats_lock
)
4115 __releases(&netdev_priv(dev
)->hwstats_lock
)
4117 struct net_device
*dev
= (struct net_device
*) data
;
4118 struct fe_priv
*np
= netdev_priv(dev
);
4120 /* If lock is currently taken, the stats are being refreshed
4121 * and hence fresh enough */
4122 if (spin_trylock(&np
->hwstats_lock
)) {
4123 nv_update_stats(dev
);
4124 spin_unlock(&np
->hwstats_lock
);
4127 if (!np
->in_shutdown
)
4128 mod_timer(&np
->stats_poll
,
4129 round_jiffies(jiffies
+ STATS_INTERVAL
));
4132 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4134 struct fe_priv
*np
= netdev_priv(dev
);
4135 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
4136 strlcpy(info
->version
, FORCEDETH_VERSION
, sizeof(info
->version
));
4137 strlcpy(info
->bus_info
, pci_name(np
->pci_dev
), sizeof(info
->bus_info
));
4140 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4142 struct fe_priv
*np
= netdev_priv(dev
);
4143 wolinfo
->supported
= WAKE_MAGIC
;
4145 spin_lock_irq(&np
->lock
);
4147 wolinfo
->wolopts
= WAKE_MAGIC
;
4148 spin_unlock_irq(&np
->lock
);
4151 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4153 struct fe_priv
*np
= netdev_priv(dev
);
4154 u8 __iomem
*base
= get_hwbase(dev
);
4157 if (wolinfo
->wolopts
== 0) {
4159 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4161 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4163 if (netif_running(dev
)) {
4164 spin_lock_irq(&np
->lock
);
4165 writel(flags
, base
+ NvRegWakeUpFlags
);
4166 spin_unlock_irq(&np
->lock
);
4168 device_set_wakeup_enable(&np
->pci_dev
->dev
, np
->wolenabled
);
4172 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4174 struct fe_priv
*np
= netdev_priv(dev
);
4178 spin_lock_irq(&np
->lock
);
4179 ecmd
->port
= PORT_MII
;
4180 if (!netif_running(dev
)) {
4181 /* We do not track link speed / duplex setting if the
4182 * interface is disabled. Force a link check */
4183 if (nv_update_linkspeed(dev
)) {
4184 if (!netif_carrier_ok(dev
))
4185 netif_carrier_on(dev
);
4187 if (netif_carrier_ok(dev
))
4188 netif_carrier_off(dev
);
4192 if (netif_carrier_ok(dev
)) {
4193 switch (np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4194 case NVREG_LINKSPEED_10
:
4197 case NVREG_LINKSPEED_100
:
4200 case NVREG_LINKSPEED_1000
:
4207 ecmd
->duplex
= DUPLEX_HALF
;
4209 ecmd
->duplex
= DUPLEX_FULL
;
4214 ethtool_cmd_speed_set(ecmd
, speed
);
4215 ecmd
->autoneg
= np
->autoneg
;
4217 ecmd
->advertising
= ADVERTISED_MII
;
4219 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4220 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4221 if (adv
& ADVERTISE_10HALF
)
4222 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4223 if (adv
& ADVERTISE_10FULL
)
4224 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4225 if (adv
& ADVERTISE_100HALF
)
4226 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4227 if (adv
& ADVERTISE_100FULL
)
4228 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4229 if (np
->gigabit
== PHY_GIGABIT
) {
4230 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4231 if (adv
& ADVERTISE_1000FULL
)
4232 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4235 ecmd
->supported
= (SUPPORTED_Autoneg
|
4236 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4237 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4239 if (np
->gigabit
== PHY_GIGABIT
)
4240 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4242 ecmd
->phy_address
= np
->phyaddr
;
4243 ecmd
->transceiver
= XCVR_EXTERNAL
;
4245 /* ignore maxtxpkt, maxrxpkt for now */
4246 spin_unlock_irq(&np
->lock
);
4250 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4252 struct fe_priv
*np
= netdev_priv(dev
);
4253 u32 speed
= ethtool_cmd_speed(ecmd
);
4255 if (ecmd
->port
!= PORT_MII
)
4257 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4259 if (ecmd
->phy_address
!= np
->phyaddr
) {
4260 /* TODO: support switching between multiple phys. Should be
4261 * trivial, but not enabled due to lack of test hardware. */
4264 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4267 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4268 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4269 if (np
->gigabit
== PHY_GIGABIT
)
4270 mask
|= ADVERTISED_1000baseT_Full
;
4272 if ((ecmd
->advertising
& mask
) == 0)
4275 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4276 /* Note: autonegotiation disable, speed 1000 intentionally
4277 * forbidden - no one should need that. */
4279 if (speed
!= SPEED_10
&& speed
!= SPEED_100
)
4281 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4287 netif_carrier_off(dev
);
4288 if (netif_running(dev
)) {
4289 unsigned long flags
;
4291 nv_disable_irq(dev
);
4292 netif_tx_lock_bh(dev
);
4293 netif_addr_lock(dev
);
4294 /* with plain spinlock lockdep complains */
4295 spin_lock_irqsave(&np
->lock
, flags
);
4298 * this can take some time, and interrupts are disabled
4299 * due to spin_lock_irqsave, but let's hope no daemon
4300 * is going to change the settings very often...
4302 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4303 * + some minor delays, which is up to a second approximately
4306 spin_unlock_irqrestore(&np
->lock
, flags
);
4307 netif_addr_unlock(dev
);
4308 netif_tx_unlock_bh(dev
);
4311 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4316 /* advertise only what has been requested */
4317 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4318 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4319 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4320 adv
|= ADVERTISE_10HALF
;
4321 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4322 adv
|= ADVERTISE_10FULL
;
4323 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4324 adv
|= ADVERTISE_100HALF
;
4325 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4326 adv
|= ADVERTISE_100FULL
;
4327 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisements but disable tx pause */
4328 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4329 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4330 adv
|= ADVERTISE_PAUSE_ASYM
;
4331 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4333 if (np
->gigabit
== PHY_GIGABIT
) {
4334 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4335 adv
&= ~ADVERTISE_1000FULL
;
4336 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4337 adv
|= ADVERTISE_1000FULL
;
4338 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4341 if (netif_running(dev
))
4342 netdev_info(dev
, "link down\n");
4343 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4344 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4345 bmcr
|= BMCR_ANENABLE
;
4346 /* reset the phy in order for settings to stick,
4347 * and cause autoneg to start */
4348 if (phy_reset(dev
, bmcr
)) {
4349 netdev_info(dev
, "phy reset failed\n");
4353 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4354 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4361 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4362 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4363 if (speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4364 adv
|= ADVERTISE_10HALF
;
4365 if (speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4366 adv
|= ADVERTISE_10FULL
;
4367 if (speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4368 adv
|= ADVERTISE_100HALF
;
4369 if (speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4370 adv
|= ADVERTISE_100FULL
;
4371 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4372 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisements but disable tx pause */
4373 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4374 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4376 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4377 adv
|= ADVERTISE_PAUSE_ASYM
;
4378 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4380 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4381 np
->fixed_mode
= adv
;
4383 if (np
->gigabit
== PHY_GIGABIT
) {
4384 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4385 adv
&= ~ADVERTISE_1000FULL
;
4386 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4389 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4390 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4391 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4392 bmcr
|= BMCR_FULLDPLX
;
4393 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4394 bmcr
|= BMCR_SPEED100
;
4395 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4396 /* reset the phy in order for forced mode settings to stick */
4397 if (phy_reset(dev
, bmcr
)) {
4398 netdev_info(dev
, "phy reset failed\n");
4402 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4403 if (netif_running(dev
)) {
4404 /* Wait a bit and then reconfigure the nic. */
4411 if (netif_running(dev
)) {
4419 #define FORCEDETH_REGS_VER 1
4421 static int nv_get_regs_len(struct net_device
*dev
)
4423 struct fe_priv
*np
= netdev_priv(dev
);
4424 return np
->register_size
;
4427 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4429 struct fe_priv
*np
= netdev_priv(dev
);
4430 u8 __iomem
*base
= get_hwbase(dev
);
4434 regs
->version
= FORCEDETH_REGS_VER
;
4435 spin_lock_irq(&np
->lock
);
4436 for (i
= 0; i
<= np
->register_size
/sizeof(u32
); i
++)
4437 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4438 spin_unlock_irq(&np
->lock
);
4441 static int nv_nway_reset(struct net_device
*dev
)
4443 struct fe_priv
*np
= netdev_priv(dev
);
4449 netif_carrier_off(dev
);
4450 if (netif_running(dev
)) {
4451 nv_disable_irq(dev
);
4452 netif_tx_lock_bh(dev
);
4453 netif_addr_lock(dev
);
4454 spin_lock(&np
->lock
);
4457 spin_unlock(&np
->lock
);
4458 netif_addr_unlock(dev
);
4459 netif_tx_unlock_bh(dev
);
4460 netdev_info(dev
, "link down\n");
4463 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4464 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4465 bmcr
|= BMCR_ANENABLE
;
4466 /* reset the phy in order for settings to stick*/
4467 if (phy_reset(dev
, bmcr
)) {
4468 netdev_info(dev
, "phy reset failed\n");
4472 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4473 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4476 if (netif_running(dev
)) {
4488 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4490 struct fe_priv
*np
= netdev_priv(dev
);
4492 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4493 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4495 ring
->rx_pending
= np
->rx_ring_size
;
4496 ring
->tx_pending
= np
->tx_ring_size
;
4499 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4501 struct fe_priv
*np
= netdev_priv(dev
);
4502 u8 __iomem
*base
= get_hwbase(dev
);
4503 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4504 dma_addr_t ring_addr
;
4506 if (ring
->rx_pending
< RX_RING_MIN
||
4507 ring
->tx_pending
< TX_RING_MIN
||
4508 ring
->rx_mini_pending
!= 0 ||
4509 ring
->rx_jumbo_pending
!= 0 ||
4510 (np
->desc_ver
== DESC_VER_1
&&
4511 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4512 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4513 (np
->desc_ver
!= DESC_VER_1
&&
4514 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4515 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4519 /* allocate new rings */
4520 if (!nv_optimized(np
)) {
4521 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4522 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4525 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4526 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4529 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4530 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4531 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4532 /* fall back to old rings */
4533 if (!nv_optimized(np
)) {
4535 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4536 rxtx_ring
, ring_addr
);
4539 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4540 rxtx_ring
, ring_addr
);
4548 if (netif_running(dev
)) {
4549 nv_disable_irq(dev
);
4550 nv_napi_disable(dev
);
4551 netif_tx_lock_bh(dev
);
4552 netif_addr_lock(dev
);
4553 spin_lock(&np
->lock
);
4563 /* set new values */
4564 np
->rx_ring_size
= ring
->rx_pending
;
4565 np
->tx_ring_size
= ring
->tx_pending
;
4567 if (!nv_optimized(np
)) {
4568 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4569 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4571 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4572 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4574 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4575 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4576 np
->ring_addr
= ring_addr
;
4578 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4579 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4581 if (netif_running(dev
)) {
4582 /* reinit driver view of the queues */
4584 if (nv_init_ring(dev
)) {
4585 if (!np
->in_shutdown
)
4586 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4589 /* reinit nic view of the queues */
4590 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4591 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4592 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4593 base
+ NvRegRingSizes
);
4595 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4598 /* restart engines */
4600 spin_unlock(&np
->lock
);
4601 netif_addr_unlock(dev
);
4602 netif_tx_unlock_bh(dev
);
4603 nv_napi_enable(dev
);
4611 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4613 struct fe_priv
*np
= netdev_priv(dev
);
4615 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4616 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4617 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4620 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4622 struct fe_priv
*np
= netdev_priv(dev
);
4625 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4626 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4627 netdev_info(dev
, "can not set pause settings when forced link is in half duplex\n");
4630 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4631 netdev_info(dev
, "hardware does not support tx pause frames\n");
4635 netif_carrier_off(dev
);
4636 if (netif_running(dev
)) {
4637 nv_disable_irq(dev
);
4638 netif_tx_lock_bh(dev
);
4639 netif_addr_lock(dev
);
4640 spin_lock(&np
->lock
);
4643 spin_unlock(&np
->lock
);
4644 netif_addr_unlock(dev
);
4645 netif_tx_unlock_bh(dev
);
4648 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4649 if (pause
->rx_pause
)
4650 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4651 if (pause
->tx_pause
)
4652 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4654 if (np
->autoneg
&& pause
->autoneg
) {
4655 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4657 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4658 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4659 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisements but disable tx pause */
4660 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4661 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4662 adv
|= ADVERTISE_PAUSE_ASYM
;
4663 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4665 if (netif_running(dev
))
4666 netdev_info(dev
, "link down\n");
4667 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4668 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4669 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4671 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4672 if (pause
->rx_pause
)
4673 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4674 if (pause
->tx_pause
)
4675 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4677 if (!netif_running(dev
))
4678 nv_update_linkspeed(dev
);
4680 nv_update_pause(dev
, np
->pause_flags
);
4683 if (netif_running(dev
)) {
4690 static int nv_set_loopback(struct net_device
*dev
, netdev_features_t features
)
4692 struct fe_priv
*np
= netdev_priv(dev
);
4693 unsigned long flags
;
4695 int err
, retval
= 0;
4697 spin_lock_irqsave(&np
->lock
, flags
);
4698 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4699 if (features
& NETIF_F_LOOPBACK
) {
4700 if (miicontrol
& BMCR_LOOPBACK
) {
4701 spin_unlock_irqrestore(&np
->lock
, flags
);
4702 netdev_info(dev
, "Loopback already enabled\n");
4705 nv_disable_irq(dev
);
4706 /* Turn on loopback mode */
4707 miicontrol
|= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
4708 err
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
);
4711 spin_unlock_irqrestore(&np
->lock
, flags
);
4714 if (netif_running(dev
)) {
4715 /* Force 1000 Mbps full-duplex */
4716 nv_force_linkspeed(dev
, NVREG_LINKSPEED_1000
,
4719 netif_carrier_on(dev
);
4721 spin_unlock_irqrestore(&np
->lock
, flags
);
4723 "Internal PHY loopback mode enabled.\n");
4726 if (!(miicontrol
& BMCR_LOOPBACK
)) {
4727 spin_unlock_irqrestore(&np
->lock
, flags
);
4728 netdev_info(dev
, "Loopback already disabled\n");
4731 nv_disable_irq(dev
);
4732 /* Turn off loopback */
4733 spin_unlock_irqrestore(&np
->lock
, flags
);
4734 netdev_info(dev
, "Internal PHY loopback mode disabled.\n");
4738 spin_lock_irqsave(&np
->lock
, flags
);
4740 spin_unlock_irqrestore(&np
->lock
, flags
);
4745 static netdev_features_t
nv_fix_features(struct net_device
*dev
,
4746 netdev_features_t features
)
4748 /* vlan is dependent on rx checksum offload */
4749 if (features
& (NETIF_F_HW_VLAN_TX
|NETIF_F_HW_VLAN_RX
))
4750 features
|= NETIF_F_RXCSUM
;
4755 static void nv_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
4757 struct fe_priv
*np
= get_nvpriv(dev
);
4759 spin_lock_irq(&np
->lock
);
4761 if (features
& NETIF_F_HW_VLAN_RX
)
4762 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
;
4764 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
4766 if (features
& NETIF_F_HW_VLAN_TX
)
4767 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANINS
;
4769 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
4771 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4773 spin_unlock_irq(&np
->lock
);
4776 static int nv_set_features(struct net_device
*dev
, netdev_features_t features
)
4778 struct fe_priv
*np
= netdev_priv(dev
);
4779 u8 __iomem
*base
= get_hwbase(dev
);
4780 netdev_features_t changed
= dev
->features
^ features
;
4783 if ((changed
& NETIF_F_LOOPBACK
) && netif_running(dev
)) {
4784 retval
= nv_set_loopback(dev
, features
);
4789 if (changed
& NETIF_F_RXCSUM
) {
4790 spin_lock_irq(&np
->lock
);
4792 if (features
& NETIF_F_RXCSUM
)
4793 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4795 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4797 if (netif_running(dev
))
4798 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4800 spin_unlock_irq(&np
->lock
);
4803 if (changed
& (NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
))
4804 nv_vlan_mode(dev
, features
);
4809 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4811 struct fe_priv
*np
= netdev_priv(dev
);
4815 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4816 return NV_TEST_COUNT_EXTENDED
;
4818 return NV_TEST_COUNT_BASE
;
4820 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
)
4821 return NV_DEV_STATISTICS_V3_COUNT
;
4822 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4823 return NV_DEV_STATISTICS_V2_COUNT
;
4824 else if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4825 return NV_DEV_STATISTICS_V1_COUNT
;
4833 static void nv_get_ethtool_stats(struct net_device
*dev
,
4834 struct ethtool_stats
*estats
, u64
*buffer
)
4835 __acquires(&netdev_priv(dev
)->hwstats_lock
)
4836 __releases(&netdev_priv(dev
)->hwstats_lock
)
4838 struct fe_priv
*np
= netdev_priv(dev
);
4840 spin_lock_bh(&np
->hwstats_lock
);
4841 nv_update_stats(dev
);
4842 memcpy(buffer
, &np
->estats
,
4843 nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4844 spin_unlock_bh(&np
->hwstats_lock
);
4847 static int nv_link_test(struct net_device
*dev
)
4849 struct fe_priv
*np
= netdev_priv(dev
);
4852 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4853 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4855 /* check phy link status */
4856 if (!(mii_status
& BMSR_LSTATUS
))
4862 static int nv_register_test(struct net_device
*dev
)
4864 u8 __iomem
*base
= get_hwbase(dev
);
4866 u32 orig_read
, new_read
;
4869 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4871 /* xor with mask to toggle bits */
4872 orig_read
^= nv_registers_test
[i
].mask
;
4874 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4876 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4878 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4881 /* restore original value */
4882 orig_read
^= nv_registers_test
[i
].mask
;
4883 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4885 } while (nv_registers_test
[++i
].reg
!= 0);
4890 static int nv_interrupt_test(struct net_device
*dev
)
4892 struct fe_priv
*np
= netdev_priv(dev
);
4893 u8 __iomem
*base
= get_hwbase(dev
);
4896 u32 save_msi_flags
, save_poll_interval
= 0;
4898 if (netif_running(dev
)) {
4899 /* free current irq */
4901 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4904 /* flag to test interrupt handler */
4907 /* setup test irq */
4908 save_msi_flags
= np
->msi_flags
;
4909 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4910 np
->msi_flags
|= 0x001; /* setup 1 vector */
4911 if (nv_request_irq(dev
, 1))
4914 /* setup timer interrupt */
4915 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4916 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4918 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4920 /* wait for at least one interrupt */
4923 spin_lock_irq(&np
->lock
);
4925 /* flag should be set within ISR */
4926 testcnt
= np
->intr_test
;
4930 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4931 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4932 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4934 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4936 spin_unlock_irq(&np
->lock
);
4940 np
->msi_flags
= save_msi_flags
;
4942 if (netif_running(dev
)) {
4943 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4944 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4945 /* restore original irq */
4946 if (nv_request_irq(dev
, 0))
4953 static int nv_loopback_test(struct net_device
*dev
)
4955 struct fe_priv
*np
= netdev_priv(dev
);
4956 u8 __iomem
*base
= get_hwbase(dev
);
4957 struct sk_buff
*tx_skb
, *rx_skb
;
4958 dma_addr_t test_dma_addr
;
4959 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
4961 int len
, i
, pkt_len
;
4963 u32 filter_flags
= 0;
4964 u32 misc1_flags
= 0;
4967 if (netif_running(dev
)) {
4968 nv_disable_irq(dev
);
4969 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
4970 misc1_flags
= readl(base
+ NvRegMisc1
);
4975 /* reinit driver view of the rx queue */
4979 /* setup hardware for loopback */
4980 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
4981 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
4983 /* reinit nic view of the rx queue */
4984 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4985 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4986 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4987 base
+ NvRegRingSizes
);
4990 /* restart rx engine */
4993 /* setup packet for tx */
4994 pkt_len
= ETH_DATA_LEN
;
4995 tx_skb
= netdev_alloc_skb(dev
, pkt_len
);
4997 netdev_err(dev
, "netdev_alloc_skb() failed during loopback test\n");
5001 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
5002 skb_tailroom(tx_skb
),
5003 PCI_DMA_FROMDEVICE
);
5004 pkt_data
= skb_put(tx_skb
, pkt_len
);
5005 for (i
= 0; i
< pkt_len
; i
++)
5006 pkt_data
[i
] = (u8
)(i
& 0xff);
5008 if (!nv_optimized(np
)) {
5009 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
5010 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5012 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
5013 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
5014 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5016 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5017 pci_push(get_hwbase(dev
));
5021 /* check for rx of the packet */
5022 if (!nv_optimized(np
)) {
5023 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
5024 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
5027 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
5028 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
5031 if (flags
& NV_RX_AVAIL
) {
5033 } else if (np
->desc_ver
== DESC_VER_1
) {
5034 if (flags
& NV_RX_ERROR
)
5037 if (flags
& NV_RX2_ERROR
)
5042 if (len
!= pkt_len
) {
5045 rx_skb
= np
->rx_skb
[0].skb
;
5046 for (i
= 0; i
< pkt_len
; i
++) {
5047 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
5055 pci_unmap_single(np
->pci_dev
, test_dma_addr
,
5056 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
5058 dev_kfree_skb_any(tx_skb
);
5063 /* drain rx queue */
5066 if (netif_running(dev
)) {
5067 writel(misc1_flags
, base
+ NvRegMisc1
);
5068 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
5075 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
5077 struct fe_priv
*np
= netdev_priv(dev
);
5078 u8 __iomem
*base
= get_hwbase(dev
);
5080 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
5082 if (!nv_link_test(dev
)) {
5083 test
->flags
|= ETH_TEST_FL_FAILED
;
5087 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
5088 if (netif_running(dev
)) {
5089 netif_stop_queue(dev
);
5090 nv_napi_disable(dev
);
5091 netif_tx_lock_bh(dev
);
5092 netif_addr_lock(dev
);
5093 spin_lock_irq(&np
->lock
);
5094 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5095 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
5096 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5098 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5102 /* drain rx queue */
5104 spin_unlock_irq(&np
->lock
);
5105 netif_addr_unlock(dev
);
5106 netif_tx_unlock_bh(dev
);
5109 if (!nv_register_test(dev
)) {
5110 test
->flags
|= ETH_TEST_FL_FAILED
;
5114 result
= nv_interrupt_test(dev
);
5116 test
->flags
|= ETH_TEST_FL_FAILED
;
5124 if (!nv_loopback_test(dev
)) {
5125 test
->flags
|= ETH_TEST_FL_FAILED
;
5129 if (netif_running(dev
)) {
5130 /* reinit driver view of the rx queue */
5132 if (nv_init_ring(dev
)) {
5133 if (!np
->in_shutdown
)
5134 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5136 /* reinit nic view of the rx queue */
5137 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5138 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5139 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5140 base
+ NvRegRingSizes
);
5142 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5144 /* restart rx engine */
5146 netif_start_queue(dev
);
5147 nv_napi_enable(dev
);
5148 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5153 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5155 switch (stringset
) {
5157 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5160 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5165 static const struct ethtool_ops ops
= {
5166 .get_drvinfo
= nv_get_drvinfo
,
5167 .get_link
= ethtool_op_get_link
,
5168 .get_wol
= nv_get_wol
,
5169 .set_wol
= nv_set_wol
,
5170 .get_settings
= nv_get_settings
,
5171 .set_settings
= nv_set_settings
,
5172 .get_regs_len
= nv_get_regs_len
,
5173 .get_regs
= nv_get_regs
,
5174 .nway_reset
= nv_nway_reset
,
5175 .get_ringparam
= nv_get_ringparam
,
5176 .set_ringparam
= nv_set_ringparam
,
5177 .get_pauseparam
= nv_get_pauseparam
,
5178 .set_pauseparam
= nv_set_pauseparam
,
5179 .get_strings
= nv_get_strings
,
5180 .get_ethtool_stats
= nv_get_ethtool_stats
,
5181 .get_sset_count
= nv_get_sset_count
,
5182 .self_test
= nv_self_test
,
5185 /* The mgmt unit and driver use a semaphore to access the phy during init */
5186 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5188 struct fe_priv
*np
= netdev_priv(dev
);
5189 u8 __iomem
*base
= get_hwbase(dev
);
5191 u32 tx_ctrl
, mgmt_sema
;
5193 for (i
= 0; i
< 10; i
++) {
5194 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5195 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5200 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5203 for (i
= 0; i
< 2; i
++) {
5204 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5205 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5206 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5208 /* verify that semaphore was acquired */
5209 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5210 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5211 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
)) {
5221 static void nv_mgmt_release_sema(struct net_device
*dev
)
5223 struct fe_priv
*np
= netdev_priv(dev
);
5224 u8 __iomem
*base
= get_hwbase(dev
);
5227 if (np
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5228 if (np
->mgmt_sema
) {
5229 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5230 tx_ctrl
&= ~NVREG_XMITCTL_HOST_SEMA_ACQ
;
5231 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5237 static int nv_mgmt_get_version(struct net_device
*dev
)
5239 struct fe_priv
*np
= netdev_priv(dev
);
5240 u8 __iomem
*base
= get_hwbase(dev
);
5241 u32 data_ready
= readl(base
+ NvRegTransmitterControl
);
5242 u32 data_ready2
= 0;
5243 unsigned long start
;
5246 writel(NVREG_MGMTUNITGETVERSION
, base
+ NvRegMgmtUnitGetVersion
);
5247 writel(data_ready
^ NVREG_XMITCTL_DATA_START
, base
+ NvRegTransmitterControl
);
5249 while (time_before(jiffies
, start
+ 5*HZ
)) {
5250 data_ready2
= readl(base
+ NvRegTransmitterControl
);
5251 if ((data_ready
& NVREG_XMITCTL_DATA_READY
) != (data_ready2
& NVREG_XMITCTL_DATA_READY
)) {
5255 schedule_timeout_uninterruptible(1);
5258 if (!ready
|| (data_ready2
& NVREG_XMITCTL_DATA_ERROR
))
5261 np
->mgmt_version
= readl(base
+ NvRegMgmtUnitVersion
) & NVREG_MGMTUNITVERSION
;
5266 static int nv_open(struct net_device
*dev
)
5268 struct fe_priv
*np
= netdev_priv(dev
);
5269 u8 __iomem
*base
= get_hwbase(dev
);
5275 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5276 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
) & ~BMCR_PDOWN
);
5278 nv_txrx_gate(dev
, false);
5279 /* erase previous misconfiguration */
5280 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5282 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5283 writel(0, base
+ NvRegMulticastAddrB
);
5284 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5285 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5286 writel(0, base
+ NvRegPacketFilterFlags
);
5288 writel(0, base
+ NvRegTransmitterControl
);
5289 writel(0, base
+ NvRegReceiverControl
);
5291 writel(0, base
+ NvRegAdapterControl
);
5293 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5294 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5296 /* initialize descriptor rings */
5298 oom
= nv_init_ring(dev
);
5300 writel(0, base
+ NvRegLinkSpeed
);
5301 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5303 writel(0, base
+ NvRegUnknownSetupReg6
);
5305 np
->in_shutdown
= 0;
5308 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5309 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5310 base
+ NvRegRingSizes
);
5312 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5313 if (np
->desc_ver
== DESC_VER_1
)
5314 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5316 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5317 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5318 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5320 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5321 if (reg_delay(dev
, NvRegUnknownSetupReg5
,
5322 NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5323 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
))
5325 "%s: SetupReg5, Bit 31 remained off\n", __func__
);
5327 writel(0, base
+ NvRegMIIMask
);
5328 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5329 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5331 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5332 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5333 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5334 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5336 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5338 get_random_bytes(&low
, sizeof(low
));
5339 low
&= NVREG_SLOTTIME_MASK
;
5340 if (np
->desc_ver
== DESC_VER_1
) {
5341 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5343 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5344 /* setup legacy backoff */
5345 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5347 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5348 nv_gear_backoff_reseed(dev
);
5351 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5352 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5353 if (poll_interval
== -1) {
5354 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5355 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5357 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5359 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5360 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5361 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5362 base
+ NvRegAdapterControl
);
5363 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5364 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5366 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5368 i
= readl(base
+ NvRegPowerState
);
5369 if ((i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5370 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5374 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5376 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5378 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5379 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5382 if (nv_request_irq(dev
, 0))
5385 /* ask for interrupts */
5386 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5388 spin_lock_irq(&np
->lock
);
5389 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5390 writel(0, base
+ NvRegMulticastAddrB
);
5391 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5392 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5393 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5394 /* One manual link speed update: Interrupts are enabled, future link
5395 * speed changes cause interrupts and are handled by nv_link_irq().
5399 miistat
= readl(base
+ NvRegMIIStatus
);
5400 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5402 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5405 ret
= nv_update_linkspeed(dev
);
5407 netif_start_queue(dev
);
5408 nv_napi_enable(dev
);
5411 netif_carrier_on(dev
);
5413 netdev_info(dev
, "no link during initialization\n");
5414 netif_carrier_off(dev
);
5417 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5419 /* start statistics timer */
5420 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5421 mod_timer(&np
->stats_poll
,
5422 round_jiffies(jiffies
+ STATS_INTERVAL
));
5424 spin_unlock_irq(&np
->lock
);
5426 /* If the loopback feature was set while the device was down, make sure
5427 * that it's set correctly now.
5429 if (dev
->features
& NETIF_F_LOOPBACK
)
5430 nv_set_loopback(dev
, dev
->features
);
5438 static int nv_close(struct net_device
*dev
)
5440 struct fe_priv
*np
= netdev_priv(dev
);
5443 spin_lock_irq(&np
->lock
);
5444 np
->in_shutdown
= 1;
5445 spin_unlock_irq(&np
->lock
);
5446 nv_napi_disable(dev
);
5447 synchronize_irq(np
->pci_dev
->irq
);
5449 del_timer_sync(&np
->oom_kick
);
5450 del_timer_sync(&np
->nic_poll
);
5451 del_timer_sync(&np
->stats_poll
);
5453 netif_stop_queue(dev
);
5454 spin_lock_irq(&np
->lock
);
5458 /* disable interrupts on the nic or we will lock up */
5459 base
= get_hwbase(dev
);
5460 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5463 spin_unlock_irq(&np
->lock
);
5469 if (np
->wolenabled
|| !phy_power_down
) {
5470 nv_txrx_gate(dev
, false);
5471 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5474 /* power down phy */
5475 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5476 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
)|BMCR_PDOWN
);
5477 nv_txrx_gate(dev
, true);
5480 /* FIXME: power down nic */
5485 static const struct net_device_ops nv_netdev_ops
= {
5486 .ndo_open
= nv_open
,
5487 .ndo_stop
= nv_close
,
5488 .ndo_get_stats64
= nv_get_stats64
,
5489 .ndo_start_xmit
= nv_start_xmit
,
5490 .ndo_tx_timeout
= nv_tx_timeout
,
5491 .ndo_change_mtu
= nv_change_mtu
,
5492 .ndo_fix_features
= nv_fix_features
,
5493 .ndo_set_features
= nv_set_features
,
5494 .ndo_validate_addr
= eth_validate_addr
,
5495 .ndo_set_mac_address
= nv_set_mac_address
,
5496 .ndo_set_rx_mode
= nv_set_multicast
,
5497 #ifdef CONFIG_NET_POLL_CONTROLLER
5498 .ndo_poll_controller
= nv_poll_controller
,
5502 static const struct net_device_ops nv_netdev_ops_optimized
= {
5503 .ndo_open
= nv_open
,
5504 .ndo_stop
= nv_close
,
5505 .ndo_get_stats64
= nv_get_stats64
,
5506 .ndo_start_xmit
= nv_start_xmit_optimized
,
5507 .ndo_tx_timeout
= nv_tx_timeout
,
5508 .ndo_change_mtu
= nv_change_mtu
,
5509 .ndo_fix_features
= nv_fix_features
,
5510 .ndo_set_features
= nv_set_features
,
5511 .ndo_validate_addr
= eth_validate_addr
,
5512 .ndo_set_mac_address
= nv_set_mac_address
,
5513 .ndo_set_rx_mode
= nv_set_multicast
,
5514 #ifdef CONFIG_NET_POLL_CONTROLLER
5515 .ndo_poll_controller
= nv_poll_controller
,
5519 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5521 struct net_device
*dev
;
5526 u32 powerstate
, txreg
;
5527 u32 phystate_orig
= 0, phystate
;
5528 int phyinitialized
= 0;
5529 static int printed_version
;
5531 if (!printed_version
++)
5532 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5535 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5540 np
= netdev_priv(dev
);
5542 np
->pci_dev
= pci_dev
;
5543 spin_lock_init(&np
->lock
);
5544 spin_lock_init(&np
->hwstats_lock
);
5545 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5547 init_timer(&np
->oom_kick
);
5548 np
->oom_kick
.data
= (unsigned long) dev
;
5549 np
->oom_kick
.function
= nv_do_rx_refill
; /* timer handler */
5550 init_timer(&np
->nic_poll
);
5551 np
->nic_poll
.data
= (unsigned long) dev
;
5552 np
->nic_poll
.function
= nv_do_nic_poll
; /* timer handler */
5553 init_timer_deferrable(&np
->stats_poll
);
5554 np
->stats_poll
.data
= (unsigned long) dev
;
5555 np
->stats_poll
.function
= nv_do_stats_poll
; /* timer handler */
5557 err
= pci_enable_device(pci_dev
);
5561 pci_set_master(pci_dev
);
5563 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5567 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5568 np
->register_size
= NV_PCI_REGSZ_VER3
;
5569 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5570 np
->register_size
= NV_PCI_REGSZ_VER2
;
5572 np
->register_size
= NV_PCI_REGSZ_VER1
;
5576 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5577 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5578 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5579 addr
= pci_resource_start(pci_dev
, i
);
5583 if (i
== DEVICE_COUNT_RESOURCE
) {
5584 dev_info(&pci_dev
->dev
, "Couldn't find register window\n");
5588 /* copy of driver data */
5589 np
->driver_data
= id
->driver_data
;
5590 /* copy of device id */
5591 np
->device_id
= id
->device
;
5593 /* handle different descriptor versions */
5594 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5595 /* packet format 3: supports 40-bit addressing */
5596 np
->desc_ver
= DESC_VER_3
;
5597 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5599 if (pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(39)))
5600 dev_info(&pci_dev
->dev
,
5601 "64-bit DMA failed, using 32-bit addressing\n");
5603 dev
->features
|= NETIF_F_HIGHDMA
;
5604 if (pci_set_consistent_dma_mask(pci_dev
, DMA_BIT_MASK(39))) {
5605 dev_info(&pci_dev
->dev
,
5606 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5609 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5610 /* packet format 2: supports jumbo frames */
5611 np
->desc_ver
= DESC_VER_2
;
5612 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5614 /* original packet format */
5615 np
->desc_ver
= DESC_VER_1
;
5616 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5619 np
->pkt_limit
= NV_PKTLIMIT_1
;
5620 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5621 np
->pkt_limit
= NV_PKTLIMIT_2
;
5623 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5624 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5625 dev
->hw_features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
5626 NETIF_F_TSO
| NETIF_F_RXCSUM
;
5629 np
->vlanctl_bits
= 0;
5630 if (id
->driver_data
& DEV_HAS_VLAN
) {
5631 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5632 dev
->hw_features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5635 dev
->features
|= dev
->hw_features
;
5637 /* Add loopback capability to the device. */
5638 dev
->hw_features
|= NETIF_F_LOOPBACK
;
5640 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5641 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5642 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5643 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5644 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5648 np
->base
= ioremap(addr
, np
->register_size
);
5652 np
->rx_ring_size
= RX_RING_DEFAULT
;
5653 np
->tx_ring_size
= TX_RING_DEFAULT
;
5655 if (!nv_optimized(np
)) {
5656 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5657 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5659 if (!np
->rx_ring
.orig
)
5661 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5663 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5664 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5666 if (!np
->rx_ring
.ex
)
5668 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5670 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5671 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5672 if (!np
->rx_skb
|| !np
->tx_skb
)
5675 if (!nv_optimized(np
))
5676 dev
->netdev_ops
= &nv_netdev_ops
;
5678 dev
->netdev_ops
= &nv_netdev_ops_optimized
;
5680 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5681 SET_ETHTOOL_OPS(dev
, &ops
);
5682 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5684 pci_set_drvdata(pci_dev
, dev
);
5686 /* read the mac address */
5687 base
= get_hwbase(dev
);
5688 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5689 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5691 /* check the workaround bit for correct mac address order */
5692 txreg
= readl(base
+ NvRegTransmitPoll
);
5693 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5694 /* mac address is already in correct order */
5695 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5696 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5697 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5698 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5699 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5700 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5701 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5702 /* mac address is already in correct order */
5703 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5704 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5705 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5706 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5707 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5708 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5710 * Set orig mac address back to the reversed version.
5711 * This flag will be cleared during low power transition.
5712 * Therefore, we should always put back the reversed address.
5714 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5715 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5716 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5718 /* need to reverse mac address to correct order */
5719 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5720 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5721 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5722 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5723 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5724 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5725 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5726 dev_dbg(&pci_dev
->dev
,
5727 "%s: set workaround bit for reversed mac addr\n",
5730 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5732 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5734 * Bad mac address. At least one bios sets the mac address
5735 * to 01:23:45:67:89:ab
5737 dev_err(&pci_dev
->dev
,
5738 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5740 eth_hw_addr_random(dev
);
5741 dev_err(&pci_dev
->dev
,
5742 "Using random MAC address: %pM\n", dev
->dev_addr
);
5745 /* set mac address */
5746 nv_copy_mac_to_hw(dev
);
5749 writel(0, base
+ NvRegWakeUpFlags
);
5751 device_set_wakeup_enable(&pci_dev
->dev
, false);
5753 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5755 /* take phy and nic out of low power mode */
5756 powerstate
= readl(base
+ NvRegPowerState2
);
5757 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5758 if ((id
->driver_data
& DEV_NEED_LOW_POWER_FIX
) &&
5759 pci_dev
->revision
>= 0xA3)
5760 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5761 writel(powerstate
, base
+ NvRegPowerState2
);
5764 if (np
->desc_ver
== DESC_VER_1
)
5765 np
->tx_flags
= NV_TX_VALID
;
5767 np
->tx_flags
= NV_TX2_VALID
;
5770 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
)
5771 np
->msi_flags
|= NV_MSI_CAPABLE
;
5773 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5774 /* msix has had reported issues when modifying irqmask
5775 as in the case of napi, therefore, disable for now
5778 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5782 if (optimization_mode
== NV_OPTIMIZATION_MODE_CPU
) {
5783 np
->irqmask
= NVREG_IRQMASK_CPU
;
5784 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5785 np
->msi_flags
|= 0x0001;
5786 } else if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
&&
5787 !(id
->driver_data
& DEV_NEED_TIMERIRQ
)) {
5788 /* start off in throughput mode */
5789 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5790 /* remove support for msix mode */
5791 np
->msi_flags
&= ~NV_MSI_X_CAPABLE
;
5793 optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
5794 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5795 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5796 np
->msi_flags
|= 0x0003;
5799 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5800 np
->irqmask
|= NVREG_IRQ_TIMER
;
5801 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5802 np
->need_linktimer
= 1;
5803 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5805 np
->need_linktimer
= 0;
5808 /* Limit the number of tx's outstanding for hw bug */
5809 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5811 if (((id
->driver_data
& DEV_NEED_TX_LIMIT2
) == DEV_NEED_TX_LIMIT2
) &&
5812 pci_dev
->revision
>= 0xA2)
5816 /* clear phy state and temporarily halt phy interrupts */
5817 writel(0, base
+ NvRegMIIMask
);
5818 phystate
= readl(base
+ NvRegAdapterControl
);
5819 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5821 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5822 writel(phystate
, base
+ NvRegAdapterControl
);
5824 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5826 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5827 /* management unit running on the mac? */
5828 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
) &&
5829 (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) &&
5830 nv_mgmt_acquire_sema(dev
) &&
5831 nv_mgmt_get_version(dev
)) {
5833 if (np
->mgmt_version
> 0)
5834 np
->mac_in_use
= readl(base
+ NvRegMgmtUnitControl
) & NVREG_MGMTUNITCONTROL_INUSE
;
5835 /* management unit setup the phy already? */
5836 if (np
->mac_in_use
&&
5837 ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5838 NVREG_XMITCTL_SYNC_PHY_INIT
)) {
5839 /* phy is inited by mgmt unit */
5842 /* we need to init the phy */
5847 /* find a suitable phy */
5848 for (i
= 1; i
<= 32; i
++) {
5850 int phyaddr
= i
& 0x1F;
5852 spin_lock_irq(&np
->lock
);
5853 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5854 spin_unlock_irq(&np
->lock
);
5855 if (id1
< 0 || id1
== 0xffff)
5857 spin_lock_irq(&np
->lock
);
5858 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5859 spin_unlock_irq(&np
->lock
);
5860 if (id2
< 0 || id2
== 0xffff)
5863 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5864 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5865 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5866 np
->phyaddr
= phyaddr
;
5867 np
->phy_oui
= id1
| id2
;
5869 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5870 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5871 np
->phy_oui
= PHY_OUI_REALTEK
;
5872 /* Setup phy revision for Realtek */
5873 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5874 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5879 dev_info(&pci_dev
->dev
, "open: Could not find a valid PHY\n");
5883 if (!phyinitialized
) {
5887 /* see if it is a gigabit phy */
5888 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5889 if (mii_status
& PHY_GIGABIT
)
5890 np
->gigabit
= PHY_GIGABIT
;
5893 /* set default link speed settings */
5894 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
5898 err
= register_netdev(dev
);
5900 dev_info(&pci_dev
->dev
, "unable to register netdev: %d\n", err
);
5904 if (id
->driver_data
& DEV_HAS_VLAN
)
5905 nv_vlan_mode(dev
, dev
->features
);
5907 netif_carrier_off(dev
);
5909 dev_info(&pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5910 dev
->name
, np
->phy_oui
, np
->phyaddr
, dev
->dev_addr
);
5912 dev_info(&pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5913 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
5914 dev
->features
& (NETIF_F_IP_CSUM
| NETIF_F_SG
) ?
5916 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
5918 dev
->features
& (NETIF_F_LOOPBACK
) ?
5920 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
5921 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
5922 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
5923 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
5924 np
->need_linktimer
? "lnktim " : "",
5925 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
5926 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
5933 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
5934 pci_set_drvdata(pci_dev
, NULL
);
5938 iounmap(get_hwbase(dev
));
5940 pci_release_regions(pci_dev
);
5942 pci_disable_device(pci_dev
);
5949 static void nv_restore_phy(struct net_device
*dev
)
5951 struct fe_priv
*np
= netdev_priv(dev
);
5952 u16 phy_reserved
, mii_control
;
5954 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
5955 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
5956 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
5957 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
5958 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
5959 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
5960 phy_reserved
|= PHY_REALTEK_INIT8
;
5961 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
5962 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
5964 /* restart auto negotiation */
5965 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
5966 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
5967 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
5971 static void nv_restore_mac_addr(struct pci_dev
*pci_dev
)
5973 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
5974 struct fe_priv
*np
= netdev_priv(dev
);
5975 u8 __iomem
*base
= get_hwbase(dev
);
5977 /* special op: write back the misordered MAC address - otherwise
5978 * the next nv_probe would see a wrong address.
5980 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
5981 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
5982 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
5983 base
+ NvRegTransmitPoll
);
5986 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
5988 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
5990 unregister_netdev(dev
);
5992 nv_restore_mac_addr(pci_dev
);
5994 /* restore any phy related changes */
5995 nv_restore_phy(dev
);
5997 nv_mgmt_release_sema(dev
);
5999 /* free all structures */
6001 iounmap(get_hwbase(dev
));
6002 pci_release_regions(pci_dev
);
6003 pci_disable_device(pci_dev
);
6005 pci_set_drvdata(pci_dev
, NULL
);
6008 #ifdef CONFIG_PM_SLEEP
6009 static int nv_suspend(struct device
*device
)
6011 struct pci_dev
*pdev
= to_pci_dev(device
);
6012 struct net_device
*dev
= pci_get_drvdata(pdev
);
6013 struct fe_priv
*np
= netdev_priv(dev
);
6014 u8 __iomem
*base
= get_hwbase(dev
);
6017 if (netif_running(dev
)) {
6021 netif_device_detach(dev
);
6023 /* save non-pci configuration space */
6024 for (i
= 0; i
<= np
->register_size
/sizeof(u32
); i
++)
6025 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
6030 static int nv_resume(struct device
*device
)
6032 struct pci_dev
*pdev
= to_pci_dev(device
);
6033 struct net_device
*dev
= pci_get_drvdata(pdev
);
6034 struct fe_priv
*np
= netdev_priv(dev
);
6035 u8 __iomem
*base
= get_hwbase(dev
);
6038 /* restore non-pci configuration space */
6039 for (i
= 0; i
<= np
->register_size
/sizeof(u32
); i
++)
6040 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
6042 if (np
->driver_data
& DEV_NEED_MSI_FIX
)
6043 pci_write_config_dword(pdev
, NV_MSI_PRIV_OFFSET
, NV_MSI_PRIV_VALUE
);
6045 /* restore phy state, including autoneg */
6048 netif_device_attach(dev
);
6049 if (netif_running(dev
)) {
6051 nv_set_multicast(dev
);
6056 static SIMPLE_DEV_PM_OPS(nv_pm_ops
, nv_suspend
, nv_resume
);
6057 #define NV_PM_OPS (&nv_pm_ops)
6060 #define NV_PM_OPS NULL
6061 #endif /* CONFIG_PM_SLEEP */
6064 static void nv_shutdown(struct pci_dev
*pdev
)
6066 struct net_device
*dev
= pci_get_drvdata(pdev
);
6067 struct fe_priv
*np
= netdev_priv(dev
);
6069 if (netif_running(dev
))
6073 * Restore the MAC so a kernel started by kexec won't get confused.
6074 * If we really go for poweroff, we must not restore the MAC,
6075 * otherwise the MAC for WOL will be reversed at least on some boards.
6077 if (system_state
!= SYSTEM_POWER_OFF
)
6078 nv_restore_mac_addr(pdev
);
6080 pci_disable_device(pdev
);
6082 * Apparently it is not possible to reinitialise from D3 hot,
6083 * only put the device into D3 if we really go for poweroff.
6085 if (system_state
== SYSTEM_POWER_OFF
) {
6086 pci_wake_from_d3(pdev
, np
->wolenabled
);
6087 pci_set_power_state(pdev
, PCI_D3hot
);
6091 #define nv_shutdown NULL
6092 #endif /* CONFIG_PM */
6094 static DEFINE_PCI_DEVICE_TABLE(pci_tbl
) = {
6095 { /* nForce Ethernet Controller */
6096 PCI_DEVICE(0x10DE, 0x01C3),
6097 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6099 { /* nForce2 Ethernet Controller */
6100 PCI_DEVICE(0x10DE, 0x0066),
6101 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6103 { /* nForce3 Ethernet Controller */
6104 PCI_DEVICE(0x10DE, 0x00D6),
6105 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6107 { /* nForce3 Ethernet Controller */
6108 PCI_DEVICE(0x10DE, 0x0086),
6109 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6111 { /* nForce3 Ethernet Controller */
6112 PCI_DEVICE(0x10DE, 0x008C),
6113 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6115 { /* nForce3 Ethernet Controller */
6116 PCI_DEVICE(0x10DE, 0x00E6),
6117 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6119 { /* nForce3 Ethernet Controller */
6120 PCI_DEVICE(0x10DE, 0x00DF),
6121 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6123 { /* CK804 Ethernet Controller */
6124 PCI_DEVICE(0x10DE, 0x0056),
6125 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6127 { /* CK804 Ethernet Controller */
6128 PCI_DEVICE(0x10DE, 0x0057),
6129 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6131 { /* MCP04 Ethernet Controller */
6132 PCI_DEVICE(0x10DE, 0x0037),
6133 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6135 { /* MCP04 Ethernet Controller */
6136 PCI_DEVICE(0x10DE, 0x0038),
6137 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6139 { /* MCP51 Ethernet Controller */
6140 PCI_DEVICE(0x10DE, 0x0268),
6141 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6143 { /* MCP51 Ethernet Controller */
6144 PCI_DEVICE(0x10DE, 0x0269),
6145 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6147 { /* MCP55 Ethernet Controller */
6148 PCI_DEVICE(0x10DE, 0x0372),
6149 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6151 { /* MCP55 Ethernet Controller */
6152 PCI_DEVICE(0x10DE, 0x0373),
6153 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6155 { /* MCP61 Ethernet Controller */
6156 PCI_DEVICE(0x10DE, 0x03E5),
6157 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6159 { /* MCP61 Ethernet Controller */
6160 PCI_DEVICE(0x10DE, 0x03E6),
6161 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6163 { /* MCP61 Ethernet Controller */
6164 PCI_DEVICE(0x10DE, 0x03EE),
6165 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6167 { /* MCP61 Ethernet Controller */
6168 PCI_DEVICE(0x10DE, 0x03EF),
6169 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6171 { /* MCP65 Ethernet Controller */
6172 PCI_DEVICE(0x10DE, 0x0450),
6173 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6175 { /* MCP65 Ethernet Controller */
6176 PCI_DEVICE(0x10DE, 0x0451),
6177 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6179 { /* MCP65 Ethernet Controller */
6180 PCI_DEVICE(0x10DE, 0x0452),
6181 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6183 { /* MCP65 Ethernet Controller */
6184 PCI_DEVICE(0x10DE, 0x0453),
6185 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6187 { /* MCP67 Ethernet Controller */
6188 PCI_DEVICE(0x10DE, 0x054C),
6189 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6191 { /* MCP67 Ethernet Controller */
6192 PCI_DEVICE(0x10DE, 0x054D),
6193 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6195 { /* MCP67 Ethernet Controller */
6196 PCI_DEVICE(0x10DE, 0x054E),
6197 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6199 { /* MCP67 Ethernet Controller */
6200 PCI_DEVICE(0x10DE, 0x054F),
6201 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6203 { /* MCP73 Ethernet Controller */
6204 PCI_DEVICE(0x10DE, 0x07DC),
6205 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6207 { /* MCP73 Ethernet Controller */
6208 PCI_DEVICE(0x10DE, 0x07DD),
6209 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6211 { /* MCP73 Ethernet Controller */
6212 PCI_DEVICE(0x10DE, 0x07DE),
6213 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6215 { /* MCP73 Ethernet Controller */
6216 PCI_DEVICE(0x10DE, 0x07DF),
6217 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6219 { /* MCP77 Ethernet Controller */
6220 PCI_DEVICE(0x10DE, 0x0760),
6221 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6223 { /* MCP77 Ethernet Controller */
6224 PCI_DEVICE(0x10DE, 0x0761),
6225 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6227 { /* MCP77 Ethernet Controller */
6228 PCI_DEVICE(0x10DE, 0x0762),
6229 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6231 { /* MCP77 Ethernet Controller */
6232 PCI_DEVICE(0x10DE, 0x0763),
6233 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6235 { /* MCP79 Ethernet Controller */
6236 PCI_DEVICE(0x10DE, 0x0AB0),
6237 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6239 { /* MCP79 Ethernet Controller */
6240 PCI_DEVICE(0x10DE, 0x0AB1),
6241 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6243 { /* MCP79 Ethernet Controller */
6244 PCI_DEVICE(0x10DE, 0x0AB2),
6245 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6247 { /* MCP79 Ethernet Controller */
6248 PCI_DEVICE(0x10DE, 0x0AB3),
6249 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6251 { /* MCP89 Ethernet Controller */
6252 PCI_DEVICE(0x10DE, 0x0D7D),
6253 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
,
6258 static struct pci_driver driver
= {
6260 .id_table
= pci_tbl
,
6262 .remove
= __devexit_p(nv_remove
),
6263 .shutdown
= nv_shutdown
,
6264 .driver
.pm
= NV_PM_OPS
,
6267 static int __init
init_nic(void)
6269 return pci_register_driver(&driver
);
6272 static void __exit
exit_nic(void)
6274 pci_unregister_driver(&driver
);
6277 module_param(max_interrupt_work
, int, 0);
6278 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6279 module_param(optimization_mode
, int, 0);
6280 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6281 module_param(poll_interval
, int, 0);
6282 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6283 module_param(msi
, int, 0);
6284 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6285 module_param(msix
, int, 0);
6286 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6287 module_param(dma_64bit
, int, 0);
6288 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6289 module_param(phy_cross
, int, 0);
6290 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6291 module_param(phy_power_down
, int, 0);
6292 MODULE_PARM_DESC(phy_power_down
, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6293 module_param(debug_tx_timeout
, bool, 0);
6294 MODULE_PARM_DESC(debug_tx_timeout
,
6295 "Dump tx related registers and ring when tx_timeout happens");
6297 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6298 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6299 MODULE_LICENSE("GPL");
6301 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6303 module_init(init_nic
);
6304 module_exit(exit_nic
);